ZL30622LDF1

ZL30622 3-Input, 3-Output Any-to-Any Frequency Timing Card PLL with Ultra-Low Jitter Product Brief September 2015 Ordering Information Features  Low-Bandwidth DPLL ZL30622LDG1 ZL30622LDF1  ITU-T G.813/G.8262 compliance (options 1 & 2) 32 Pin QFN 32 Pin QFN Trays Tape and Reel Matte Tin  Programmable bandwidth, 0.1Hz to 500Hz Package size: 5 x 5 mm  Attenuates jitter up to several UI -40C to +85C  Freerun or holdover on loss of all inputs  Hitless reference switching  In 2xCMOS mode, the P and N pins can be different frequencies (e.g. 125MHz and 25MHz)  High-resolution holdover averaging  Per-output supply pin with CMOS output voltages from 1.5V to 3.3V  Digitally controlled phase adjustment  Input Clocks  Precise output alignment circuitry and peroutput phase adjustment  Three inputs, two differential/CMOS, one CMOS  Any input frequency from 8kHz to 1250MHz (8kHz to 300MHz for CMOS)  Per-output enable/disable and glitchless start/stop (stop high or low)  Per-input activity and frequency monitoring  General Features  Automatic or manual reference switching  Automatic self-configuration at power-up from internal EEPROM; up to four configurations pin-selectable  Low-Jitter Fractional-N APLL and 3 Outputs  Any output frequency from