ACT8342QKCQI-T

ACT8342 Rev 3, 11-Sep-09 Three Channel Integrated Power Management IC for Handheld Portable Equipment FEATURES • Multiple Patents Pending • Three Integrated Regulators − 350mA PWM Step-Down DC/DC − 80mA Low Noise LDO − 150mA Low Noise LDO GENERAL DESCRIPTION The patent-pending ACT8342 is a complete, cost effective, highly-efficient ActivePMUTM power management solution that is ideal for a wide range of portable handheld equipment. This device integrates one PWM step-down DC/DC converter and two low noise, low dropout linear regulators (LDOs) in a single, thin, space-saving package. This device is ideal for a wide range of portable handheld equipment that can benefit from the advantages of ActivePMUTM technology but does not require a high level of integration. REG1 is a fixed-frequency, current-mode PWM step-down DC/DC converter that is optimized for high efficiency and is capable of supplying up to 350mA output current. REG1’s output is available in a variety of factory-preset output voltage options, and an adjustable output voltage mode is also available. REG2 and REG3 are low noise, high PSRR linear regulators that are capable of supplying up to 80mA and 150mA, respectively. The ACT8342 is available in a tiny 3mm × 3mm 16-pin Thin-QFN package that is just 0.75mm thin. • Independent Enable/Disable Control • Minimal External Components • 3×3mm, Thin-QFN (TQFN33-16) Package − Only 0.75mm Height − RoHS Compliant APPLICATIONS • Portable Devices and PDAs • MP3/MP4 Players • Wireless Handhelds • GPS Receivers, etc. SYSTEM BLOCK DIAGRAM Battery nRSTO nMSTR nIRQ ON1 ON2 ON3 REG1 Step-Down DC/DC OUT1 Adjustable, or 1.2V to 3.3V Up to 350mA OUT2 1.4V to 3.7V Up to 80mA OUT3 1.4V to 3.7V Up to 150mA System Control REG2 LDO Pb Pb-free REG3 ACT8342 Active LDO PMU TM Innovative PowerTM ActivePMUTM is a trademark of Active-Semi. -1- www.active-semi.com Copyright © 2008 Active-Semi, Inc. ACT8342 Rev 3, 11-Sep-09 FUNCTIONAL BLOCK DIAGRAM OUT2 nRSTO Active-Semi ACT8342 VP1 To Battery INL REG1 nMSTR SW1 OUT1 GP1 OUT1 PUSH BUTTON OUT2 nIRQ INL ON1 ON2 ON3 REFBP Reference GA REG2 LDO To Battery or OUT1 System Control OUT2 REG3 LDO OUT3 Innovative PowerTM ActivePMUTM is a trademark of Active-Semi. -2- www.active-semi.com Copyright © 2008 Active-Semi, Inc. ACT8342 Rev 3, 11-Sep-09 ORDERING INFORMATION PART NUMBER ACT8342QKCQI-T ACT8342QKP2D-T VOUT1 1.2V 1.2V VOUT2 2.85V 2.2V VOUT3 2.85V 2.6V PACKAGE TQFN33-16 TQFN33-16 PINS 16 16 TEMPERATURE RANGE -40°C to +85°C -40°C to +85°C REG1 OUTPUT VOLTAGE CODES A Adjustable C 1.2V P 1.3V J 1.4V D 1.5V E 1.8V F 2.5V I 2.8V Q 2.85V G 3.0V H 3.3V REG2 OUTPUT VOLTAGE CODES J 1.4V D 1.5V L 1.7V E 1.8V 2 2.2V F 2.5V I 2.8V Q 2.85V G 3.0V H 3.3V REG3 OUTPUT VOLTAGE CODES E 1.4V G 1.5V K 1.7V M 1.8V B 2.5V D 2.6V H 2.8V I 2.85V L 3.0V R 3.3V : Output voltage options detailed in this table represent standard voltage options, and are available for samples or production orders. Additional output voltage options, as detailed in the Output Voltage Codes table, are available for production subject to minimum order quantities. Contact Active-Semi for more information regarding semi-custom output voltage combinations. : All Active-Semi components are RoHS Compliant and with Pb-free plating unless specified differently. The term Pb-free means semiconductor products that are in compliance with current RoHS (Restriction of Hazardous Substances) standards. PIN CONFIGURATION TOP VIEW REFBP ON3 15 16 nIRQ nMSTR nRSTO OUT1 1 2 3 4 5 VP1 Thin-QFN (TQFN33-16) Innovative PowerTM ActivePMUTM is a trademark of Active-Semi. GA ACT8342 GA 14 7 GP1 13 12 11 10 9 ON1 ON2 OUT3 INL 6 SW1 8 OUT2 -3- www.active-semi.com Copyright © 2008 Active-Semi, Inc. ACT8342 Rev 3, 11-Sep-09 PIN DESCRIPTIONS PIN 1 2 3 NAME nIRQ nMSTR nRSTO DESCRIPTION Open-Drain Push-Button Status Output. nIRQ is an open-drain output which sinks current when nMSTR is asserted or when a fault-condition occurs. If interrupts are not masked. Master Enable Input. Drive nMSTR to GA or to a logic low to enable the IC. Open-Drain Reset Output. nRSTO asserts low for the reset timeout period of 300ms whenever the IC is enabled. Output Feedback Sense. For fixed output voltage options REG1, connect this pin directly to the output node to connect the internal feedback network to the output voltage. For adjustable output voltage Options REG1. The voltage at this pin is regulated to 0.625V. Connect this pin to the center point of the output voltage feedback network between Output Node and GA to set the output voltage. Power Input for REG1. Bypass to GP1 with a high quality ceramic capacitor placed as close as possible to the IC. Switching node Output for REG1. Connect this pin to the switching end of the inductor. Power Ground for REG1. Connect GA, GP1 together at a single point as close to the IC as possible. Output voltage for REG2. Capable of delivering up to 80mA of output current. Output is discharged to ground with 650Ω resistor when disabled. Power input for REG2, REG3. Bypass to GA with a high quality ceramic capacitor placed as close as possible to the IC. Output voltage for REG3. Capable of delivering up to 150mA of output current. Output is discharged to ground with 650Ω resistor when disabled. Enable Control Input for REG2. Drive ON2 to INL or to a logic high for normal operation, drive to GA or a logic low to disable REG2. Enable control input for REG1. Drive ON1 to the VP1 or a logic high for normal operation, drive to GA or a logic low to disable REG1. Reference Noise Bypass. Connect a 0.01µF ceramic capacitor from REFBP to GA. This pin is discharged to GA in shutdown. Analog Ground. Connect GA directly to a quiet ground node. Connect GA, GP1 together at a single point as close to the IC as possible. Enable control input for REG3. Drive ON3 to the INL or a logic high for normal operation, drive to GA or a logic low to disable REG3. 4 OUT1 5 6 7 8 9 10 11 12 13 14, 16 15 VP1 SW1 GP1 OUT2 INL OUT3 ON2 ON1 REFBP GA ON3 Innovative PowerTM ActivePMUTM is a trademark of Active-Semi. -4- www.active-semi.com Copyright © 2008 Active-Semi, Inc. ACT8342 Rev 3, 11-Sep-09 ABSOLUTE MAXIMUM RATINGS PARAMETER SW1 to GP1, INL, VP1, OUT1, OUT2, OUT3, ON1, ON2, ON3, nMSTR, nRSTO, nIRQ, REFBP to GA SW1 to VP1 GP1 to GA Junction to Ambient Thermal Resistance (θJA) Operating Temperature Range Junction Temperature Storage Temperature Lead Temperature (Soldering, 10 sec) VALUE -0.3 to +6 -6 to +0.3 -0.3 to +0.3 33 -40 to 85 125 -55 to 150 300 UNIT V V V °C/W °C °C °C °C : Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may affect device reliability. Innovative PowerTM ActivePMUTM is a trademark of Active-Semi. -5- www.active-semi.com Copyright © 2008 Active-Semi, Inc. ACT8342 Rev 3, 11-Sep-09 SYSTEM MANAGEMENT ELECTRICAL CHARACTERISTICS (VINL = 3.6V, TA = 25°C, unless otherwise specified.) PARAMETER INL Operating Voltage Range INL UVLO Threshold INL UVLO Hysteresis Oscillator Frequency INL Supply Current nMSTR Internal Pull-Up Resistance Logic High Input Voltage Logic Low Input Voltage Logic Low Output Voltage Leakage Current nRSTO Delay Thermal Shutdown Temperature Thermal Shutdown Hysteresis TEST CONDITIONS INL Voltage Rising INL Voltage Falling MIN 2.7 2.25 TYP 2.5 90 MAX 5.5 2.7 UNIT V V mV 1.35 ON1 = ON2 = ON3 = GA 250 ON1, ON2, ON3, nMSTR ON1, ON2, ON3, nMSTR ISINK = 5mA nIRQ, nRSTO, VnRSTO = VnIRQ = 4.2V 240 Temperature rising Temperature falling 1.4 1.6 1.5 500 1.85 MHz µA kΩ V 0.4 0.3 1 300 160 20 360 V V µA ms °C °C Innovative PowerTM ActivePMUTM is a trademark of Active-Semi. -6- www.active-semi.com Copyright © 2008 Active-Semi, Inc. ACT8342 Rev 3, 11-Sep-09 SYSTEM MANAGEMENT FUNCTIONAL DESCRIPTION General Description The ACT8342 offers an array of system management functions that allow it to provide optimal performance in a wide range of applications. timing and sequence. The ACT8342 asserts nIRQ low when nMSTR is asserted low, providing a simple means of alerting the system processor when the user wishes to shut the system down. Asserting nIRQ interrupts the system processor, initiating an interrupt service routine in the processor which will reveal that the user pressed the push-button. The microprocessor may validate the input, such as by ensuring that the push-button is asserted for a minimum amount of time, then initiates a software-controlled power-down routine, the final step of which is to de-assert the ON1 input, disabling REG1 and REG2 and shutting the system down. nMSTR Enable Input In most applications, connect nMSTR to an active low, momentary push-button switch to utilize the ACT8342’s closed-loop enable/disable functionality. If a momentary-on switch is not used, drive nMSTR to GA or to a logic low to initiate a startup sequence. Enable/Disable Inputs T he ACT8342 provides three manual enable/disable inputs. When driven high, ON1 enables REG1, ON2 enables REG2, and ON3 enables OUT3. nIRQ Output The ACT8342 provides an active-low, open-drain push-button status output that sinks current when nMSTR is driven to a logic-low. Connect a pull-up resistor from nIRQ to an appropriate voltage supply. nIRQ is typically used to drive the interrupt input of the system processor, and is useful in a variety of software-controlled enable/disable control routines. Thermal Shutdown The ACT8342 integrates thermal shutdown protection circuitry to prevent damage resulting from excessive thermal stress, as may be encountered under fault conditions. This circuitry disables all regulators if the ACT8342 die temperature exceeds 160°C, and prevents the regulators from being enabled until the IC temperature drops by 20°C (typ). System Startup and Shutdown The ACT8342 features a flexible control architecture that supports a variety of softwarecontrolled enable/disable functions that make it a simple yet flexible and highly configurable solution. The ACT8342 is automatically enabled when any of the following conditions exists: 1) nMSTR is asserted low, or 2) ON1 is asserted high, or 3) ON2 is asserted high, or 4) ON3 is asserted high. If any of these conditions is true, the ACT8342 enables and ON1 drives REG1, ON2 drives REG2, and ON3 drives REG3. Manual Enable Due to Asserting nMSTR Low System startup is initiated when the user presses the push-button, asserting nMSTR low. When this occurs, REG1 is enabled, which in turn enables the processor to allow it to control the system power up sequence. Once the power-up routine is successfully completed, the microprocessor must assert ON1 so that the ACT8342 remains enabled after the push-button is released by the user. Upon completion of the start-up sequence the processor assumes control of the power system and all further operation is software-controlled. Manual Enable Due to Asserting ON1 High The ACT8342 is compatible with applications that do not utilize it’s push-button control function, and may be enabled by simply driving ON1 to a logichigh. In this case, the signal driving ON1 controls enable/disable timing, although software-controlled enable/disable sequences are still supported if the processor assumes control of the power system once the startup sequence is completed. Shutdown Sequence Once a successful power-up routine is completed, the system processor controls the operation of the power system, including the system shutdown Innovative PowerTM ActivePMUTM is a trademark of Active-Semi. -7- www.active-semi.com Copyright © 2008 Active-Semi, Inc. ACT8342 Rev 3, 11-Sep-09 SYSTEM MANAGEMENT TYPICAL PERFORMANCE CHARACTERISTICS (VINL = 3.6V, TA = 25°C, unless otherwise specified.) Oscillator Frequency vs. Temperature 1.71 1.68 ACT8342-001 Frequency (MHz) 1.65 1.62 1.59 1.56 1.53 1.50 -40 -20 0 20 40 60 85 Temperature (°C) Startup Sequence ACT8342-002 CH1 CH2 CH3 CH4 CH1: VnMSTR, 5V/div CH2: VnRSTO, 2V/div CH3: VON1, 5V/div CH4: VOUT1, 2V/div TIME: 100ms/div Shutdown Sequence ACT8342-003 CH1 CH2 CH3 CH4 CH1: VnMSTR, 5V/div CH2: VnIRQ, 2V/div CH3: VON1, 5V/div CH4: VOUT1, 2V/div TIME: 100ms/div Innovative PowerTM ActivePMUTM is a trademark of Active-Semi. -8- www.active-semi.com Copyright © 2008 Active-Semi, Inc. ACT8342 Rev 3, 11-Sep-09 STEP-DOWN DC/DC CONVERTER ELECTRICAL CHARACTERISTICS (REG1) (VVP1 = 3.6V, TA = 25°C, unless otherwise specified.) PARAMETER VP1 Operating Voltage Range VP1 UVLO Threshold VP1 UVLO Hysteresis Standby Supply Current Shutdown Supply Current Adjustable Output Option Regulation Voltage Output Voltage Regulation Accuracy Line Regulation Load Regulation Current Limit Oscillator Frequency PMOS On-Resistance NMOS On-Resistance SW1 Leakage Current Power Good Threshold Minimum On-Time TEST CONDITIONS Input Voltage Rising Input Voltage Falling MIN 3.1 2.9 TYP 3 90 130 MAX 5.5 3.1 UNIT V V mV 200 1 µA µA V ON1 = GA, VVP1 = 4.2V 0.1 0.625 VNOM1 < 1.3V, IOUT1 = 10mA VNOM1 ≥ 1.3V, IOUT1 = 10mA VVP1 = Max(VNOM1 + 1V, 3.2V) to 5.5V IOUT1 = 10mA to 350mA -2.4% -1.2% VNOM1 VNOM1 0.15 0.0017 +1.8% +1.8% V %/V %/mA A 0.45 VOUT1 ≥ 20% of VNOM1 VOUT1 = 0V ISW1 = -100mA ISW1 = 100mA VVP1 = 5.5V, VSW1 = 5.5V or 0V 1.35 0.6 1.6 530 0.52 0.27 0.88 0.46 1 94 70 1.85 MHz kHz Ω Ω µA %VNOM1 ns : VNOM1 refers to the nominal output voltage level for VOUT1 as defined by the Ordering Information section. Innovative PowerTM ActivePMUTM is a trademark of Active-Semi. -9- www.active-semi.com Copyright © 2008 Active-Semi, Inc. ACT8342 Rev 3, 11-Sep-09 STEP-DOWN DC/DC CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS (ACT8342QKCQI, VVP1 = 3.6V, L = 3.3µH, CVP1 = 2.2μF, COUT1 = 10μF, TA = 25°C, unless otherwise specified.) REG1 Efficiency vs. Load Current 95 90 85 VOUT1 = 1.2V VIN = 3.6V 650 REG1 Transient Peak Inductor Current Peak Inductor Current (mA) ACT8342-004 ACT8342-005 630 Efficiency (%) 80 75 70 65 60 55 50 1 10 VIN = 4.2V 610 590 570 550 100 1000 3.0 3.5 4.0 4.5 5.0 5.5 Output Current (mA) VP1 Voltage (V) REG1 MOSFET Resistance 600 500 PMOS 400 300 200 100 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 NMOS 0.2 ACT8342-006 REG1 Load Regulation ACT8342-007 Load Regulation Error (%) 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 4.2V RDSON (mΩ) 3.6V 0 50 100 150 200 250 300 350 400 VP1 Voltage (V) Output Current (mA) OUT1 Regulation Voltage 0.67 0.56 0.44 ACT8342-008 IOUT1 = 35mA OUT1 Voltage (%) 0.33 0.22 0.11 0.00 -0.11 -0.22 -0.33 -0.44 -0.56 -0.67 -40 -20 0 20 40 60 85 Temperature (°C) Innovative PowerTM ActivePMUTM is a trademark of Active-Semi. - 10 - www.active-semi.com Copyright © 2008 Active-Semi, Inc. ACT8342 Rev 3, 11-Sep-09 STEP-DOWN DC/DC CONVERTER FUNCTIONAL DESCRIPTION General Description REG1 is a fixed-frequency, current-mode, synchronous PWM step-down converters that achieves a peak efficiency of up to 97%. REG1 is capable of supplying up to 350mA of output current and operates with a fixed frequency of 1.6MHz, minimizing noise in sensitive applications and allowing the use of small external components. REG1 is available with a variety of standard and custom output voltages, as well as an adjustable output voltage option. Input Capacitor Selection The input capacitor reduces peak currents and noise induced upon the voltage source. A 2.2µF ceramic input capacitor is recommended for most applications. Output Capacitor Selection For most applications, a 10µF ceramic output capacitor is recommended. Although REG1 was designed to take advantage of the benefits of ceramic capacitors, namely small size and very-low ESR, low-ESR tantalum capacitors can provide acceptable results as well. 100% Duty Cycle Operation REG1 is capable of operating at up to 100% duty cycle. During 100% duty-cycle operation, the high-side power MOSFET is held on continuously, providing a direct connection from the input to the output (through the inductor), ensuring the lowest possible dropout voltage in battery-powered applications. Inductor Selection REG1 utilizes current-mode control and a proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over its full operating range. REG1 was optimized for operation with a 3.3µH inductor, although inductors in the 2.2µH to 4.7µH range can be used. Choose an inductor with a low DC-resistance, and avoid inductor saturation by choosing inductors with DC ratings that exceed the maximum output current of the application by at least 30%. Synchronous Rectification R EG1 features an integrated n-channel synchronous rectifier, which maximizes efficiency and minimizes the total solution size and cost by eliminating the need for an external rectifier. Enabling and Disabling REG1 REG1 is enabled or disabled using ON1. Drive ON1 to a logic-high to enable REG1. Drive ON1 to a logic-low to disable REG1, reducing supply current to less than 1µA. Thermal Shutdown The ACT8342 integrates thermal shutdown protection circuitry to prevent damage resulting from excessive thermal stress, as may be encountered under fault conditions. This circuitry disables all regulators if the ACT8342 die temperature exceeds 160°C, and prevents the regulators from being enabled until the IC temperature drops by 20°C (typ). Soft-Start REG1 includes internal soft-start circuitry, and enabled its output voltage tracks an internal 80µs soft-start ramp so that it powers up in a monotonic manner that is independent of loading. Output Voltage Programming Figure 4 shows the feedback network necessary to set the output voltage when using the adjustable output voltage option. Select components as follows: Set RFB2 = 51KΩ, then calculate RFB1 using the following equation: Compensation REG1 utilizes current-mode control and a proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over its full operating range. No compensation design is required, simply follow a few simple guidelines described below when choosing external components. ⎛V ⎞ RFB1 = RFB 2 ⎜ OUT1 − 1 ⎟ ⎜V ⎟ ⎝ FB ⎠ Where VFB is 0.625V (1) Innovative PowerTM ActivePMUTM is a trademark of Active-Semi. - 11 - www.active-semi.com Copyright © 2008 Active-Semi, Inc. ACT8342 Rev 3, 11-Sep-09 STEP-DOWN DC/DC CONVERTER Figure 4: Output Voltage Programming OUT1 ACT8342 OUT1 CFF RFB1 VFB RFB2 Finally choose CFF using the following equation: C FF = 2.2 × 10 −6 R FB1 (2) where RFB1 = 47kΩ, use 47pF. PCB Layout Considerations High switching frequencies and large peak currents make PC board layout an important part of stepdown DC/DC converter design. A good design minimizes excessive EMI on the feedback paths and voltage gradients in the ground plane, both of which can result in instability or regulation errors. Step-down DC/DCs exhibit discontinuous input current, so the input capacitors should be placed as close as possible to the IC, and avoiding the use of vias if possible. The inductor, input filter capacitor, and output filter capacitor should be connected as close together as possible, with short, direct, and wide traces. The ground nodes for each regulator's power loops should be connected at a single point in a star-ground configuration, and this point should be connected to the backside ground plane with multiple vias. For fixed output voltage options, connect the output node directly to the OUT1 pin. For adjustable output voltage options, connect the feedback resistors and feed-forward capacitor to the OUT1 pin through the shortest possible route. In both cases, the feedback path should be routed to maintain sufficient distance from switching nodes to prevent noise injection. Finally, the exposed pad should be directly connected to the backside ground plane using multiple vias to achieve low electrical and thermal resistance. Innovative PowerTM ActivePMUTM is a trademark of Active-Semi. - 12 - www.active-semi.com Copyright © 2008 Active-Semi, Inc. ACT8342 Rev 3, 11-Sep-09 LOW-DROPOUT LINEAR REGULATORS ELECTRICAL CHARACTERISTICS (REG2) (VINL = 3.6V, COUT2 = 1µF, TA = 25°C, unless otherwise specified.) PARAMETER INL Operating Voltage Range INL UVLO Threshold UVLO Hysteresis Output Voltage Accuracy Line Regulation Error Load Regulation Error Power Supply Rejection Ratio TEST CONDITIONS VINL Input Rising VINL Input Falling TA = 25°C TA = -40°C to 85°C VINL = Max(VOUT2 + 0.5V, 3.6V) to 5.5V IOUT2 = 1mA to 80mA f = 1kHz, IOUT2 = 80mA, COUT2 = 1µF f = 10kHz, IOUT2 = 80mA, COUT2 = 1µF Regulator Enabled Regulator Disabled IOUT2 = 40mA, VOUT2 > 3.1V MIN 3.1 2.9 TYP 3 0.1 MAX 5.5 3.1 UNIT V V V -1.2 -2.5 VNOM21 VNOM2 0 -0.004 70 60 50 0 100 +2 +3 % mV %/mA dB Supply Current per Output Dropout Voltage2 Output Current Current Limit Internal Soft-Start Power Good Flag High Threshold Output Noise Stable COUT2 Range Discharge Resistor in Shutdown µA 200 80 mV mA mA VOUT2 = 95% of regulation voltage 90 100 µs % µVRMS 20 µF Ω VOUT2, hysteresis = -4% COUT2 = 10µF, f = 10Hz to 100kHz 1 LDO Disabled 89 40 650 : VNOM2 refers to the nominal output voltage level for VOUT2 as defined by the Ordering Information section. : Dropout Voltage is defined as the differential voltage between input and output when the output voltage drops 100mV below the regulation voltage at 1V differential voltage. : LDO current limit is defined as the output current at which the output voltage drops to 95% of the respective regulation voltage. Under heavy overload conditions the output current limit folds back by 30% (typ) Innovative PowerTM ActivePMUTM is a trademark of Active-Semi. - 13 - www.active-semi.com Copyright © 2008 Active-Semi, Inc. ACT8342 Rev 3, 11-Sep-09 LOW-DROPOUT LINEAR REGULATORS ELECTRICAL CHARACTERISTICS (REG3) (VINL = 3.6V, COUT3 = 1µF, TA = 25°C, unless otherwise specified.) PARAMETER INL Operating Voltage Range INL UVLO Threshold UVLO Hysteresis Output Voltage Accuracy Line Regulation Error Load Regulation Error Power Supply Rejection Ratio TEST CONDITIONS VINL Input Rising VINL Input Falling TA = 25°C TA = -40°C to 85°C VINL = Max(VOUT3 + 0.5V, 3.6V) to 5.5V IOUT3 = 1mA to 150mA f = 1kHz, IOUT3 = 150mA, COUT3 = 1µF f = 10kHz, IOUT3 = 150mA, COUT3 = 1µF Regulator Enabled Regulator Disabled IOUT3 = 80mA, VOUT3 > 3.1V MIN 3.1 2.9 TYP 3 0.1 MAX 5.5 3.1 UNIT V V V -1.2 -2.5 VNOM31 VNOM3 0 -0.004 70 60 50 0 100 +2 +3 % mV %/mA dB Supply Current per Output Dropout Voltage2 Output Current Current Limit Internal Soft-Start Power Good Flag High Threshold Output Noise Stable COUT3 Range Discharge Resistor in Shutdown µA 200 150 mV mA mA VOUT3 = 95% of regulation voltage 170 100 µs % µVRMS 20 µF Ω VOUT3, hysteresis = -4% COUT3 = 10µF, f = 10Hz to 100kHz 1 LDO Disabled 89 40 650 : VNOM3 refers to the nominal output voltage level for VOUT2 as defined by the Ordering Information section. : Dropout Voltage is defined as the differential voltage between input and output when the output voltage drops 100mV below the regulation voltage at 1V differential voltage. : LDO current limit is defined as the output current at which the output voltage drops to 95% of the respective regulation voltage. Under heavy overload conditions the output current limit folds back by 30% (typ) Innovative PowerTM ActivePMUTM is a trademark of Active-Semi. - 14 - www.active-semi.com Copyright © 2008 Active-Semi, Inc. ACT8342 Rev 3, 11-Sep-09 LOW-DROPOUT LINEAR REGULATORS TYPICAL PERFORMANCE CHARACTERISTICS (ACT8342QKCQI, VINL = 5V, TA = 25°C, unless otherwise specified.) Load Regulation 0.20 0.15 0.5 Output Voltage Deviation vs. Temperature Output Voltage Deviation (%) ACT8342-009 ACT8342-010 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -40 -15 10 35 60 85 ILOAD = 0mA Output Voltage (%) 0.10 0.05 0.00 LDO2 -0.05 -0.10 -0.15 -0.20 0 20 40 60 80 100 120 140 LDO3 160 Load Current (mA) Temperature (°C) LDO2 Dropout voltage vs. Output current 300 200 ACT8342-011 LDO3 Dropout voltage vs. Output current ACT8342-012 Dropout Voltage (mV) Dropout Voltage (mV) 250 200 3.1V 150 3.7V 100 50 0 0 20 40 60 80 100 160 3.1V 3.7V 80 120 40 0 120 0 20 40 60 80 100 120 140 160 Output Current (mA) Output Current (mA) Region of Stable COUT ESR vs. Output Current 1 ACT8342-013 LDO Output Voltage Noise ACT8342-014 ESR (Ω) CH1 0.1 Stable ESR 0.01 0 50 100 150 Output Current (mA) CH1: VOUTx, 200µV/div (AC COUPLED) TIME: 200ms/div Innovative PowerTM ActivePMUTM is a trademark of Active-Semi. - 15 - www.active-semi.com Copyright © 2008 Active-Semi, Inc. ACT8342 Rev 3, 11-Sep-09 LOW-DROPOUT LINEAR REGULATORS FUNCTIONAL DESCRIPTION General Description REG2 and REG3 are low-noise, low-dropout linear regulators (LDOs) that are optimized for low-noise and high-PSRR operation, achieving more than 60dB PSRR at frequencies up to 10kHz. A good design places input and output capacitors as close to the LDO inputs and output as possible, and utilizes a star-ground configuration for all regulators to prevent noise-coupling through ground. Output traces should be routed to avoid close proximity to noisy nodes, particularly the SW nodes of the DC/DCs. Output Current Capability REG2 supplies up to 80mA while REG3 supplies up to 150mA of load current. Excellent performance is achieved over each regulator's entire load current ranges. Output Current Limit In order to ensure safe operation under over-load conditions, each LDO features current-limit circuitry with current fold-back. The current-limit circuitry limits the current that can be drawn from the output, providing protection in over-load conditions. For additional protection under extreme over current conditions, current-fold-back protection reduces the current-limit by approximately 30% under extreme overload conditions. Enabling and Disabling the LDOs REG2 and REG3 are enabled or disabled using ON2 and ON3. Drive ON2 and ON3 to a logic-high to enable REG2 and REG3. Drive ON2 and ON3 to a logic-low to disable REG2 and REG3, reducing supply current to less than 1µA. Output Capacitor Selection REG2 and REG3 each require only a small ceramic capacitor for stability. For best performance, each output capacitor should be connected directly between the OUT2 and OUT3 and G pins as possible, with a short and direct connection. To ensure best performance for the device, the output capacitor should have a minimum capacitance of 1µF, and ESR value between 10mΩ and 200mΩ. High quality ceramic capacitors such as X7R and X5R dielectric types are strongly recommended. PCB Layout Considerations The ACT8342’s LDOs provide good DC, AC, and noise performance over a wide range of operating conditions, and are relatively insensitive to layout considerations. When designing a PCB, however, careful layout is necessary to prevent other circuitry from degrading LDO performance. Innovative PowerTM ActivePMUTM is a trademark of Active-Semi. - 16 - www.active-semi.com Copyright © 2008 Active-Semi, Inc. ACT8342 Rev 3, 11-Sep-09 PACKAGE INFORMATION PACKAGE OUTLINE TQFN33-16 PACKAGE OUTLINE AND DIMENSIONS D SYMBOL A A1 E DIMENSION IN MILLIMETERS MIN 0.700 0.000 0.153 2.900 2.900 1.600 1.600 0.180 DIMENSION IN INCHES MIN 0.028 0.000 0.006 0.114 0.114 0.063 0.063 0.007 MAX 0.800 0.050 0.253 3.100 3.100 1.800 1.800 0.300 MAX 0.031 0.002 0.010 0.122 0.122 0.071 0.071 0.012 A3 D E D2 A1 E2 b A3 A e L 0.500 TYP 0.300 0.200 0.500 0.400 0.020 TYP 0.012 0.008 0.020 0.016 e K E1 D1 Active-Semi, Inc. reserves the right to modify the circuitry or specifications without notice. Users should evaluate each product to make sure that it is suitable for their applications. Active-Semi products are not intended or authorized for use as critical components in lifesupport devices or systems. Active-Semi, Inc. does not assume any liability arising out of the use of any product or circuit described in this datasheet, nor does it convey any patent license. Active-Semi and its logo are trademarks of Active-Semi, Inc. For more information on this and other products, contact sales@activesemi.com or visit http://www.active-semi.com. For other inquiries, please send to: 1270 Oakmead Parkway, Suite 310, Sunnyvale, California 94085-4044, USA Innovative PowerTM ActivePMUTM is a trademark of Active-Semi. b L K - 17 - www.active-semi.com Copyright © 2008 Active-Semi, Inc.