ACT8865
Rev 7, 22-Mar-16
Advanced PMU for Atmel SAMA5Dx Series & SAM9 Series Processors
such as human-machine interfaces, control panels,
smart grid infrastructures, network gateways, M2M
systems, 2D barcode scanners, barcode printers,
machine vision equipment, as well as home and
commercial building automations, POS terminals,
medical devices and white goods.
This device features three step-down DC/DC
converters and four low-noise, low-dropout linear
regulators.
FEATURES
Three Step-Down DC/DC Converters
Four Low-Dropout Linear Regulators
I2CTM Serial Interface
Advanced Enable/Disable Sequencing Controller
Minimal External Components
Tiny 4×4mm TQFN44-32 Package
0.75mm Package Height
Pb-Free and RoHS Compliant
The three DC/DC converters utilize a highefficiency, fixed-frequency (2MHz), current-mode
PWM control architecture that requires a minimum
number of external components. Two DC/DCs are
capable of supplying up to 1150mA of output
current, while the third supports up to 1300mA. All
four low-dropout linear regulators are highperformance, low-noise, regulators that supply up to
320mA.
GENERAL DESCRIPTION
The ACT8865 is a complete, cost effective, highlyefficient ActivePMUTM power management solution,
optimized for the unique power, voltagesequencing, and control requirements of the Atmel
SAMA5D2 series ,SAMA5D3 series: SAMA5D
[31/33/34/35/36], and SAM9 series:SAM9G
[15/25/35/45/46]; SAM9X[25/35], SAM9M[10/11],
SAM9N[11/12] processors. It is ideal for a wide range
of high performance portable handheld applications
The ACT8865 is available in a compact, Pb-Free
and RoHS-compliant TQFN44-32 package.
TYPICAL APPLICATION DIAGRAM
Atmel
SAMA5Dx
ACT8865
PUSH BUTTON
nPBIN
REG1
1.8V
1150mA
VDDIODDR etc.
REG2
1.2V
1150mA
VDDCORE_GBIT ENET etc.
REG3
3.3V
1300mA
VDDIOP etc.
REG4
320mA
VDDFUSE
REG5
320mA
VDDANA
REG6
320mA
Auxiliary 1
REG7
320mA
Auxiliary 1
TWD
TWCK
SDA
SCL
NRST
FIQ/IRQ
GPIO
nRSTO
nIRQ
nPBSTAT
-1ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
www.active-semi.com
Copyright © 2016 Active-Semi, Inc.
ACT8865
Rev 7, 22-Mar-16
TABLE OF CONTENTS
General Information ..................................................................................................................................... p. 01
Functional Block Diagram ............................................................................................................................ p. 03
Ordering Information .................................................................................................................................... p. 04
Pin Configuration ......................................................................................................................................... p. 04
Pin Descriptions ........................................................................................................................................... p. 05
Absolute Maximum Ratings ......................................................................................................................... p. 07
I2C Interface Electrical Characteristics ........................................................................................................ p. 08
Global Register Map .................................................................................................................................... p. 09
Register and Bit Descriptions ...................................................................................................................... p. 10
System Control Electrical Characteristics.................................................................................................... p. 14
Step-Down DC/DC Electrical Characteristics .............................................................................................. p. 15
Low-Noise LDO Electrical Characteristics ................................................................................................... p. 16
Typical Performance Characteristics ........................................................................................................... p. 17
System control information .......................................................................................................................... p. 21
Interfacing with the Atmel SAMA5D2, SAMA5D3 Series & SAM9 Series Processors .................... p. 21
Control Signals ................................................................................................................................. p. 22
Push-Button Control ......................................................................................................................... p. 22
Control Sequences ........................................................................................................................... p. 23
Functional Description ................................................................................................................................. p. 24
I2C Interface ..................................................................................................................................... p. 24
Voltage Monitor and Interrupt........................................................................................................... p. 24
Thermal Shutdown ........................................................................................................................... p. 24
Step-Down DC/DC Regulators .................................................................................................................... p. 25
General Description.......................................................................................................................... p. 25
100% Duty Cycle Operation ............................................................................................................. p. 25
Synchronous Rectification ................................................................................................................ p. 25
Soft-Start .......................................................................................................................................... p. 25
Compensation .................................................................................................................................. p. 25
OK[ ] and Output Fault Interrupt ....................................................................................................... p. 25
PCB Layout Considerations ............................................................................................................. p. 26
Low-Noise, Low-Dropout Linear Regulators................................................................................................ p. 27
General Description.......................................................................................................................... p. 27
Output Current Limit ......................................................................................................................... p. 27
Compensation .................................................................................................................................. p. 27
Configuration Options....................................................................................................................... p. 27
OK[ ] and Output Fault Interrupt ....................................................................................................... p. 27
PCB Layout Considerations ............................................................................................................. p. 28
Errata Info .................................................................................................................................................... p. 29
Errata Name ..................................................................................................................................... p. 29
Device Identification ......................................................................................................................... p. 29
Recommendation ............................................................................................................................. p. 29
Workaround ...................................................................................................................................... p. 29
TQFN44-32 Package Outline and Dimensions ........................................................................................... p. 30
Revision History ........................................................................................................................................... p. 31
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ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
Copyright © 2016 Active-Semi, Inc.
ACT8865
Rev 7, 22-Mar-16
REG3
REG2
REG1
FUNCTIONAL BLOCK DIAGRAM
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ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
Copyright © 2016 Active-Semi, Inc.
ACT8865
Rev 7, 22-Mar-16
ORDERING INFORMATION
TEMPERATURE
RANGE
PART NUMBER
VOUT1
VOUT2
VOUT3
VOUT4 VOUT5 VOUT6 VOUT7 PACKAGE PINS
ACT8865QI305-T
1.8V
1.2V
3.3V
2.5V 3.3V OFF OFF TQFN44-32
32
-40°C to +85°C
ACT8865QI405-T
1.5V/1.35V
1.2V
3.3V
2.5V 3.3V OFF OFF TQFN44-32
32
-40°C to +85°C
: All Active-Semi components are RoHS Compliant and with Pb-free plating unless specified differently. The term Pb-free means
semiconductor products that are in compliance with current RoHS (Restriction of Hazardous Substances) standards.
: Standard product options are identified in this table. Contact factory for custom options, minimum order quantity is 12,000 units.
: To select VSTBYx as a output regulation voltage of REGx, drive VSEL to a logic high. The VSTBYx can be set by software via I2C
interface, refer to appropriate sections of this datasheet for VSTBYx setting.
: VOUT2 = 1.2V @VSEL=0 and VOUT2 = 1.0V @VSEL=VIN
: VOUT1 = 1.35V @VSEL=VIN and VOUT1 = 1.5V @VSEL=0 for ACT8865QI405-T regulator setting.
PIN CONFIGURATION
VP1
SW1
GP1
GP2
SW2
VP2
NC2
PWRHLD
nRSTO
nIRQ
nPBSTAT
GP3
SW3
VP3
nPBIN
REFBP
TOP VIEW
Thin - QFN (TQFN44-32)
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ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
Copyright © 2016 Active-Semi, Inc.
ACT8865
Rev 7, 22-Mar-16
PIN DESCRIPTIONS
PIN
NAME
DESCRIPTION
1
OUT1
Output Feedback Sense for REG1. Connect this pin directly to the output node to connect the
internal feedback network to the output voltage.
2
GA
Analog Ground. Connect GA directly to a quiet ground node. Connect GA, GP1,GP2 and GP3
together at a single point as close to the IC as possible.
3
OUT4
Output Voltage for REG4. Capable of delivering up to 320mA of output current. Connect a 3.3µF
ceramic capacitor from OUT4 to GA. The output is discharged to GA with 1.5kΩ resistor when
disabled.
4
OUT5
Output Voltage for REG5. Capable of delivering up to 320mA of output current. Connect a 3.3µF
ceramic capacitor from OUT5 to GA. The output is discharged to GA with 1.5kΩ resistor when
disabled.
5
INL45
Power Input for REG4 and REG5. Bypass to GA with a high quality ceramic capacitor placed as
close to the IC as possible.
6
INL67
Power Input for REG6 and REG7. Bypass to GA with a high quality ceramic capacitor placed as
close to the IC as possible.
7
OUT6
Output Voltage for REG6. Capable of delivering up to 320mA of output current. Connect a 3.3µF
ceramic capacitor from OUT6 to GA. The output is discharged to GA with 1.5kΩ resistor when
disabled.
8
OUT7
Output Voltage for REG7. Capable of delivering up to 320mA of output current. Connect a 3.3µF
ceramic capacitor from OUT7 to GA. The output is discharged to GA with 1.5kΩ resistor when
disabled.
9
nPBIN
Master Enable Input. Drive nPBIN to GA through a 50kΩ resistor to enable the IC, drive nPBIN
directly to GA to assert a manual reset condition. Refer to the nPBIN Multi-Function Input section
for more information. nPBIN is internally pulled up to VVDDREF through a 35kΩ resistor.
10
PWRHLD
Power Hold Input. Refer to the Control Sequences section for more information.
11
nRSTO
Active Low Reset Output. See the nRSTO Output section for more information.
12
nIRQ
13
nPBSTAT
Active-Low Open-Drain Push-Button Status Output. nPBSTAT is asserted low whenever the
nPBIN is pushed, and is high-Z otherwise. See the nPBSTAT Output section for more information.
14
GP3
Power Ground for REG3. Connect GA, GP1, GP2, and GP3 together at a single point as close to
the IC as possible.
15
SW3
Switching Node Output for REG3. Connect this pin to the switching end of the inductor.
16
VP3
Power Input for REG3. Bypass to GP3 with a high quality ceramic capacitor placed as close to the
IC as possible.
17
PWREN
18
NC1
19
OUT3
Output Feedback Sense for REG3. Connect this pin directly to the output node to connect the
internal feedback network to the output voltage.
20
VSEL
Step-Down DC/DCs Output Voltage Selection. Drive to logic low to select default output voltage.
Drive to logic high to select secondary output voltage. See the Output Voltage Programming
section for more information.
21
SCL
Clock Input for I2C Serial Interface.
22
SDA
Data Input for I2C Serial Interface. Data is read on the rising edge of SCL.
Open-Drain Interrupt Output. nIRQ asserts any time an unmasked fault condition exists or an
interrupt occurs. See the nIRQ Output section for more information.
Power Enable Input. Refer to the Control Sequences section for more information.
Not Connected. Not internally connected.
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ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
Copyright © 2016 Active-Semi, Inc.
ACT8865
Rev 7, 22-Mar-16
PIN DESCRIPTIONS CONT’D
PIN
23
NAME
DESCRIPTION
Power supply for the internal reference. Connect this pin directly to the system power supply.
VDDREF Bypass VDDREF to GA with a 100nF capacitor placed as close to the IC as possible. Star
connection with VP1, VP2 and VP3 preferred.
Output Feedback Sense for REG2. Connect this pin directly to the output node to connect the
internal feedback network to the output voltage.
24
OUT2
25
NC2
Not Connected. Not internally connected.
26
VP2
Power Input for REG2 and System Control. Bypass to GP2 with a high quality ceramic capacitor
placed as close to the IC as possible.
27
SW2
Switching Node Output for REG2. Connect this pin to the switching end of the inductor.
28
GP2
Power Ground for REG2. Connect GA, GP1,GP2 and GP3 together at a single point as close to
the IC as possible.
29
GP1
Power Ground for REG1. Connect GA, GP1,GP2 and GP3 together at a single point as close to
the IC as possible.
30
SW1
Switching Node Output for REG1. Connect this pin to the switching end of the inductor.
31
VP1
Power Input for REG1. Bypass to GP1 with a high quality ceramic capacitor placed as close to
the IC as possible.
32
REFBP
EP
EP
Reference Bypass. Connect a 0.047μF ceramic capacitor from REFBP to GA. This pin is
discharged to GA in shutdown.
Exposed Pad. Must be soldered to ground on PCB.
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ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
Copyright © 2016 Active-Semi, Inc.
ACT8865
Rev 7, 22-Mar-16
ABSOLUTE MAXIMUM RATINGS
PARAMETER
VALUE
UNIT
VP1 to GP1, VP2 to GP2, VP3 to GP3
-0.3 to + 6
V
INL, VDDREF to GA
-0.3 to + 6
V
-0.3 to (VVDDREF + 0.3)
V
-0.3 to + 6
V
SW1, OUT1 to GP1
-0.3 to (VVP1 + 0.3)
V
SW2, OUT2 to GP2
-0.3 to (VVP2 + 0.3)
V
SW3, OUT3 to GP3
-0.3 to (VVP3 + 0.3)
V
OUT4, OUT5, OUT6, OUT7 to GA
-0.3 to (VINL + 0.3)
V
-0.3 to + 0.3
V
27.5
°C/W
Operating Ambient Temperature
-40 to 85
°C
Maximum Junction Temperature
125
°C
-65 to 150
°C
300
°C
nPBIN, SCL, SDA, REFBP, PWRHLD, PWREN, VSEL to GA
nRSTO, nIRQ, nPBSTAT to GA
GP1, GP2, GP3 to GA
Junction to Ambient Thermal Resistance (θJA)
Storage Temperature
Lead Temperature (Soldering, 10 sec)
: Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may
affect device reliability.
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ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
Copyright © 2016 Active-Semi, Inc.
ACT8865
Rev 7, 22-Mar-16
I2C INTERFACE ELECTRICAL CHARACTERISTICS
(VVP1 = VVP2 = VVP3 = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
MIN
SCL, SDA Input Low
VVDDREF = 3.1V to 5.5V, TA = -40ºC to 85ºC
SCL, SDA Input High
VVDDREF = 3.1V to 5.5V, TA = -40ºC to 85ºC
TYP
UNIT
0.35
V
1.55
V
SDA Leakage Current
SCL Leakage Current
1
SDA Output Low
MAX
IOL = 5mA
1
µA
2
µA
0.35
V
SCL Clock Period, tSCL
1.5
µs
SDA Data Setup Time, tSU
100
ns
SDA Data Hold Time, tHD
300
ns
Start Setup Time, tST
For Start Condition
100
ns
Stop Setup Time, tSP
For Stop Condition
100
ns
Figure 1:
I2C Compatible Serial Bus Timing
tSCL
SCL
tST
tHD
tSU
tSP
SDA
Start
condition
Stop
condition
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ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
Copyright © 2016 Active-Semi, Inc.
ACT8865
Rev 7, 22-Mar-16
GLOBAL REGISTER MAP
BITS
OUTPUT ADDRESS
SYS
SYS
0x00
0x01
REG1
0x20
REG1
0x21
REG1
REG2
0x22
0x30
REG2
0x31
REG2
0x32
REG3
REG3
0x40
0x41
REG3
0x42
REG4
0x50
REG4
REG5
0x51
0x54
REG5
0x55
REG6
0x60
REG6
REG7
REG7
0x61
0x64
0x65
D7
D6
D5
D4
NAME
TRST
DEFAULT
1
nSYSMODE nSYSLEVMSK nSYSSTAT
1
0
R
NAME
Reserved
Reserved
MSTROFF
Reserved
D3
D2
D1
D0
SYSLEV[3] SYSLEV[2] SYSLEV[1] SYSLEV[0]
0
1
SCRATCH SCRATCH
1
1
Reserved
SCRATCH
DEFAULT
0
0
0
0
0
0
0
0
NAME
Reserved
Reserved
VSET1[5]
VSET1[4]
VSET1[3]
VSET1[2]
VSET1[1]
VSET1[0]
DEFAULT
0
0
1
0
0
1
0
0
VSET2[0]
NAME
Reserved
Reserved
VSET2[5]
VSET2[4]
VSET2[3]
VSET2[2]
VSET2[1]
DEFAULT
0
0
1
0
0
1
0
0
NAME
ON
PHASE
MODE
DELAY[2]
DELAY[1]
DELAY[0]
nFLTMSK
OK
DEFAULT
0
0
1
0
0
1
0
R
NAME
Reserved
Reserved
VSET1[5]
VSET1[4]
VSET1[3]
VSET1[2]
VSET1[1]
VSET1[0]
DEFAULT
0
0
0
1
1
0
0
0
NAME
Reserved
Reserved
VSET2[5]
VSET2[4]
VSET2[3]
VSET2[2]
VSET2[1]
VSET2[0]
DEFAULT
0
0
0
1
0
0
0
0
OK
NAME
ON
PHASE
MODE
DELAY[2]
DELAY[1]
DELAY[0]
nFLTMSK
DEFAULT
0
0
1
0
1
0
0
R
NAME
Reserved
Reserved
VSET1[5]
VSET1[4]
VSET1[3]
VSET1[2]
VSET1[1]
VSET1[0]
DEFAULT
0
0
1
1
1
0
0
1
NAME
Reserved
Reserved
VSET2[5]
VSET2[4]
VSET2[3]
VSET2[2]
VSET2[1]
VSET2[0]
DEFAULT
0
0
1
1
1
0
0
1
NAME
ON
PWRSTAT
MODE
DELAY[2]
DELAY[1]
DELAY[0]
nFLTMSK
OK
DEFAULT
0
0
1
0
0
0
0
R
VSET[0]
NAME
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
DEFAULT
0
0
1
1
0
0
0
1
NAME
ON
DIS
LOWIQ
DELAY[2]
DELAY[1]
DELAY[0]
nFLTMSK
OK
DEFAULT
0
1
0
0
1
1
0
R
NAME
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
DEFAULT
0
0
1
1
1
0
0
1
NAME
ON
DIS
LOWIQ
DELAY[2]
DELAY[1]
DELAY[0]
nFLTMSK
OK
DEFAULT
0
1
0
0
0
0
0
R
VSET[0]
NAME
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
DEFAULT
0
0
0
0
0
0
0
0
NAME
ON
DIS
LOWIQ
DELAY[2]
DELAY[1]
DELAY[0]
nFLTMSK
OK
DEFAULT
0
1
0
0
0
0
0
R
NAME
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
DEFAULT
0
0
0
0
0
0
0
0
NAME
ON
DIS
LOWIQ
DELAY[2]
DELAY[1]
DELAY[0]
nFLTMSK
OK
DEFAULT
0
1
0
0
0
0
0
R
: Default values of ACT8865QI305-T.
: All bits are automatically cleared to default values when the input power is removed or falls below the system UVLO.
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ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
Copyright © 2016 Active-Semi, Inc.
ACT8865
Rev 7, 22-Mar-16
REGISTER AND BIT DESCRIPTIONS
Table 1:
Global Register Map
OUTPUT ADDRESS BIT
SYS
0x00
[7]
NAME
ACCESS
TRST
R/W
Reset Timer Setting. Defines the reset timeout threshold. See
nRSTO Output section for more information.
R/W
SYSLEV Mode Select. Defines the response to the SYSLEV
voltage detector, 1: Generate an interrupt when VVDDREF falls
below the programmed SYSLEV threshold, 0: automatic
shutdown when VVDDREF falls below the programmed SYSLEV
threshold.
R/W
System Voltage Level Interrupt Mask. Disabled interrupt by
default, set to 1 to enable this interrupt. See the Programmable
System Voltage Monitor section for more information
nSYSMODE
DESCRIPTION
SYS
0x00
[6]
SYS
0x00
[5] nSYSLEVMSK
SYS
0x00
[4]
nSYSSTAT
R
SYS
0x00
[3:0]
SYSLEV
R/W
SYS
0x01
[7:6]
-
R
SYS
0x01
[5]
MSTROFF
R/W
SYS
0x01
[4]
-
R
SYS
0x01
[3:1]
SCRATCH
R/W
Scratchpad Bits. Non-functional bits, maybe be used by user to
store system status information. Volatile bits, which are cleared
upon system shutdown.
SYS
0x01
[0]
SCRATCH
R/W
Scratchpad Bits. Non-functional bits, maybe be used by user to
store system status information. Volatile bits, which are cleared
upon system shutdown.
REG1
0x20
[7:6]
-
R
REG1
0x20
[5:0]
VSET1
R/W
REG1
0x21
[7:6]
-
R
REG1
0x21
[5:0]
VSET2
R/W
Secondary Output Voltage Selection. Valid when VSEL is driven
high. See the Output Voltage Programming section for more
information.
REG1
0x22
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit
to 0 to disable the regulator.
REG1
0x22
[6]
PHASE
R/W
Regulator Phase Control. Set bit to 1 for regulator to operate
180° out of phase with the oscillator, clear bit to 0 for regulator to
operate in phase with the oscillator.
REG1
0x22
[5]
MODE
R/W
Regulator Mode Select. Set bit to 1 for fixed-frequency PWM
under all load conditions, clear bit to 0 to transit to power-savings
mode under light-load conditions.
REG1
0x22
[4:2]
DELAY
R/W
Regulator Turn-On Delay Control. See the REG1, REG2, REG3
Turn-on Delay section for more information.
REG1
0x22
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable to faultinterrupts, clear bit to 0 to disable fault-interrupts.
System Voltage Status. Value is 1 when VVDDREF is lower than the
SYSLEV voltage threshold, value is 0 when VVDDREF is higher
than the system voltage detection threshold.
System Voltage Detect Threshold. Defines the SYSLEV voltage
threshold. See the Programmable System Voltage Monitor
section for more information.
Reserved.
Master Off Control. Set bit to 1 to turn off all regulators. The bit
will be automatically cleared to 0 when nPBIN is asserted.
Reserved.
Reserved.
Primary Output Voltage Selection. Valid when VSEL is driven low.
See the Output Voltage Programming section for more
information.
Reserved.
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Copyright © 2016 Active-Semi, Inc.
ACT8865
Rev 7, 22-Mar-16
REGISTER AND BIT DESCRIPTIONS CONT’D
OUTPUT
ADDRESS
BIT
NAME
ACCESS
REG1
0x22
[0]
OK
R/W
REG2
0x30
[7:6]
-
R
REG2
0x30
[5:0]
VSET1
R/W
REG2
0x31
[7:6]
-
R
DESCRIPTION
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
Reserved.
Primary Output Voltage Selection. Valid when VSEL is driven
low. See the Output Voltage Programming section for more
information.
Reserved.
REG2
0x31
[5:0]
VSET2
R/W
Secondary Output Voltage Selection. Valid when VSEL is
driven high. See the Output Voltage Programming section for
more information.
REG2
0x32
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG2
0x32
[6]
PHASE
R/W
Regulator Phase Control. Set bit to 1 for regulator to operate
180° out of phase with the oscillator, clear bit to 0 for regulator
to operate in phase with the oscillator.
REG2
0x32
[5]
MODE
R/W
Regulator Mode Select. Set bit to 1 for fixed-frequency PWM
under all load conditions, clear bit to 0 to transit to powersavings mode under light-load conditions.
REG2
0x32
[4:2]
DELAY
R/W
Regulator Turn-On Delay Control. See the REG1, REG2,
REG3 Turn-on Delay section for more information.
REG2
0x32
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable to faultinterrupts, clear bit to 0 to disable fault-interrupts.
REG2
0x32
[0]
OK
R/W
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG3
0x40
[7:6]
-
R
REG3
0x40
[5:0]
VSET1
R/W
REG3
0x41
[7:6]
-
R
Reserved.
Primary Output Voltage Selection. Valid when VSEL is driven
low. See the Output Voltage Programming section for more
information.
Reserved.
REG3
0x41
[5:0]
VSET2
R/W
Secondary Output Voltage Selection. Valid when VSEL is
driven high. See the Output Voltage Programming section for
more information.
REG3
0x42
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG3
0x42
[6]
PWRSTAT
R/W
Configures regulator behavior with respect to the nPBIN input.
Set bit to 0 to enable regulator when nPBIN is asserted.
REG3
0x42
[5]
MODE
R/W
Regulator Mode Select. Set bit to 1 for fixed-frequency PWM
under all load conditions, clear bit to 0 to transition to powersavings mode under light-load conditions.
REG3
0x42
[4:2]
DELAY
R/W
Regulator Turn-On Delay Control. See the REG1, REG2,
REG3 Turn-on Delay section for more information.
REG3
0x42
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable to faultinterrupts, clear bit to 0 to disable fault-interrupts.
REG3
0x42
[0]
OK
R/W
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG4
0x50
[7:6]
-
R
Reserved.
REG4
0x50
[5:0]
VSET
R/W
Output Voltage Selection. See the Output Voltage
Programming section for more information.
REG4
0x51
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
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I2CTM is a trademark of NXP.
Copyright © 2016 Active-Semi, Inc.
ACT8865
Rev 7, 22-Mar-16
REGISTER AND BIT DESCRIPTIONS CONT’D
OUTPUT
ADDRESS
BIT
NAME
ACCESS
DESCRIPTION
REG4
0x51
[6]
DIS
R/W
Output Discharge Control. When activated, discharges LDO
output to GA through 1.5kΩ when in shutdown. Set bit to 1 to
enable output voltage discharge in shutdown, clear bit to 0 to
disable this function.
REG4
0x51
[5]
LOWIQ
R/W
LDO Low-IQ Mode Control. Set bit to 1 for low-power
operating mode, clear bit to 0 for normal mode.
REG4
0x51
[4:2]
DELAY
R/W
Regulator Turn-On Delay Control. See the REG4, REG5,
REG6, REG7 Turn-on Delay section for more information.
REG4
0x51
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable to faultinterrupts, clear bit to 0 to disable fault-interrupts.
REG4
0x51
[0]
OK
R/W
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG5
0x54
[7:6]
-
R
REG5
0x54
[5:0]
VSET
R/W
Output Voltage Selection. See the Output Voltage
Programming section for more information.
REG5
0x55
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
Reserved.
REG5
0x55
[6]
DIS
R/W
Output Discharge Control. When activated, discharges LDO
output to GA through 1.5kΩ when in shutdown. Set bit to 1 to
enable output voltage discharge in shutdown, clear bit to 0 to
disable this function.
REG5
0x55
[5]
LOWIQ
R/W
LDO Low-IQ Mode Control. Set bit to 1 for low-power
operating mode, clear bit to 0 for normal mode.
REG5
0x55
[4:2]
DELAY
R/W
Regulator Turn-On Delay Control. See the REG4, REG5,
REG6, REG7 Turn-on Delay section for more information.
REG5
0x55
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable to faultinterrupts, clear bit to 0 to disable fault-interrupts.
REG5
0x55
[0]
OK
R/W
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG6
0x60
[7:6]
-
R
REG6
0x60
[5:0]
VSET
R/W
Output Voltage Selection. See the Output Voltage
Programming section for more information.
REG6
0x61
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
Reserved.
REG6
0x61
[6]
DIS
R/W
Output Discharge Control. When activated, discharges LDO
output to GA through 1.5kΩ when in shutdown. Set bit to 1 to
enable output voltage discharge in shutdown, clear bit to 0 to
disable this function.
REG6
0x61
[5]
LOWIQ
R/W
LDO Low-IQ Mode Control. Set bit to 1 for low-power
operating mode, clear bit to 0 for normal mode.
REG6
0x61
[4:2]
DELAY
R/W
Regulator Turn-On Delay Control. See the REG4, REG5,
REG6, REG7 Turn-on Delay section for more information.
REG6
0x61
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable to faultinterrupts, clear bit to 0 to disable fault-interrupts.
REG6
0x61
[0]
OK
R/W
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG7
0x64
[7:6]
-
R
Reserved.
REG7
0x64
[5:0]
VSET
R/W
Output Voltage Selection. See the Output Voltage
Programming section for more information.
REG7
0x65
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
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I2CTM is a trademark of NXP.
Copyright © 2016 Active-Semi, Inc.
ACT8865
Rev 7, 22-Mar-16
REGISTER AND BIT DESCRIPTIONS CONT’D
OUTPUT
ADDRESS
BIT
NAME
ACCESS
DESCRIPTION
REG7
0x65
[6]
DIS
R/W
Output Discharge Control. When activated, discharges LDO
output to GA through 1.5kΩ when in shutdown. Set bit to 1 to
enable output voltage discharge in shutdown, clear bit to 0 to
disable this function.
REG7
0x65
[5]
LOWIQ
R/W
LDO Low-IQ Mode Control. Set bit to 1 for low-power
operating mode, clear bit to 0 for normal mode.
REG7
0x65
[4:2]
DELAY
R/W
Regulator Turn-On Delay Control. See the REG4, REG5,
REG6, REG7 Turn-on Delay section for more information.
REG7
0x65
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable to faultinterrupts, clear bit to 0 to disable fault-interrupts.
REG7
0x65
[0]
OK
R/W
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
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ACT8865
Rev 7, 22-Mar-16
SYSTEM CONTROL ELECTRICAL CHARACTERISTICS
(VVP1 = VVP2 = VVP3 = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
Input Voltage Range
MIN
2.7
UVLO Threshold Voltage
VVDDREF Rising
UVLO Hysteresis
VVDDREF Falling
2.2
Supply Current
Shutdown Supply Current
2.45
UNIT
5.5
V
2.65
V
mV
13.85
mA
REG1, REG2, REG3, REG4, REG5,
REG6 and REG7 Enabled. (PWM Mode)
14
REG1, REG2, REG3, REG4, REG5,
REG6 and REG7 Enabled. (PFM Mode,
VIN = 3.6V)
420
All Regulators Disabled
1.5
3.0
µA
2
2.2
MHz
Oscillator Frequency
1.8
µA
1.4
V
Logic Low Input Voltage
Leakage Current
VnIRQ = VnRSTO = 4.2V
Low Level Output Voltage
ISINK = 5mA
nRSTO Delay
Thermal Shutdown Temperature
MAX
200
REG1, REG2, REG3 Enabled. REG4
REG5, REG6 and REG7 Disabled.
Logic High Input Voltage
TYP
Temperature rising
Thermal Shutdown Hysteresis
0.4
V
1
µA
0.35
V
64
ms
160
°C
20
°C
: PWRHLD, PWREN, VSEL are logic inputs.
: nPBSTAT, nIRQ, nRSTO are open drain outputs.
: Typical value shown. Actual value may vary from 56.3ms to 72.8ms.
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I2CTM is a trademark of NXP.
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ACT8865
Rev 7, 22-Mar-16
STEP-DOWN DC/DC ELECTRICAL CHARACTERISTICS
(VVP1 = VVP2 = VVP3 = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
CONDITIONS
Operating Voltage Range
MIN
TYP
2.7
UVLO Threshold
Input Voltage Rising
UVLO Hysteresis
Input Voltage Falling
100
Regulator Enabled (PWM Mode)
4.5
Regulator Enabled (PFM Mode)
65
VVP = 5.5V, Regulator Disabled
0
Quiescent Supply Current
Shutdown Current
Output Voltage Accuracy
2.5
VOUT ≥ 1.2V, IOUT = 10mA
VOUT < 1.2V, IOUT = 10mA
Line Regulation
VVP = Max(VNOM +1, 3.2V) to 5.5V
Load Regulation
IOUT = 10mA to IMAX
Power Good Threshold
VOUT Rising
Power Good Hysteresis
VOUT Falling
Oscillator Frequency
-1%
-2%
VOUT ≥ 20% of VNOM
2.6
MAX
UNIT
5.5
V
2.7
V
7.0
mA
mV
µA
1
VNOM
1%
VNOM
2%
V
0.15
%/V
0.0017
%/mA
93
%VNOM
2
1.8
VOUT = 0V
µA
2
%VNOM
2.2
MHz
500
kHz
Soft-Start Period
400
µs
Minimum On-Time
75
ns
REG1
Maximum Output Current
1.15
Current Limit
1.5
A
1.8
2.1
A
PMOS On-Resistance
ISW1 = -100mA
0.16
Ω
NMOS On-Resistance
ISW1 = 100mA
0.16
Ω
SW1 Leakage Current
VVP1 = 5.5V, VSW1 = 0 or 5.5V
1
µA
REG2
Maximum Output Current
1.15
Current Limit
1.5
A
1.8
2.1
A
PMOS On-Resistance
ISW2 = -100mA
0.16
Ω
NMOS On-Resistance
ISW2 = 100mA
0.16
Ω
SW2 Leakage Current
VVP2 = 5.5V, VSW2 = 0 or 5.5V
1
µA
2.5
A
REG3
Maximum Output Current
1.30
Current Limit
1.7
A
2.1
PMOS On-Resistance
ISW3 = -100mA
0.16
Ω
NMOS On-Resistance
ISW3 = 100mA
0.16
Ω
SW3 Leakage Current
VVP3 = 5.5V, VSW3 = 0 or 5.5V
0
1
µA
: VNOM refers to the nominal output voltage level for VOUT as defined by the Ordering Information section.
: IMAX Maximum Output Current.
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ACT8865
Rev 7, 22-Mar-16
LOW-NOISE LDO ELECTRICAL CHARACTERISTICS
(VINL = 3.6V, COUT4 = COUT5 = 1.5µF, COUT6 = COUT7 = 3.3µF, LOWIQ[ ] = [0], TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
Operating Voltage Range
Output Voltage Accuracy
MIN
TYP
MAX
UNIT
5.5
V
2.5
VOUT ≥ 1.2V, TA = 25°C, IOUT = 10mA
-1%
VNOM
2%
VOUT < 1.2V, TA = 25°C, IOUT = 10mA
-2%
VNOM
4%
VINL = Max (VOUT + 0.5V, 3.6V) to 5.5V
0.05
Line Regulation
VINL = Max (VOUT + 0.5V, 3.6V) to 5.5V
LOWIQ[ ] = [1]
0.5
Load Regulation
IOUT = 1mA to IMAX
0.08
Power Supply Rejection Ratio
Supply Current per Output
mV/V
V/A
f = 1kHz, IOUT = 20mA, VOUT =1.2V
75
f = 10kHz, IOUT = 20mA, VOUT =1.2V
65
Regulator Enabled, LOWIQ[ ] = [0]
37
60
Regulator Enabled, LOWIQ[ ] = [1]
31
52
0
1
Regulator Disabled
Soft-Start Period
V
dB
µA
VOUT = 2.9V
140
µs
Power Good Threshold
VOUT Rising
89
%
Power Good Hysteresis
VOUT Falling
3
%
Output Noise
IOUT = 20mA, f = 10Hz to 100kHz, VOUT =
1.2V
50
µVRMS
Discharge Resistance
LDO Disabled, DIS[ ] = 1
1.5
kΩ
REG4
Dropout Voltage
IOUT = 160mA, VOUT > 3.1V
Maximum Output Current
Current Limit
90
180
320
VOUT = 95% of regulation voltage
Stable COUT4 Range
mV
mA
400
mA
3.3
20
µF
280
mV
REG5
Dropout Voltage
IOUT = 160mA, VOUT > 3.1V
Maximum Output Current
Current Limit
VOUT = 95% of regulation voltage
Stable COUT5 Range
140
320
mA
400
mA
3.3
20
µF
180
mV
REG6
Dropout Voltage
IOUT = 160mA, VOUT > 3.1V
Maximum Output Current
Current Limit
90
320
VOUT = 95% of regulation voltage
Stable COUT6 Range
mA
400
mA
3.3
20
µF
280
mV
REG7
Dropout Voltage
IOUT = 160mA, VOUT > 3.1V
Maximum Output Current
Current Limit
Stable COUT7 Range
VOUT = 95% of regulation voltage
140
320
mA
400
mA
3.3
20
µF
: VNOM refers to the nominal output voltage level for VOUT as defined by the Ordering Information section.
: IMAX Maximum Output Current.
: Dropout Voltage is defined as the differential voltage between input and output when the output voltage drops 100mV below the
regulation voltage (for 3.1V output voltage or higher)
: LDO current limit is defined as the output current at which the output voltage drops to 95% of the respective regulation voltage.
Under heavy overload conditions the output current limit folds back by 30% (typ)
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Copyright © 2016 Active-Semi, Inc.
ACT8865
Rev 7, 22-Mar-16
TYPICAL PERFORMANCE CHARACTERISTICS
(VVP1 = VVP2 = VVP3 = 3.6V, TA = 25°C, unless otherwise specified.)
Frequency vs. Temperature
VREF vs. Temperature
0
-0.42
-20
0
20
40
60
80
100
1.5
1
0.5
0
-0.5
Typical VREF=1.2V
-0.84
-40
2
Frequency (%)
VREF (%)
0.42
2.5
ACT8865-002
ACT8865-001
0.84
Typical Oscillator Frequency=2MHz
-1
-40
120
-20
0
20
40
60
Temperature (°C)
Temperature (°C)
nPBIN Startup Sequence
PWRHLD Startup Sequence
ACT8865-004
ACT8865-003
CH1
CH1
CH2
CH2
CH3
CH3
CH4
CH4
CH5
CH5
80 85
CH6
CH6
CH1: VnPBIN, 2V/div
CH2: VOUT5, 2V/div
CH3: VOUT3, 2V/div
CH4: VOUT1, 1V/div
CH5: VOUT2, 1V/div
CH6: VOUT4, 2V/div
TIME: 1ms/div
CH1: VPWRHLD, 2V/div
CH2: VOUT5, 2V/div
CH3: VOUT3, 2V/div
CH4: VOUT1, 1V/div
CH5: VOUT2, 1V/div
CH6: VOUT4, 2V/div
TIME: 1ms/div
PWREN Startup Sequence
ACT8865-005
CH1
CH2
CH3
CH1: VPWREN, 2V/div
CH2: VOUT6, 500mV/div
CH3: VOUT7, 500mV/div
TIME: 4ms/div
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I2CTM is a trademark of NXP.
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ACT8865
Rev 7, 22-Mar-16
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(TA = 25°C, unless otherwise specified.)
Push-Button Response (First Power-Up)
Manual Reset Response
ACT8865-007
ACT8865-006
CH1
CH1
CH2
CH3
CH2
CH3
CH1: VnPBIN, 2V/div
CH2: VnPBSTAT, 2V/div
CH3: VnRSTO, 2V/div
TIME: 20ms/div
CH1: VnPBIN, 2V/div
CH2: VnPBSTAT, 2V/div
CH3:VnRSTO , 2V/div
TIME: 30ms/div
nPBIN Resistor = 50kΩ
REG2 Efficiency vs. Output Current
REG1 Efficiency vs. Output Current
Efficiency (%)
80
VIN = 3.6V
80
VIN = 5.0V
VIN = 4.2V
60
VOUT = 1.2V
Efficiency (%)
VIN = 3.6V
ACT8865-009
VOUT = 1.8V
100
ACT8865-008
100
nPBIN Resistor = 0Ω
40
20
VIN = 5.0V
VIN = 4.2V
60
40
20
0
0
1
10
100
1000
1
10
Output Current (mA)
100
1000
Output Current (mA)
REG3 Efficiency vs. Output Current
100
Efficiency (%)
80
VIN = 4.2V
VIN = 3.6V
ACT8865-010
VOUT = 3.3V
VIN=5.0V
60
40
20
0
1
10
100
1000
Output Current (mA)
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Copyright © 2016 Active-Semi, Inc.
ACT8865
Rev 7, 22-Mar-16
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(TA = 25°C, unless otherwise specified.)
REG2 Output Voltage vs. Temperature
REG1 Output Voltage vs. Temperature
Output Voltage (V)
1.809
1.803
1.797
1.791
1.785
-40
-20
0
20
40
60
80
100
3.310
VOUT2 = 3.3V
ILOAD = 100mA
3.306
Output Voltage (V)
VOUT3 = 1.8V
ILOAD = 100mA
3.302
3.298
3.294
3.290
-40
120
-20
0
20
40
60
80
100
120
Temperature (°C)
Temperature (°C)
REG1, 2, 3 MOSFET Resistance
REG3 Output Voltage vs. Temperature
1.202
1.198
ILOAD = 100mA
300
250
RDSON (mΩ)
1.206
ACT8865-014
350
ACT8865-013
1.210 V
OUT1 = 1.2V
ILOAD = 100mA
Output Voltage (V)
ACT8865-012
ACT8865-011
1.815
200
PMOS
NMOS
150
100
1.194
1.190
-40
50
0
-20
0
20
40
60
Temperature (°C)
80
100
120
3.0
3.5
4.0
4.5
5.0
5.5
Input Voltage (V)
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ACT8865
Rev 7, 22-Mar-16
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(TA = 25°C, unless otherwise specified.)
REG4, 5, 6, 7 Output Voltage vs. Output Current
VOUT > 1.2V
0%
-2%
VOUT ≤ 1.2V
-4%
200
Dropout Voltage (mV)
Error Percent (%)
2%
REG4, 6 Dropout Voltage vs. Output Current
ACT8865-016
ACT8865-015
4%
-6%
150
100
50
0
0
50
100
150
200
250
300
350
0
400
50
100
250
300
350
REG4, 5, 6, 7 Output Voltage vs. Temperature
REG5, 7 Dropout Voltage vs. Output Current
200
150
100
Error Percent (%)
250
4%
2%
ACT8865-018
ACT8865-017
300
Dropout Voltage (mV)
200
Output Current (mA)
Output Current (mA)
VOUT ≤ 1.2V
0%
VOUT > 1.2V
-2%
50
-4%
0
0
50
100
150
200
250
300
350
-40
-20
0
20
40
60
Output Current (mA)
Temperature (°C)
Region of Stable COUT ESR vs. Output Current
LDO Output Voltage Noise
80
ACT8865-020
ACT8865-019
1
ESR (Ω)
150
CH1
0.1
Stable ESR
0.01
0
50
100
150
Output Current (mA)
200
250
CH1: VOUTx, 200µV/div (AC COUPLED)
TIME: 200ms/div
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I2CTM is a trademark of NXP.
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ACT8865
Rev 7, 22-Mar-16
SYSTEM CONTROL INFORMATION
Interfacing with the Atmel SAMA5D2, SAMA5D3 Series & SAM9 Series Processors
The ACT8865 is optimized for use in applications
using the following Atmel platforms: SAMA5D2,
SAMA5D3 series and SAM9 series processors,
supporting the power domains as shown in the
Table 2:
ACT8865 and Atmel SAMA5D2, SAMA5D3 Series & SAM9 Series Power Domains
:
POWER DOMAIN
ACT8865 CHANNEL
TYPE
DEFAULT VOLTAGE CURRENT CAPABILITY
VDDIODDR/VDDCORE_LPDDR
REG1
DC/DC 1.8V / 1.5V / 1.35V
1100mA
VDDCORE_GBIT ENET,
VDDIO_LPDDR
REG2
DC/DC
1.2V
1100mA
VDDIOP, VDDOSC, VDDUTMII,
VDDIOM,10/100 ENET
REG3
DC/DC
3.3V
1200mA
VDDFUSE
REG4
LDO
2.5V
320mA
VDDANA
REG5
LDO
3.3V
320mA
Auxiliary 1
REG6
LDO
0.6V
320mA
Auxiliary 2
REG7
LDO
0.6V
320mA
VOUT2 = 1.2V @ VSEL=0 (SAMA5 series) and VOUT2 = 1.0V @ VSEL=VIN (SAM9 series)
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I2CTM is a trademark of NXP.
Copyright © 2016 Active-Semi, Inc.
ACT8865
Rev 7, 22-Mar-16
SYSTEM CONTROL INFORMATION
nRSTO Output
Control Signals
Enable Inputs
The ACT8865 features a variety of control inputs,
which are used to enable and disable outputs
depending upon the desired mode of operation.
PWREN, PWRHLD are logic inputs, while nPBIN is
a unique, multi-function input. Refer to the
Processor Specification for a description of which
channels are controlled by each input.
nPBIN Multi-Function Input
ACT8865 features the nPBIN multi-function pin,
which combines system enable/disable control with
a hardware reset function. Select either of the two
pin functions by asserting this pin, either through a
direct connection to GA, or through a 50kΩ resistor
to GA, as shown in Figure 2.
Figure 2:
nPBIN Input
nRSTO is an open-drain output which asserts low
upon startup or when manual reset is asserted via
the nPBIN input. When asserted on startup, nRSTO
remains low until reset time-out period expires after
OUT3 reaches its power-OK threshold. When
asserted due to manual-reset, nRSTO immediately
asserts low, then remains asserted low until the
nPBIN input is de-asserted and the reset time-out
period expires.
Connect a 10kΩ or greater pull-up resistor from
nRSTO to an appropriate voltage supply (typically
OUT3).
nIRQ Output
nIRQ is an open-drain output that asserts low any
time an interrupt is generated. Connect a 10kΩ or
greater pull-up resistor from nIRQ to an appropriate
voltage supply. nIRQ is typically used to drive the
interrupt input of the system processor.
Many of the ACT8865's functions support interruptgeneration as a result of various conditions. These
are typically masked by default, but may be
unmasked via the I2C interface. For more
information about the available fault conditions,
refer to the appropriate sections of this datasheet.
Manual Reset Function
The second major function of the nPBIN input is to
provide a manual-reset input for the processor. To
manually-reset the processor, drive nPBIN directly
to GA through a low impedance (less than 2.5kΩ).
When this occurs, nRSTO immediately asserts low,
then remains asserted low until the nPBIN input is
de-asserted and the reset time-out period expires.
nPBSTAT Output
nPBSTAT is an open-drain output that reflects the
state of the nPBIN input; nPBSTAT is asserted low
whenever nPBIN is asserted, and is high-Z
otherwise. This output is typically used as an
interrupt signal to the processor, to initiate a
software-programmable routine such as operating
mode selection or to open a menu. Connect
nPBSTAT to an appropriate supply voltage
(typically OUT3) through a 10kΩ or greater resistor.
Note that under some conditions a false interrupt
may be generated upon initial startup. For this
reason, it is recommended that the interrupt service
routine check and validate nSYSLEVMSK[-] and
nFLTMSK[-] bits before processing an interrupt
generated by these bits. These interrupts may be
validated by nSYSSTAT[-], OK[-] bits.
Push-Button Control
The ACT8865 is designed to initiate a system
enable sequence when the nPBIN multi-function
input is asserted. Once this occurs, a power-on
sequence commences, as described below. The
power-on sequence must complete and the
microprocessor must take control (by asserting
PWREN or PWRHLD) before nPBIN is de-asserted.
If the microprocessor is unable to complete its
power-up routine successfully before the user
releases the push-button, the ACT8865
automatically shuts the system down. This provides
protection against accidental or momentary
assertions of the push-button. If desired, longer
“push-and-hold” times can be implemented by
simply adding an additional time delay before
asserting PWREN or PWRHLD.
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ACT8865
Rev 7, 22-Mar-16
Control Sequences
The ACT8865 features a variety of control
sequences that are optimized for supporting system
enable and disable sequences of Atmel SAMA5D2,
SAMA5D3 Series: SAMA5D[31/33/34/35/36] and
SAM9 series: SAM9G[15/25/35/45/46], SAM9X
[25/35], SAM9M[10/11], SAM9N[11/12] application
processor.
Enabling/Disabling Sequence
A typical enable sequence is initiated whenever
nPBIN is asserted low via 50KΩ resistance. The
enable sequence begins by enabling REG3/REG5.
When REG3/REG5 reaches its power-OK
threshold, nRSTO is asserted low, resetting the
microprocessor. When REG3/REG5 reaches its
power-OK threshold for 2ms, REG1 is enabled.
When REG3/REG5 reaches its power-OK threshold
for 4ms, REG2 is enabled. When REG3/REG5
reaches its power-OK threshold for 8ms, REG4 is
enabled. When REG3 is above its power-OK
threshold when the reset timer expires, nRSTO is
de-asserted, allowing the microprocessor to begin
its boot sequence. REG6 and REG7 can be
enabled or disabled by PWREN after system
powers up.
During the boot sequence, the microprocessor must
assert PWRHLD, holding the regulators to ensure
that the system remains powered after nPBIN is
released.
As with the enable sequence, a typical disable
sequence is initiated when the user presses the
push-button, which interrupts the processor via the
nPBSTAT output. The actual disable sequence is
completely software-controlled, but typically
involved initiating various “clean-up” processes
before finally set MSTROFF[] bit to 1 to shut the
system down.
Figure 3:
Enable/Disable Sequence for ACT8865QI305-T and ACT8865QI405-T.
: Typical value shown,
actual delay time may vary from (T-1ms) x 88% to T x 112%, where T is the typical delay time setting.
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ACT8865
Rev 7, 22-Mar-16
FUNCTIONAL DESCRIPTION
I2C Interface
below the SYSLEV[-] voltage threshold:
2
The ACT8865 features an I C interface that allows
advanced programming capability to enhance overall
system performance. To ensure compatibility with a
wide range of system processors, the I2C interface
supports clock speeds of up to 400kHz (“Fast-Mode”
operation) and uses standard I2C commands. I2C
write-byte commands are used to program the
ACT8865, and I2C read-byte commands are used to
read the ACT8865’s internal registers. The ACT8865
always operates as a slave device, and is addressed
using a 7-bit slave address followed by an eighth bit,
which indicates whether the transaction is a readoperation or a write-operation, [1011011x].
SDA is a bi-directional data line and SCL is a clock
input. The master device initiates a transaction by
issuing a START condition, defined by SDA
transitioning from high to low while SCL is high. Data
is transferred in 8-bit packets, beginning with the
MSB, and is clocked-in on the rising edge of SCL.
Each packet of data is followed by an “Acknowledge”
(ACK) bit, used to confirm that the data was
transmitted successfully.
For more information regarding the I2C 2-wire serial
interface, go to the NXP website: http://www.nxp.com.
Voltage Monitor and Interrupt
Programmable System Voltage Monitor
The ACT8865 features a programmable systemvoltage monitor, which monitors the voltage at
VDDREF and compares it to a programmable
threshold voltage. The programmable voltage
threshold is programmed by SYSLEV[3:0], as shown
in Table 3.
SYSLEV[ ] is set to 3.0V by default. There is a
200mV rising hysteresis on SYSLEV[ ] threshold
such that VVDDREF needs to be 3.2V(typ) or higher in
order to power up the IC.
The nSYSSTAT[-] bit reflects the output of an
internal voltage comparator that monitors VDDREF
relative to the SYSLEV[-] voltage threshold, the
value of nSYSTAT[-] = 1 when VVDDREF is lower than
the SYSLEV[-] voltage threshold, and nSYSTAT[-] =
0 when VVDDREF is higher than the SYSLEV[-]
voltage threshold. Note that the SYSLEV[-] voltage
threshold is defined for falling voltages, and that the
comparator produces about 200mV of hysteresis at
VDDREF. As a result, once VVDDREF falls below the
SYSLEV threshold, its voltage must increase by
more than about 200mV to clear that condition.
After the IC is powered up, the ACT8865 responds in
one of two ways when the voltage at VDDREF falls
1) If nSYSMODE[-] = 1 (default case), when system
vo l ta g e
l e ve l
i n te r r u p t
is
unmasked
(nSYSLEVMSK[ ]=1) and VVDDREF falls below the
programmable threshold, the ACT8865 asserts
nIRQ, providing a software “under-voltage alarm”.
The response to this interrupt is controlled by the
CPU, but will typically initiate a controlled shutdown
sequence either or alert the user that the battery is
low. In this case the interrupt is cleared when
VVDDREF rises up again above the SYSLEV rising
threshold and nSYSSTAT[-] is read via I2C.
2) If nSYSMODE[-] = 0, when VVDDREF falls below the
programmable threshold the ACT8865 shuts down,
immediately disabling all regulators. This option is
useful for implementing a programmable “undervoltage lockout” function that forces the system off
when the battery voltage falls below the SYSLEV
threshold voltage. Since this option does not support
a controlled shutdown sequence, it is generally used
as a "fail-safe" to shut the system down when the
battery voltage is too low.
Table 3:
SYSLEV Falling Threshold
SYSLEV[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
SYSLEV Falling Threshold
(Hysteresis = 200mV)
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
Thermal Shutdown
The ACT8865 integrates thermal shutdown
protection circuitry to prevent damage resulting from
excessive thermal stress, as may be encountered
under fault conditions. This circuitry disables all
regulators if the ACT8865 die temperature exceeds
160°C, and prevents the regulators from being
enabled until the IC temperature drops by 20°C (typ).
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ACT8865
Rev 7, 22-Mar-16
STEP-DOWN DC/DC REGULATORS
General Description
The ACT8865 features three synchronous, fixedfrequency, current-mode PWM step down converters
that achieve peak efficiencies of up to 97%. REG1
and REG2 are capable of supplying up to 1150mA of
output current, while REG3 supports up to 1300mA.
These regulators operate with a fixed frequency of
2MHz, minimizing noise in sensitive applications and
allowing the use of small external components.
100% Duty Cycle Operation
Each regulator is capable of operating at up to 100%
duty cycle. During 100% duty-cycle operation, the
high-side power MOSFET is held on continuously,
providing a direct connection from the input to the
output (through the inductor), ensuring the lowest
possible dropout voltage in battery powered
applications.
Synchronous Rectification
REG1, REG2, and REG3 each feature integrated nchannel synchronous rectifiers, maximizing efficiency
and minimizing the total solution size and cost by
eliminating the need for external rectifiers.
Soft-Start
When enabled, each output voltages tracks an
internal 400μs soft-start ramp, minimizing input
current during startup and allowing each regulator to
power up in a smooth, monotonic manner that is
independent of output load conditions.
Compensation
Each buck regulator utilizes current-mode control and
a proprietary internal compensation scheme to
simultaneously simplify external component selection
and optimize transient performance over its full
operating range. No compensation design is
required; simply follow a few simple guidelines
described below when choosing external
components.
Input Capacitor Selection
The input capacitor reduces peak currents and noise
induced upon the voltage source. A 4.7μF ceramic
capacitor is recommended for each regulator in most
applications.
Output Capacitor Selection
For most applications, 22μF ceramic output
capacitors are recommended for REG1/REG2/
REG3.
Despite the advantages of ceramic capacitors, care
must be taken during the design process to ensure
stable operation over the full operating voltage and
temperature range. Ceramic capacitors are available
in a variety of dielectrics, each of which exhibits
different characteristics that can greatly affect
performance over their temperature and voltage
ranges.
Two of the most common dielectrics are Y5V and
X5R. Whereas Y5V dielectrics are inexpensive and
can provide high capacitance in small packages, their
capacitance varies greatly over their voltage and
temperature ranges and are not recommended for
DC/DC applications. X5R and X7R dielectrics are
more suitable for output capacitor applications, as
their characteristics are more stable over their
operating ranges, and are highly recommended.
Inductor Selection
REG1, REG2, and REG3 utilize current-mode control
and a proprietary internal compensation scheme to
simultaneously simplify external component selection
and optimize transient performance over their full
operating range. These devices were optimized for
operation with 2.2μH inductors, although inductors in
the 1.5μH to 3.3μH range can be used. Choose an
inductor with a low DC-resistance, and avoid inductor
saturation by choosing inductors with DC ratings that
exceed the maximum output current by at least 30%.
Enable / Disable Control
During normal operation, each buck may be enabled
or disabled via I2C interface by writing to that
regulator's ON[] bit. The regulator accepts rising or
falling edge of ON[] bit as on/off signal. To enable the
regulator, clear ON[] to 0 first then set to 1. To disable
the regulator, set ON[] to 1 first then clear it to 0.
REG1, REG2, REG3 Turn-On Delay
Each of REG1/REG2/REG3 features a
programmable Turn-On Delay which help ensure a
reliable qualification. This delay is programmed by
DELAY[2:0], as shown in Table 5.
Operating Mode
REG1, REG2, and REG3 each operate in fixedfrequency PWM mode at medium to heavy loads
when MODE[ ] bit is set to 0, and transition to a
proprietary power-saving mode at light loads in
order to maximize standby battery life. In
applications where low noise is critical, force fixedfrequency PWM operation across the entire load
current range, at the expense of light-load
efficiency, by setting the MODE[ ] bit to 1.
OK[ ] and Output Fault Interrupt
Each DC/DC features a power-OK status bit that
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can be read by the system microprocessor via the
I2C interface. If an output voltage is lower than the
power-OK threshold, typically 7% below the
programmed regulation voltage, that regulator's
OK[ ] bit will be 0.
If a DC/DC's nFLTMSK[-] bit is set to 1, the
ACT8865 will interrupt the processor if that DC/DC's
output voltage falls below the power-OK threshold.
In this case, nIRQ will assert low and remain
asserted until the OK[ ] bit has been read via I2C.
PCB Layout Considerations
High switching frequencies and large peak currents
make PC board layout an important part of stepdown DC/DC converter design.
close as possible to the IC, and avoiding the use of
via if possible. The inductor, input filter capacitor,
and output filter capacitor should be connected as
close together as possible, with short, direct, and
wide traces. The ground nodes for each regulator's
power loop should be connected at a single point in
a star-ground configuration, and this point should
be connected to the backside ground plane with
multiple via. The output node for each regulator
should be connected to its corresponding OUTx pin
through the shortest possible route, while keeping
sufficient distance from switching nodes to prevent
noise injection. Finally, the exposed pad should be
directly connected to the backside ground plane
using multiple via to achieve low electrical and
thermal resistance.
Step-down DC/DCs exhibit discontinuous input
current, so the input capacitors should be placed as
Table 4:
REGx/VSET[ ] Output Voltage Setting
REGx/VSET[2:0]
REGx/VSET[5:3]
000
001
010
011
100
101
110
111
000
0.600
0.800
1.000
1.200
1.600
2.000
2.400
3.200
001
0.625
0.825
1.025
1.250
1.650
2.050
2.500
3.300
010
0.650
0.850
1.050
1.300
1.700
2.100
2.600
3.400
011
0.675
0.875
1.075
1.350
1.750
2.150
2.700
3.500
100
0.700
0.900
1.100
1.400
1.800
2.200
2.800
3.600
101
0.725
0.925
1.125
1.450
1.850
2.250
2.900
3.700
110
0.750
0.950
1.150
1.500
1.900
2.300
3.000
3.800
111
0.775
0.975
1.175
1.550
1.950
2.350
3.100
3.900
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ACT8865
Rev 7, 22-Mar-16
LOW-NOISE, LOW-DROPOUT LINEAR REGULATORS
General Description
REG4, REG5, REG6 and REG7 are low-noise, lowdropout linear regulators (LDOs) that supply up to
320mA. Each LDO has been optimized to achieve
low noise and high-PSRR, achieving more than
65dB PSRR at frequencies up to 10kHz.
Output Current Limit
Each LDO contains current-limit circuitry featuring a
current-limit fold-back function. During normal and
moderate overload conditions, the regulators can
support more than their rated output currents.
During extreme overload conditions, however, the
current limit is reduced by approximately 30%,
reducing power dissipation within the IC.
Compensation
regulator's ON[] bit. The regulator accepts rising or
falling edge of ON[] bit as on/off signal. To enable the
regulator, clear ON[] to 0 first then set to 1. To disable
the regulator, set ON[] to 1 first then clear it to 0.
REG4, REG5, REG6, REG7 Turn-on Delay
Each of REG4, REG5, REG6 and REG7 features a
programmable Turn-on Delay which help ensure a
reliable qualification. This delay is programmed by
DELAY[2:0], as shown in Table 5.
Table 5:
REGx/DELAY[ ] Turn-On Delay
DELAY[2] DELAY[1] DELAY[0] TURN-ON DELAY
0
0
0
0 ms
0
0
1
2 ms
0
1
0
4 ms
The LDOs are internally compensated and require
very little design effort, simply select input and
output capacitors according to the guidelines below.
0
1
1
8 ms
1
0
0
16 ms
1
0
1
32 ms
Input Capacitor Selection
1
1
0
64 ms
Each LDO requires a small 1μF ceramic output
capacitor for stability. For best performance, each
output capacitor should be connected directly
between the output and GA pins, as close to the
output as possible, and with a short, direct
connection. High quality ceramic capacitors such as
X7R and X5R dielectric types are strongly
recommended.
1
1
1
128 ms
Output Capacitor Selection
Each LDO requires a small 3.3μF ceramic output
capacitor for stability. For best performance, each
output capacitor should be connected directly
between the output and GA pins, as close to the
output as possible, and with a short, direct
connection. High quality ceramic capacitors such as
X7R and X5R dielectric types are strongly
recommended.
Configuration Options
Output Voltage Programming
By default, each LDO powers up and regulates to
its default output voltage. Once the system is
enabled, each output voltage may be independently
programmed to a different value by writing to the
regulator's VSET[-] register via the I2C serial
interface as shown in Table 4.
Enable / Disable Control
During normal operation, each LDO may be enabled
or disabled via I2C interface by writing to that
Output Discharge
Each of the ACT8865’s LDOs features an optional
output discharge function, which discharges the
output to ground through a 1.5kΩ resistance when
the LDO is disabled. This feature may be enabled
or disabled by setting DIS[-] via; set DIS[-] to 1 to
enable this function, clear DIS[-] to 0 to disable it.
Low-Power Mode
Each of ACT8865's LDOs features a LOWIQ[-] bit
which, when set to 1, reduces the LDO's quiescent
current by about 16%, saving power and extending
battery lifetime.
OK[ ] and Output Fault Interrupt
Each LDO features a power-OK status bit that
be read by the system microprocessor via
interface. If an output voltage is lower than
power-OK threshold, typically 11% below
programmed regulation voltage, the value of
regulator's OK[-] bit will be 0.
can
the
the
the
that
If a LDO's nFLTMSK[-] bit is set to 1, the ACT8865
will interrupt the processor if that LDO's output
voltage falls below the power-OK threshold. In this
case, nIRQ will assert low and remain asserted until
the OK[-] bit has been read via I2C.
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ACT8865
Rev 7, 22-Mar-16
PCB Layout Considerations
PCB Layout Considerations The ACT8865’s LDOs
provide good DC, AC, and noise performance over
a wide range of operating conditions, and are
relatively insensitive to layout considerations. When
designing a PCB, however, careful layout is
necessary to prevent other circuitry from degrading
LDO performance.
A good design places input and output capacitors
as close to the LDO inputs and output as possible,
and utilizes a star-ground configuration for all
regulators to prevent noise-coupling through
ground. Output traces should be routed to avoid
close proximity to noisy nodes, particularly the SW
nodes of the DC/DCs.
REFBP is a filtered reference noise, and internally
has a direct connection to the linear regulator
controller. Any noise injected onto REFBP will
directly affect the outputs of the linear regulators,
and therefore special care should be taken to
ensure that no noise is injected to the outputs via
REFBP. As with the LDO output capacitors, the
REFBP bypass capacitor should be placed as close
to the IC as possible, with short, direct connections
to the star-ground. Avoid the use of via whenever
possible. Noisy nodes, such as from the DC/DCs,
should be routed as far away from REFBP as
possible.
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ACT8865
Rev 7, 22-Mar-16
ERRATA INFO
Errata Name: ACT8865 creates I2C BUS
Disable ACT8865QI303 I2C Interface
contention
To disable the I2C interface of ACT8865QI303 and
configure the SDA and SCL pins to input logic pins,
customer can use I2C to write the following
commands in sequence below:
Device Identification: Parts marked
ACT8865QI405, ACT8865QI305 and
ACT8865QI303
Description:
2
The ACT8865 features an I C interface that only
supports standard single-byte I2C command. After it
detects a START condition, it will wait for its correct
device address to issue the Acknowledge (ACK) by
pulling the SDA low. Therefore, if the ACT8865 I2C
bus shares with a multiple-byte I2C device, it would
accidently issue an ACK once its address is detected
and pull SDA low during mass data transmission
between the MCU and the co-slave device. This
action would cause the I2C BUS to be frozen
unexpectedly.
Recommendation:
To avoid the I2C BUS contention, we highly
recommend customer to use ACT8865 I2C
separately from a multiple-byte I2C device such as a
touch screen controller.
1.Write address 0x0B with 0xE9
2.Write address 0x02 with 0x07
3.Write address 0x03 with 0x01
Disable ACT8865QI305 and ACT8865QI405 I2C
Interface
To disable the I2C interface of ACT8865QI305 and
ACT8865QI405 and configure the SDA and SCL
pins to input logic pins, customer can use I2C to
write the following commands in sequence below:
1.Write address 0x0B with 0xEE
2.Write address 0x02 with 0x07
3.Write address 0x03 with 0x01
4.Write address 0x0B with 0xEF
5.Write address 0x02 with 0x07
6.Write address 0x03 with 0x01
However, in case the ACT8865 has to share the
I2C bus with a multiple-byte I2C device, the
ACT8865 features a function to allow customer to
disable its I2C interface to avoid the conflict.
Workaround:
For cases where ACT8865 I2C lines are already
shared with some other components, ACT8865
features a function to allow user to disable its I2C
interface to avoid conflicts. The following I2C write
sequences perform this operation and configure
SDA and SCL as high-Z pin.
: After disable the I2C interface, the ACT8865 will only become accessible by I2C after its power supply is reset.
: Please ensure to ignore any I2C failure report while processing the command sequence.
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ACT8865
Rev 7, 22-Mar-16
TQFN44-32 PACKAGE OUTLINE AND DIMENSIONS
D
D/ 2
SYMBOL
E/ 2
E
A3
MAX
MIN
MAX
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
D2
L
0.150
0.250
0.008
0.006
0.010
4.000 TYP
0.158 TYP
E
4.000 TYP
0.158 TYP
D2
2.500
2.800
0.098
0.110
E2
2.500
2.800
0.098
0.110
L
b
0.200
D
e
A1
DIMENSION IN
INCHES
MIN
b
A
DIMENSION IN
MILLIMETERS
R
0.400 TYP
0.250
0.476
0.250
0.016 TYP
0.010
0.019
0.010
e
E2
R
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ACT8865
Rev 7, 22-Mar-16
REVISION HISTORY
REVISION
DATE
DESCRIPTION
Rev PrB
20 Jun 2013
Initial Release.
Rev 0
18 Jul 2013
Updated Table 2.
Rev 1
01 Aug 2013
Updated general description and typical application diagram.
Rev 2
11 Feb 2014
Added the power consumption information of PFM mode in EC Table.
Rev 3
30 Jun 2014
Updated the Ordering Information, Global Register Map, Power Domain
Form, Enable/Disable sequence description and chart and TPCs.
Rev 4
15 Jul 2014
Disable I2C Interface Section.
Rev 5
10 Jun 2015
Add part number of ACT8865QI405-T and update enable/ disable control
for Buck and LDO.
Rev 6
18 Jun 2016
Add SAMA5D2 supported and update the trade mark
Rev 7
22 Mar 2016
Change Dimension in milLimeters L/D2/E2
Active-Semi, Inc. reserves the right to modify the circuitry or specifications without notice. Users should evaluate each
product to make sure that it is suitable for their applications. Active-Semi products are not intended or authorized for use
as critical components in life-support devices or systems. Active-Semi, Inc. does not assume any liability arising out of
the use of any product or circuit described in this datasheet, nor does it convey any patent license.
Active-Semi and its logo are trademarks of Active-Semi, Inc. For more information on this and other products, contact
sales@active-semi.com or visit http://www.active-semi.com.
is a registered trademark of Active-Semi.
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