UF3C120080B7S

1200V-85mW SiC FET Rev. B, May 2023 DATASHEET Description UF3C120080B7S This SiC FET device is based on a unique ‘cascode’ circuit configuration, in which a normally-on SiC JFET is co-packaged with a Si MOSFET to produce a normally-off SiC FET device. The device’s standard gate-drive characteristics allows for a true “drop-in replacement” to Si IGBTs, Si FETs, SiC MOSFETs or Si superjunction devices. Available in the D2PAK-7L package, this device exhibits ultralow gate charge and exceptional reverse recovery characteristics, making it ideal for switching inductive loads , and any application requiring standard gate drive. D (Tab) Features Tab w On-resistance RDS(on): 85mW (typ) w Operating temperature: 175°C (max) G (1) 1 w Excellent reverse recovery: Qrr = 140nC w Low body diode VFSD: 1.5V 7 w Low gate charge: QG = 23nC KS (2) w Threshold voltage VG(th): 4.8V (typ) allowing 0 to 15V drive S (3-7) w Package creepage and clearance distance > 6.1mm w Kelvin source pin for optimized switching performance w ESD protected, HBM class 2 Part Number Package Marking UF3C120080B7S D2PAK-7L UF3C120080B7S Typical applications Any controlled environment such as w Telecom and Server Power w Industrial power supplies w Power factor correction modules w Motor drives w Induction heating Datasheet: UF3C120080B7S Rev. B, May 2023 1 Maximum Ratings Parameter Symbol VDS VGS Drain-source voltage Gate-source voltage Continuous drain current 1 ID Pulsed drain current 2 Single pulsed avalanche energy 3 Power dissipation Maximum junction temperature Operating and storage temperature IDM EAS Ptot TJ,max TJ, TSTG Tsolder Reflow soldering temperature Test Conditions DC TC = 25°C TC = 100°C TC = 25°C L=15mH, IAS =2.8A TC = 25°C reflow MSL 3 Value Units 1200 -25 to +25 28.8 21 77 58.5 190 175 -55 to 175 V V A A A mJ W °C °C 245 °C 1. Limited by TJ,max 2. Pulse width tp limited by TJ,max 3. Starting TJ = 25°C Thermal Characteristics Parameter Thermal resistance, junction-to-case Datasheet: UF3C120080B7S Symbol Test Conditions RqJC Rev. B, May 2023 Value Min Typ Max 0.61 0.79 Units °C/W 2 Electrical Characteristics (TJ = +25°C unless otherwise specified) Typical Performance - Static Parameter Drain-source breakdown voltage Total drain leakage current Total gate leakage current Drain-source on-resistance Gate threshold voltage Gate resistance Symbol Test Conditions BVDS VGS=0V, ID=1mA IDSS IGSS RDS(on) VG(th) RG Value Min Typ Max 1200 V VDS=1200V, VGS=0V, TJ=25°C 0.7 VDS=1200V, VGS=0V, TJ=175°C 3 VDS=0V, TJ=25°C, VGS=-20V / +20V 6 20 VGS=12V, ID=20A, TJ=25°C 85 105 VGS=12V, ID=20A, TJ=125°C VGS=12V, ID=20A, TJ=175°C VDS=5V, ID=10mA Units 75 mA mA mW 135 177 4 f=1MHz, open drain 4.8 4.2 6 V W Typical Performance - Reverse Diode Parameter Diode continuous forward current 1 Diode pulse current 2 Forward voltage Test Conditions IS TC=25°C 28.8 A IS,pulse TC=25°C 77 A VFSD Reverse recovery charge Qrr Reverse recovery time trr Reverse recovery charge Qrr Reverse recovery time trr Datasheet: UF3C120080B7S Value Symbol Min Typ VGS=0V, IS=10A, TJ=25°C 1.5 VGS=0V, IS=10A, TJ=175°C 2 VR=800V, IS=20A, VGS=-5V, RG_EXT=22W di/dt=2800A/ms, TJ=25°C VR=800V, IS=20A, VGS=-5V, RG_EXT=22W di/dt=2800A/ms, TJ=150°C Rev. B, May 2023 Max Units 2 V 140 nC 23 ns 118 nC 19 ns 3 Typical Performance - Dynamic Parameter Value Symbol Test Conditions Ciss Coss Crss VDS=100V, VGS=0V f=100kHz 754 97 0.8 pF Effective output capacitance, energy related Coss(er) VDS=0V to 800V, VGS=0V 54 pF Effective output capacitance, time related Coss(tr) VDS=0V to 800V, VGS=0V 122 pF COSS stored energy Eoss VDS=800V, VGS=0V 17.3 mJ Total gate charge Gate-drain charge Gate-source charge QG QGD QGS VDS=800V, ID=20A, VGS = -5V to 12V 23 5 11 nC Turn-on delay time td(on) Input capacitance Output capacitance Reverse transfer capacitance Rise time Turn-off delay time Fall time tr td(off) tf Turn-on energy EON Turn-off energy EOFF Total switching energy Turn-on delay time Rise time Turn-off delay time Fall time ETOTAL td(on) tr td(off) tf Turn-on energy EON Turn-off energy EOFF Total switching energy Datasheet: UF3C120080B7S ETOTAL VDS=800V, ID=20A, Gate Driver =-5V to +12V, Turn-on RG,EXT=8.5W, Turn-off RG,EXT=22W Inductive Load, FWD: same device with VGS = -5V, RG = 22W, TJ=25°C VDS=800V, ID=20A, Gate Driver =-5V to +12V, Turn-on RG,EXT=8.5W, Turn-off RG,EXT=22W Inductive Load, FWD: same device with VGS = -5V, RG = 22W, TJ=150°C Rev. B, May 2023 Min Typ Max Units 33 7 30 ns 9 340 48 mJ 388 31 6 30 ns 8 312 42 mJ 354 4 60 60 50 50 Drain Current, ID (A) Drain Current, ID (A) Typical Performance Diagrams 40 30 Vgs = 15V Vgs = 8V 20 Vgs = 7V Vgs = 6.5V 10 30 Vgs = 15V Vgs = 8V Vgs = 7V Vgs = 6.5V Vgs = 6V 20 10 Vgs = 6V 0 0 0 1 2 3 4 5 6 7 8 Drain-Source Voltage, VDS (V) 9 10 Figure 1. Typical output characteristics at TJ = - 55°C, tp < 250ms 0 1 2 3 4 5 6 7 8 9 Drain-Source Voltage, VDS (V) 10 Figure 2. Typical output characteristics at TJ = 25°C, tp < 250ms 60 2.5 40 30 On Resistance, RDS_ON (P.U.) Vgs = 15V Vgs = 8V Vgs = 7V Vgs = 6V Vgs = 5.5V Vgs = 5V 50 Drain Current, ID (A) 40 20 10 2.0 1.5 1.0 0.5 0.0 0 0 1 2 3 4 5 6 7 8 Drain-Source Voltage, VDS (V) 9 Figure 3. Typical output characteristics at TJ = 175°C, tp < 250ms Datasheet: UF3C120080B7S -75 -50 -25 0 25 50 75 100 125 150 175 Junction Temperature, TJ (°C) 10 Figure 4. Normalized on-resistance vs. temperature at VGS = 12V and ID = 20A Rev. B, May 2023 5 60 Tj = 175°C Tj = 25°C Tj = - 55°C 250 200 150 100 Tj = 25°C Tj = 175°C 40 30 20 50 10 0 0 0 10 20 30 40 Drain Current, ID (A) 50 60 Figure 5. Typical drain-source on-resistances at VGS = 12V 0 2 3 4 5 6 7 8 Gate-Source Voltage, VGS (V) 9 10 Gate-Source Voltage, VGS (V) 20 5 4 3 2 1 0 -100 1 Figure 6. Typical transfer characteristics at VDS = 5V 6 Threshold Voltage, Vth (V) Tj = -55°C 50 Drain Current, ID (A) On-Resistance, RDS(on) (mW) 300 15 10 5 0 -5 -50 0 50 100 150 Junction Temperature, TJ (°C) 10 20 30 40 Gate Charge, QG (nC) Figure 7. Threshold voltage vs. junction temperature at VDS = 5V and ID = 10mA Datasheet: UF3C120080B7S 0 200 Figure 8. Typical gate charge at VDS = 800V and ID = 20A Rev. B, May 2023 6 0 0 Vgs = -5V Vgs = 0V Vgs = 5V -10 Vgs = - 5V -5 Drain Current, ID (A) Drain Current, ID (A) -5 Vgs = 8V -15 -20 -25 Vgs = 0V Vgs = 5V -10 Vgs = 8V -15 -20 -25 -30 -30 -4 -3 -2 -1 Drain-Source Voltage, VDS (V) 0 Figure 9. 3rd quadrant characteristics at TJ = -55°C -4 -3 -2 -1 Drain-Source Voltage, VDS (V) 0 Figure 10. 3rd quadrant characteristics at TJ = 25°C 0 40 30 -10 -15 EOSS (mJ) Drain Current, ID (A) -5 Vgs = - 5V 20 Vgs = 0V -20 10 Vgs = 5V -25 Vgs = 8V 0 -30 -4 -3 -2 -1 Drain-Source Voltage, VDS (V) Figure 11. 3rd quadrant characteristics at TJ = 175°C Datasheet: UF3C120080B7S 0 0 200 400 600 800 1000 Drain-Source Voltage, VDS (V) 1200 Figure 12. Typical stored energy in COSS at VGS = 0V Rev. B, May 2023 7 1.E+04 35 Capacitance, C (pF) 1.E+02 Coss 1.E+01 Crss 1.E+00 30 DC Drain Current, ID (A) Ciss 1.E+03 25 20 15 10 5 0 1.E-01 0 -75 -50 -25 0 25 50 75 100 125 150 175 Case Temperature, TC (°C) 200 400 600 800 1000 1200 Drain-Source Voltage, VDS (V) Figure 13. Typical capacitances at f = 100kHz and VGS = 0V Figure 14. DC drain current derating 1 Thermal Impedance, ZqJC (°C/W) Power Dissipation, Ptot (W) 200 150 100 50 0 -75 -50 -25 0 25 50 75 100 125 150 175 Case Temperature, TC (°C) Figure 15. Total power dissipation Datasheet: UF3C120080B7S 0.1 0.01 D = 0.5 D = 0.3 D = 0.1 D = 0.05 D = 0.02 D = 0.01 Single Pulse 0.001 1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 Pulse Time, tp (s) Figure 16. Maximum transient thermal impedance Rev. B, May 2023 8 800 100 Switching Energy (mJ) Drain Current, ID (A) 1ms 10 10ms 100ms 1 1ms DC 600 500 400 Etot Eon Eoff 300 200 100 10ms 0 0.1 1 0 10 100 1000 Drain-Source Voltage, VDS (V) Figure 17. Safe operation area at TC = 25°C, D = 0, Parameter tp 5 10 15 20 25 Drain Current, ID (A) 30 35 Figure 18. Clamped inductive switching energy vs. drain current at TJ = 25°C 500 120 400 Turn-Off Energy, EOFF (mJ) Turn-on Energy, EON (mJ) VDS = 800V, VGS = -5V/12V RG_ON = 8.5W, RG_OFF = 22W FWD: same device with VGS = 5V, RG = 22W 700 300 200 VDS = 800V, VGS = -5V/12V ID = 20A, TJ = 25°C FWD: same device with VGS = - 5V, RG = 22W 100 100 80 60 40 VDS = 800V, VGS = -5V/12V ID = 20A, TJ =25°C FWD: same device with VGS = -5V 20 0 0 0 5 10 15 20 Total External RG, RG,EXT_ON (W) Figure 19. Clamped inductive switching turn-on energy vs. RG,EXT_ON Datasheet: UF3C120080B7S 0 25 20 40 60 80 Total External RG, RG,EXT_OFF (W) 100 Figure 20. Clamped inductive switching turn-off energy vs. RG,EXT_OFF Rev. B, May 2023 9 400 150 300 Etot Eon Eoff 250 200 100 VGS = -5V/12V, RG_ON = 8.5W, RG_OFF = 22W, FWD: same device with VGS = -5V, RG = 22W 150 100 VDS = 800V, IS = 20A, di/dt = 2800A/ms, VGS = -5V, RG =22W Qrr (nC) Switching Energy (mJ) 350 50 50 0 0 0 25 50 75 100 125 150 Junction Temperature, TJ (°C) 175 Figure 21. Clamped inductive switching energy vs. junction temperature at VDS = 800V and ID = 20A 0 25 50 75 100 125 150 Junction Temperature, TJ (°C) 175 Figure 22. Reverse recovery charge Qrr vs. junction temperature Applications Information SiC FETs are enhancement-mode power switches formed by a high-voltage SiC depletion-mode JFET and a low-voltage silicon MOSFET connected in series. The silicon MOSFET serves as the control unit while the SiC JFET provides high voltage blocking in the off state. This combination of devices in a single package provides compatibility with standard gate drivers and offers superior performance in terms of low on-resistance (RDS(on)), output capacitance (Coss), gate charge (QG), and reverse recovery charge (Qrr) leading to low conduction and switching losses. The SiC FETs also provide excellent reverse conduction capability eliminating the need for an external anti-parallel diode. Like other high performance power switches, proper PCB layout design to minimize circuit parasitics is strongly recommended due to the high dv/dt and di/dt rates. An external gate resistor is recommended when the FET is working in the diode mode in order to achieve the optimum reverse recovery performance. For more information on SiC FET operation, see www.unitedsic.com. A snubber circuit with a small R(G), or gate resistor, provides better EMI suppression with higher efficiency compared to using a high R(G) value. There is no extra gate delay time when using the snubber circuitry, and a small R(G) will better control both the turn-off V(DS) peak spike and ringing duration, while a high R(G) will damp the peak spike but result in a longer delay time. In addition, the total switching loss when using a snubber circuit is less than using high R(G), while greatly reducing E(OFF) from mid-to-full load range with only a small increase in E(ON). Efficiency will therefore improve with higher load current. For more information on how a snubber circuit will improve overall system performance, visit the UnitedSiC website at www.unitedsic.com Datasheet: UF3C120080B7S Rev. B, May 2023 10 Important notice The information contained herein is believed to be reliable; however, Qorvo makes no warranties regarding the information contained herein and assumes no responsibility or liability whatsoever for the use of the information contained herein. All information contained herein is subject to change without notice. Customers should obtain and verify the latest relevant information before placing orders for Qorvo products. The information contained herein or any use of such information does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other intellectual property rights, whether with regard to such information itself or anything described by such information. THIS INFORMATION DOES NOT CONSTITUTE A WARRANTY WITH RESPECT TO THE PRODUCTS DESCRIBED HEREIN, AND QORVO HEREBY DISCLAIMS ANY AND ALL WARRANTIES WITH RESPECT TO SUCH PRODUCTS WHETHER EXPRESS OR IMPLIED BY LAW, COURSE OF DEALING, COURSE OF PERFORMANCE, USAGE OF TRADE OR OTHERWISE, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Without limiting the generality of the foregoing, Qorvo products are not warranted or authorized for use as critical components in medical, life-saving, or life-sustaining applications, or other applications where a failure would reasonably be expected to cause severe personal injury or death. Datasheet: UF3C120080B7S Rev. B, May 2023 11