1200V-16mW SiC FET
Rev. B, December 2019
DATASHEET
Description
UF3SC120016K4S
CASE
This SiC FET device is based on a unique ‘cascode’ circuit
configuration, in which a normally-on SiC JFET is co-packaged with a Si
MOSFET to produce a normally-off SiC FET device. The device’s
standard gate-drive characteristics allows for a true “drop-in
replacement” to Si IGBTs, Si FETs, SiC MOSFETs or Si superjunction
devices. Available in the TO-247-4L package, this device exhibits ultralow gate charge and exceptional reverse recovery characteristics,
making it ideal for switching inductive loads , and any application
requiring standard gate drive.
CASE
D (1)
Features
w Typical on-resistance RDS(on),typ of 16mW
w Maximum operating temperature of 175°C
G (4)
w Excellent reverse recovery
w Low gate charge
w Low intrinsic capacitance
KS (3)
w ESD protected, HBM class 2
S (2)
1 2 34
w TO-247-4L package for faster switching, clean gate waveforms
Typical applications
Part Number
Package
Marking
w EV charging
UF3SC120016K4S
TO-247-4L
UF3SC120016K4S
w PV inverters
w Switch mode power supplies
w Power factor correction modules
w Motor drives
w Induction heating
Datasheet: UF3SC120016K4S
Rev. B, December 2019
1
Maximum Ratings
Parameter
Test Conditions
Symbol
VDS
VGS
Drain-source voltage
Gate-source voltage
Continuous drain current 1
ID
Pulsed drain current 2
Single pulsed avalanche energy 3
Power dissipation
Maximum junction temperature
Operating and storage temperature
IDM
EAS
Ptot
TJ,max
TJ, TSTG
Max. lead temperature for soldering,
1/8” from case for 5 seconds
TL
DC
TC = 25°C
TC = 100°C
TC = 25°C
L = 15mH, IAS =6.6A
TC = 25°C
Value
Units
1200
-20 to +20
107
77
350
327
517
175
-55 to 175
V
V
A
A
A
mJ
W
°C
°C
250
°C
1. Limited by TJ,max
2. Pulse width tp limited by TJ,max
3. Starting TJ = 25°C
Thermal Characteristics
Parameter
Thermal resistance, junction-to-case
Datasheet: UF3SC120016K4S
Symbol
Test Conditions
RqJC
Rev. B, December 2019
Value
Min
Typ
Max
0.22
0.29
Units
°C/W
2
Electrical Characteristics (TJ = +25°C unless otherwise specified)
Typical Performance - Static
Parameter
Drain-source breakdown voltage
Total drain leakage current
Total gate leakage current
Drain-source on-resistance
Gate threshold voltage
Gate resistance
Symbol
Test Conditions
BVDS
VGS=0V, ID=1mA
IDSS
IGSS
RDS(on)
VG(th)
RG
Value
Min
Typ
Max
1200
V
VDS=1200V,
VGS=0V, TJ=25°C
1.2
VDS=1200V,
VGS=0V, TJ=175°C
3.7
VDS=0V, TJ=25°C,
VGS=-20V / +20V
4.5
20
VGS=12V, ID=50A,
TJ=25°C
16
21
VGS=12V, ID=50A,
TJ=125°C
VGS=12V, ID=50A,
TJ=175°C
VDS=5V, ID=10mA
Units
300
mA
mA
mW
25
33
4
f=1MHz, open drain
4.7
0.8
6
1.5
V
W
Typical Performance - Reverse Diode
Parameter
Diode continuous forward current 1
Diode pulse current 2
Forward voltage
Test Conditions
IS
TC=25°C
107
A
IS,pulse
TC=25°C
350
A
VFSD
Reverse recovery charge
Qrr
Reverse recovery time
trr
Reverse recovery charge
Qrr
Reverse recovery time
trr
Datasheet: UF3SC120016K4S
Value
Symbol
Min
Typ
VGS=0V, IF=50A,
TJ=25°C
1.47
VGS=0V, IF=50A,
TJ=175°C
1.95
VR=800V, IF=80A,
VGS=-5V, RG_EXT=5W
di/dt=1750A/ms,
TJ=25°C
VR=800V, IF=80A,
VGS=-5V, RG_EXT=5W
di/dt=1750A/ms,
TJ=150°C
Rev. B, December 2019
Max
Units
2
V
605
nC
66
ns
621
nC
72
ns
3
Typical Performance - Dynamic
Parameter
Value
Symbol
Test Conditions
Ciss
Coss
Crss
VDS=800V, VGS=0V
f=100kHz
7824
216
3.1
pF
Effective output capacitance, energy
related
Coss(er)
VDS=0V to 800V,
VGS=0V
243
pF
Effective output capacitance, time
related
Coss(tr)
VDS=0V to 800V,
VGS=0V
540
pF
COSS stored energy
Eoss
VDS=800V, VGS=0V
78
mJ
Total gate charge
Gate-drain charge
Gate-source charge
QG
QGD
QGS
VDS=800V, ID=80A,
VGS = -5V to 15V
218
24
96
nC
Turn-on delay time
td(on)
Input capacitance
Output capacitance
Reverse transfer capacitance
Rise time
Turn-off delay time
Fall time
tr
td(off)
tf
Turn-on energy
EON
Turn-off energy
EOFF
Total switching energy
Turn-on delay time
Rise time
Turn-off delay time
Fall time
ETOTAL
td(on)
tr
td(off)
tf
Turn-on energy
EON
Turn-off energy
EOFF
Total switching energy
Datasheet: UF3SC120016K4S
ETOTAL
VDS=800V, ID=80A, Gate
Driver =-5V to +15V,
Turn-on RG,EXT=1.5W,
Turn-off RG,EXT=5W
Inductive Load,
FWD: same device with
VGS = -5V, RG = 5W,
TJ=25°C
VDS=800V, ID=80A, Gate
Driver =-5V to +15V,
Turn-on RG,EXT=1.5W,
Turn-off RG,EXT=5W
Inductive Load,
FWD: same device with
VGS = -5V, RG = 5W,
TJ=150°C
Rev. B, December 2019
Min
Typ
Max
Units
33
59
73
ns
12
2552
150
mJ
2702
33
63
79
ns
12
2820
154
mJ
2974
4
Typical Performance - Dynamic (continued)
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Symbol
td(on)
tr
td(off)
tf
Turn-on energy
EON
Turn-off energy
EOFF
Total switching energy
Turn-on delay time
Rise time
Turn-off delay time
Fall time
ETOTAL
td(on)
tr
td(off)
tf
Turn-on energy
EON
Turn-off energy
EOFF
Total switching energy
Datasheet: UF3SC120016K4S
ETOTAL
Test Conditions
Value
Min
Typ
Max
Units
33
VDS=800V, ID=80A, Gate
Driver =-5V to +15V,
Turn-on RG,EXT=1.5W,
Turn-off RG,EXT=5W
Inductive Load,
FWD: UJ3D1250K,
TJ=25°C
VDS=800V, ID=80A, Gate
Driver =-5V to +15V,
Turn-on RG,EXT=1.5W,
Turn-off RG,EXT=5W
Inductive Load,
FWD: UJ3D1250K,
TJ=150°C
Rev. B, December 2019
58
73
ns
11
1815
140
mJ
1955
33
64
78
ns
12
1947
158
mJ
2105
5
250
250
200
200
Drain Current, ID (A)
Drain Current, ID (A)
Typical Performance Diagrams
Vgs = 15V
150
Vgs = 10V
Vgs = 8V
100
Vgs = 7V
Vgs = 6.5V
50
Vgs = 6V
Vgs = 15V
Vgs = 10V
Vgs = 8V
100
Vgs = 7V
Vgs = 6.5V
50
Vgs = 6V
0
0
0
1
2 3 4 5 6 7 8
Drain-Source Voltage, VDS (V)
9
10
Figure 1. Typical output characteristics at TJ = - 55°C,
tp < 250ms
250
1
2
3 4 5 6 7 8 9
Drain-Source Voltage, VDS (V)
10
Figure 2. Typical output characteristics at TJ = 25°C,
tp < 250ms
On Resistance, RDS_ON (P.U.)
150
0
2.5
Vgs = 15V
Vgs = 8V
Vgs = 7V
Vgs = 6V
Vgs = 5.5V
Vgs = 5V
200
Drain Current, ID (A)
150
100
50
2.0
1.5
1.0
0.5
0.0
0
0
1
2
3
4
5 6
7 8
Drain-Source Voltage, VDS (V)
9
Figure 3. Typical output characteristics at TJ = 175°C,
tp < 250ms
Datasheet: UF3SC120016K4S
-75 -50 -25 0 25 50 75 100 125 150 175
Junction Temperature, TJ (°C)
10
Figure 4. Normalized on-resistance vs. temperature
at VGS = 12V and ID = 50A
Rev. B, December 2019
6
200
Tj = 175°C
Tj = 25°C
Tj = - 55°C
40
Drain Current, ID (A)
On-Resistance, RDS(on) (mW)
50
30
20
10
180
Tj = -55°C
160
Tj = 25°C
140
Tj = 175°C
120
100
80
60
40
20
0
0
0
25
50 75 100 125 150 175 200
Drain Current, ID (A)
Figure 5. Typical drain-source on-resistances at VGS =
12V
0
9
10
20
Gate-Source Voltage, VGS (V)
Threshold Voltage, Vth (V)
2 3 4 5 6 7 8
Gate-Source Voltage, VGS (V)
Figure 6. Typical transfer characteristics at VDS = 5V
6
5
4
3
2
1
0
-100
1
15
10
5
0
-5
-50
0
50
100
150
Junction Temperature, TJ (°C)
Figure 7. Threshold voltage vs. junction temperature
at VDS = 5V and ID = 10mA
Datasheet: UF3SC120016K4S
0
200
50
100
150
Gate Charge, QG (nC)
200
250
Figure 8. Typical gate charge at VDS = 800V and ID =
80A
Rev. B, December 2019
7
0
0
-25
Vgs = 0V
Drain Current, ID (A)
Drain Current, ID (A)
Vgs = - 5V
Vgs = -5V
-25
Vgs = 5V
-50
Vgs = 8V
-75
-100
-125
Vgs = 5V
-50
Vgs = 8V
-75
-100
-125
-150
-150
-4
-3
-2
-1
Drain-Source Voltage, VDS (V)
0
Figure 9. 3rd quadrant characteristics at TJ = -55°C
-4
-3
-2
-1
Drain-Source Voltage, VDS (V)
0
Figure 10. 3rd quadrant characteristics at TJ = 25°C
0
200
175
-25
150
-50
EOSS (mJ)
Drain Current, ID (A)
Vgs = 0V
-75
Vgs = - 5V
-100
100
75
Vgs = 0V
50
Vgs = 5V
-125
125
25
Vgs = 8V
0
-150
-4
-3
-2
-1
Drain-Source Voltage, VDS (V)
Figure 11. 3rd quadrant characteristics at TJ = 175°C
Datasheet: UF3SC120016K4S
0
0
200
400
600
800 1000
Drain-Source Voltage, VDS (V)
1200
Figure 12. Typical stored energy in COSS at VGS = 0V
Rev. B, December 2019
8
1.E+05
120
Capacitance, C (pF)
1.E+03
DC Drain Current, ID (A)
Ciss
1.E+04
Coss
1.E+02
1.E+01
80
60
40
20
Crss
0
1.E+00
0
-75 -50 -25 0 25 50 75 100 125 150 175
Case Temperature, TC (°C)
200 400 600 800 1000 1200
Drain-Source Voltage, VDS (V)
Figure 13. Typical capacitances at f = 100kHz and VGS
= 0V
Figure 14. DC drain current derating
1.E+00
Thermal Impedance, ZqJC (°C/W)
600
Power Dissipation, Ptot (W)
100
500
400
300
200
100
0
1.E-01
D = 0.5
D = 0.3
D = 0.1
D = 0.05
D = 0.02
D = 0.01
Single Pulse
1.E-02
1.E-03
1.E-04
1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00
-75 -50 -25 0 25 50 75 100 125 150 175
Case Temperature, TC (°C)
Figure 15. Total power dissipation
Datasheet: UF3SC120016K4S
Pulse Time, tp (s)
Figure 16. Maximum transient thermal impedance
Rev. B, December 2019
9
3500
Drain Current, ID (A)
100
10ms
100ms
10
1ms
1
10ms
DC
Switching Energy (mJ)
1ms
2500
2000
1500
VDS = 800V, VGS = -5V/15V
RG_ON = 1.5W, RG_OFF = 5W
FWD: same device with
VGS = -5V, RG = 5W
1000
500
0
0.1
1
0
10
100
1000
Drain-Source Voltage, VDS (V)
Figure 17. Safe operation area at TC = 25°C, D = 0,
Parameter tp
20
40
60
Drain Current, ID (A)
80
100
Figure 18. Clamped inductive switching energy vs.
drain current at TJ = 25°C
3500
1000
900
Turn-Off Energy, EOFF (mJ)
3000
Turn-on Energy, EON (mJ)
Etot
Eon
Eoff
3000
2500
2000
1500
VDS = 800V, VGS = -5V/15V
ID = 80A, TJ = 25°C
FWD: same device with
VGS = - 5V, RG = 5W
1000
500
800
700
600
500
400
300
VDS = 800V, VGS = -5V/15V
ID = 80A, TJ =25°C
FWD: same device with
VGS = -5V, RG = 5W
200
100
0
0
0
5
10
15
Total External RG, RG,EXT_ON (W)
Figure 19. Clamped inductive switching turn-on
energy vs. RG,EXT_ON
Datasheet: UF3SC120016K4S
0
20
10
20
30
40
Total External RG, RG,EXT_OFF (W)
50
Figure 20. Clamped inductive switching turn-off
energy vs. RG,EXT_OFF
Rev. B, December 2019
10
700
3000
600
2500
500
Etot
Eon
Eoff
2000
Qrr (nC)
Switching Energy (mJ)
3500
1500
VGS = -5V/15V, RG_ON = 1.5W,
RG_OFF = 5W, FWD: same device
with VGS = -5V, RG = 5W
1000
500
400
300
200
100
0
0
0
25
50
75 100 125 150
Junction Temperature, TJ (°C)
175
Figure 21. Clamped inductive switching energy vs.
junction temperature at VDS = 800V and ID = 80A
0
25
50
75 100 125 150
Junction Temperature, TJ (°C)
175
Figure 22. Reverse recovery charge Qrr vs. junction
temperature
3500
2500
VDS = 800V, VGS = -5V/15V
RG_ON = 1.5W, RG_OFF = 5W
FWD: UJ3D1250K
3000
2500
Switching Energy (mJ)
Switching Energy (mJ)
VDS = 800V, IS = 80A,
di/dt = 1750A/ms,
VGS = -5V, RG =5W
Etot
Eon
Eoff
2000
1500
1000
2000
Etot
Eon
Eoff
1500
1000
VGS = -5V/15V,
RG_ON = 1.5W, RG_OFF = 5W,
FWD: UJ3D1250K
500
500
0
0
20
40
60
80
Drain Current, ID (A)
100
Figure 23. Clamped inductive switching energy vs.
drain current at TJ = 25°C
Datasheet: UF3SC120016K4S
0
120
0
25
50
75 100 125 150
Junction Temperature, TJ (°C)
175
Figure 24. Clamped inductive switching energy vs.
junction temperature at VDS = 800V and ID = 80A
Rev. B, December 2019
11
Applications Information
SiC FETs are enhancement-mode power switches formed by a highvoltage SiC depletion-mode JFET and a low-voltage silicon MOSFET
connected in series. The silicon MOSFET serves as the control unit
while the SiC JFET provides high voltage blocking in the off state. This
combination of devices in a single package provides compatibility with
standard gate drivers and offers superior performance in terms of low
on-resistance (RDS(on)), output capacitance (Coss), gate charge (QG), and
reverse recovery charge (Qrr) leading to low conduction and switching
losses. The SiC FETs also provide excellent reverse conduction
capability eliminating the need for an external anti-parallel diode.
Information on all products and contained herein is intended for
description only. No license, express or implied, to any intellectual
property rights is granted within this document.
UnitedSiC assumes no liability whatsoever relating to the choice,
selection or use of the UnitedSiC products and services described
herein.
Like other high performance power switches, proper PCB layout
design to minimize circuit parasitics is strongly recommended due to
the high dv/dt and di/dt rates. An external gate resistor is
recommended when the FET is working in the diode mode in order to
achieve the optimum reverse recovery performance. For more
information on SiC FET operation, see www.unitedsic.com.
Disclaimer
UnitedSiC reserves the right to change or modify any of the products
and their inherent physical and technical specifications without prior
notice. UnitedSiC assumes no responsibility or liability for any errors
or inaccuracies within.
Datasheet: UF3SC120016K4S
Rev. B, December 2019
12