1200V-30mW SiC FET
Rev. A, April 2022
DATASHEET
Description
The UF4SC120030K4S is a 1200V, 30mW G4 SiC FET. It is based on a
unique ‘cascode’ circuit configuration, in which a normally-on SiC JFET
is co-packaged with a Si MOSFET to produce a normally-off SiC FET
device. The device’s standard gate-drive characteristics allows for a
true “drop-in replacement” to Si IGBTs, Si FETs, SiC MOSFETs or Si
superjunction devices. Available in the TO-247-4L package, this
device exhibits ultra-low gate charge and exceptional reverse
recovery characteristics, making it ideal for switching inductive loads
and any application requiring standard gate drive.
UF4SC120030K4S
CASE
CASE
D (1)
Features
w On-resistance RDS(on): 30mW (typ)
G (4)
w Operating temperature: 175°C (max)
w Excellent reverse recovery: Qrr = 277nC
KS (3)
w Low body diode VFSD: 1.22V
w Low gate charge: QG = 37.8nC
S (2)
1 2 34
w Threshold voltage VG(th): 4.8V (typ) allowing 0 to 15V drive
w Low intrinsic capacitance
w ESD protected: HBM class 2 and CDM class C3
w TO-247-4L package for faster switching, clean gate waveforms
Part Number
Package
Marking
UF4SC120030K4S
TO-247-4L
UF4SC120030K4S
Typical applications
w EV charging
w PV inverters
w Switch mode power supplies
w Power factor correction modules
w Motor drives
w Induction heating
Datasheet: UF4SC120030K4S
Rev. A, April 2022
1
Maximum Ratings
Parameter
Symbol
Test Conditions
VDS
Drain-source voltage
VGS
Gate-source voltage
Continuous drain current 1
ID
Pulsed drain current 2
Single pulsed avalanche energy 3
SiC FET dv/dt ruggedness
Power dissipation
Maximum junction temperature
Operating and storage temperature
IDM
EAS
dv/dt
Ptot
TJ,max
TJ, TSTG
Max. lead temperature for soldering,
1/8” from case for 5 seconds
DC
AC (f > 1Hz)
TC ≤ 40°C
TC =100°C
TC = 25°C
L=15mH, IAS =3.6A
VDS ≤ 800V
TC = 25°C
TL
Value
Units
1200
-20 to +20
-25 to +25
53
41
164
97
200
341
175
-55 to 175
V
V
V
A
A
A
mJ
V/ns
W
°C
°C
250
°C
1. Limited by bondwires
2. Pulse width tp limited by TJ,max
3. Starting TJ = 25°C
Thermal Characteristics
Parameter
Thermal resistance, junction-to-case
Datasheet: UF4SC120030K4S
Symbol
Test Conditions
RqJC
Rev. A, April 2022
Value
Min
Typ
Max
0.34
0.44
Units
°C/W
2
Electrical Characteristics (TJ = +25°C unless otherwise specified)
Typical Performance - Static
Parameter
Drain-source breakdown voltage
Total drain leakage current
Total gate leakage current
Drain-source on-resistance
Gate threshold voltage
Gate resistance
Symbol
Test Conditions
BVDS
VGS=0V, ID=1mA
IDSS
IGSS
RDS(on)
VG(th)
RG
Value
Min
Typ
Max
1200
V
VDS=1200V,
VGS=0V, TJ=25°C
1
VDS=1200V,
VGS=0V, TJ=175°C
15
VDS=0V, TJ=25°C,
VGS=-20V / +20V
6
20
VGS=12V, ID=20A,
TJ=25°C
30
39
VGS=12V, ID=20A,
TJ=125°C
VGS=12V, ID=20A,
TJ=175°C
VDS=5V, ID=10mA
Units
50
mA
mA
mW
56
77
4
f=1MHz, open drain
4.8
4.5
6
V
W
Typical Performance - Reverse Diode
Parameter
Diode continuous forward current 1
Diode pulse current 2
Forward voltage
Test Conditions
IS
TC ≤ 40°C
53
A
IS,pulse
TC = 25°C
164
A
VFSD
Reverse recovery charge
Qrr
Reverse recovery time
trr
Reverse recovery charge
Qrr
Reverse recovery time
trr
Datasheet: UF4SC120030K4S
Value
Symbol
VGS=0V, IS=15A,
TJ=25°C
VGS=0V, IS=15A,
TJ=175°C
VR=800V, IS=30A,
VGS=0V, RG=18W
di/dt=1840A/ms,
TJ=25°C
VR=800V, IS=30A,
VGS=0V, RG=18W
di/dt=1840A/ms,
TJ=150°C
Rev. A, April 2022
Min
Typ
1.22
Max
Units
1.35
V
1.68
277
nC
14
ns
298
nC
12.8
ns
3
Typical Performance - Dynamic
Parameter
Value
Symbol
Test Conditions
Ciss
Coss
Crss
VDS=800V, VGS=0V
f=100kHz
1450
65
2
pF
Effective output capacitance, energy
related
Coss(er)
VDS=0V to 800V,
VGS=0V
82
pF
Effective output capacitance, time
related
Coss(tr)
VDS=0V to 800V,
VGS=0V
150
pF
COSS stored energy
Eoss
VDS=800V, VGS=0V
26
mJ
Total gate charge
Gate-drain charge
Gate-source charge
QG
QGD
QGS
VDS=800V, ID=30A,
VGS = 0V to 15V
37.8
8
11.8
nC
Turn-on delay time
td(on)
Input capacitance
Output capacitance
Reverse transfer capacitance
Rise time
Turn-off delay time
Fall time
tr
td(off)
tf
Turn-on energy including RS energy
EON
Turn-off energy including RS energy
EOFF
Min
Typ
Note 4 and 5,
VDS=800V, ID=30A, Gate
Driver =0V to +15V,
RG_ON=1W, RG_OFF=18W,
inductive Load,
FWD: same device with VGS
= 0V and RG =18W,
Snubber: Rs=10W, Cs=47pF
TJ=25°C
19
77
423
73
Snubber RS energy during turn-on
ERS_ON
Snubber RS energy during turn-off
ERS_OFF
1.5
td(on)
13
Turn-off delay time
Fall time
tr
td(off)
tf
Turn-on energy including RS energy
EON
Turn-off energy including RS energy
EOFF
Total switching energy
ETOTAL
Snubber RS energy during turn-on
ERS_ON
Snubber RS energy during turn-off
ERS_OFF
Note 4 and 5,
VDS=800V, ID=30A, Gate
Driver =0V to +15V,
RG_ON=1W, RG_OFF=18W,
inductive Load,
FWD: same device with VGS
= 0V and RG =18W,
Snubber: Rs=10W, Cs=47pF
TJ=150°C
ns
11
ETOTAL
Rise time
Units
12
Total switching energy
Turn-on delay time
Max
496
mJ
1.7
20
85
ns
12
500
97
597
mJ
1.6
1.4
4. Measured with the switching test circuit in Figure 26.
5. In this datasheet, all the switching energies (turn-on energy, turn-off energy and total energy) presented in the tables and Figures include
the device RC snubber energy losses.
Datasheet: UF4SC120030K4S
Rev. A, April 2022
4
80
80
70
70
60
60
50
Drain Current, ID (A)
Drain Current, ID (A)
Typical Performance Diagrams
Vgs = 15V
Vgs = 8V
Vgs = 7V
Vgs = 6.5V
Vgs = 6V
40
30
20
10
40
Vgs = 15V
Vgs = 8V
30
Vgs = 7V
20
Vgs = 6.5V
10
0
Vgs = 6V
0
0
1
2 3 4 5 6 7 8
Drain-Source Voltage, VDS (V)
9
10
Figure 1. Typical output characteristics at TJ = - 55°C,
tp < 250ms
0
1
2
3 4 5 6 7 8 9
Drain-Source Voltage, VDS (V)
10
Figure 2. Typical output characteristics at TJ = 25°C, tp
< 250ms
80
3.0
On Resistance, RDS_ON (P.U.)
70
Drain Current, ID (A)
50
60
50
40
Vgs = 15V
Vgs = 8V
30
Vgs = 7V
20
Vgs = 6.5V
10
Vgs = 6V
Vgs = 5.5V
2.5
2.0
1.5
1.0
0.5
0.0
0
10
-75 -50 -25 0 25 50 75 100 125 150 175
Junction Temperature, TJ (°C)
Figure 3. Typical output characteristics at TJ = 175°C,
tp < 250ms
Figure 4. Normalized on-resistance vs. temperature at
VGS = 12V at ID = 30A
0
1
2 3 4 5 6 7 8
Drain-Source Voltage, VDS (V)
Datasheet: UF4SC120030K4S
9
Rev. A, April 2022
5
60
Tj = 175°C
Tj = 25°C
Tj = -55°C
120
100
80
60
40
Tj = 25°C
Tj = 175°C
40
30
20
10
20
0
0
0
20
40
60
Drain Current, ID (A)
80
Figure 5. Typical drain-source on-resistances at VGS =
12V
0
2 3 4 5 6 7 8
Gate-Source Voltage, VGS (V)
9
10
Gate-Source Voltage, VGS (V)
20
5
4
3
2
1
0
-100
1
Figure 6. Typical transfer characteristics at VDS = 5V
6
Threshold Voltage, Vth (V)
Tj = -55°C
50
Drain Current, ID (A)
On-Resistance, RDS(on) (mW)
140
15
10
5
0
-5
-50
0
50
100
150
Junction Temperature, TJ (°C)
0
10
20
30
40
50
60
Gate Charge, QG (nC)
Figure 7. Threshold voltage vs. junction temperature at
VDS = 5V and ID = 10mA
Datasheet: UF4SC120030K4S
-10
200
Figure 8. Typical gate charge at VDS = 5V and ID = 30A
Rev. A, April 2022
6
0
0
Vgs = - 5V
Vgs = 0V
-10
Drain Current, ID (A)
Drain Current, ID (A)
Vgs = -5V
Vgs = 5V
Vgs = 8V
-20
-30
-40
Vgs = 5V
Vgs = 8V
-20
-30
-40
-4
-3
-2
-1
Drain-Source Voltage, VDS (V)
0
Figure 9. 3rd quadrant characteristics at TJ = -55°C
-4
-3
-2
-1
Drain-Source Voltage, VDS (V)
0
Figure 10. 3rd quadrant characteristics at TJ = 25°C
0
60
Vgs = - 5V
50
Vgs = 0V
-10
Vgs = 5V
40
Vgs = 8V
EOSS (mJ)
Drain Current, ID (A)
Vgs = 0V
-10
-20
30
20
-30
10
0
-40
-4
-3
-2
-1
Drain-Source Voltage, VDS (V)
Figure 11. 3rd quadrant characteristics at TJ = 175°C
Datasheet: UF4SC120030K4S
0
0
200
400
600
800 1000
Drain-Source Voltage, VDS (V)
1200
Figure 12. Typical stored energy in COSS at VGS = 0V
Rev. A, April 2022
7
10000
60
Coss
100
50
DC Drain Current, ID (A)
Capacitance, C (pF)
Ciss
1000
10
40
30
20
10
Crss
0
1
0
-75 -50 -25 0 25 50 75 100 125 150 175
Case Temperature, TC (°C)
200 400 600 800 1000 1200
Drain-Source Voltage, VDS (V)
Figure 13. Typical capacitances at f = 100kHz and VGS =
0V
Figure 14. DC drain current derating
1
350
Thermal Impedance, ZqJC (°C/W)
Power Dissipation, Ptot (W)
400
300
250
200
150
100
50
0
-75 -50 -25 0 25 50 75 100 125 150 175
Case Temperature, TC (°C)
Figure 15. Total power dissipation
Datasheet: UF4SC120030K4S
0.1
0.01
D = 0.5
D = 0.3
D = 0.1
D = 0.05
D = 0.02
D = 0.01
Single Pulse
0.001
1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00
Pulse Time, tp (s)
Figure 16. Maximum transient thermal impedance
Rev. A, April 2022
8
350
300
1ms
250
10ms
10
100ms
1
DC
Qrr (nC)
Drain Current, ID (A)
100
200
150
50
10ms
0.1
1
0
10
100
1000
Drain-Source Voltage, VDS (V)
0
Figure 17. Safe operation area at TC = 25°C, D = 0,
Parameter tp
Snubber RS Energy (mJ)
Switching Energy (mJ)
6
VGS = 0V/15V, RG_ON=1W,
RG_OFF=18W, Snubber: Rs=10W,
Cs=47pF FWD: same device with
VGS = 0V, RG = 18W
1000
Etot
Eon
Eoff
750
25
500
250
0
5
4
3
2
Etot
Eon
Eoff
0
10
20
30
40
50
Drain Current, ID (A)
60
70
Figure 19. Clamped inductive switching energy vs.
drain current at VDS = 800V and TJ = 25°C
Datasheet: UF4SC120030K4S
175
VGS = 0V/15V, RG_ON=1W,
RG_OFF=18W, Snubber: Rs=10W,
Cs=47pF FWD: same device with
VGS = 0V, RG = 18W
1
0
50
75 100 125 150
Junction Temperature, TJ (°C)
Figure 18. Reverse recovery charge Qrr vs. junction
temperature at VDS = 800V
1500
1250
IS = 30A,
di/dt = 1840A/ms,
VGS = 0V, RG =18W
100
1ms
0
10
20
30
40
50
Drain Current, ID (A)
60
70
Figure 20. RC snubber energy losses vs. drain current at
VDS = 800V, ID = 30A, and TJ = 25°C
Rev. A, April 2022
9
700
2
Eon
Eoff
500
Snubber Rs Energy (mJ)
Switching Energy (mJ)
600
Eon
Eoff
400
VGS = 0V/15V, Snubber:
Rs=10W, Cs=47pF, FWD: same
device with VGS = 0V
300
200
1.5
1
VGS = 0V/15V, Snubber:
Rs=10W, Cs=47pF: FWD: same
device with VGS = 0V
100
0
0.5
0
10
20
30
External RG, RG_EXT (W)
40
50
Figure 21. Clamped inductive switching energies vs.
RG,EXT at VDS = 800V, ID =30A, and TJ = 25°C
800
Snubber Energy (mJ)
Switching Energy (mJ)
600
500
400
VGS = 0V/15V, RG_ON=1W, RG_OFF=18W,
Snubber: Rs=10W, Cs=47pF FWD: same
device with VGS = 0V, RG = 18W
300
200
10
20
30
External RG, RG_EXT (W)
40
50
Figure 22. RC snubber energy losses vs. RG,EXT at VDS =
800V, ID = 30A, and TJ = 25°C
80
Etot
Eon
Eoff
700
0
VGS = 0V/15V, RG_ON=1W,
RG_OFF=18W, Snubber: Rs=10W,
Cs=47pF, FWD: same device
with VGS = 0V, RG = 18W
60
Rs_Etot
Rs_Eon
Rs_Eoff
40
20
100
0
0
0
50
100 150 200 250 300 350 400
Snubber Capacitance, Cs (pF)
Figure 23. Clamped inductive switching energies vs.
snubber capacitance CS at VDS = 800V, ID = 30A, and
TJ = 25°C
Datasheet: UF4SC120030K4S
0
50
100 150 200 250 300 350 400
Snubber Capacitance, Cs (pF)
Figure 24. RC snubber energy losses vs. snubber
capacitance CS at VDS = 800V, ID =30A, and TJ = 25°C
Rev. A, April 2022
10
Switching Energy (mJ)
700
Etot
Eon
Eoff
600
500
400
VGS = 0V/15V, RG_ON=1W, RG_OFF=18W,
Snubber: Rs=10W, Cs=47pF FWD: same
device with VGS = 0V, RG = 18W
300
200
100
0
0
25
50
75 100 125 150
Junction Temperature, TJ (°C)
175
Figure 25. Clamped inductive switching energy vs.
junction temperature at VDS =800V and ID =30A
Datasheet: UF4SC120030K4S
Figure 26. Schematic of the half-bridge mode switching
test circuit. Note, a bus RC snubber (RBS = 2.5W,
CBS=100nF) is used to reduce the power loop high
frequency oscillations.
Rev. A, April 2022
11
Applications Information
SiC FETs are enhancement-mode power switches formed by a high-voltage SiC depletion-mode JFET and a low-voltage silicon MOSFET
connected in series. The silicon MOSFET serves as the control unit while the SiC JFET provides high voltage blocking in the off state. This
combination of devices in a single package provides compatibility with standard gate drivers and offers superior performance in terms of low
on-resistance (RDS(on)), output capacitance (Coss), gate charge (QG), and reverse recovery charge (Qrr) leading to low conduction and switching
losses. The SiC FETs also provide excellent reverse conduction capability eliminating the need for an external anti-parallel diode.
Like other high performance power switches, proper PCB layout design to minimize circuit parasitics is strongly recommended due to the high
dv/dt and di/dt rates. An external gate resistor is recommended when the FET is working in the diode mode in order to achieve the optimum
reverse recovery performance. For more information on SiC FET operation, see www.unitedsic.com.
A snubber circuit with a small R(G), or gate resistor, provides better EMI suppression with higher efficiency compared to using a high R(G) value.
There is no extra gate delay time when using the snubber circuitry, and a small R(G) will better control both the turn-off V(DS) peak spike and
ringing duration, while a high R(G) will damp the peak spike but result in a longer delay time. In addition, the total switching loss when using a
snubber circuit is less than using high R(G), while greatly reducing E(OFF) from mid-to-full load range with only a small increase in E(ON). Efficiency
will therefore improve with higher load current. For more information on how a snubber circuit will improve overall system performance, visit
the UnitedSiC website at www.unitedsic.com
Important notice
The information contained herein is believed to be reliable; however, Qorvo makes no warranties regarding the information contained herein
and assumes no responsibility or liability whatsoever for the use of the information contained herein. All information contained herein is
subject to change without notice. Customers should obtain and verify the latest relevant information before placing orders for Qorvo
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rights, licenses, or any other intellectual property rights, whether with regard to such information itself or anything described by such
information. THIS INFORMATION DOES NOT CONSTITUTE A WARRANTY WITH RESPECT TO THE PRODUCTS DESCRIBED HEREIN,
AND QORVO HEREBY DISCLAIMS ANY AND ALL WARRANTIES WITH RESPECT TO SUCH PRODUCTS WHETHER EXPRESS OR IMPLIED
BY LAW, COURSE OF DEALING, COURSE OF PERFORMANCE, USAGE OF TRADE OR OTHERWISE, INCLUDING THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Without limiting the generality of the foregoing,
Qorvo products are not warranted or authorized for use as critical components in medical, life-saving, or life-sustaining applications, or other
applications where a failure would reasonably be expected to cause severe personal injury or death.
Datasheet: UF4SC120030K4S
Rev. A, April 2022
12