UJ3C065030K3S

650V-27mW SiC FET Rev. D, December 2019 DATASHEET Description UJ3C065030K3S CASE CASE D (2) This SiC FET device is based on a unique ‘cascode’ circuit configuration, in which a normally-on SiC JFET is co-packaged with a Si MOSFET to produce a normally-off SiC FET device. The device’s standard gate-drive characteristics allows for a true “drop-in replacement” to Si IGBTs, Si FETs, SiC MOSFETs or Si superjunction devices. Available in the TO-247-3L package, this device exhibits ultralow gate charge and exceptional reverse recovery characteristics, making it ideal for switching inductive loads and any application requiring standard gate drive. Features w Typical on-resistance RDS(on),typ of 27mW w Maximum operating temperature of 175°C G (1) w Excellent reverse recovery w Low gate charge w Low intrinsic capacitance 1 2 3 w ESD protected, HBM class 2 S (3) Typical applications Part Number Package Marking UJ3C065030K3S TO-247-3L UJ3C065030K3S w EV charging w PV inverters w Switch mode power supplies w Power factor correction modules w Motor drives w Induction heating Datasheet: UJ3C065030K3S Rev. D, December 2019 1 Maximum Ratings Parameter Symbol VDS VGS Drain-source voltage Gate-source voltage Continuous drain current 1 ID Pulsed drain current 2 Single pulsed avalanche energy 3 Power dissipation Maximum junction temperature Operating and storage temperature IDM EAS Ptot TJ,max TJ, TSTG Max. lead temperature for soldering, 1/8” from case for 5 seconds TL Test Conditions DC TC = 25°C TC = 100°C TC = 25°C L=15mH, IAS =4A TC = 25°C Value Units 650 -25 to +25 85 62 230 120 441 175 -55 to 175 V V A A A mJ W °C °C 250 °C 1. Limited by TJ,max 2. Pulse width tp limited by TJ,max 3. Starting TJ = 25°C Thermal Characteristics Parameter Thermal resistance, junction-to-case Datasheet: UJ3C065030K3S Symbol Test Conditions RqJC Rev. D, December 2019 Value Min Typ Max 0.26 0.34 Units °C/W 2 Electrical Characteristics (TJ = +25°C unless otherwise specified) Typical Performance - Static Parameter Drain-source breakdown voltage Total drain leakage current Total gate leakage current Drain-source on-resistance Gate threshold voltage Gate resistance Symbol Test Conditions BVDS VGS=0V, ID=1mA IDSS IGSS RDS(on) VG(th) RG Value Min Typ Max 650 V VDS=650V, VGS=0V, TJ=25°C 6 VDS=650V, VGS=0V, TJ=175°C 30 VDS=0V, TJ=25°C, VGS=-20V / +20V 6 20 VGS=12V, ID=50A, TJ=25°C 27 35 VGS=12V, ID=50A, TJ=125°C VGS=12V, ID=50A, TJ=175°C VDS=5V, ID=10mA Units 150 mA mA mW 35 43 4 f=1MHz, open drain 5 4.5 6 V W Typical Performance - Reverse Diode Parameter Diode continuous forward current 1 Diode pulse current 2 Forward voltage Test Conditions IS TC=25°C 85 A IS,pulse TC=25°C 230 A VFSD Reverse recovery charge Qrr Reverse recovery time trr Datasheet: UJ3C065030K3S Value Symbol Min Typ VGS=0V, IF=20A, TJ=25°C 1.3 VGS=0V, IF=20A, TJ=175°C 1.35 VR=400V, IF=50A, VGS=0V, RG_EXT=20W di/dt=1550A/ms, TJ=150°C Rev. D, December 2019 Max Units 1.4 V 400 nC 33 ns 3 Typical Performance - Dynamic Parameter Value Symbol Test Conditions Ciss Coss Crss VDS=100V, VGS=0V f=100kHz 1500 320 2.3 pF Effective output capacitance, energy related Coss(er) VDS=0V to 400V, VGS=0V 230 pF Effective output capacitance, time related Coss(tr) VDS=0V to 400V, VGS=0V 520 pF COSS stored energy Eoss VDS=400V, VGS=0V 18.5 mJ Total gate charge Gate-drain charge Gate-source charge QG QGD QGS VDS=400V, ID=50A, VGS = -5V to15V 51 11 19 nC Turn-on delay time td(on) Input capacitance Output capacitance Reverse transfer capacitance Rise time Turn-off delay time Fall time tr td(off) tf Turn-on energy EON Turn-off energy EOFF Total switching energy Datasheet: UJ3C065030K3S ETOTAL Min Typ Max Units 44 VDS=400V, ID=50A, Gate Driver =-5V to +15V, Turn-on RG,EXT=1W, Turn-off RG,EXT=20W Inductive Load, FWD: UJ3D065030TS, TJ=150°C Rev. D, December 2019 26 63 ns 17 657 330 mJ 987 4 200 200 150 150 Drain Current, ID (A) Drain Current, ID (A) Typical Performance Diagrams Vgs = 15V 100 Vgs = 10V Vgs = 8V Vgs = 7.5V 50 Vgs = 7V 100 Vgs = 15V Vgs = 10V Vgs = 8V 50 Vgs = 7V Vgs = 6.5V Vgs = 6.5V 0 0 0 1 2 3 4 5 6 7 8 Drain-Source Voltage, VDS (V) 9 10 Figure 1. Typical output characteristics at TJ = - 55°C, tp < 250ms 100 2 3 4 5 6 7 8 9 Drain-Source Voltage, VDS (V) 10 2.0 Vgs = 15V Vgs = 10V Vgs = 8V Vgs = 7V Vgs = 6.5V Vgs = 6V 150 1 Figure 2. Typical output characteristics at TJ = 25°C, tp < 250ms On Resistance, RDS_ON (P.U.) Drain Current, ID (A) 200 0 50 1.5 1.0 0.5 0.0 0 0 1 2 3 4 5 6 7 8 Drain-Source Voltage, VDS (V) 9 Figure 3. Typical output characteristics at TJ = 175°C, tp < 250ms Datasheet: UJ3C065030K3S -75 -50 -25 0 25 50 75 100 125 150 175 Junction Temperature, TJ (°C) 10 Figure 4. Normalized on-resistance vs. temperature at VGS = 12V and ID = 50A Rev. D, December 2019 5 150 Tj = 175°C Tj = 25°C Tj = - 55°C 80 60 40 20 Tj = 25°C Tj = 175°C 100 75 50 25 0 0 0 25 50 75 100 Drain Current, ID (A) 125 150 Figure 5. Typical drain-source on-resistances at VGS = 12V 0 2 3 4 5 6 7 8 Gate-Source Voltage, VGS (V) 9 10 Gate-Source Voltage, VGS (V) 20 5 4 3 2 1 0 -100 1 Figure 6. Typical transfer characteristics at VDS = 5V 6 Threshold Voltage, Vth (V) Tj = -55°C 125 Drain Current, ID (A) On-Resistance, RDS(on) (mW) 100 15 10 5 0 -5 -50 0 50 100 150 Junction Temperature, TJ (°C) Figure 7. Threshold voltage vs. junction temperature at VDS = 5V and ID = 10mA Datasheet: UJ3C065030K3S 0 200 10 20 30 40 Gate Charge, QG (nC) 50 60 Figure 8. Typical gate charge at VDS = 400V and ID = 50A Rev. D, December 2019 6 0 0 Vgs = - 5V Vgs = 0V -25 Drain Current, ID (A) Drain Current, ID (A) Vgs = -5V Vgs = 5V Vgs = 8V -50 -75 -100 Vgs = 0V -25 Vgs = 5V Vgs = 8V -50 -75 -100 -4 -3 -2 -1 Drain-Source Voltage, VDS (V) 0 Figure 9. 3rd quadrant characteristics at TJ = -55°C -4 -3 -2 -1 Drain-Source Voltage, VDS (V) 0 Figure 10. 3rd quadrant characteristics at TJ = 25°C 0 45 35 -25 30 -50 EOSS (mJ) Drain Current, ID (A) 40 Vgs = - 5V -75 25 20 Vgs = 0V 15 Vgs = 5V 10 Vgs = 8V 5 0 -100 -4 -3 -2 -1 Drain-Source Voltage, VDS (V) Figure 11. 3rd quadrant characteristics at TJ = 175°C Datasheet: UJ3C065030K3S 0 0 100 200 300 400 500 Drain-Source Voltage, VDS (V) 600 Figure 12. Typical stored energy in COSS at VGS = 0V Rev. D, December 2019 7 10,000 100 DC Drain Current, ID (A) Capacitance, C (pF) Ciss 1,000 Coss 100 10 Crss 80 60 40 20 0 1 0 100 200 300 400 500 Drain-Source Voltage, VDS (V) -75 -50 -25 0 25 50 75 100 125 150 175 Case Temperature, TC (°C) 600 Figure 13. Typical capacitances at f = 100kHz and VGS = 0V Figure 14. DC drain current derating Thermal Impedance, ZqJC (°C/W) Power Dissipation, Ptot (W) 500 400 300 200 100 0 -75 -50 -25 0 25 50 75 100 125 150 175 Case Temperature, TC (°C) Figure 15. Total power dissipation Datasheet: UJ3C065030K3S 0.1 0.01 D = 0.5 D = 0.3 D = 0.1 D = 0.05 D = 0.02 D = 0.01 Single Pulse 0.001 1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 Pulse Time, tp (s) Figure 16. Maximum transient thermal impedance Rev. D, December 2019 8 1200 10ms 10 100ms 1ms 1 DC Switching Energy (mJ) Drain Current, ID (A) 100 10ms 1000 800 Etot Eon Eoff 600 400 200 0.1 0 1 10 100 1000 Drain-Source Voltage, VDS (V) 0 Figure 17. Safe operation area at TC = 25°C, D = 0, Parameter tp 10 20 30 40 Drain Current, ID (A) 50 60 Figure 18. Clamped inductive switching energy vs. drain current at TJ = 150°C 800 1000 800 Turn-Off Energy, Eoff (mJ) Turn-on Energy, Eon (mJ) VDS = 400V, VGS = -5V/15V RG_ON=1W, RG_OFF=20W, FWD: UJ3D06530TS 1ms 600 VDS = 400V, ID = 50A, VGS = -5V/15V, TJ = 150°C FWD: UJ3D065030TS 400 200 VDS = 400V, ID = 50A, VGS = -5V/15V, TJ = 150°C FWD: UJ3D065030TS 600 400 200 0 0 0 5 10 15 Total External Turn-on RG, RG_EXT (W) Figure 19. Clamped inductive switching turn-on energy vs. RG,EXT_ON Datasheet: UJ3C065030K3S 0 20 20 40 60 80 Total External Turn-off RG, RG,EXT (W) 100 Figure 20. Clamped inductive switching turn-off energy vs. RG,EXT_OFF Rev. D, December 2019 9 Switching Energy (mJ) 1200 1000 Etot Eon Eoff 800 600 400 VGS = -5V/15V, RG_ON = 1W, RG_OFF = 20W, FWD: UJ3D065030TS 200 0 0 25 50 75 100 125 150 Junction Temperature, TJ (°C) 175 Figure 21. Clamped inductive switching energy vs. junction temperature at VDS =400V and ID = 50A Applications Information SiC FETs are enhancement-mode power switches formed by a highvoltage SiC depletion-mode JFET and a low-voltage silicon MOSFET connected in series. The silicon MOSFET serves as the control unit while the SiC JFET provides high voltage blocking in the off state. This combination of devices in a single package provides compatibility with standard gate drivers and offers superior performance in terms of low on-resistance (RDS(on)), output capacitance (Coss), gate charge (QG), and reverse recovery charge (Qrr) leading to low conduction and switching losses. The SiC FETs also provide excellent reverse conduction capability eliminating the need for an external anti-parallel diode. Information on all products and contained herein is intended for description only. No license, express or implied, to any intellectual property rights is granted within this document. UnitedSiC assumes no liability whatsoever relating to the choice, selection or use of the UnitedSiC products and services described herein. Like other high performance power switches, proper PCB layout design to minimize circuit parasitics is strongly recommended due to the high dv/dt and di/dt rates. An external gate resistor is recommended when the FET is working in the diode mode in order to achieve the optimum reverse recovery performance. For more information on SiC FET operation, see www.unitedsic.com. Disclaimer UnitedSiC reserves the right to change or modify any of the products and their inherent physical and technical specifications without prior notice. UnitedSiC assumes no responsibility or liability for any errors or inaccuracies within. Datasheet: UJ3C065030K3S Rev. D, December 2019 10