1200V-70mW SiC FET
Rev. B, December 2019
DATASHEET
Description
UJ3C120070K3S
CASE
CASE
D (2)
This SiC FET device is based on a unique ‘cascode’ circuit
configuration, in which a normally-on SiC JFET is co-packaged with a Si
MOSFET to produce a normally-off SiC FET device. The device’s
standard gate-drive characteristics allows for a true “drop-in
replacement” to Si IGBTs, Si FETs, SiC MOSFETs or Si superjunction
devices. Available in the TO-247-3L package, this device exhibits ultralow gate charge and exceptional reverse recovery characteristics,
making it ideal for switching inductive loads, and any application
requiring standard gate drive.
Features
w Typical on-resistance RDS(on),typ of 70mW
G (1)
w Maximum operating temperature of 175°C
w Excellent reverse recovery
w Low gate charge
1
w Low intrinsic capacitance
2 3
S (3)
w ESD protected, HBM class 2
Typical applications
Part Number
Package
Marking
UJ3C120070K3S
TO-247-3L
UJ3C120070K3S
w EV charging
w PV inverters
w Switch mode power supplies
w Power factor correction modules
w Motor drives
w Induction heating
Datasheet: UJ3C120070K3S
Rev. B, December 2019
1
Maximum Ratings
Parameter
Symbol
VDS
VGS
Drain-source voltage
Gate-source voltage
Continuous drain current 1
ID
Pulsed drain current 2
Single pulsed avalanche energy 3
Power dissipation
Maximum junction temperature
Operating and storage temperature
IDM
EAS
Ptot
TJ,max
TJ, TSTG
Max. lead temperature for soldering,
1/8” from case for 5 seconds
TL
Test Conditions
DC
TC = 25°C
TC = 100°C
TC = 25°C
L=15mH, IAS =2.8A
TC = 25°C
Value
Units
1200
-25 to +25
34.5
25.5
80
58.5
254.2
175
-55 to 175
V
V
A
A
A
mJ
W
°C
°C
250
°C
1. Limited by TJ,max
2. Pulse width tp limited by TJ,max
3. Starting TJ = 25°C
Thermal Characteristics
Parameter
Thermal resistance, junction-to-case
Datasheet: UJ3C120070K3S
Symbol
Test Conditions
RqJC
Rev. B, December 2019
Value
Min
Typ
Max
0.45
0.59
Units
°C/W
2
Electrical Characteristics (TJ = +25°C unless otherwise specified)
Typical Performance - Static
Parameter
Drain-source breakdown voltage
Total drain leakage current
Total gate leakage current
Drain-source on-resistance
Gate threshold voltage
Gate resistance
Symbol
Test Conditions
BVDS
VGS=0V, ID=1mA
IDSS
IGSS
RDS(on)
VG(th)
RG
Value
Min
Typ
Max
1200
V
VDS=1200V,
VGS=0V, TJ=25°C
0.5
VDS=1200V,
VGS=0V, TJ=175°C
7
VDS=0V, TJ=25°C,
VGS=-20V / +20V
6
20
VGS=12V, ID=20A,
TJ=25°C
70
90
VGS=12V, ID=20A,
TJ=175°C
VDS=5V, ID=10mA
Units
75
mA
mA
mW
148
4
f=1MHz, open drain
5
4.5
6
V
W
Typical Performance - Reverse Diode
Parameter
Diode continuous forward current 1
Diode pulse current
2
Forward voltage
Test Conditions
IS
TC=25°C
34.5
A
IS,pulse
TC=25°C
80
A
VFSD
Reverse recovery charge
Qrr
Reverse recovery time
trr
Reverse recovery charge
Qrr
Reverse recovery time
trr
Datasheet: UJ3C120070K3S
Value
Symbol
Min
Typ
VGS=0V, IF=10A,
TJ=25°C
1.41
VGS=0V, IF=10A,
TJ=175°C
1.9
VR=800V, IF=20A,
VGS=-5V, RG_EXT=22W
di/dt=1150A/ms,
TJ=25°C
VR=800V, IF=20A,
VGS=-5V, RG_EXT=22W
di/dt=1150A/ms,
TJ=150°C
Rev. B, December 2019
Max
Units
2
V
125
nC
38
ns
131
nC
38
ns
3
Typical Performance - Dynamic
Parameter
Value
Symbol
Test Conditions
Ciss
Coss
Crss
VDS=100V, VGS=0V
f=100kHz
1500
114
2.1
pF
Effective output capacitance, energy
related
Coss(er)
VDS=0V to 800V,
VGS=0V
63
pF
Effective output capacitance, time
related
Coss(tr)
VDS=0V to 800V,
VGS=0V
128
pF
COSS stored energy
Eoss
VDS=800V, VGS=0V
20
mJ
Total gate charge
Gate-drain charge
Gate-source charge
QG
QGD
QGS
VDS=800V, ID=20A,
VGS = -5V to 15V
46
7
19
nC
Turn-on delay time
td(on)
Input capacitance
Output capacitance
Reverse transfer capacitance
Rise time
Turn-off delay time
Fall time
tr
td(off)
tf
Turn-on energy
EON
Turn-off energy
EOFF
Total switching energy
Turn-on delay time
Rise time
Turn-off delay time
Fall time
ETOTAL
td(on)
tr
td(off)
tf
Turn-on energy
EON
Turn-off energy
EOFF
Total switching energy
Datasheet: UJ3C120070K3S
ETOTAL
VDS=800V, ID=20A, Gate
Driver =-5V to +15V,
Turn-on RG,EXT=1W,
Turn-off RG,EXT=22W
Inductive Load,
FWD: same device with
VGS = -5V, RG = 22W,
TJ=25°C
VDS=800V, ID=20A, Gate
Driver =-5V to +15V,
Turn-on RG,EXT=1W,
Turn-off RG,EXT=22W
Inductive Load,
FWD: same device with
VGS = -5V, RG = 22W,
TJ=150°C
Rev. B, December 2019
Min
Typ
Max
Units
38
17
58
ns
9
569
37
mJ
606
35
17
59
ns
10
557
43
mJ
600
4
60
60
50
50
Drain Current, ID (A)
Drain Current, ID (A)
Typical Performance Diagrams
40
Vgs = 15V
30
Vgs = 8V
Vgs = 7V
20
Vgs = 6.5V
Vgs = 6V
10
Vgs = 15V
30
Vgs = 8V
20
Vgs = 7V
Vgs = 6.5V
10
0
Vgs = 6V
0
0
1
2
3
4
5
6
7
8
Drain-Source Voltage, VDS (V)
9
10
Figure 1. Typical output characteristics at TJ = - 55°C,
tp < 250ms
60
30
1
2
3
4
5
6
7
8
9
Drain-Source Voltage, VDS (V)
10
Figure 2. Typical output characteristics at TJ = 25°C,
tp < 250ms
On Resistance, RDS_ON (P.U.)
40
0
2.5
Vgs = 15V
Vgs = 8V
Vgs = 7V
Vgs = 6V
Vgs = 5.5V
Vgs = 5V
50
Drain Current, ID (A)
40
20
10
2.0
1.5
1.0
0.5
0.0
0
0
1
2
3
4
5
6
7
8
Drain-Source Voltage, VDS (V)
9
Figure 3. Typical output characteristics at TJ = 175°C,
tp < 250ms
Datasheet: UJ3C120070K3S
-75 -50 -25 0 25 50 75 100 125 150 175
Junction Temperature, TJ (°C)
10
Figure 4. Normalized on-resistance vs. temperature
at VGS = 12V and ID = 20A
Rev. B, December 2019
5
60
Tj = 175°C
Tj = 25°C
Tj = - 55°C
250
200
150
100
50
Tj = 25°C
Tj = 175°C
40
30
20
10
0
0
0
10
20
30
40
Drain Current, ID (A)
50
60
Figure 5. Typical drain-source on-resistances at VGS =
12V
0
2 3 4 5 6 7 8
Gate-Source Voltage, VGS (V)
9
10
Gate-Source Voltage, VGS (V)
20
5
4
3
2
1
0
-100
1
Figure 6. Typical transfer characteristics at VDS = 5V
6
Threshold Voltage, Vth (V)
Tj = -55°C
50
Drain Current, ID (A)
On-Resistance, RDS(on) (mW)
300
15
10
5
0
-5
-50
0
50
100
150
Junction Temperature, TJ (°C)
Figure 7. Threshold voltage vs. junction temperature
at VDS = 5V and ID = 10mA
Datasheet: UJ3C120070K3S
0
200
10
20
30
40
Gate Charge, QG (nC)
50
60
Figure 8. Typical gate charge at VDS = 800V and ID =
20A
Rev. B, December 2019
6
0
0
Vgs = -5V
Vgs = 0V
Vgs = 5V
-10
Vgs = - 5V
-5
Drain Current, ID (A)
Drain Current, ID (A)
-5
Vgs = 8V
-15
-20
-25
Vgs = 0V
Vgs = 5V
-10
Vgs = 8V
-15
-20
-25
-30
-30
-4
-3
-2
-1
Drain-Source Voltage, VDS (V)
0
Figure 9. 3rd quadrant characteristics at TJ = -55°C
-4
-3
-2
-1
Drain-Source Voltage, VDS (V)
0
Figure 10. 3rd quadrant characteristics at TJ = 25°C
0
40
30
-10
-15
EOSS (mJ)
Drain Current, ID (A)
-5
Vgs = - 5V
20
Vgs = 0V
-20
10
Vgs = 5V
-25
Vgs = 8V
0
-30
-4
-3
-2
-1
Drain-Source Voltage, VDS (V)
Figure 11. 3rd quadrant characteristics at TJ = 175°C
Datasheet: UJ3C120070K3S
0
0
200
400
600
800 1000
Drain-Source Voltage, VDS (V)
1200
Figure 12. Typical stored energy in COSS at VGS = 0V
Rev. B, December 2019
7
1.E+04
40
35
DC Drain Current, ID (A)
Capacitance, C (pF)
Ciss
1.E+03
1.E+02
Coss
1.E+01
Crss
30
25
20
15
10
5
0
1.E+00
0
-75 -50 -25 0 25 50 75 100 125 150 175
Case Temperature, TC (°C)
200 400 600 800 1000 1200
Drain-Source Voltage, VDS (V)
Figure 13. Typical capacitances at f = 100kHz and VGS
= 0V
Figure 14. DC drain current derating
1
Thermal Impedance, ZqJC (°C/W)
Power Dissipation, Ptot (W)
300
250
200
150
100
50
0
-75 -50 -25 0 25 50 75 100 125 150 175
Case Temperature, TC (°C)
Figure 15. Total power dissipation
Datasheet: UJ3C120070K3S
0.1
0.01
D = 0.5
D = 0.3
D = 0.1
D = 0.05
D = 0.02
D = 0.01
Single Pulse
0.001
1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01
Pulse Time, tp (s)
Figure 16. Maximum transient thermal impedance
Rev. B, December 2019
8
1400
100
10
10ms
100ms
1
Switching Energy (mJ)
Drain Current, ID (A)
1ms
1ms
DC
1000
800
Etot
Eon
Eoff
600
400
200
10ms
0
0.1
1
0
10
100
1000
Drain-Source Voltage, VDS (V)
Figure 17. Safe operation area at TC = 25°C, D = 0,
Parameter tp
700
140
600
120
500
400
300
VDS = 800V, VGS = -5V/15V
ID = 20A, TJ = 25°C
FWD: same device with VGS = -5V,
RG = 22W
200
100
5
10
15
20
25
Drain Current, ID (A)
30
35
Figure 18. Clamped inductive switching energy vs.
drain current at TJ = 25°C
Turn-Off Energy, EOFF (mJ)
Turn-on Energy, EON (mJ)
VDS = 800V, VGS = -5V/15V
RG_ON = 1W, RG_OFF = 22W
FWD: same device with VGS = 5V, RG = 22W
1200
VDS = 800V, VGS = -5V/15V
ID = 20A, TJ =25°C
FWD: same device with VGS =
-5V, RG = 22W
100
80
60
40
20
0
0
0
5
10
15
Total External RG, RG,EXT_ON (W)
Figure 19. Clamped inductive switching turn-on
energy vs. RG,EXT_ON
Datasheet: UJ3C120070K3S
0
20
20
40
60
80
Total External RG, RG,EXT_OFF (W)
100
Figure 20. Clamped inductive switching turn-off
energy vs. RG,EXT_OFF
Rev. B, December 2019
9
200
600
150
500
Etot
Eon
Eoff
400
300
Qrr (nC)
Switching Energy (mJ)
700
VGS = -5V/15V, RG_ON =1W, RG_OFF =
22W, FWD: same device with VGS =
-5V, RG = 22W
200
100
100
VDS = 800V, IS = 20A,
di/dt = 1150A/ms,
VGS = -5V, RG =22W
50
0
0
0
25
50
75 100 125 150
Junction Temperature, TJ (°C)
175
Figure 21. Clamped inductive switching energy vs.
junction temperature at VDS = 800V and ID = 20A
0
25
50
75 100 125 150
Junction Temperature, TJ (°C)
175
Figure 22. Reverse recovery charge Qrr vs. junction
temperature
Applications Information
SiC FETs are enhancement-mode power switches formed by a highvoltage SiC depletion-mode JFET and a low-voltage silicon MOSFET
connected in series. The silicon MOSFET serves as the control unit
while the SiC JFET provides high voltage blocking in the off state. This
combination of devices in a single package provides compatibility with
standard gate drivers and offers superior performance in terms of low
on-resistance (RDS(on)), output capacitance (Coss), gate charge (QG), and
reverse recovery charge (Qrr) leading to low conduction and switching
losses. The SiC FETs also provide excellent reverse conduction
capability eliminating the need for an external anti-parallel diode.
Information on all products and contained herein is intended for
description only. No license, express or implied, to any intellectual
property rights is granted within this document.
UnitedSiC assumes no liability whatsoever relating to the choice,
selection or use of the UnitedSiC products and services described
herein.
Like other high performance power switches, proper PCB layout
design to minimize circuit parasitics is strongly recommended due to
the high dv/dt and di/dt rates. An external gate resistor is
recommended when the FET is working in the diode mode in order to
achieve the optimum reverse recovery performance. For more
information on SiC FET operation, see www.unitedsic.com.
Disclaimer
UnitedSiC reserves the right to change or modify any of the products
and their inherent physical and technical specifications without prior
notice. UnitedSiC assumes no responsibility or liability for any errors
or inaccuracies within.
Datasheet: UJ3C120070K3S
Rev. B, December 2019
10