UJ3C120150K3S

1200V-150mW SiC FET Rev. C, December 2019 DATASHEET Description UJ3C120150K3S CASE CASE D (2) This SiC FET device is based on a unique ‘cascode’ circuit configuration, in which a normally-on SiC JFET is co-packaged with a Si MOSFET to produce a normally-off SiC FET device. The device’s standard gate-drive characteristics allows for a true “drop-in replacement” to Si IGBTs, Si FETs, SiC MOSFETs or Si superjunction devices. Available in the TO-247-3L package, this device exhibits ultralow gate charge and exceptional reverse recovery characteristics, making it ideal for switching inductive loads, and any application requiring standard gate drive. Features w Typical on-resistance RDS(on),typ of 150mW w Maximum operating temperature of 175°C G (1) w Excellent reverse recovery w Low gate charge w Low intrinsic capacitance 1 w ESD protected, HBM class 2 2 3 S (3) Typical applications Part Number Package Marking w EV charging UJ3C120150K3S TO-247-3L UJ3C120150K3S w PV inverters w Switch mode power supplies w Power factor correction modules w Motor drives w Induction heating Datasheet: UJ3C120150K3S Rev. C, December 2019 1 Maximum Ratings Parameter Symbol VDS VGS Drain-source voltage Gate-source voltage Continuous drain current 1 ID Pulsed drain current 2 Single pulsed avalanche energy 3 Power dissipation Maximum junction temperature Operating and storage temperature IDM EAS Ptot TJ,max TJ, TSTG Max. lead temperature for soldering, 1/8” from case for 5 seconds TL Test Conditions DC TC = 25°C TC = 100°C TC = 25°C L=15mH, IAS =2A TC = 25°C Value Units 1200 -25 to +25 18.4 13.8 38 30 166.7 175 -55 to 175 V V A A A mJ W °C °C 250 °C 1. Limited by TJ,max 2. Pulse width tp limited by TJ,max 3. Starting TJ = 25°C Thermal Characteristics Parameter Thermal resistance, junction-to-case Datasheet: UJ3C120150K3S Symbol Test Conditions RqJC Rev. C, December 2019 Value Min Typ Max 0.7 0.9 Units °C/W 2 Electrical Characteristics (TJ = +25°C unless otherwise specified) Typical Performance - Static Parameter Drain-source breakdown voltage Total drain leakage current Total gate leakage current Drain-source on-resistance Gate threshold voltage Gate resistance Symbol Test Conditions BVDS VGS=0V, ID=1mA IDSS IGSS RDS(on) VG(th) RG Value Min Typ Max 1200 V VDS=1200V, VGS=0V, TJ=25°C 2 VDS=1200V, VGS=0V, TJ=175°C 17 VDS=0V, TJ=25°C, VGS=-20V / +20V 4 20 VGS=12V, ID=5A, TJ=25°C 150 180 VGS=12V, ID=5A, TJ=125°C VGS=12V, ID=5A, TJ=175°C VDS=5V, ID=10mA Units 50 mA mA mW 250 330 3.5 f=1MHz, open drain 4.4 4.6 5.5 V W Typical Performance - Reverse Diode Parameter Diode continuous forward current 1 Diode pulse current 2 Forward voltage Test Conditions IS TC=25°C 18.4 A IS,pulse TC=25°C 38 A VFSD Reverse recovery charge Qrr Reverse recovery time trr Datasheet: UJ3C120150K3S Value Symbol Min Typ VGS=0V, IF=5A, TJ=25°C 1.46 VGS=0V, IF=5A, TJ=175°C 2 VR=800V, IF=13A, VGS=0V, RG_EXT=20W di/dt=1700A/ms, TJ=150°C Rev. C, December 2019 Max Units 2 V 63 nC 28 ns 3 Typical Performance - Dynamic Parameter Value Symbol Test Conditions Ciss Coss Crss VDS=100V, VGS=0V f=100kHz 738 58 1.8 pF Effective output capacitance, energy related Coss(er) VDS=0V to 800V, VGS=0V 34 pF Effective output capacitance, time related Coss(tr) VDS=0V to 800V, VGS=0V 68 pF COSS stored energy Eoss VDS=800V, VGS=0V 10.8 mJ Total gate charge Gate-drain charge Gate-source charge QG QGD QGS VDS=800V, ID=13A, VGS = -5V to15V 30 6 10 nC Turn-on delay time td(on) Input capacitance Output capacitance Reverse transfer capacitance Rise time Turn-off delay time Fall time tr td(off) tf Turn-on energy EON Turn-off energy EOFF Total switching energy Datasheet: UJ3C120150K3S ETOTAL VDS=800V, ID=13A, Gate Driver =-5V to +15V, Turn-on RG,EXT=1W, Turn-off RG,EXT=20W Inductive Load, FWD: UJ3D1205TS TJ=150°C Rev. C, December 2019 Min Typ Max Units 21 10 36 ns 7 175 46 mJ 221 4 40 40 30 30 Drain Current, ID (A) Drain Current, ID (A) Typical Performance Diagrams Vgs = 15V Vgs = 7V Vgs = 6.5V Vgs = 6V Vgs = 5.5V 20 10 20 Vgs = 15V Vgs = 7V Vgs = 6.5V 10 Vgs = 6V Vgs = 5.5V 0 0 0 1 2 3 4 5 6 7 8 Drain-Source Voltage, VDS (V) 9 10 Figure 1. Typical output characteristics at TJ = - 55°C, tp < 250ms 0 2 3 4 5 6 7 8 9 Drain-Source Voltage, VDS (V) 10 Figure 2. Typical output characteristics at TJ = 25°C, tp < 250ms 40 2.5 On Resistance, RDS_ON (P.U.) Vgs = 15V Drain Current, ID (A) 1 Vgs = 6V 30 Vgs = 5.5V Vgs = 5V Vgs = 4.5V 20 10 2.0 1.5 1.0 0.5 0.0 0 0 1 2 3 4 5 6 7 8 Drain-Source Voltage, VDS (V) 9 Figure 3. Typical output characteristics at TJ = 175°C, tp < 250ms Datasheet: UJ3C120150K3S -75 -50 -25 0 25 50 75 100 125 150 175 Junction Temperature, TJ (°C) 10 Figure 4. Normalized on-resistance vs. temperature at VGS = 12V and ID = 5A Rev. C, December 2019 5 30 Tj = 175°C Tj = 25°C Tj = - 55°C 600 500 400 300 200 Tj = 25°C Tj = 175°C 20 15 10 5 100 0 0 0 5 10 15 20 25 Drain Current, ID (A) 30 35 Figure 5. Typical drain-source on-resistances at VGS = 12V 0 2 3 4 5 6 7 8 Gate-Source Voltage, VGS (V) 9 10 Gate-Source Voltage, VGS (V) 20 5 4 3 2 1 0 -100 1 Figure 6. Typical transfer characteristics at VDS = 5V 6 Threshold Voltage, Vth (V) Tj = -55°C 25 Drain Current, ID (A) On-Resistance, RDS(on) (mW) 700 15 10 5 0 -5 -50 0 50 100 150 Junction Temperature, TJ (°C) Figure 7. Threshold voltage vs. junction temperature at VDS = 5V and ID = 10mA Datasheet: UJ3C120150K3S 0 200 10 20 30 Gate Charge, QG (nC) 40 Figure 8. Typical gate charge at VDS = 800V and ID = 13A Rev. C, December 2019 6 0 -2 Vgs = -5V -4 Vgs = 5V Vgs = 0V Vgs = 8V -6 -8 -10 -12 Vgs = 0V -4 Vgs = 5V Vgs = 8V -6 -8 -10 -12 -14 -14 -4 -3 -2 -1 Drain-Source Voltage, VDS (V) 0 Figure 9. 3rd quadrant characteristics at TJ = -55°C -4 -3 -2 -1 Drain-Source Voltage, VDS (V) 0 Figure 10. 3rd quadrant characteristics at TJ = 25°C 0 25 -2 20 -4 EOSS (mJ) Drain Current, ID (A) Vgs = - 5V -2 Drain Current, ID (A) Drain Current, ID (A) 0 -6 Vgs = - 5V -8 Vgs = 0V -10 Vgs = 5V 10 5 Vgs = 8V -12 15 0 -14 -4 -3 -2 -1 Drain-Source Voltage, VDS (V) Figure 11. 3rd quadrant characteristics at TJ = 175°C Datasheet: UJ3C120150K3S 0 0 200 400 600 800 1000 Drain-Source Voltage, VDS (V) 1200 Figure 12. Typical stored energy in COSS at VGS = 0V Rev. C, December 2019 7 10,000 20 Ciss 1,000 100 DC Drain Current, ID (A) Capacitance, C (pF) 18 Coss 10 Crss 16 14 12 10 8 6 4 2 0 1 0 -75 -50 -25 0 25 50 75 100 125 150 175 Case Temperature, TC (°C) 200 400 600 800 1000 1200 Drain-Source Voltage, VDS (V) Figure 13. Typical capacitances at f = 100kHz and VGS = 0V Figure 14. DC drain current derating Thermal Impedance, ZqJC (°C/W) Power Dissipation, Ptot (W) 200 150 100 50 0 -75 -50 -25 0 25 50 75 100 125 150 175 Case Temperature, TC (°C) Figure 15. Total power dissipation Datasheet: UJ3C120150K3S 1 0.1 0.01 D = 0.5 D = 0.3 D = 0.1 D = 0.05 D = 0.02 D = 0.01 Single Pulse 0.001 1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 Pulse Time, tp (s) Figure 16. Maximum transient thermal impedance Rev. C, December 2019 8 400 1ms 10ms 100ms Switching Energy (mJ) Drain Current, ID (A) 10 1 1ms DC 300 250 Etot Eon Eoff 200 150 100 50 10ms 0 0.1 1 0 10 100 1000 Drain-Source Voltage, VDS (V) Figure 17. Safe operation area at TC = 25°C, D = 0, Parameter tp 5 10 Drain Current, ID (A) 15 20 Figure 18. Clamped inductive switching energy vs. drain current at TJ = 150°C 300 125 250 Turn-Off Energy, EOFF (mJ) Turn-on Energy, EON (mJ) VDS = 800V, VGS = -5V/15V RG_ON = 1W, RG_OFF = 20W FWD: UJ3D1205TS TJ = 150°C 350 200 150 VDS = 800V, VGS = -5V/15V ID = 13A, TJ = 150°C FWD:UJ3D1205TS 100 50 100 75 50 VDS = 800V, VGS = -5V/15V ID = 13A, TJ = 150°C FWD: UJ3D1205TS 25 0 0 0 5 10 15 Total External RG, RG,EXT_ON (W) Figure 19. Clamped inductive switching turn-on energy vs. RG,EXT_ON Datasheet: UJ3C120150K3S 0 20 20 40 60 80 Total External RG, RG,EXT_OFF (W) 100 Figure 20. Clamped inductive switching turn-off energy vs. RG,EXT_OFF Rev. C, December 2019 9 Switching Energy (mJ) 300 Etot Eon Eoff 250 200 150 VGS = -5V/15V, RG_ON = 1W, RG_OFF = 20W FWD: UJ3D1205TS 100 50 0 0 25 50 75 100 125 150 Junction Temperature, TJ (°C) 175 Figure 21. Clamped inductive switching energy vs. junction temperature at VDS = 800V and ID = 13A Applications Information SiC FETs are enhancement-mode power switches formed by a highvoltage SiC depletion-mode JFET and a low-voltage silicon MOSFET connected in series. The silicon MOSFET serves as the control unit while the SiC JFET provides high voltage blocking in the off state. This combination of devices in a single package provides compatibility with standard gate drivers and offers superior performance in terms of low on-resistance (RDS(on)), output capacitance (Coss), gate charge (QG), and reverse recovery charge (Qrr) leading to low conduction and switching losses. The SiC FETs also provide excellent reverse conduction capability eliminating the need for an external anti-parallel diode. Information on all products and contained herein is intended for description only. No license, express or implied, to any intellectual property rights is granted within this document. UnitedSiC assumes no liability whatsoever relating to the choice, selection or use of the UnitedSiC products and services described herein. Like other high performance power switches, proper PCB layout design to minimize circuit parasitics is strongly recommended due to the high dv/dt and di/dt rates. An external gate resistor is recommended when the FET is working in the diode mode in order to achieve the optimum reverse recovery performance. For more information on SiC FET operation, see www.unitedsic.com. Disclaimer UnitedSiC reserves the right to change or modify any of the products and their inherent physical and technical specifications without prior notice. UnitedSiC assumes no responsibility or liability for any errors or inaccuracies within. Datasheet: UJ3C120150K3S Rev. C, December 2019 10