UJ4C075060K4S

750V-58mW SiC FET Rev. A, October 2020 DATASHEET Description UJ4C075060K4S CASE CASE D (1) The UJ4C075060K4S is a 750V, 58mW G4 SiC FET. It is based on a unique ‘cascode’ circuit configuration, in which a normally-on SiC JFET is co-packaged with a Si MOSFET to produce a normally-off SiC FET device. The device’s standard gate-drive characteristics allows for a true “drop-in replacement” to Si IGBTs, Si FETs, SiC MOSFETs or Si superjunction devices. Available in the TO-247-4L package, this device exhibits ultra-low gate charge and exceptional reverse recovery characteristics, making it ideal for switching inductive loads and any application requiring standard gate drive. Features w On-resistance RDS(on): 58mW (typ) G (4) w Operating temperature: 175°C (max) w Excellent reverse recovery: Qrr = 52nC KS (3) w Low body diode VFSD: 1.31V w Low gate charge: QG = 37.8nC S (2) 1 2 34 w Threshold voltage VG(th): 4.8V (typ) allowing 0 to 15V drive w Low intrinsic capacitance w ESD protected, HBM class 2 w TO-247-4L package for faster switching, clean gate waveforms Part Number Package Marking UJ4C075060K4S TO-247-4L UJ4C075060K4S Typical applications w EV charging w PV inverters w Switch mode power supplies w Power factor correction modules w Motor drives w Induction heating Datasheet: UJ4C075060K4S Rev. A, October 2020 1 Maximum Ratings Parameter Symbol VDS VGS Drain-source voltage Gate-source voltage Continuous drain current 1 ID Pulsed drain current 2 Single pulsed avalanche energy 3 Power dissipation Maximum junction temperature Operating and storage temperature IDM EAS Ptot TJ,max TJ, TSTG Max. lead temperature for soldering, 1/8” from case for 5 seconds TL Test Conditions DC TC = 25°C TC = 100°C TC = 25°C L=15mH, IAS =1.8A TC = 25°C Value Units 750 -20 to +20 28 20.6 62 24.3 155 175 -55 to 175 V V A A A mJ W °C °C 250 °C 1. Limited by TJ,max 2. Pulse width tp limited by TJ,max 3. Starting TJ = 25°C Thermal Characteristics Parameter Thermal resistance, junction-to-case Datasheet: UJ4C075060K4S Symbol Test Conditions RqJC Rev. A, October 2020 Value Min Typ Max 0.75 0.97 Units °C/W 2 Electrical Characteristics (TJ = +25°C unless otherwise specified) Typical Performance - Static Parameter Drain-source breakdown voltage Total drain leakage current Total gate leakage current Drain-source on-resistance Gate threshold voltage Gate resistance Symbol Test Conditions BVDS VGS=0V, ID=1mA IDSS IGSS RDS(on) VG(th) RG Value Min Typ Max 750 V VDS=750V, VGS=0V, TJ=25°C 0.7 VDS=750V, VGS=0V, TJ=175°C 15 VDS=0V, TJ=25°C, VGS=-20V / +20V 4.7 20 VGS=12V, ID=20A, TJ=25°C 58 74 VGS=12V, ID=20A, TJ=125°C VGS=12V, ID=20A, TJ=175°C VDS=5V, ID=10mA Units 40 mA mA mW 106 147 4 f=1MHz, open drain 4.8 4.5 6 V W Typical Performance - Reverse Diode Parameter Diode continuous forward current 1 Diode pulse current 2 Forward voltage Test Conditions IS TC=25°C 28 A IS,pulse TC=25°C 62 A VFSD Reverse recovery charge Qrr Reverse recovery time trr Reverse recovery charge Qrr Reverse recovery time trr Datasheet: UJ4C075060K4S Value Symbol VGS=0V, IF=10A, TJ=25°C VGS=0V, IF=10A, TJ=175°C VR=400V, IF=20A, VGS=0V, RG_EXT=20W di/dt=1060A/ms, TJ=25°C VR=400V, IF=20A, VGS=0V, RG_EXT=20W di/dt=1060A/ms, TJ=150°C Rev. A, October 2020 Min Typ 1.31 Max Units 1.75 V 1.8 52 nC 16 ns 58 nC 19 ns 3 Typical Performance - Dynamic Parameter Value Symbol Test Conditions Ciss Coss Crss VDS=100V, VGS=0V f=100kHz 1422 68 2.7 pF Effective output capacitance, energy related Coss(er) VDS=0V to 400V, VGS=0V 50 pF Effective output capacitance, time related Coss(tr) VDS=0V to 400V, VGS=0V 94 pF COSS stored energy Eoss VDS=400V, VGS=0V 4 mJ Total gate charge Gate-drain charge Gate-source charge QG QGD QGS VDS=400V, ID=20A, VGS = 0V to 15V 37.8 8 11.8 nC Turn-on delay time td(on) Input capacitance Output capacitance Reverse transfer capacitance Rise time Turn-off delay time Fall time tr td(off) tf Turn-on energy EON Turn-off energy EOFF Total switching energy Turn-on delay time Rise time Turn-off delay time Fall time ETOTAL td(on) tr td(off) tf Turn-on energy EON Turn-off energy EOFF Total switching energy ETOTAL Note 4, VDS=400V, ID=20A, Gate Driver =0V to +15V, Turn-on RG,EXT=1W, Turn-off RG,EXT=20W Inductive Load, FWD: same device with VGS = 0V, RG = 20W, TJ=25°C Note 4, VDS=400V, ID=20A, Gate Driver =0V to +15V, Turn-on RG,EXT=1W, Turn-off RG,EXT=20W Inductive Load, FWD: same device with VGS = 0V, RG = 20W, TJ=150°C Min Typ Max Units 12 19 78 ns 12 126 37 mJ 163 12 21 83 ns 14 151 50 mJ 201 4. Measured with the half-bridge mode switching test circuit in Figure 28. Datasheet: UJ4C075060K4S Rev. A, October 2020 4 Typical Performance - Dynamic (continued) Parameter Turn-on delay time Rise time Turn-off delay time Fall time Symbol Test Conditions td(on) tr td(off) tf Turn-on energy including RS energy EON Turn-off energy including RS energy EOFF Value Min Typ Note 5, VDS=400V, ID=20A, Gate Driver =0V to +15V, RG,EXT=1W, inductive Load, FWD: same device with VGS = 0V and RG = 1W, RC snubber: RS1=10W and CS1=95pF, TJ=25°C 22 31 142 17 Snubber RS energy during turn-on ERS_ON Snubber RS energy during turn-off ERS_OFF 1 td(on) 12 Turn-off delay time Fall time tr td(off) tf Turn-on energy including RS energy EON Turn-off energy including RS energy EOFF Total switching energy ETOTAL Snubber RS energy during turn-on ERS_ON Snubber RS energy during turn-off ERS_OFF Turn-on delay time Rise time Turn-off delay time Fall time td(on) tr td(off) tf Turn-on energy EON Turn-off energy EOFF Total switching energy Turn-on delay time Rise time Turn-off delay time Fall time ETOTAL td(on) tr td(off) tf Turn-on energy EON Turn-off energy EOFF Total switching energy ETOTAL Note 5, VDS=400V, ID=20A, Gate Driver =0V to +15V, RG,EXT=1W, inductive Load, FWD: same device with VGS = 0V and RG = 1W, RC snubber: RS1=10W and CS1=95pF, TJ=150°C ns 9 ETOTAL Rise time Units 12 Total switching energy Turn-on delay time Max 159 mJ 0.7 25 35 ns 9 153 18 171 mJ 0.7 1 Note 6, VDS=400V, ID=20A, Gate Driver = 0V to +15V, Turn-on RG,EXT=1W, Turn-off RG,EXT=20W Inductive Load, FWD: UJ3D06510TS TJ=25°C Note 6, VDS=400V, ID=20A, Gate Driver =0V to +15V, Turn-on RG,EXT=1W, Turn-off RG,EXT=20W Inductive Load, FWD:UJ3D06510TS TJ=150°C 12 18 78 ns 12 90 37 mJ 127 12 19 84 ns 15 104 49 mJ 153 5. Measured with the chopper mode switching test circuit in Figure 30. 6. Measured with the chopper mode switching test circuit in Figure 29. Datasheet: UJ4C075060K4S Rev. A, October 2020 5 50 50 40 40 30 Drain Current, ID (A) Drain Current, ID (A) Typical Performance Diagrams Vgs = 15V Vgs = 10V Vgs = 8V 20 Vgs = 7.5V Vgs = 7V 10 Vgs = 6.5V 30 Vgs = 8V Vgs = 7V 10 Vgs = 6.5V Vgs = 6V 0 0 0 1 2 3 4 5 6 7 8 Drain-Source Voltage, VDS (V) 9 10 Figure 1. Typical output characteristics at TJ = - 55°C, tp < 250ms 50 0 2 3 4 5 6 7 8 9 Drain-Source Voltage, VDS (V) 10 3.0 On Resistance, RDS_ON (P.U.) Vgs = 8V Vgs = 6V Vgs = 5.5V 30 1 Figure 2. Typical output characteristics at TJ = 25°C, tp < 250ms Vgs = 15V 40 Drain Current, ID (A) Vgs = 15V 20 Vgs = 5V 20 10 2.5 2.0 1.5 1.0 0.5 0.0 0 0 1 2 3 4 5 6 7 8 Drain-Source Voltage, VDS (V) 9 Figure 3. Typical output characteristics at TJ = 175°C, tp < 250ms Datasheet: UJ4C075060K4S -75 -50 -25 0 25 50 75 100 125 150 175 Junction Temperature, TJ (°C) 10 Figure 4. Normalized on-resistance vs. temperature at VGS = 12V and ID = 20A Rev. A, October 2020 6 30 Tj = 175°C Tj = 25°C Tj = - 55°C 200 150 100 50 Tj = 25°C Tj = 175°C 20 15 10 5 0 0 0 10 20 30 Drain Current, ID (A) 40 50 Figure 5. Typical drain-source on-resistances at VGS = 12V 0 2 3 4 5 6 7 8 Gate-Source Voltage, VGS (V) 9 10 Gate-Source Voltage, VGS (V) 20 5 4 3 2 1 0 -100 1 Figure 6. Typical transfer characteristics at VDS = 5V 6 Threshold Voltage, Vth (V) Tj = -55°C 25 Drain Current, ID (A) On-Resistance, RDS(on) (mW) 250 15 10 5 Vds = 400V Vds = 500V 0 -5 -50 0 50 100 150 Junction Temperature, TJ (°C) Figure 7. Threshold voltage vs. junction temperature at VDS = 5V and ID = 10mA Datasheet: UJ4C075060K4S -10 200 0 10 20 30 40 Gate Charge, QG (nC) 50 60 Figure 8. Typical gate charge at ID = 20A Rev. A, October 2020 7 0 0 Vgs = -5V Vgs = 0V Vgs = 5V -10 Vgs = 8V -15 -20 -25 Vgs = 0V Vgs = 5V -10 Vgs = 8V -15 -20 -25 -30 -30 -4 -3 -2 -1 Drain-Source Voltage, VDS (V) 0 Figure 9. 3rd quadrant characteristics at TJ = -55°C -4 -3 -2 -1 Drain-Source Voltage, VDS (V) 0 Figure 10. 3rd quadrant characteristics at TJ = 25°C 0 14 -5 12 10 -10 EOSS (mJ) Drain Current, ID (A) Vgs = - 5V -5 Drain Current, ID (A) Drain Current, ID (A) -5 -15 Vgs = - 5V -20 6 4 Vgs = 0V Vgs = 5V -25 8 2 Vgs = 8V 0 -30 -4 -3 -2 -1 Drain-Source Voltage, VDS (V) Figure 11. 3rd quadrant characteristics at TJ = 175°C Datasheet: UJ4C075060K4S 0 0 100 200 300 400 500 600 700 800 Drain-Source Voltage, VDS (V) Figure 12. Typical stored energy in COSS at VGS = 0V Rev. A, October 2020 8 35 Ciss 100 DC Drain Current, ID (A) Capacitance, C (pF) 1,000 Coss 10 30 25 20 15 10 Crss 5 0 1 0 -75 -50 -25 0 25 50 75 100 125 150 175 Case Temperature, TC (°C) 100 200 300 400 500 600 700 800 Drain-Source Voltage, VDS (V) Figure 13. Typical capacitances at f = 100kHz and VGS = 0V Figure 14. DC drain current derating 175 Thermal Impedance, ZqJC (°C/W) Power Dissipation, Ptot (W) 200 150 125 100 75 50 25 0 -75 -50 -25 0 25 50 75 100 125 150 175 Case Temperature, TC (°C) Figure 15. Total power dissipation Datasheet: UJ4C075060K4S 1 0.1 0.01 D = 0.5 D = 0.3 D = 0.1 D = 0.05 D = 0.02 D = 0.01 Single Pulse 0.001 1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 Pulse Time, tp (s) Figure 16. Maximum transient thermal impedance Rev. A, October 2020 9 100 70 60 50 10 10ms 100ms 1 DC Qrr (nC) Drain Current, ID (A) 1ms 20 1ms IS = 20A, di/dt = 1060A/ms, VGS = 0V, RG =20W 10 10ms 0 10 100 1000 Drain-Source Voltage, VDS (V) 0 Figure 17. Safe operation area at TC = 25°C, D = 0, Parameter tp 300 250 200 Switching Energy (mJ) VDS = 400V, VGS = 0V/15V RG_ON=1W, RG_OFF=20W, FWD: same device with VGS = 0V, RG = 20W Etot Eon Eoff 150 100 200 150 0 0 10 15 20 Drain Current, ID (A) 25 30 Figure 19. Clamped inductive switching energy vs. drain current at VDS = 400V and TJ = 25°C Datasheet: UJ4C075060K4S 175 Etot Eon Eoff 100 50 5 50 75 100 125 150 Junction Temperature, TJ (°C) VDS = 500V, VGS = 0V/15V RG_ON=1W, RG_OFF=20W, FWD: same device with VGS = 0V, RG = 20W 250 50 0 25 Figure 18. Reverse recovery charge Qrr vs. junction temperature 300 Switching Energy (mJ) Vds = 400V 30 0.1 1 Vds = 500V 40 0 5 10 15 20 Drain Current, ID (A) 25 30 Figure 20. Clamped inductive switching energy vs. drain current at VDS = 500V and TJ = 25°C Rev. A, October 2020 10 200 Turn-Off Energy, Eoff (mJ) Turn-on Energy, Eon (mJ) 200 150 100 VDS = 400V, ID = 20A, VGS = 0V/15V, TJ = 25°C FWD: same device with VGS = 0V, RG =20W 50 150 100 50 0 0 0 5 10 15 20 Total External Turn-on RG, RG_EXT (W) 250 VDS = 400V, ID = 20A, VGS = 0V/15V, RG_ON = 1W, RG_OFF = 20W, FWD: same device with VGS = 0V, RG =20W 50 100 Figure 22. Clamped inductive switching turn-off energy vs. RG,EXT_OFF Switching Energy (mJ) 150 100 20 40 60 80 Total External Turn-off RG, RG,EXT (W) 300 Etot Eon Eoff 200 0 25 Figure 21. Clamped inductive switching turn-on energy vs. RG,EXT_ON Switching Energy (mJ) VDS = 400V, ID = 20A, VGS = 0V/15V, TJ = 25°C FWD: same device with VGS = 0V, RG =20W Etot Eon Eoff 250 200 150 VDS = 500V, ID = 20A, VGS = 0V/15V, RG_ON = 1W, RG_OFF = 20W, FWD: same device with VGS = 0V, RG =20W 100 50 0 0 0 25 50 75 100 125 150 Junction Temperature, TJ (°C) 175 Figure 23. Clamped inductive switching energy vs. junction temperature at VDS =400V and ID = 20A Datasheet: UJ4C075060K4S 0 25 50 75 100 125 150 Junction Temperature, TJ (°C) 175 Figure 24. Clamped inductive switching energy vs. junction temperature at VDS =500V and ID = 20A Rev. A, October 2020 11 350 VDS = 400V, VGS = 0V/15V RG_ON=1W, RG_OFF=20W, FWD: UJ3D06510TS 200 150 Etot Eon Eoff 100 250 200 Etot Eon Eoff 150 100 50 50 0 0 0 5 10 15 20 Drain Current, ID (A) 25 30 Figure 24. Clamped inductive switching energy vs. drain current at VDS = 400V and TJ = 25°C 0 5 10 15 20 Drain Current, ID (A) 25 30 Figure 25. Clamped inductive switching energy vs. drain current at VDS = 500V and TJ = 25°C 200 250 VDS = 400V, VGS = 0V/15V, RG_ON = 1W, RG_OFF = 20W, FWD: UJ3D06510TS 150 100 Switching Energy (mJ) Switching Energy (mJ) VDS = 500V, VGS = 0V/15V RG_ON=1W, RG_OFF=20W, FWD: UJ3D06510TS 300 Switching Energy (mJ) Switching Energy (mJ) 250 Etot Eon Eoff 50 VDS = 500V, VGS = 0V/15V, RG_ON = 1W, RG_OFF = 20W, FWD: UJ3D06510TS 200 150 Etot Eon Eoff 100 50 0 0 0 25 50 75 100 125 150 Junction Temperature, TJ (°C) 175 Figure 26. Clamped inductive switching energy vs. junction temperature at VDS =400V and ID = 20A Datasheet: UJ4C075060K4S 0 25 50 75 100 125 150 Junction Temperature, TJ (°C) 175 Figure 27. Clamped inductive switching energy vs. junction temperature at VDS =500V and ID = 20A Rev. A, October 2020 12 Figure 28. Schematic of the half-bridge mode switching test circuit. Note, a bus RC snubber (RS = 2.5W, CS=100nF) is used to reduce the power loop high frequency oscillations. Figure 29. Schematic of the chopper mode switching test circuit. Note, a bus RC snubber (RS = 2.5W, CS=100nF) is used to reduce the power loop high frequency oscillations. Figure 30. Schematic of the half-bridge mode switching test circuit with device RC snubbers (Rs1 =10W, Cs1 = 95pF) and a bus RC snubber (RS = 2.5W, CS=100nF). Datasheet: UJ4C075060K4S Rev. A, October 2020 13 Applications Information SiC FETs are enhancement-mode power switches formed by a high-voltage SiC depletion-mode JFET and a low-voltage silicon MOSFET connected in series. The silicon MOSFET serves as the control unit while the SiC JFET provides high voltage blocking in the off state. This combination of devices in a single package provides compatibility with standard gate drivers and offers superior performance in terms of low on-resistance (RDS(on)), output capacitance (Coss), gate charge (QG), and reverse recovery charge (Qrr) leading to low conduction and switching losses. The SiC FETs also provide excellent reverse conduction capability eliminating the need for an external anti-parallel diode. Like other high performance power switches, proper PCB layout design to minimize circuit parasitics is strongly recommended due to the high dv/dt and di/dt rates. An external gate resistor is recommended when the FET is working in the diode mode in order to achieve the optimum reverse recovery performance. For more information on SiC FET operation, see www.unitedsic.com. A snubber circuit with a small R(G), or gate resistor, provides better EMI suppression with higher efficiency compared to using a high R(G) value. There is no extra gate delay time when using the snubber circuitry, and a small R(G) will better control both the turn-off V(DS) peak spike and ringing duration, while a high R(G) will damp the peak spike but result in a longer delay time. In addition, the total switching loss when using a snubber circuit is less than using high R(G), while greatly reducing E(OFF) from mid-to-full load range with only a small increase in E(ON). Efficiency will therefore improve with higher load current. For more information on how a snubber circuit will improve overall system performance, visit the UnitedSiC website at www.unitedsic.com Disclaimer UnitedSiC reserves the right to change or modify any of the products and their inherent physical and technical specifications without prior notice. UnitedSiC assumes no responsibility or liability for any errors or inaccuracies within. Information on all products and contained herein is intended for description only. No license, express or implied, to any intellectual property rights is granted within this document. UnitedSiC assumes no liability whatsoever relating to the choice, selection or use of the UnitedSiC products and services described herein. Datasheet: UJ4C075060K4S Rev. A, October 2020 14