129798-HMC903LP3E

FUNCTIONAL BLOCK DIAGRAM 13 NIC GND 2 11 GND RFIN 3 10 RFOUT NIC 4 9 NIC NIC NIC 8 NIC 7 12 PACKAGE BASE GND 14479-001 14 VDD2 15 VDD1 1 5 Point to point radios Point to multipoint radios Military and space Test instrumentation NIC VGG2 APPLICATIONS HMC903LP3E 6 Low noise figure: 1.7 dB typical at 6 GHz to 16 GHz High gain: 18.5 dB typical at 6 GHz to 16 GHz Output power for 1 dB compression (P1dB): 14.5 dBm typical at 6 GHz to 16 GHz Single-supply voltage: 3.5 V at 80 mA typical Output third-order intercept (IP3): 25 dBm typical 50 Ω matched input/output Self biased with optional bias control for IDQ reduction 16-lead, 3 mm × 3 mm, LFCSP package VGG1 FEATURES 16 NIC Data Sheet GaAs, pHEMT, MMIC, Low Noise Amplifier, 6 GHz to 17 GHz HMC903LP3E Figure 1. GENERAL DESCRIPTION The HMC903LP3E is a self biased, gallium arsenide (GaAs), monolithic microwave integrated circuit (MMIC), pseudomorphic (pHEMT), low noise amplifier (LNA) with an option bias control for IDQ reduction. It is housed in a 16-lead, 3 mm × 3 mm, LFCSP package. The HMC903LP3E amplifier operates from 6 GHz to 17 GHz, providing 18.5 dB of small signal gain and 1.7 dB noise figure in the 6 GHz to 16 GHz band, and an output IP3 of 25 dBm full band 6 GHz to 17 GHz, while requiring only 80 mA from a 3.5 V supply. Rev. G The P1dB output power of 14.5 dBm enables the LNA to function as a local oscillator (LO) driver for balanced, I/Q or image reject mixers. The HMC903LP3E also features an input and an output that are dc blocked and internally matched to 50 Ω, making it ideal for high capacity microwave radios and video satellite (VSAT) applications. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com HMC903LP3E Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions..............................5 Applications ....................................................................................... 1 Interface Schematics .....................................................................5 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ..............................................6 General Description ......................................................................... 1 Theory of Operation .........................................................................9 Revision History ............................................................................... 2 Applications Information .............................................................. 10 Specifications..................................................................................... 3 Recommended Bias Sequence During Power Up .................. 10 6 GHz to 16 GHz Frequency Range ........................................... 3 Recommended Bias Sequence During Power Down ............ 10 16 GHz to 17 GHz Frequency Range ......................................... 3 Evaluation PCB ........................................................................... 11 Absolute Maximum Ratings ............................................................ 4 Typical Application Circuits ..................................................... 12 Thermal Resistance ...................................................................... 4 Outline Dimensions ....................................................................... 13 ESD Caution .................................................................................. 4 Ordering Guide .......................................................................... 13 REVISION HISTORY 7/2017—Rev. F to Rev. G Changed HMC903 to HMC903LP3E ......................... Throughout Changes to Figure 1 .......................................................................... 1 Changes to RF Input Parameter, Table 3 ....................................... 4 This Hittite Microwave product data sheet has been reformatted to the styles and standards of Analog Devices, Inc. 1/2017—v06.0816 (HMC903LP3E) to Rev. F Updated Format .................................................................. Universal Changes to Features Section, Figure 1, and General Description Section .................................................................................................1 Add Thermal Resistance Section and Table 5; Renumbered Sequentially ........................................................................................4 Changes to Figure 2 and Table 5......................................................5 Added Theory of Operation Section ..............................................9 Added Applications Information Section ................................... 10 Updated Outline Dimensions ....................................................... 13 Added Ordering Guide .................................................................. 13 Rev. G | Page 2 of 13 Data Sheet HMC903LP3E SPECIFICATIONS TA = 25°C, VDD1 = VDD2 = 3.5 V, IDQ = 80 mA (VGG1 = VGG2 = open for normal, self biased operation), unless otherwise noted. 6 GHz TO 16 GHz FREQUENCY RANGE Table 1. Parameter GAIN Gain Variation over Temperature NOISE FIGURE1 RETURN LOSS Input Output OUTPUT POWER For 1 dB Compression (P1dB)1 Saturated (PSAT)1 OUTPUT THIRD-ORDER INTERCEPT (IP3) SUPPLY CURRENT (IDQ) 1 Min 16.5 13 22 Typ 18.5 0.012 1.7 Max 2.2 Unit dB dB/°C dB 12 12 dB dB 14.5 16.5 25 80 dBm dBm dBm mA 110 Board loss removed from gain, power, and noise figure measurements. 16 GHz TO 17 GHz FREQUENCY RANGE Table 2. Parameter GAIN Gain Variation over Temperature NOISE FIGURE1 RETURN LOSS Input Output OUTPUT POWER For 1 dB Compression (P1dB)1 Saturated (PSAT)1 OUTPUT THIRD-ORDER INTERCEPT (IP3) SUPPLY CURRENT (IDQ) 1 Min 15 12 22 Board loss removed from gain, power, and noise figure measurements. Rev. G | Page 3 of 13 Typ 18 0.012 2.2 Max 2.5 Unit dB dB/°C dB 11 14 dB dB 13 16.5 25 80 dBm dBm dBm mA 110 HMC903LP3E Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. Parameter Drain Bias Voltage RF Input Power Gate Bias Voltage VGG1 VGG2 Continuous Power Dissipation, PDISS (TA = 85°C, Derate 6.9 mW/°C Above 85°C) Channel Temperature Maximum Peak Reflow Temperature Storage Temperature Operating Temperature ESD Sensitivity (Human Body Model) Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Rating 4.5 V 20 dBm Table 4. Thermal Resistance −0.8 V to +0.2 V −0.8 V to +0.2 V 0.45 W Package Type1 HCP-16-1 1 150°C 260°C −65°C to +85°C −40°C to +85°C Class 0, Passed 150 V θJC 144.8 Unit °C/W Thermal impedance simulated values are based on JEDEC 2s2p thermal test board. See JEDEC JESD51. ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. G | Page 4 of 13 Data Sheet HMC903LP3E NIC 14 VDD2 13 NIC 11 GND 10 RFOUT 9 NIC PACKAGE BASE GND NOTES 1. NIC = NOT INTERNALLY CONNECTED. 2. EXPOSED PAD. THE PACKAGE BOTTOM HAS AN EXPOSED METAL GROUND PADDLE THAT MUST CONNECT TO RF/DC GROUND. 14479-002 4 NIC 8 NIC 12 NIC 3 TOP VIEW (Not to Scale) 5 RFIN HMC903LP3E 7 2 VGG2 GND 6 1 VGG1 NIC 15 VDD1 16 NIC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1, 4, 5, 8, 9, 12, 13, 16 2, 11 3 6, 7 Mnemonic NIC GND RFIN VGG1, VGG2 10 14, 15 RFOUT VDD1, VDD2 EPAD Description Not Internally Connected. However, all data shown was measured with these pins connected to RF/dc ground externally. Ground. Connect these pins to RF/dc ground. See Figure 3 for the interface schematic. RF Input. This pin is ac-coupled and matched to 50 Ω. See Figure 4 for the interface schematic. Optional Gate Controls for the Amplifier. If left open, the amplifier runs self biased at the standard current. Applying a negative voltage reduces the drain current. External capacitors are required (see Figure 24). See Figure 5 for the interface schematic. RF Output. This pin is ac-coupled and matched to 50 Ω. See Figure 6 for the interface schematic. Power Supply Voltages for the Amplifier. See assembly for the required external components (see Figure 23 and Figure 24). See Figure 7 for the interface schematic. Exposed Pad. The package bottom has an exposed metal ground paddle that must connect to RF/dc ground. RFOUT 14479-003 GND Figure 6. RFOUT Interface Schematic Figure 3. GND Interface Schematic VDD1 , VDD2 14479-007 14479-004 RFIN Figure 7. VDD1 and VDD2 Interface Schematic 14479-005 Figure 4. RFIN Interface Schematic VGG1, VGG2 14479-006 INTERFACE SCHEMATICS Figure 5. VGG1 and VGG2 Interface Schematic Rev. G | Page 5 of 13 HMC903LP3E Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 25 24 +85°C +25°C –40°C 22 S11 S21 S22 20 5 GAIN (dB) RESPONSE (dB) 15 –5 18 16 14 –15 5 7 9 11 13 15 17 19 FREQUENCY (GHz) 10 6 OUTPUT RETURN LOSS (dB) –15 –25 18 FREQUENCY (GHz) –10 –15 –20 6 8 10 12 14 16 18 FREQUENCY (GHz) Figure 12. Output Return Loss vs. Frequency for Various Temperatures Figure 9. Input Return Loss vs. Frequency for Various Temperatures 6 30 +85°C +25°C –40°C 5 25 OUTPUT IP3 (dBm) NOISE FIGURE (dB) –5 –25 14479-009 –20 16 18 4 3 2 20 15 10 1 +85°C +25°C –40°C 6 8 10 12 14 FREQUENCY (GHz) 16 18 5 14479-010 0 Figure 10. Noise Figure vs. Frequency for Various Temperatures (Board Loss Removed from Gain, Power, and Noise Figure Measurements) 6 8 10 12 14 FREQUENCY (GHz) 16 18 14479-013 INPUT RETURN LOSS (dB) –10 14 16 +85°C +25°C –40°C –5 12 14 0 +85°C +25°C –40°C 10 12 Figure 11. Gain vs. Frequency for Various Temperatures (Board Loss Removed from Gain, Power, and Noise Figure Measurements) 0 8 10 FREQUENCY (GHz) Figure 8. Broadband Gain and Return Loss (Board Loss Removed from Gain, Power, and Noise Figure Measurements) vs. Frequency 6 8 14479-012 3 14479-008 –25 14479-011 12 Figure 13. Output Third-Order Intercept (IP3) vs. Frequency for Various Temperatures Rev. G | Page 6 of 13 HMC903LP3E 25 25 20 20 PSAT (dBm) 15 10 5 15 10 5 +85°C +25°C –40°C +85°C +25°C –40°C 8 10 12 14 16 18 FREQUENCY (GHz) 0 6 12 14 16 18 Figure 17. Saturated Output Power (PSAT) vs. Frequency for Various Temperatures (Board Loss Removed from Gain, Power, and Noise Figure Measurements) 0 24 +85°C +25°C –40°C 20 POUT (dBm), GAIN (dB), PAE (%) –10 REVERSE ISOLATION (dB) 10 FREQUENCY (GHz) Figure 14. Output Power for 1 dB Compression (P1dB) vs. Frequency for Various Temperatures (Board Loss Removed from Gain, Power, and Noise Figure Measurements) –20 –30 –40 –50 16 12 8 4 GAIN POUT PAE 0 6 8 10 12 14 16 18 FREQUENCY (GHz) –4 –20 14479-015 –60 7 20 6 92 18 5 90 3 12 2 10 1 –8 –5 –2 1 4 88 IDD (mA) 14 –11 94 NOISE FIGURE (dB) 4 GAIN P1dB NOISE FIGURE –14 Figure 18. Output Power (POUT), Gain, and Power Added Efficiency (PAE) vs. Input Power (Board Loss Removed from Gain, Power, and Noise Figure Measurements) 22 16 –17 INPUT POWER (dBm) Figure 15. Reverse Isolation vs. Frequency for Various Temperatures GAIN (dB), P1dB (dBm) 8 14479-017 6 14479-014 0 14479-018 P1dB (dBm) Data Sheet 86 84 82 78 –30 14479-016 3.5 VDD (V) 0 4.0 Figure 16. Gain, Output Power for 1 dB Compression (P1dB), and Noise Figure vs. Supply Voltage (VDD) at 12 GHz (Board Loss Removed from Gain, Power, and Noise Figure Measurements) –27 –24 –21 –18 –15 –12 –9 INPUT POWER (dBm) –6 –3 0 3 14479-019 80 8 3.0 Figure 19. Supply Current (IDD) vs. Input Power (Board Loss Removed from Gain Measurement and Data Taken at VDD1 = VDD2 = 3 V) Rev. G | Page 7 of 13 Data Sheet 30 120 25 100 20 80 15 60 10 40 0 –0.7 20 IP3 GAIN IDD 0 –0.6 –0.5 –0.4 –0.3 –0.2 VGG1, VGG2 GATE VOLTAGE (V dc) –0.1 0 14479-020 5 IDD (mA) GAIN (dB), IP3 (dBm) HMC903LP3E Figure 20. Gain, Output Third-Order Intercept (IP3), and Supply Current (IDD) vs. VGG1, VGG2 Gate Voltage Rev. G | Page 8 of 13 Data Sheet HMC903LP3E THEORY OF OPERATION The HMC903LP3E is a gallium arsenide (GaAs), monolithic microwave integrated circuit (MMIC), pseudomorphic (pHEMT), low noise amplifier. The HMC903LP3E amplifier uses two gain stages in series, and the basic schematic of the amplifier is shown in Figure 21, which forms a low noise amplifier operating from 6 GHz to 17 GHz with excellent noise figure performance. VDD1 VDD2 RFOUT VGG1 VGG2 14479-021 RFIN Figure 21. Basic Schematic of the Amplifier The HMC903LP3E has single-ended input and output ports whose impedances are nominally equal to 50 Ω over the 6 GHz to 17 GHz frequency range. Consequently, it can directly insert into a 50 Ω system with no required impedance matching circuitry, which also means that multiple HMC903LP3E amplifiers can be cascaded back to back without the need for external matching circuitry. The input and output impedances are sufficiently stable vs. variations in temperature and supply voltage that no impedance matching compensation is required. Note that it is critical to supply very low inductance ground connections to the GND pins and to the package base exposed pad to ensure stable operation. To achieve optimal performance from the HMC903LP3E and to prevent damage to the device, do not exceed the absolute maximum ratings. Rev. G | Page 9 of 13 HMC903LP3E Data Sheet APPLICATIONS INFORMATION Figure 22 shows the basic connections for operating the HMC903LP3E. Both the RFIN and RFOUT ports have on-chip dc block capacitors that eliminate the need for external ac coupling capacitors. The HMC903LP3E has VGG1 and VGG2 optional gate bias pins. When these pins are left open, the amplifier runs in self biased operation with a typical IDQ = 80 mA, when VDD1/VDD2 = 3.5 V. When using the VGG1 and VGG2 gate bias pins, follow the recommended bias sequencing so that the amplifier is not damaged. RECOMMENDED BIAS SEQUENCE DURING POWER UP The recommended bias sequence to power up the HMC903LP3E is as follows: 1. 2. 3. 4. 5. Connect to GND. Set VGG1 and VGG2 to −2 V. Set VDD1 and VDD2 to 3.5 V. Increase VGG1 and VGG2 to achieve a typical IDQ = 80 mA. Apply the RF signal. RECOMMENDED BIAS SEQUENCE DURING POWER DOWN The recommended bias sequence to power down the HMC903LP3E is as follows: 1. 2. 3. 4. Turn off the RF signal. Decrease VGG1 and VGG2 to −2 V to achieve a typical IDQ = 0 mA. Decrease VDD1 and VDD2 to 0 V. Increase VGG1 and VGG2 to 0 V. Unless otherwise noted, all measurements and data shown were taken using the typical application circuit (see Figure 23), with the evaluation board (see Figure 22) and biased per the conditions in this section. The VDD1 and VDD2 pins are connected together, similarly the VGG1 and VGG2 pins are also connected together. The bias conditions shown in this section are the operating points recommended to optimize the overall performance. Operation using other bias conditions may provide performance that differs from what is shown in this data sheet. Decreasing the VDD1 and VDD2 levels has negligible effect on the gain and noise figure performance; however, they reduce the P1dB. This behavior is shown in Figure 8 thru Figure 20. For applications where the P1dB requirement is not stringent, the HMC903LP3E can be down biased to reduce power consumption. Rev. G | Page 10 of 13 Data Sheet HMC903LP3E EVALUATION PCB 14479-022 The circuit board used in this application must use RF circuit design techniques. Signal lines must have 50 Ω impedance, and the package ground leads and exposed paddle must be connected directly to the ground plane similar to that shown in Figure 22. Use a sufficient number of via holes to connect the top and bottom ground planes. Mount the evaluation PCB to an appropriate heat sink. The evaluation PCB shown is available from Analog Devices, Inc., upon request. Figure 22. Evaluation PCB (128395-1) Table 6. List of Materials for the Evaluation PCB Component J1, J2 J3, J4, J6 to J8 C1, C4, C7, C10 C2, C5, C8, C11 C3, C6, C9, C12 U1 PCB Description SMA connectors DC pins 100 pF capacitors, 0402 package 0.01 μF capacitors, 0402 package 4.7 μF tantalum capacitors HMC903LP3E amplifier 128395-1 evaluation PCB; circuit board material: Rogers 4350 or Arlon 25FR Rev. G | Page 11 of 13 HMC903LP3E Data Sheet TYPICAL APPLICATION CIRCUITS 2 11 3 10 4 9 RFOUT 14479-023 C4 100pF VDD2 8 12 7 1 5 RFIN + C12 C11 0.01µF 4.7µF C10 100pF 13 C7 100pF 14 C8 0.01µF 15 C9 4.7µF 6 + 16 VDD1 C1 100pF Figure 23. Standard (Self Biased) Operation Typical Application Circuit + C6 4.7µF 13 2 11 3 10 4 9 C5 0.01µF C4 100pF RFOUT C1 100pF C2 C3 0.01µF + 4.7µF VGG2 Figure 24. Gate Control, Reduced Current Operation Typical Application Circuit Rev. G | Page 12 of 13 14479-024 VGG1 VDD2 8 12 7 1 5 RFIN + C12 C11 0.01µF 4.7µF C10 100pF C7 100pF 14 C8 0.01µF 15 C9 4.7µF 6 + 16 VDD1 Data Sheet HMC903LP3E OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 3.10 3.00 SQ 2.90 0.50 BSC PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 16 13 1 12 EXPOSED PAD 1.95 1.70 SQ 1.50 4 9 TOP VIEW 8 5 BOTTOM VIEW 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND 0.05 MAX FUNCTION DESCRIPTIONS 0.02 NOM SECTION OF THIS DATA SHEET. COPLANARITY 0.08 0.20 REF 0.90 0.85 0.80 SEATING PLANE PKG-004863 0.45 0.40 0.35 COMPLIANT WITH JEDEC STANDARDS MO-220-VEED-4. 03-15-2017-B PIN 1 INDICATOR 0.30 0.25 0.20 Figure 25. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.85 mm Package Height (HCP-16-1) Dimensions shown in millimeters ORDERING GUIDE Model1 HMC903LP3E Temperature Range −40°C to +85°C Lead Finish 100% Matte Sn Package Description 16-Lead LFCSP Package Option HCP-16-1 HMC903LP3ETR −40°C to +85°C 100% Matte Sn 16-Lead LFCSP HCP-16-1 129798-HMC903LP3E 1 2 Evaluation Board The HMC903LP3E is a RoHS Compliant Part. The four digital lot number for the HMC903LP3E is XXXX. ©2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D14479-0-7/17(G) Rev. G | Page 13 of 13 Branding2 903 XXXX 903 XXXX