5962-8770102RA

a FEATURES On-Chip Latches for Both DACs +5 V to +15 V Operation DACs Matched to 1% Four Quadrant Multiplication TTL/CMOS Compatible Latch Free (Protection Schottkys not Required) APPLICATIONS Digital Control of: Gain/Attenuation Filter Parameters Stereo Audio Circuits X-Y Graphics CMOS Dual 8-Bit Buffered Multiplying DAC AD7528 FUNCTIONAL BLOCK DIAGRAM VREF A RFB A VDD DB0 DATA INPUTS DB7 INPUT BUFFER OUT A LATCH DAC A AGND AD7528 DAC A/ DAC B CS RFB B CONTROL LOGIC OUT B WR LATCH DAC B DGND VREF B ORDERING GUIDE1 GENERAL DESCRIPTION The AD7528 is a monolithic dual 8-bit digital/analog converter featuring excellent DAC-to-DAC matching. It is available in skinny 0.3" wide 20-lead DIPs and in 20-lead surface mount packages. Separate on-chip latches are provided for each DAC to allow easy microprocessor interface. Data is transferred into either of the two DAC data latches via a common 8-bit TTL/CMOS compatible input port. Control input DAC A/DAC B determines which DAC is to be loaded. The AD7528’s load cycle is similar to the write cycle of a random access memory and the device is bus compatible with most 8-bit microprocessors, including 6800, 8080, 8085, Z80. The device operates from a +5 V to +15 V power supply, dissipating only 20 mW of power. Both DACs offer excellent four quadrant multiplication characteristics with a separate reference input and feedback resistor for each DAC. PRODUCT HIGHLIGHTS 1. DAC-to-DAC matching: since both of the AD7528 DACs are fabricated at the same time on the same chip, precise matching and tracking between DAC A and DAC B is inherent. The AD7528’s matched CMOS DACs make a whole new range of applications circuits possible, particularly in the audio, graphics and process control areas. Model2 Temperature Ranges Relative Gain Accuracy Error Package Options 3 AD7528JN AD7528KN AD7528LN AD7528JP AD7528KP AD7528LP AD7528JR AD7528KR AD7528LR AD7528AQ AD7528BQ AD7528CQ AD7528SQ AD7528TQ AD7528UQ –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –55°C to +125°C –55°C to +125°C –55°C to +125°C ± 1 LSB ± 1/2 LSB ± 1/2 LSB ± 1 LSB ± 1/2 LSB ± 1/2 LSB ± 1 LSB ± 1/2 LSB ± 1/2 LSB ± 1 LSB ± 1/2 LSB ± 1/2 LSB ± 1 LSB ± 1/2 LSB ± 1/2 LSB N-20 N-20 N-20 P-20A P-20A P-20A R-20 R-20 R-20 Q-20 Q-20 Q-20 Q-20 Q-20 Q-20 ± 4 LSB ± 2 LSB ± 1 LSB ± 4 LSB ± 2 LSB ± 1 LSB ± 4 LSB ± 2 LSB ± 1 LSB ± 4 LSB ± 2 LSB ± 1 LSB ± 4 LSB ± 2 LSB ± 1 LSB NOTES 1 Analog Devices reserves the right to ship side-brazed ceramic in lieu of cerdip. Parts will be marked with cerdip designator “Q.” 2 Processing to MIL-STD-883C, Class B is available. To order, add suffix “/883B” to part number. For further information, see Analog Devices’ 1990 Military Products Databook. 3 N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC. 2. Small package size: combining the inputs to the on-chip DAC latches into a common data bus and adding a DAC A/DAC B select line has allowed the AD7528 to be packaged in either a small 20-lead DIP, SOIC or PLCC. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 AD7528–SPECIFICATIONS (V REF A = VREF B = +10 V; OUT A = OUT B = O V unless otherwise noted) V DD = +5 V Parameter STATIC PERFORMANCE2 Resolution Relative Accuracy Differential Nonlinearity Gain Error TA = +25°C TMIN, TMAX TA= +25°C TMIN, TMAX Units All J, A, S K, B, T L, C, U All 8 ±1 ± 1/2 ± 1/2 ±1 8 ±1 ± 1/2 ± 1/2 ±1 8 ±1 ± 1/2 ± 1/2 ±1 8 ±1 ± 1/2 ± 1/2 ±1 Bits LSB max LSB max LSB max LSB max J, A, S K, B, T L, C, U ±4 ±2 ±1 ±6 ±4 ±3 ±4 ±2 ±1 ±5 ±3 ±1 LSB max LSB max LSB max All ± 0.007 ± 0.007 ± 0.0035 ± 0.0035 %/°C max All All All ± 50 ± 50 8 15 ± 400 ± 400 8 15 ± 50 ± 50 8 15 ± 200 ± 200 8 15 nA max nA max kΩ min kΩ max All ±1 ±1 ±1 ±1 % max All 2.4 2.4 13.5 13.5 V min All 0.8 0.8 1.5 1.5 V max All ±1 ± 10 ±1 ± 10 µA max All All 10 15 10 15 10 15 10 15 pF max pF max Gain Temperature Coefficient3 ∆Gain/∆Temperature Output Leakage Current OUT A (Pin 2) OUT B (Pin 20) Input Resistance (V REF A, V REF B) VREF A/V REF B Input Resistance Match DIGITAL INPUTS4 Input High Voltage VIH Input Low Voltage VIL Input Current IIN Input Capacitance DB0–DB7 WR, CS, DAC A/DAC B SWITCHING CHARACTERISTICS 3 Chip Select to Write Set Up Time tCS Chip Select to Write Hold Time tCH DAC Select to Write Set Up Time tAS DAC Select to Write Hold Time tAH Data Valid to Write Set Up Time tDS Data Valid to Write Hold Time tDH Write Pulsewidth tWR POWER SUPPLY IDD VDD = +15 V Version1 Test Conditions/Comments This is an Endpoint Linearity Specification All Grades Guaranteed Monotonic Over Full Operating Temperature Range Measured Using Internal R FB A and RFB B Both DAC Latches Loaded with 11111111 Gain Error is Adjustable Using Circuits of Figures 4 and 5 DAC Latches Loaded with 00000000 Input Resistance TC = –300 ppm/°C, Typical Input Resistance is 11 kΩ VIN = 0 or V DD See Timing Diagram All 90 100 60 80 ns min All 0 0 10 15 ns min All 90 100 60 80 ns min All 0 0 10 15 ns min All 80 90 30 40 ns min All 0 0 0 0 ns min All 90 100 60 80 ns min All All 2 100 2 500 2 100 2 500 mA max µA max See Figure 3 All Digital Inputs VIL or VIH All Digital Inputs 0 V or V DD (Measured Using Recommended P.C. Board Layout (Figure 7) and AD644 as AC PERFORMANCE CHARACTERISTICS5 Output Amplifiers) V DD = +5 V VDD = +15 V Parameter Version1 TA = +25°C TMIN, TMAX TA= +25°C TMIN, TMAX Units Test Conditions/Comments DC SUPPLY REJECTION (∆GAIN/∆VDD) All 0.02 0.04 0.01 0.02 % per % max ∆V DD = ± 5% CURRENT SETTLING TIME2 All 350 400 180 200 ns max PROPAGATION DELAY (From Digital Input to 90% of Final Analog Output Current) All 220 270 80 100 ns max DIGITAL-TO-ANALOG GLITCH IMPULSE All 160 OUTPUT CAPACITANCE COUT A COUT B COUT A COUT B 50 50 120 120 50 50 120 120 50 50 120 120 –70 –70 –65 –65 –70 –70 AC FEEDTHROUGH 6 VREF A to OUT A VREF B to OUT B All All 440 –2– To 1/2 LSB. OUT A/OUT B Load = 100 Ω. WR = CS = 0 V. DB0–DB7 = 0 V to VDD or VDD to 0 V VREF A = VREF B = +10 V OUT A, OUT B Load = 100 Ω C EXT = 13 pF WR = CS = 0 V DB0–DB7 = 0 V to VDD or VDD to 0 V nV sec typ For Code Transition 00000000 to 11111111 50 50 120 120 pF max pF max pF max pF max DAC Latches Loaded with 00000000 –65 –65 dB max dB max VREF A, VREF B = 20 V p-p Sine Wave @ 100 kHz DAC Latches Loaded with 11111111 REV. B AD7528 V DD = +5 V Parameter Version1 TA = +25°C CHANNEL-TO-CHANNEL ISOLATION VREF A to OUT B All VREF B to OUT A VDD = +15 V TMIN, TMAX TA= +25°C TMIN, TMAX Units Test Conditions/Comments –77 –77 dB typ –77 –77 dB typ Both DAC Latches Loaded with 11111111. VREF A = 20 V p-p Sine Wave @ 100 kHz VREF B = 0 V see Figure 6. VREF A = 20 V p-p Sine Wave @ 100 kHz VREF A = 0 V see Figure 6. DIGITAL CROSSTALK All 30 60 nV sec typ Measured for Code Transition 00000000 to 11111111 HARMONIC DISTORTlON All –85 –85 dB typ VIN = 6 V rms @ 1 kHz NOTES 1 Temperature Ranges are J, K, L Versions: –40°C to +85°C A, B, C Versions: –40°C to +85°C S, T, U Versions: –55°C to +125°C 2 Specifications applies to both DACs in AD7528. 3 Guaranteed by design but not production tested. 4 Logic inputs are MOS Gates. Typical input current (+25°C) is less than 1 nA. 5 These characteristics are for design guidance only and are not subject to test. 6 Feedthrough can be further reduced by connecting the metal lid on the ceramic package (suffix D) to DGND. AD7528, ideal maximum output is VREF – 1 LSB. Gain error of both DACs is adjustable to zero with external resistance. Output Capacitance Capacitance from OUT A or OUT B to AGND. Digital to Analog Glitch lmpulse The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-secs or nV-secs depending upon whether the glitch is measured as a current or voltage signal. Glitch impulse is measured with VREF A, VREF B = AGND. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted) VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3 V DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3 V Digital Input Voltage to DGND . . . . . . . –0.3 V, VDD + 0.3 V VPIN2, V PIN20 to AGND . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V VREF A, VREF B to AGND . . . . . . . . . . . . . . . . . . . . . . . ± 25 V VRFB A, VRFB B to AGND . . . . . . . . . . . . . . . . . . . . . . . ± 25 V Power Dissipation (Any Package) to +75°C . . . . . . . 450 mW Derates above +75°C by . . . . . . . . . . . . . . . . . . . 6 mW/°C Operating Temperature Range Commercial (J, K, L) Grades . . . . . . . . . . . –40°C to +85°C Industrial (A, B, C) Grades . . . . . . . . . . . . –40°C to +85°C Extended (S, T, U) Grades . . . . . . . . . . . –55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C Propagation Delay This is a measure of the internal delays of the circuit and is defined as the time from a digital input change to the analog output current reaching 90% of its final value. Channel-to-Channel Isolation The proportion of input signal from one DAC’s reference input which appears at the output of the other DAC, expressed as a ratio in dB. Digital Crosstalk The glitch energy transferred to the output of one converter due to a change in digital input code to the other converter. Specified in nV secs. PIN CONFIGURATIONS CAUTION: 2. Do not insert this device into powered sockets. Remove power before insertion or removal. RFB A OUT A AGND OUT B RFB B PLCC 1. ESD sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subjected to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. 3 2 1 20 19 PIN 1 IDENTIFIER VREF A 4 DGND 5 AD7528 DAC A/DAC B 6 TERMINOLOGY Relative Accuracy TOP VIEW (Not to Scale) (MSB) DB7 7 Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ± 1 LSB max over the operating temperature range ensures monotonicity. 9 10 11 12 13 DB5 DB4 DB3 DB2 DB1 DB6 8 Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero and full scale and is normally expressed in LSBs or as a percentage of full scale reading. 18 VREF B 17 VDD 16 WR 15 CS 14 DB0 (LSB) DIP, SOIC OUT B AGND 1 20 OUT A 2 19 RFB B RFB A 3 18 VREF B VREF A 4 17 VDD WR AD7528 TOP VIEW 15 CS (Not to Scale) 14 DB0 (LSB) (MSB) DB7 7 DGND 5 16 DAC A/DAC B 6 Gain Error DB6 8 13 DB1 Gain error or full-scale error is a measure of the output error between an ideal DAC and the actual device output. For the DB5 9 12 DB2 DB4 10 11 DB3 REV. B –3– AD7528 INTERFACE LOGIC INFORMATION DAC Selection: Both DAC latches share a common 8-bit input port. The control input DAC A/DAC B selects which DAC can accept data from the input port. Figure 1. An inverted R-2R ladder structure is used, that is, binary weighted currents are switched between the DAC output and AGND thus maintaining fixed currents in each ladder leg independent of switch state. EQUIVALENT CIRCUIT ANALYSIS Mode Selection: Inputs CS and WR control the operating mode of the selected DAC. See Mode Selection Table below. Write Mode: When CS and WR are both low the selected DAC is in the write mode. The input data latches of the selected DAC are transparent and its analog output responds to activity on DB0–DB7. Hold Mode: The selected DAC latch retains the data which was present on DB0–DB7 just prior to CS or WR assuming a high state. Both analog outputs remain at the values corresponding to the data in their respective latches. Mode Selection Table DAC A/DAC B CS WR DAC A DAC B L H X X L L H X L L X H WRITE HOLD HOLD HOLD HOLD WRITE HOLD HOLD Figure 2 shows an approximate equivalent circuit for one of the AD7528’s D/A converters, in this case DAC A. A similar equivalent circuit can be drawn for DAC B. Note that AGND (Pin 1) is common for both DAC A and DAC B. The current source ILEAKAGE is composed of surface and junction leakages and, as with most semiconductor devices, approximately doubles every 10°C. The resistor RO as shown in Figure 2 is the equivalent output resistance of the device which varies with input code (excluding all 0s code) from 0.8 R to 2 R. R is typically 11 kΩ. COUT is the capacitance due to the N-channel switches and varies from about 50 pF to 120 pF depending upon the digital input. g(VREF A, N) is the Thevenin equivalent voltage generator due to the reference input voltage VREF A and the transfer function of the R-2R ladder. R RFB A OUT A RO g(VREF A, N) COUT I LKG AGND L = Low State; H = High State; X = Don’t Care. Figure 2. Equivalent Analog Output Circuit of DAC A WRITE CYCLE TIMING DIAGRAM VDD 0 t AH t AS DAC A/DAC B VDD 0 t WR VDD WRITE 0 t DS VIH VIL DATA IN (DB0 – DB7) t DH VDD DATA IN STABLE 0 NOTES: 1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF VDD. VDD = +5V, t r = t f = 20ns; VDD = +15V, t r = t f = 40ns; VIH + VIL 2. TIMING MEASUREMENT REFERENCE LEVEL IS 2 The input buffers are simple CMOS inverters designed such that when the AD7528 is operated with VDD = 5 V, the buffer converts TTL input levels (2.4 V and 0.8 V) into CMOS logic levels. When VIN is in the region of 2.0 volts to 3.5 volts the input buffers operate in their linear region and pass a quiescent current, see Figure 3. To minimize power supply currents it is recommended that the digital input voltages be as close to the supply rails (VDD and DGND) as is practically possible. The AD7528 may be operated with any supply voltage in the range 5 ≤ VDD ≤ 15 volts. With VDD = +15 V the input logic levels are CMOS compatible only, i.e., 1.5 V and 13.5 V. 9 IDD mA (VDD = +5V) CIRCUIT INFORMATION—D/A SECTION The AD7528 contains two identical 8-bit multiplying D/A converters, DAC A and DAC B. Each DAC consists of a highly stable thin film R-2R ladder and eight N-channel current steering switches. A simplified D/A circuit for DAC A is shown in R R R VREF A 2R 2R 2R 2R S1 S2 S3 S8 VDD = +15V 800 TA = +258C ALL DIGITAL INPUTS TIED TOGETHER 700 8 7 600 6 500 5 4 400 300 VDD = +5V 3 200 2 100 1 IDD mA (VDD = +15V) CHIP SELECT CIRCUIT INFORMATION–DIGITAL SECTION t CH t CS 2R 0 R RFB A OUT A AGND 1 2 3 4 5 6 7 8 VIN – Volts 9 10 11 12 13 14 Figure 3. Typical Plots of Supply Current, IDD vs. Logic Input Voltage VIN, for VDD = +5 V and +15 V DAC A DATA LATCHES AND DRIVERS Figure 1. Simplified Functional Circuit for DAC A –4– REV. B AD7528 VIN A (± 10V) Table I. Unipolar Binary Code Table R11 DAC Latch Contents MSB LSB R21 VDD DAC A/ DAC B CS C12 RFB A DB0 DATA INPUTS DB7 INPUT BUFFER AGND AD7528 10000000 C22 RFB B LATCH 10000001 AGND R41 CONTROL LOGIC WR 11111111 VOUT A OUT A DAC A LATCH OUT B DAC B VOUT B 01111111 DGND AGND 00000001 R31 00000000 VIN B (± 10V) NOTES: 1R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. SEE TABLE III FOR RECOMMENDED VALUES. 2C1, C2 PHASE COMPENSATION (10pF–15pF) IS REQUIRED WHEN USING HIGH SPEED AMPLIFIERS TO PREVENT RINGING OR OSCILLATION. ( ) Note: 1 LSB = 2−8 (V IN ) = Analog Output (DAC A or DAC B)  255  –V IN    256   129  –V IN    256  V  128  –V IN   = − IN  256  2  127  –V IN    256   1  –V IN    256   0  –V IN   =0  256  1 (V ) 256 IN Figure 4. Dual DAC Unipolar Binary Operation (2 Quadrant Multiplication); See Table I VIN A (± 10V) Table II. Bipolar (Offset Binary) Code Table R5 20kV R21 VDD DB0 DATA INPUTS DB7 RFB A INPUT BUFFER DAC A LATCH DAC Latch Contents Analog Output MSB LSB (DAC A or DAC B) R62 20kV R11 OUT A R72 10kV C13 A1 A2 VOUT A AGND 10000001 AGND 10000000 AGND DAC A/ DAC B CS WR AD7528 CONTROL LOGIC RFB B LATCH 0 R41 DAC B DGND OUT B AGND R31 A3 R8 20kV 00000001 R92 10kV R102 20kV  1  –V IN    128   127  –V IN    128   128  –V IN    128  01111111 C23 VIN B (± 10V) A4 R12 5kV AGND NOTES: 1R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. SEE TABLE III FOR RECOMMENDED VALUES. ADJUST R1 FOR VOUT A = 0V WITH CODE 10000000 IN DAC A LATCH. ADJUST R3 FOR VOUT B = 0V WITH CODE 10000000 IN DAC B LATCH. 2MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R6, R7 AND R9, R10. 3C1, C2 PHASE COMPENSATION (10pF–15pF) MAY BE REQUIRED IF A1/A3 IS A HIGH SPEED AMPLIFIER. VOUT B 00000000 ( ) Note: 1 LSB = 2−7 (V IN ) = 1 (V ) 128 IN Table III. Recommended Trim Resistor Values vs. Grade Figure 5. Dual DAC Bipolar Operation (4 Quadrant Multiplication); See Table II REV. B  127  +V IN    128  11111111 R11 5kV –5– Trim Resistor J/A/S K/B/T L/C/U R1; R3 R2; R4 1k 330 500 150 200 82 AD7528 APPLICATIONS INFORMATION Application Hints To ensure system performance consistent with AD7528 specifications, careful attention must be given to the following points: 1. GENERAL GROUND MANAGEMENT: AC or transient voltages between the AD7528 AGND and DGND can cause noise injection into the analog output. The simplest method of ensuring that voltages at AGND and DGND are equal is to tie AGND and DGND together at the AD7528. In more complex systems where the AGND–DGND intertie is on the backplane, it is recommended that diodes be connected in inverse parallel between the AD7528 AGND and DGND pins (1N914 or equivalent). 2. OUTPUT AMPLIFIER OFFSET: CMOS DACs exhibit a code-dependent output resistance which in turn causes a code-dependent amplifier noise gain. The effect is a codedependent differential nonlinearity term at the amplifier output which depends on VOS (VOS is amplifier input offset voltage). This differential nonlinearity term adds to the R/2R differential nonlinearity. To maintain monotonic operation, it is recommended that amplifier VOS be no greater than 10% of 1 LSB over the temperature range of interest. 3. HIGH FREQUENCY CONSIDERATIONS: The output capacitance of a CMOS DAC works in conjunction with the amplifier feedback resistance to add a pole to the open loop response. This can cause ringing or oscillation. Stability can be restored by adding a phase compensation capacitor in parallel with the feedback resistor. ship between input frequency and channel to channel isolation. Figure 7 shows a printed circuit layout for the AD7528 and the AD644 dual op amp which minimizes feedthrough and crosstalk. SINGLE SUPPLY APPLICATIONS The AD7528 DAC R-2R ladder termination resistors are connected to AGND within the device. This arrangement is particularly convenient for single supply operation because AGND may be biased at any voltage between DGND and VDD. Figure 8 shows a circuit which provides two +5 V to +8 V analog outputs by biasing AGND +5 V up from DGND. The two DAC reference inputs are tied together and a reference input voltage is obtained without a buffer amplifier by making use of the constant and matched impedances of the DAC A and DAC B reference inputs. Current flows through the two DAC R-2R ladders into R1 and R1 is adjusted until the VREF A and VREF B inputs are at +2 V. The two analog output voltages range from +5 V to +8 V for DAC codes 00000000 to 11111111. VDD = +15V DAC A VOUT A = +5V TO +8V DB0 DATA INPUTS DB7 CS WR SUGGESTED OP AMP: AD644 AD7528 DAC A/DAC B VOUT B = +5V TO +8V DAC B 2 VOLTS R1 10kV AD584J R2 1kV DYNAMIC PERFORMANCE GND The dynamic performance of the two DACs in the AD7528 will depend upon the gain and phase characteristics of the output amplifiers together with the optimum choice of the PC board layout and decoupling components. Figure 6 shows the relation –100 TA = +258C VDD = +15V VIN = 20V PEAK TO PEAK ISOLATION – dB –90 VDD –80 Figure 8. AD7528 Single Supply Operation Figure 9 shows DAC A of the AD7528 connected in a positive reference, voltage switching mode. This configuration is useful in that VOUT is the same polarity as VIN allowing single supply operation. However, to retain specified linearity, VIN must be in the range 0 V to +2.5 V and the output buffered or loaded with a high impedance, see Figure 10. Note that the input voltage is connected to the DAC OUT A and the output voltage is taken from the DAC VREF A pin. –70 VOUT VIN (0V TO +2.5V) VREF A –60 –50 VDD +15V 20k 50k 100k 200k INPUT FREQUENCY – Hz 500k DAC A OUT A AD7528 1M Figure 9. AD7528 in Single Supply, Voltage Switching Mode Figure 6. Channel-to-Channel Isolation 3 V+ PIN 8 OF TO-5 CAN (AD644) TA = +258C VDD = +15V ERROR – LSB AD644 V– AGND AD7528 PIN 1 C1 LOCATION VREF B* VDD WR CS LSB AD7528 C2 LOCATION *NOTE INPUT SCREENS TO REDUCE VREF A* FEEDTHROUGH. DGND LAYOUT SHOWS DAC A/DAC B COPPER SIDE (i.e., BOTTOM VIEW). MSB 2 NONLINEARITY 1 DIFFERENTIAL NONLINEARITY 2.5 Figure 7. Suggested PC Board Layout for AD7528 with AD644 Dual Op Amp 3 3.5 4 5 4.5 5.5 VIN A – Volts 6 6.5 7 7.5 Figure 10. Typical AD7528 Performance in Single Supply Voltage Switching Mode (K/B/T, L/C/U Grades) –6– REV. B AD7528 MICROPROCESSOR INTERFACE ADDRESS BUS A8–A15 A** ADDRESS BUS A0–A15 A** VMA CPU 6800 DAC A/DAC B ADDRESS DECODE LOGIC D0–D7 CS DAC A WR AD7528* DB0 DB7 DAC B A + 1** WR CS DAC A WR AD7528* DB0 DB7 DAC B A + 1** f2 DAC A/DAC B ADDRESS DECODE LOGIC CPU 8085 LATCH 8212 ALE ADDR/DATA BUS AD0–AD7 *ANALOG CIRCUITRY HAS BEEN OMITTED FOR CLARITY **A = DECODED 7528 ADDR DAC A A + 1 = DECODED 7528 ADDR DAC B NOTE: 8085 INSTRUCTION SHLD (STORE H & L DIRECT) CAN UPDATE BOTH DACs WITH DATA FROM H AND L REGISTERS DATA BUS *ANALOG CIRCUITRY HAS BEEN OMITTED FOR CLARITY **A = DECODED 7528 ADDR DAC A A + 1 = DECODED 7528 ADDR DAC B Figure 11. AD7528 Dual DAC to 6800 CPU Interface Figure 12. AD7528 Dual DAC to 8085 CPU Interface PROGRAMMABLE WINDOW COMPARATOR VCC RFB A OUT A 3 VREF A DAC A 2 DB0 DATA INPUTS DB7 CS 1kV 7 AD311 COMPARATOR AD7528 WR OUT B 2 DAC A/DAC B +VREF In the circuit of Figure 13 the AD7528 is used to implement a programmable window comparator. DACs A and B are loaded with the required upper and lower voltage limits for the test, respectively. If the test input is not within the programmed limits, the pass/fail output will indicate a fail (logic zero). VDD TEST INPUT 0 TO –VREF 3 DAC B VREF B RFB B PASS/ FAIL OUTPUT 7 AD311 COMPARATOR Figure 13. Digitally Programmable Window Comparator (Upper and Lower Limit Detector) PROGRAMMABLE STATE VARIABLE FILTER In this state variable or universal filter configuration (Figure 14) DACs A1 and B1 control the gain and Q of the filter characteristic while DACs A2 and B2 control the cutoff frequency, fC . DACs A2 and B2 must track accurately for the simple expression for fC to hold. This is readily accomplished by the AD7528. Op amps are 2 × AD644. C3 compensates for the effects of op amp gain bandwidth limitations. The filter provides low pass, high pass and band pass outputs and is ideally suited for applications where microprocessor control of filter parameters is required, e.g., equalizer, tone controls, etc. Programmable range for component values shown is fC = 0 kHz to 15 kHz and Q = 0.3 to 4.5. CIRCUIT EQUATIONS R5 30kV R3 10kV A1 VDD R4 30kV A2 C3 47pF HIGH PASS OUTPUT C1 1000pF C2 1000pF A3 A4 BAND PASS OUTPUT VDD AD7528 VIN DAC A1 RS DAC B1 RF DB0–DB7 DATA 1 DAC A2 R1 AD7528 DAC B2 R2 DB0–DB7 CS WR DAC A/DAC B DATA 2 CS WR DAC A/DAC B Figure 14. Digitally Controlled State Variable Filter REV. B –7– C1 = C 2, R1 = R2, R4 = R5 LOW PASS OUTPUT 1 2 π R1C1 R3 RF Q= × R4 RFBB1 RF AO = – RS fC = NOTE DAC Equivalent Resistance Equals 256 × ( DAC Ladder Resistance ) DAC Digital Code AD7528 In this configuration the AD7528 functions as a 2-channel digitally controlled attenuator. Ideal for stereo audio and telephone signal level control applications. Table IV gives input codes vs. attenuation for a 0 dB to 15.5 dB range.  Attenuation, dB  20   Input Code = 256 ⫻ 10 exp  − VDD VIN A DAC A A1 DB0 DATA BUS DB7 CS AD7528 WR DAC A/DAC B VIN B DAC B A2 VOUT B VOUT A SUGGESTED OP AMP: AD644 Figure 15. Digitally Controlled Dual Telephone Attenuator Table IV. Attenuation vs. DAC A, DAC B Code for the Circuit of Figure 15 Attn. DAC Input dB Code 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 Code In Decimal 11111111 11110010 11100100 11010111 11001011 11000000 10110101 10101011 10100010 10011000 10010000 10001000 10000000 01111001 01110010 01101100 Attn. DAC Input dB Code 255 242 228 215 203 192 181 171 162 152 144 136 128 121 114 108 88.0 88.5 89.0 89.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 Code In Decimal 01100110 01100000 01011011 01010110 01010001 01001100 01001000 01000100 01000000 00111101 00111001 00110110 00110011 00110000 00101110 00101011 102 96 91 86 81 76 72 68 64 61 57 54 51 48 46 43 C681e–0–9/98 DIGITALLY CONTROLLED DUAL TELEPHONE ATTENUATOR For further applications information the reader is referred to Analog Devices Application Note on the AD7528. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Lead Cerdip (Q-20) 20-Lead Plastic DIP (N-20) 1.07 (27.18) MAX 11 0.28 (7.11) 0.24 (6.1) PIN 1 1 20 10 11 1 0.32 (8.128) 0.29 (7.366) 0.97 (24.64) 0.935 (23.75) 0.20 (5.0) 0.14 (3.56) 0.14 (3.56) 0.125 (3.17) 0.15 (3.8) 0.125 (3.18) SEATING PLANE 10 PIN 1 SEATING 0.011 (0.28) 0.11 (2.79) 0.065 (1.66) PLANE 0.021 (0.533) 158 0.009 (0.23) 0.09 (2.28) 0.045 (1.15) 08 0.015 (0.381) LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH LEADS ARE SOLDER OR TIN-PLATED KOVAR OR ALLOY 42 0.011 (0.28) 0.009 (0.23) 20-Lead SOIC (R-20) 20-Lead Plastic Leaded Chip Carrier (P-20A) 0.5118 (13.00) 0.4961 (12.60) 20 11 10 0.048 (1.21) 0.042 (1.07) 0.4193 (10.65) 0.3937 (10.00) 3 4 18 TOP VIEW 0.0118 (0.30) 0.0040 (0.10) 0.1043 (2.65) 0.0926 (2.35) 8 0.02 9 (0.51) MAX 0.02 (0.51) MAX 0.0291 (0.74) 3 458 0.0098 (0.25) 88 0.0500 0.0192 (0.49) SEATING 08 (1.27) 0.0138 (0.35) PLANE 0.0125 (0.32) BSC 0.0091 (0.23) 0.12 (3.05) 0.09 (2.29) 0.020 (0.51) MIN 19 PIN 1 IDENTIFIER (PINS DOWN) PIN 1 0.180 (4.47) 0.165 (4.19) 0.395 (10.02) SQ 0.385 (9.78) 0.356 (9.04) 0.350 (8.89) SQ 0.2992 (7.60) 0.2914 (7.40) 1 0.32 (8.128) 0.30 (7.62) 0.135 (3.429) 0.125 (3.17) 0.145 (3.683) MIN 0.125 (3.175) MIN 0.07 (1.78) 0.02 (0.5) 0.11 (2.79) 158 0.05 (1.27) 0.016 (0.41) 0.09 (2.28) 08 LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH LEADS ARE SOLDER OR TIN-PLATED KOVAR OR ALLOY 42 0.255 (6.477) 0.245 (6.223) 0.021 (0.53) 0.013 (0.33) 0.050 (1.27) BSC 0.032 (0.81) 0.026 (0.66) 14 13 0.025 (0.64) MIN 0.060 (1.53) MIN 0.0500 (1.27) 0.0157 (0.40) –8– REV. B PRINTED IN U.S.A. 20