73S8009CN-32IMR/F

73S8009CN Combo ISO-7816 and USB Universal Smart Card Interface IC Simplifying System Integration™ DATA SHEET DS_8009C_026 August 2009 FEATURES • DESCRIPTION The Teridian 73S8009CN is the world’s first single-chip smart card electrical interface circuit that supports all types of smart cards: 5V, 3V and 1.8V, including traditional ISO-7816-3 asynchronous and synchronous type 1 and type 2, as well as USB, ISO-7816-12 cards. The 73S8009CN is ideally suited for applications such as desktop computers, laptops and general purpose smart card readers that require low power operation from a single 2.7V to 6.5V power supply voltage source. A power down mode (“OFF” mode) is available and exhibits a 10nA typical current consumption. The circuit provides control, conversion and regulation of power for the smart card. In addition, the circuit provides a 3.3V-regulated voltage that is used as an internal digital supply voltage to the host interface. It is also made available to supply power to some external circuitry (a host controller for instance). • For asynchronous and synchronous smart card operation, the signals for RST, CLK, I/O and auxiliary signals AUX1 and AUX2 are directly controlled from the host processor and are level-shifted by the circuit to the selected VCC value. For more design flexibility, the host processor is responsible for handling the signal timing for smart card activation and deactivation under normal conditions. The power management circuitry allows operation from a single power supply source VPC (2.7V to 6.5V). VPC is converted using an inductive, step-up power converter to the intermediate voltage, VP. VP is used by linear voltage regulators and switches internal to the IC to create the voltages VDD and as required, VCC. VDD is used by the 73S8009CN and is also made available for the companion host processor circuit or for other external circuits. The 73S8009CN features an ON/OFF pin suitable to connect to a “push-on/push-off” main system switch. When the 73S8009CN is “OFF,” the typical current drawn from VPC is 10nA. For applications that do not implement any ON/OFF system switch, the ON/OFF input pin can be driven from a digital output of the host processor. Rev. 1.4 • • • • • • Smart Card Interface:  Smart card voltage VCC: o Selectable: 1.8V, 3V or 5V o Generated by an internal voltage regulator o Provides up to 65mA to 3V and 5V cards and up to 40mA to 1.8V cards  ISO-7816-3 card emergency deactivation  Voltage supervisor detects voltage drop on VCC (card supply)  True card over-current detection 150mA max.  1 input for a card presence detection switch  Auxiliary I/O lines for synchronous and ISO-7816-12 USB card support  Proper isolation of smart card signals depending on smart card type  Card CLK clock frequency up to 20MHz  6kV ESD and short circuit protection on the card interface System Controller Interface:  Digital logic level: 3.3V  5 signal images of the card signals (RSTIN, CLKIN, I/OUC, AUX1UC and AUX2UC)  1 control signal to switch between synchronous / asynchronous and ISO-7816-12 USB smart card modes  2 inputs activate and select the card voltage (CMDVCC% and CMDVCC#)  2 outputs, interrupt to the system controller (OFF and RDY), to inform the system controller of the card presence / faults and status of the interface  1 Chip Select input  2 handshaking signals (OFF_REQ, OFF_ACK) for proper shutdown sequencing of all smart card signals ON/OFF Input for a Main System Switch DC-DC Step-up Converter:  Generates an intermediary voltage VP  Requires a single 10µH Inductor (rated for 400mA maximum peak current) VDD power supply output available to power up external circuitry: 3.3V ±0.3V, 40mA Industrial temperature range (-40 °C to +85 °C) Small format QFN32 package: 5x5mm RoHS compliant (6/6) lead-free package © 2009 Teridian Semiconductor Corporation 1 73S8009CN Data Sheet DS_8009CN_026 FUNCTIONAL DIAGRAM ON/OFF 24K Debounce and Latch VPC 10µF 0.1µF OFF_REQ ON 10uH 100K Linear/ DC - DC Converter LIN OFF OFF_ACK VP V1.8ThREF V3.0ThREF V5.0ThREF Analog Mux CS - Delay/ Debounce Circuit + RDY CMDVCC# CMDVCC% PRES TEST1 Card Supply and Control Logic VCC Regulator VCC 0.47µF Vcc Status SHUTDOWN OFF TEST2 I/OUC I/O RSTIN RST CLKIN AUX1UC To Internal Digital Logic CLK Card I/O Buffer and Signal Logic DP AUX1 DM AUX2 AUX2UC SC/USB VDD 3.3V Regulator 0.1µF VP GND GND 0.1µF GND 4.7µF Figure 1: 73S8009CN Block Diagram 2 Rev. 1.4 DS_8009CN_026 73S8009CN Data Sheet Table of Contents 1 Pinout ............................................................................................................................................. 5 2 3 Electrical Specifications................................................................................................................ 9 2.1 Absolute Maximum Ratings ..................................................................................................... 9 2.2 Recommended Operating Conditions ...................................................................................... 9 2.3 Smart Card Interface Requirements ...................................................................................... 10 2.4 Digital Signals Characteristics ............................................................................................... 12 2.5 DC Characteristics ................................................................................................................ 13 2.6 Voltage / Temperature Fault Detection Circuits...................................................................... 13 2.7 Thermal Characteristics ........................................................................................................ 13 Applications Information ............................................................................................................. 13 3.1 Example 73S8009CN Schematics ......................................................................................... 13 3.2 Power Supply and Converter ................................................................................................. 16 3.3 Interface Function - ON/OFF Modes...................................................................................... 16 3.4 System Controller Interface ................................................................................................... 18 3.5 Card Power Supply and Voltage Supervision......................................................................... 18 3.6 Activation and De-activation Sequence ................................................................................. 19 3.7 OFF and Fault Detection ....................................................................................................... 20 3.8 Chip Selection ....................................................................................................................... 21 3.9 I/O Circuitry and Timing......................................................................................................... 22 4 Equivalent Circuits ...................................................................................................................... 24 5 Mechanical Drawing .................................................................................................................... 28 6 Ordering Information ................................................................................................................... 29 7 Related Documentation ............................................................................................................... 29 8 Contact Information..................................................................................................................... 29 Rev. 1.4 3 73S8009CN Data Sheet DS_8009CN_026 Figures Figure 1: 73S8009CN Block Diagram ...................................................................................................... 2 Figure 2: 73S8009CN 32-Pin QFN Pinout ................................................................................................ 5 Figure 3: Typical 73S8009CN Application Schematic with a Main System Switch................................... 14 Figure 4: Typical 73S8009CN Application Schematic without a Main System Switch .............................. 15 Figure 5: Activation Sequence ............................................................................................................... 19 Figure 6: Deactivation Sequence ........................................................................................................... 20 Figure 7: OFF Activity ............................................................................................................................ 20 Figure 8: CS Timing Definitions.............................................................................................................. 21 Figure 9: I/O and I/OUC State Diagram .................................................................................................. 22 Figure 10: I/O – I/OUC Delays - Timing Diagram.................................................................................... 23 Figure 11: On_Off Pin ............................................................................................................................ 24 Figure 12: Open Drain type – OFF and RDY .......................................................................................... 24 Figure 13: Power Input/Output Circuit, VDD, LIN, VPC, VCC, VP ........................................................... 24 Figure 14: USB – DM, DP Pins .............................................................................................................. 25 Figure 15: Smart Card CLK Driver Circuit .............................................................................................. 25 Figure 16: Smart Card RST Driver Circuit .............................................................................................. 25 Figure 17: Smart Card IO, AUX1, and AUX2 Interface Circuit................................................................. 26 Figure 18: Smart Card IOUC, AUX1UC and AUX2UC Interface Circuit .................................................. 26 Figure 19: General Input Circuit ............................................................................................................. 27 Figure 20: OFF_REQ Interface Circuit ................................................................................................... 27 Figure 21: 32-Pin QFN Package Dimensions ......................................................................................... 28 Tables Table 1: 73S8009CN Pin Definitions ........................................................................................................ 5 Table 2: Absolute Maximum Device Ratings ............................................................................................ 9 Table 3: Recommended Operating Conditions ......................................................................................... 9 Table 4: DC Smart Card Interface Requirements ................................................................................... 10 Table 5: Digital Signals Characteristics .................................................................................................. 12 Table 6: DC Characteristics ................................................................................................................... 13 Table 7: Voltage / Temperature Fault Detection Circuits......................................................................... 13 Table 8: Thermal Characteristics ........................................................................................................... 13 Table 9: Order Numbers and Packaging Marks ...................................................................................... 29 4 Rev. 1.4 DS_8009CN_026 73S8009CN Data Sheet 1 Pinout OFF GND TEST2 VDD GND LIN VPC DP 32 31 30 29 28 27 26 25 The 73S8009CN is supplied as a 32-pin QFN package. I/OUC 1 24 ON/OFF AUX1UC 2 23 DM AUX2UC 3 22 I/O CMDVCC5 4 21 AUX1 CMDVCC3 5 20 AUX2 RSTIN 6 19 VCC CLKIN 7 18 RST RDY 8 17 GND 10 11 12 13 14 15 16 TEST1 OFF_REQ CS SC/USB PRES VP CLK OFF_ACK 9 TERIDIAN 73S8009CN Figure 2: 73S8009CN 32-Pin QFN Pinout Table 1 describes the pin functions for the device. Table 1: 73S8009CN Pin Definitions Pin Number Type Equivalent Circuit 22 IO Figure 17 Card I/O: Data signal to/from smart card. Includes an 11kΩ pull-up resistor to VCC Will be tri-stated when SC/USB is set low. AUX1 21 IO Figure 17 AUX1: Auxiliary data signal to/from smart card for synchronous smart card operation. Smart card USB DP signal for IS0-7816-12 USB smart card operation. Includes an 11kΩ pull-up resistor to VCC for synchronous / asynchronous operation only. AUX2 20 IO Figure 17 AUX2: Auxiliary data signal to/from smart card for synchronous smart card operation. Smart card USB DM signal for IS0-7816-12 USB smart card operation. Includes an 11kΩ pull-up resistor to VCC for synchronous / asynchronous operation only. RST 18 O Figure 16 Card reset: provides reset (RST) signal to card. RST is the pass through signal on RSTIN. Internal control logic will hold RST low when card is not activated or VCC is too low. Will be tri-stated when SC/USB is set low. Pin Name Description Card Interface I/O Rev. 1.4 5 73S8009CN Data Sheet DS_8009CN_026 Pin Number Type Equivalent Circuit CLK 16 O Figure 15 Card clock: provides clock signal (CLK) to card. CLK is the pass through of the signal on pin CLKIN. Internal control logic will hold CLK low when card is not activated or VCC is too low. Will be tri-stated when SC/USB is set low. PRES 14 I Figure 19 Smart card Presence switch: Active high indicates card is present. Smart card activation will not be permitted unless PRES is active. VCC 19 PSO Figure 13 Card power supply – logically controlled by sequencer, output of LDO regulator. Requires an external 0.47uF low ESR filter capacitor to GND. GND 17 GND – Pin Name Description Card ground. Host Processor Interface 6 CS 12 I Figure 19 Chip Select. When CS = 1, the control and signal pins are configured normally. When CS is set low, CMDVCC%, RSTIN, and CMDVCC# are latched. I/OUC, AUX1UC, and AUX2UC are set to high-impedance pull-up mode and do not pass data to or from the smart card. Signals RDY and OFF are disabled to prevent a low output and the internal pull-up resistors are disconnected. Should be tied to VDD when a single 73S8009CN is used. OFF 32 O Figure 12 Interrupt signal to the processor. Active Low Multi-function indicating fault conditions and card presence. Open drain output configuration – It includes an internal 20kΩ pull-up to VDD. Pull-up is disabled in Power down state and CS = 0 modes. I/OUC 1 IO Figure 18 System controller data I/O to/from the card. Includes an 11kΩ pull-up resistor to VDD. AUX1UC 2 IO Figure 18 System controller auxiliary data I/O to/from the card for synchronous / asynchronous operation mode. Connection to AUX1 is opened when SC/USB is low. Includes an 11kΩ pull-up resistor to VDD. AUX2UC 3 IO Figure 18 System controller auxiliary data I/O to/from the card for synchronous / asynchronous operation mode. Connection to AUX2 is opened when SC/USB is low. Includes an 11kΩ pull-up resistor to VDD. SC/USB 13 I Figure 19 Smart Card Interface enable, USB interface disable. Pin is provided with a weak pull-up. When high, the 73S8009CN operates in synchronous / asynchronous operation mode. When low, CLK, RST I/O, AUX1, and AUX2 are tri-stated. Pin AUX1 is connected to pin DP and pin AUX2 is connected to pin DM. DP 25 IO Figure 14 USB D+ connection to / from USB controller. When SC/USB is set low, this pin is electrically connected to the AUX1 pin, otherwise it is isolated. Rev. 1.4 DS_8009CN_026 73S8009CN Data Sheet Pin Name Pin Number Type Equivalent Circuit DM 23 IO Figure 14 USB D- connection to / from USB controller. When SC/USB is set low, this pin is electrically connected to the AUX1 pin, otherwise it is isolated. CMDVCC% CMDVCC# 4 5 I I Figure 19 Logic low on one or both of these pins will cause the LDO regulator to ramp the Vcc supply to the smart card and smart card interface to the value described in the following table: Description CMDVCC% CMDVCC# Vcc Output Voltage 0 0 1.8V 0 1 5.0V 1 0 3.0V 1 1 Vcc Off Note: See Card Power Supply and Voltage Supervision for more details. RSTIN 6 I Figure 19 Reset Input: This signal is the reset command to the card. RDY 8 O Figure 12 Signal to controller indicating the 73S8009CN is ready because VCC is above the required value after CMDVCC% and/or CMDVCC# is asserted low. A 20kΩ pull-up resistor to VDD is provided internally. Pull-up is disabled in Power down state and CS=0 modes. ON/OFF 24 I Figure 11 Power control pin. Connected to normally open SPST switch to ground. Closing switch for duration greater than de-bounce period will turn 73S8009CN circuit “on”. If the 73S8009CN is “on,” closing the switch will turn 73S8009CN to “off” state after the de-bounce period and OFF_REQ/OFF_ACK handshake. Can be controlled by a host processor digital output. OFF_REQ 11 O Figure 19 Digital output. Request to the host system controller to turn the 73S8009CN off. If ON_OFF switch is closed (to ground) for de-bounce duration and circuit is “on,” OFF_REQ will go high (request to turn OFF). Connected to OFF_ACK via 100k Ω internal resistor. 13 I Figure 19 Setting OFF_ACK high will power “off” all analog functions and disconnect the 73S8009CN from VPC. The pin has an internal 100kΩ resistor connection to OFF_REQ so that when not connected or no host interaction is required, the Acknowledge will be true and the circuit will turn “off” after the deactivation sequence is completed. CLKIN 7 I Figure 19 Clock signal source for the card clock. TEST1 10 – – Factory test pin. This pin must be tied to GND. TEST2 30 – – Factory test pin. This pin must be tied to GND. OFF_ACK Miscellaneous Rev. 1.4 7 73S8009CN Data Sheet Pin Name Pin Number DS_8009CN_026 Type Equivalent Circuit Description Power Supply and Ground VDD 29 PSO Figure 13 System interface supply voltage output and supply voltage for companion controller circuit (40mA maximum source capability). Requires a minimum of two 0.1µF capacitors to ground for proper decoupling. VPC 26 PSI Figure 13 Power supply source for main voltage converter circuit. A 10µF and a 0.1µF ceramic capacitor must be connected to this pin. LIN 27 PSI Figure 13 Connection to 10µH inductor for internal step up converter. Note: inductor must be rated for 400mA maximum peak current. VP 15 PSO Figure 13 Intermediate output of main converter circuit. Requires an external 4.7µF low ESR filter capacitor to GND. 28, 31 GND – GND 8 Ground. Rev. 1.4 DS_8009CN_026 73S8009CN Data Sheet 2 Electrical Specifications This section provides the following:       Absolute maximum ratings Recommended operating conditions Smart card interface requirements Digital signals characteristics Voltage / temperature fault detection circuits Thermal characteristics 2.1 Absolute Maximum Ratings Table 2 lists the maximum operating conditions for the 73S8009CN. Permanent device damage may occur if absolute maximum ratings are exceeded. Exposure to the extremes of the absolute maximum rating for extended periods may affect device reliability. Table 2: Absolute Maximum Device Ratings Parameter Supply Voltage VPC VDD Input Voltage for Digital Inputs Storage Temperature Pin Voltage (except card interface) Pin Voltage (card interface) Pin Voltage, LIN pin ESD Tolerance – Card interface, DP and DM pins ESD Tolerance – Other pins Pin Current, except LIN Pin Current, LIN 2.2 Rating -0.5 to 7.0 VDC -0.5 to 4.0 VDC -0.3 to (VDD +0.5) VDC -65 to 150°C -0.3 to (VDD + 0.5) VDC -0.3 to (VCC + 0.3) VDC 0.3 to 6.5 VDC +/- 6kV +/- 2kV ± 200 mA + 500 mA in, -200 mA out Recommended Operating Conditions Function operation should be restricted to the recommended operating conditions specified in Table 3. Table 3: Recommended Operating Conditions Parameter Supply voltage VPC Ambient operating temperature Rev. 1.4 Rating 2.7 to 6.5 VDC -40°C to +85°C 9 73S8009CN Data Sheet 2.3 DS_8009CN_026 Smart Card Interface Requirements Table 4 lists the 73S8009CN Smart Card interface requirements. Table 4: DC Smart Card Interface Requirements Symbol Parameter Condition Card Power Supply (VCC) Regulator General Conditions: -40C < 85C, 2.7 V < VPC < 6.5 V Inactive mode Inactive mode ICC = 1mA Active mode; ICC