73S8010R-ILR/F

73S8010R Low Cost Smart Card Interface Simplifying System Integration™ DATA SHEET DS_8010R_022 August 2009 APPLICATIONS • DESCRIPTION The Teridian 73S8010R is a single smart card interface IC that provides full electrical compliance with ISO-7816-3 and EMV 4.0 (EMV2000) specifications. Interfacing with the host is done through the two-wire 2 I C bus and one interrupt output to inform the system controller of the card presence and faults. The card clock signal can be generated by an on-chip oscillator using an external crystal, or by connection to a clock signal. The Teridian 73S8010R incorporates an ISO-7816-3 activation/deactivation sequencer that controls the card signals. Level-shifters drive the card signals with the selected card voltage (3 V or 5 V), coming from an internal Low Drop-Out (LDO) voltage regulator. This LDO regulator is powered by a dedicated power supply input, VPC. Digital circuitry is separately powered by a digital power supply, VDD. • • • ADVANTAGES • Single smart card interface • IC firmware compatible with TDA8020 • Traditional step-up converter is replaced by an LDO regulator  Greatly reduced power dissipation  Fewer external components are required  Better noise performance  High current capability (90 mA supplied to the card) • Small format (5x5x0.8 mm) QFN32 package option • True card over-current detection FEATURES • With its embedded LDO regulator, the Teridian 73S8010R is a cost-effective solution for any application where a 5 V (typically -5% +10%) power supply is available. Hardware support for auxiliary I/O lines, C4 / C8 contacts is provided. Emergency card deactivation is initiated upon card extraction or upon any fault generated by the protection circuitry. The fault can be a card over-current, a VDD (digital power supply), a VPC (regulator power supply), a VCC (card power supply) or an over-heating fault. The card over-current circuitry is a true current detect function, as opposed to VCC voltage drop detection, as usually implemented in ICC interface ICs. The VDD voltage fault has a threshold voltage that can be adjusted with an external resistor or resistor network. It allows automated card deactivation at a customized VDD voltage threshold value. It can be used, for instance, to match the system controller operating voltage range. Rev. 1.6 Set-Top-Box Conditional Access and Pay-per-View Point of Sales & Transaction Terminals Control Access & Identification Multiple card and SAM reader configurations • • • Card Interface • Complies with ISO-7816-3 and EMV 4.0 • An LDO voltage regulator provides 3 V / 5 V to the card from an external power supply input • ISO-7816-3 Activation / Deactivation sequencer with emergency automated deactivation on card removal or fault detected by the protection circuitry • Protection includes 3 voltage supervisors that detect voltage drops on VCC card and on power supplies VDD and VPC • Over-current detection 150 mA max • 1 card detection input • Auxiliary I/O lines, for C4 / C8 contact signals Host Interface • Fast mode, 400 kbps I2C slave bus • 8 possible devices in parallel • One control register and one status register • Interrupt output to the host for fault detection • Crystal oscillator or host clock, up to 27 MHz 6 kV ESD protection on the card interface SO28 or QFN32 package © 2009 Teridian Semiconductor Corporation 1 73S8010R Data Sheet DS_8010R_022 FUNCTIONAL DIAGRAM VDD GND VDDF_ADJ [17] 18 [20] 21 VPC [2] 5 [3] 6 [4, 5, 6, 9, 16, 25, 32] 7, 8, 9 NC VPC FAULT [21] 22 [1] 4 VDD VOLTAGE SUPERVISOR VOLTAGE REFERENCE GND VDD FAULT LDO REGULATOR & VOLTAGE SUPERVISORS VCC FAULT [18] 19 SCL Int_Clk [19] 20 SDA R-C OSC. SAD0 [30] 2 SAD1 [31] 3 SAD2 [12] 14 GND [15] 17 VCC I 2C DIGITAL & FAULT LOGIC [29] 1 GND [22] 23 INT ISO-7816 SEQUENCER ICC RESET BUFFER [14] 16 ICC CLOCK BUFFER [13] 15 RST CLK [7] 10 PRES [23] 24 XTALIN [24] 25 XTALOUT XTAL OSC CLOCK GENERATION OVER TEMP TEMP FAULT [8] 11 [26] 26 I/O IOUC [27] 27 AUX1UC ICC I/O BUFFERS [11] 13 AUX1 [10] 12 [28] 28 AUX2 AUX2UC Pin numbers reference the SO28 package [Pin numbers] reference the QFN32 Package Figure 1: 73S8010R Block Diagram Rev. 1.6 2 DS_8010R_022 73S8010R Data Sheet Table of Contents 1 Pinout ............................................................................................................................................. 5 2 5 Electrical Specifications................................................................................................................ 8 2.1 Absolute Maximum Ratings ..................................................................................................... 8 2.2 Recommended Operating Conditions ...................................................................................... 8 2.3 Smart Card Interface Requirements ........................................................................................ 9 2.4 Digital Signals Characteristics ............................................................................................... 11 2.5 DC Characteristics ................................................................................................................ 11 2 2.6 I C Interface Characteristics .................................................................................................. 12 2.7 Voltage / Temperature Fault Detection Circuits...................................................................... 12 Applications Information ............................................................................................................. 13 3.1 Example 73S8010R Schematics ........................................................................................... 13 3.2 System Controller Interface (I2C Bus) .................................................................................... 14 3.3 Power Supply and Voltage Supervision ................................................................................. 17 3.4 Card Power Supply ............................................................................................................... 18 3.5 Over-temperature Monitor ..................................................................................................... 18 3.6 On-chip Oscillator and Card Clock......................................................................................... 18 3.7 Activation Sequence ............................................................................................................. 19 3.8 Deactivation Sequence ......................................................................................................... 19 3.9 Interrupt ................................................................................................................................ 20 3.10 Warm Reset .......................................................................................................................... 21 3.11 I/O Circuitry and Timing......................................................................................................... 21 Mechanical Drawings .................................................................................................................. 22 4.1 32-pin QFN ........................................................................................................................... 22 4.2 28-Pin SO ............................................................................................................................. 23 Ordering Information ................................................................................................................... 24 6 Related Documentation ............................................................................................................... 24 7 Contact Information..................................................................................................................... 24 3 4 Revision History .................................................................................................................................. 25 Rev. 1.6 3 73S8010R Data Sheet DS_8010R_022 Figures Figure 1: 73S8010R Block Diagram ......................................................................................................... 2 Figure 2: 73S8010R 32-Pin QFN Pinout .................................................................................................. 5 Figure 3: 73S8010R 28-Pin SO Pinout..................................................................................................... 5 Figure 4: Typical 73S8010R Application Schematic ............................................................................... 13 2 Figure 5: I C Bus Write Protocol ............................................................................................................ 15 2 Figure 6: I C Bus Read Protocol ............................................................................................................ 16 2 Figure 7: I C Bus Timing Diagram .......................................................................................................... 16 Figure 8: Activation Sequence ............................................................................................................... 19 Figure 9: Deactivation Sequence ........................................................................................................... 20 Figure 10: Interrupt operation due to Fault and Status Conditions .......................................................... 20 Figure 11: Warm Reset Operation ......................................................................................................... 21 Figure 12: I/O Timing Diagram ............................................................................................................... 21 Figure 13: 32-pin QFN Package Dimensions ......................................................................................... 22 Figure 14: 28-Pin SO Package Dimensions ........................................................................................... 23 Tables Table 1: 73S8010R Pin Definitions .......................................................................................................... 6 Table 2: Absolute Maximum Device Ratings ............................................................................................ 8 Table 3: Recommended Operating Conditions ......................................................................................... 8 Table 4: DC Smart Card Interface Requirements ..................................................................................... 9 Table 5: Digital Signals Characteristics .................................................................................................. 11 Table 6: DC Characteristics ................................................................................................................... 11 2 Table 7: I C Characteristics ................................................................................................................... 12 Table 8: Voltage / Temperature Fault Detection Circuits......................................................................... 12 Table 9: Device Address Selection ........................................................................................................ 14 Table 10: Control Register Description ................................................................................................... 14 Table 11: Card Clock Rate Selection ..................................................................................................... 14 Table 12: Status Register Description .................................................................................................... 15 Table 13: I2C Bus Timing Parameters ................................................................................................... 16 Table 14: Choice of VCC Pin Capacitor ................................................................................................. 18 Table 15: Card Clock Divisor Options .................................................................................................... 18 Table 16: Order Numbers and Packaging Marks .................................................................................... 24 4 Rev. 1.6 DS_8010R_022 73S8010R Data Sheet 1 Pinout NC SAD2 SAD1 SAD0 AUX2UC AUX1UC I/OUC NC 32 31 30 29 28 27 26 25 The 73S8010R is supplied as a 32-pin QFN package and as a 28-pin SO package. GND 1 24 XTALOUT GND 2 23 XTALIN VPC 3 22 INT NC 4 21 GND NC 5 20 VDD NC 6 19 SDA PRES 7 18 SCL I/O 8 17 VDDF_ADJ 16 14 RST NC 13 CLK 15 12 GND VCC 11 10 AUX2 AUX1 9 NC TERIDIAN 73S8010R Figure 2: 73S8010R 32-Pin QFN Pinout SAD0 1 28 AUX2UC SAD1 2 27 AUX1UC SAD2 3 26 I/OUC GND 4 25 XTALOUT GND 5 24 XTALIN VPC 6 23 INT NC 7 22 GND NC 8 21 VDD NC 9 20 SDA PRES 10 19 SCL I/O 11 18 VDDF_ADJ AUX2 12 17 VCC AUX1 13 16 RST GND 14 15 CLK 73S8010R Figure 3: 73S8010R 28-Pin SO Pinout Rev. 1.6 5 73S8010R Data Sheet DS_8010R_022 Table 1 describes the pin functions for the device. Table 1: 73S8010R Pin Definitions Pin Name Pin (SO28) Pin (QFN32) Type Description I/O 11 8 IO Card I/O: Data signal to/from card. Includes a pull-up resistor to VCC. AUX1 13 11 IO AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC. AUX2 12 10 IO AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC. RST 16 14 O Card reset: provides reset (RST) signal to card. CLK 15 13 O Card clock: provides clock signal (CLK) to card. The crystal oscillator frequency and CLKSEL bits in the control register determine the rate of this clock. PRES 10 7 I Card Presence switch: active high indicates card is present. Includes a pull-down resistor. VCC 17 15 PSO Card power supply – logically controlled by the sequencer, output of LDO regulator. Requires an external filter capacitor to GND. GND 14 12 GND Card ground. Card Interface Miscellaneous Inputs and Outputs XTALIN 24 23 I Crystal oscillator input: can be connected to crystal or driven as a source for the card clock. XTALOUT 25 24 O Crystal oscillator output: connected to crystal. Left open if XTALIN is being used as an external clock input. VDDF_ADJ 18 17 I VDD threshold adjustment input: this pin can be used to overwrite a higher VDDF value (that controls deactivation of the card). Must be left open if unused. 7, 8, 9 4,5,6,9, 16,25,32 – NC Non-connected pin. Power Supply and Ground VDD 21 20 System interface supply voltage and supply voltage for internal circuitry. VPC 6 3 LDO regulator power supply source. GND 4 1 GND LDO regulator ground. GND 14 12 GND Smart card I/O ground. GND 5, 22 2,21 GND Digital ground. 6 Rev. 1.6 DS_8010R_022 Pin Name 73S8010R Data Sheet Pin (SO28) Pin (QFN32) Type Description Microcontroller Interface INT 23 22 O Interrupt output signal (negative assertion) to the processor. A 20 kΩ pull up to VDD is provided internally. SAD0 SAD1 SAD2 1 2 3 29 30 31 I I I Serial device address bits. Digital inputs for address selection that allows for the connection of up to 8 devices in parallel. Address selections is as follows: SAD2 SAD1 SAD0 (7 bit) I2C Address 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0x40 0x42 0x44 0x46 0x48 0x4A 0x4C 0x4E Pins SAD0 and SAD1 are internally pulled down and SAD2 is internally pulled up. The default address when unconnected is 0x48. I2C clock signal input. SCL 19 18 I SDA 20 19 I/O I2C bi-directional serial data signal. I/OUC 26 26 IO System controller data I/O to/from the card. Includes an internal pull-up resistor to VDD. AUX1UC 27 27 IO System controller auxiliary data I/O to/from the card. Includes an internal pull-up resistor to VDD. AUX2UC 28 28 IO System controller auxiliary data I/O to/from the card. Includes an internal pull-up resistor to VDD. Rev. 1.6 7 73S8010R Data Sheet DS_8010R_022 2 Electrical Specifications This section provides the following:        2.1 Absolute Maximum Ratings Recommended Operating Conditions Smart Card Interface Requirements Digital Signals Characteristics DC Characteristics I2C Interface Characteristics Voltage / Temperature Fault Detection Circuits Absolute Maximum Ratings Table 2 lists the maximum operating conditions for the 73S8010R. Permanent device damage may occur if absolute maximum ratings are exceeded. Exposure to the extremes of the absolute maximum rating for extended periods may affect device reliability. Table 2: Absolute Maximum Device Ratings Parameter Rating Supply voltage VDD -0.5 to 6.0 VDC Supply voltage VPC -0.5 to 6.0 VDC Input voltage for digital inputs -0.3 to (VDD +0.5) VDC Storage temperature -60 °C to +150 °C Pin voltage (except card interface) -0.3 to (VDD + 0.5) VDC Pin voltage (card interface) -0.3 to (VCC + 0.5) VDC ESD tolerance – Card interface pins +/- 6 kV ESD tolerance – Other pins +/- 2 kV Note: ESD testing on smart card pins is HBM condition, 3 pulses, each polarity referenced to ground. 2.2 Recommended Operating Conditions Function operation should be restricted to the recommended operating conditions specified in Table 3. Table 3: Recommended Operating Conditions Parameter 8 Rating Supply voltage VDD 2.7 to 5.5 VDC Supply voltage VPC 4.75 to 5.5 VDC Ambient operating temperature -40 °C to +85 °C Input voltage for digital inputs 0 V to VDD to +0.3 V Rev. 1.6 DS_8010R_022 2.3 73S8010R Data Sheet Smart Card Interface Requirements Table 4 lists the 73S8010R Smart Card interface requirements. Table 4: DC Smart Card Interface Requirements Symbol Parameter Condition Min Nom Max Unit Card Power Supply (VCC) Regulator General Conditions: -40 °C < T < 85 °C, 4.75 V < VPC < 5.5 V, 2.7 V < VDD < 5.5 V VCC Card supply voltage including ripple and noise Inactive mode -0.1 – 0.1 V Inactive mode ICC = 1 mA -0.1 – 0.4 V Active mode; ICC < 65 mA; 5 V 4.60 – 5.25 V Active mode; ICC < 90 mA; 5 V 4.55 – Active mode; ICC < 90 mA; 3 V 2.80 – 3.2 V Active mode; single pulse of 100 mA for 2 µs; 5 V, fixed load = 25 mA 4.6 – 5.25 V Active mode; single pulse of 100 mA for 2 µs; 3 V, fixed load = 25 mA 2.76 – 3.2 V Active mode; current pulses of 40 nAs with peak |ICC | < 200 mA, t < 400 ns; 5 V 4.6 – 5.25 V Active mode; current pulses of 40 nAs with peak |ICC | < 200 mA, t 4.6 or 2.7 volts as selected V 9 73S8010R Data Sheet Symbol DS_8010R_022 Parameter Condition Min Nom Max Unit Interface Requirements – Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC, AUX2UC. ISHORTL, ISHORTH, and VINACT requirements do not pertain to I/OUC, AUX1UC, AUX2UC. VOH Output level, high (I/O, AUX1, AUX2) IOH = 0 µA 0.9 * VCC – VCC+0.1 V IOH = -40 µA 0.75 * VCC – VCC+0.1 V Output level, high (I/OUC, AUX1UC, AUX2UC) IOH = 0 µA 0.9 * VCC – VDD+0.1 V IOH = -40 µA 0.75 * VCC – VDD+0.1 V VOL Output level, low IOL = 1 mA – – 0.3 V VIH Input level, high (I/O, AUX1, AUX2) 1.8 – VCC+0.30 V VIH Input level, high (I/OUC, AUX1UC, AUX2UC) 1.8 – VCC+0.30 V VIL Input level, low -0.3 – 0.8 V VINACT Output voltage when outside of session IOL = 0 – – 0.1 V IOL = 1 mA – – 0.3 V VOH ILEAK Input leakage VIH = VCC – – 10 µA IIL Input current, low VIL = 0 – – 0.65 mA ISHORTL Short circuit output current For output low, shorted to VCC through 33 Ω – – 15 mA ISHORTH Short circuit output current For output high, shorted to ground through 33 Ω – – 15 mA t R, t F Output rise time, fall time For I/O, AUX1, AUX2, CL = 80 pF, 10% to 90%. For I/OUC, AUX1UC, AUX2UC, CL=50 pF, 10% to 90%. – – 100 ns tIR, tIF Input rise, fall times – – 1 µs RPU Internal pull-up resistor 8 11 14 kΩ Output stable for >200 ns FDMAX Maximum data rate – – 1 MHz TFDIO Delay, I/O to I/OUC, Falling edge from master I/OUC to I/O, AUX1 to to slave measured at AUX1UC, AUX1UC to 50% point AUX1, AUX2 to AUX2UC, AUX2UC to AUX2 60 100 200 ns TRDIO Delay, I/O to I/OUC, Rising edge from master I/OUC to I/O, AUX1 to to slave measured at AUX1UC, AUX1UC to 50% point AUX1, AUX2 to AUX2UC, AUX2UC to AUX2 – 25 90 ns CIN Input capacitance – – 10 pF 10 Rev. 1.6 DS_8010R_022 Symbol 73S8010R Data Sheet Parameter Condition Min Nom Max Unit 0.9 * VCC – VCC V Reset and Clock for card interface, RST, CLK VOH Output level, high IOH = -200 µA VOL Output level, low IOL = 200 µA 0 – 0.3 V VINACT Output voltage when outside of session IOL = 0 – – 0.1 V – – 0.3 V IRST_LIM Output current limit, RST – – 30 mA ICLK_LIM Output current limit, CLK t R, t F Output rise time, fall time δ 2.4 IOL = 1 mA Duty cycle for CLK – – 70 mA CL = 35 pF for CLK, 10% to 90% – – 8 ns CL = 200 pF for RST, 10% to 90% – – 100 ns CL =35 pF, FCLK ≤ 20MHz 45 – 55 % Digital Signals Characteristics Table 5 lists the 73S8010R digital signals characteristics. Table 5: Digital Signals Characteristics Symbol Parameter Condition Min Nom Max Unit Digital I/O except for OSC I/O VIL Input low voltage -0.3 – 0.8 V VIH Input high voltage 0.7 * VDD – VDD+0.3 V VOL Output low voltage IOL = 2 mA – 0.45 V VOH Output high voltage IOH = -1 mA ROUT Pull-up resistor; INT |I IL1 | Input leakage current VDD-0.45 – – 20 – kΩ -5 – 5 μA GND < VIN < VDD V Oscillator (XTALIN) I/O VILXTAL Input low voltage - XTALIN -0.3 – 0.5 V VIHXTAL Input high voltage - XTALIN 0.7*VDD – VDD+0.3 V IILXTAL Input current - XTALIN -30 – 30 μA 2.5 GND < VIN < VDD DC Characteristics Table 6 lists the DC characteristics. Table 6: DC Characteristics Symbol Parameter IDD Supply current on VDD IPC Supply current on VPC Rev. 1.6 Condition VCC on, ICC = 0 I/O, AUX1, AUX2 = high Min Nom Max Unit – 1.5 3.0 mA – 0.45 0.65 mA 11 73S8010R Data Sheet 2.6 DS_8010R_022 I2C Interface Characteristics 2 Table 7 lists the I C Interface characteristics. 2 Table 7: I C Characteristics Symbol Parameter Condition Min Nom Max Unit VIL Input low voltage -0.3 – 0.3 * VDD V VIH Input high voltage 0.7 * VDD – VDD+0.3 V VOL Output low voltage – – 0.40 V CIN Pin capacitance – – 10 pF IIN Output high voltage IOH = -1 mA VDD - 0.45 – TF Output fall time CL = 0 to 400 pF 20 + 0.1*CL – 250 ns TSP Pulse width of spikes that are suppressed Transition from valid logic level to opposite level – – 50 ns 2.7 IOL = 3 mA V Voltage / Temperature Fault Detection Circuits Table 8 lists the voltage / temperature fault detection circuits. Table 8: Voltage / Temperature Fault Detection Circuits Symbol Parameter Condition Min Nom Max Unit VDDF VP over-current fault No external resistor on VDDF_ADJ pin 2.15 – 2.4 V VPCF VPC fault (VPC Voltage Supervisor threshold) VPC < VCC, a transient event – VCC - 0.2 – V VCCF VCC fault (VCC Voltage Supervisor threshold) VCC = 5 V 4.20 – 4.55 V VCC = 3 V 2.5 – 2.7 V 115 – 145 °C TF 12 Die over temperature fault Rev. 1.6 DS_8010R_022 73S8010R Data Sheet 3 Applications Information This section provides general usage information for the design and implementation of the 73S8010R. 3.1 Example 73S8010R Schematics Figure 4 shows a typical application schematic for the implementation of the 73S8010R. Note that minor changes may occur to the reference material from time to time and the reader is encouraged to contact Teridian for the latest information AUX2UC_to/from_uC AUX1UC_to.from_uC See NOTE 5 I/OUC_to/from_uC See note 7 See NOTE 3 SAD0 External_clock_from uC SAD1 - OR SAD2 C2 VDD 22pF C4 C5 VPC 100nF 10uF See note 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 AUX2UC AUX1UC I/OUC XTALOUT XTALIN INT GND VDD SDA SCL VDDF_ADJ VCC RST CLK SAD0 SAD1 SAD2 GND GND VPC NC NC NC PRES I/O AUX2 AUX1 GND 73S8010R Y1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 R3 Rext2 CRYSTAL C3 22pF See NOTE 4 See NOTE 1 VDD C6 100nF R1 Rext1 SO28 R4 R5 2K 2K See note 6 INT_interrupt_to_uC SDA_to/from_uC SCK_from_uC VDD ISO7816=1uF, EMV=3.3uF Low ESR ( .5 μs t3 = > 0.5 μs t2 t3 t4 t2 = > 7.5 μs t4 = > 0.5 μs Figure 9: Deactivation Sequence 3.9 Interrupt The Interrupt is an active low interrupt. It is set low if any of the following internal faults are detected: • • • VCC fault VDD fault VPC fault The interrupt will also be set if one of the following status bit conditions is detected: • • • • Early ATR Mute ATR Card insert or card extract Protection status from Over-current or Over-heating When the interrupt is set low by the detection of one of the status bits, it is set high when the status bits are read. (READ STATUS DONE) Figure 10 shows the interrupt operation resulting from the fault or status bit conditions. INT ANY FAULT STATUS BITS READ STATUS DONE Figure 10: Interrupt operation due to Fault and Status Conditions A power-on-reset event will reset all of the control and status registers to their default states. A VDD fault event does not reset these registers, but it will signal an interrupt condition and by the action of the timer that creates the interval “t1,” not clearing the interrupt until VDD is valid for at least t1. A VDD fault can be considered valid for VDD as low as 1.5 to 1.8 volts. At the lower range of VDD fault, POR will be asserted. 20 Rev. 1.6 DS_8010R_022 73S8010R Data Sheet 3.10 Warm Reset 2 The 73S8010R automatically asserts a warm reset to the card when instructed through bit 1 of the I C Control register (bit Warm Reset). The warm reset length is automatically defined as 42,000 card clock cycles. The Warm Reset bit is automatically reset when the card starts answering or when the card is declared mute. IO Warm Reset (bit 1) RST t3 t2 t1 t1 > 1.5µs, Warm Reset Starts t2 = 42000 card clock cycles, End of Warm Reset t3 = Resets Warm Reset bit 1 when detected ATR or Mute Figure 11: Warm Reset Operation 3.11 I/O Circuitry and Timing The states of the I/O, AUX1, and AUX2 pins are low after power-on-reset and they are high when the activation sequencer enables the I/O reception state. See Section 3.7 Activation Sequence for more details on when the I/O reception is enabled. The states of the I/OUC, AUX1UC, and AUX2UC are high after power on reset. When the control I/O enable bit (bit 7) of the control register is set, the first I/O line on which a falling edge is detected becomes the input I/O line and the other becomes the output I/O line. When the input I/O line rising edge is detected, then both I/O lines return to their neutral state. The delay between these signals is shown in Figure 12. IO IOUC tIO_HL Delay from I/O to I/OUC: Delay from I/OUC to I/O: tIO_LH tIO_HL = 100ns tIOuc_HL = 100ns tIOUC_HL tIOUC_LH tIO_LH = 25ns tIOUC_LH = 25ns Figure 12: I/O Timing Diagram Rev. 1.6 21 73S8010R Data Sheet DS_8010R_022 4 Mechanical Drawings 4.1 32-pin QFN 0.85 NOM./ 0.9MAX. 0.00 / 0.005 5 0.20 REF. 2.5 1 2.5 2 3 5 SEATING PLANE TOP VIEW SIDE VIEW 0.35 / 0.45 3.0 / 3.75 CHAMFERED 0.30 0.18 / 0.3 1.5 / 1.875 1 2 3 3.0 / 3.75 0.25 1.5 / 1.875 0.5 0.2 MIN. 0.35 / 0.45 0.5 0.25 BOTTOM VIEW Figure 13: 32-pin QFN Package Dimensions 22 Rev. 1.6 DS_8010R_022 4.2 73S8010R Data Sheet 28-Pin SO .050 TYP. (1.270) .305 (7.747) .285 (7.239) PIN NO. 1 BEVEL .715 (18.161) .695 (17.653) .0115 (0.29) .003 (0.076) .110 (2.790) .092 (2.336) .420 (10.668) .390 (9.906) .016 nom (0.40) .335 (8.509) .320 (8.128) Figure 14: 28-Pin SO Package Dimensions Rev. 1.6 23 73S8010R Data Sheet DS_8010R_022 5 Ordering Information Table 16 lists the order numbers and packaging marks used to identify 73S8010R products. Table 16: Order Numbers and Packaging Marks Part Description Order Number Packaging Mark 73S8010R–SOL, 28-pin Lead-Free SO 73S8010R -IL/F 73S8010R -IL 73S8010R–SOL, 28-pin Lead-Free SO Tape / Reel 73S8010R -ILR/F 73S8010R -IL 73S8010R–QFN, 32-pin Lead-Free QFN 73S8010R -IM/F 73S8010R 73S8010R -IMR/F 73S8010R 73S8010R–QFN, 32-pin Lead-Free QFN Tape / Reel 6 Related Documentation The following 73S8010R documents are available from Teridian Semiconductor Corporation: 73S8010R 28SO Demo Board User’s Guide 7 Contact Information For more information about Teridian Semiconductor products or to check the availability of the 73S8010R, contact us at: 6440 Oak Canyon Road Suite 100 Irvine, CA 92618-5201 Telephone: (714) 508-8800 FAX: (714) 508-8878 Email: scr.support@teridian.com For a complete list of worldwide sales offices, go to http://www.teridian.com. 24 Rev. 1.6 DS_8010R_022 73S8010R Data Sheet Revision History Revision Date Description 1.0 7/1/2004 First publication. 1.1 11/10/2004 Make revisions to all references of “I/O” as it relates to the pins for the smart card and microcontroller interfaces, i.e. IO -> I/O and IOUC -> I/OUC. This is done to insure consistency and follow the designations used in ISO 7816. Remove the MLP pin numbering in the pin description. Correct the clock division table under CARD CLOCK. Change the value of R2 on the typical application schematic. The original value is 100 KΩ and the updated value is 10 KΩ. The PRES input has a high impedance pull down resistor and the 100 KΩ for R2 is too high to insure a valid logic level on this input. 1.3 10/26/2005 Remove NDS references in application schematic. 1.5 1/21/2008 Removed leaded package option, replaced 32QFN punched with SAWN, updated 28SO dimension. Changed dimension of bottom exposed pad on 32QFN mechanical package figure. 1.6 8/28/2009 Added Section 6, Related Documentation and Section 7, Contact Information. Formatted to the corporate style. Added document number. Miscellaneous editorial changes. Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation. Simplifying System Integration is a trademark of Teridian Semiconductor Corporation. All other trademarks are the property of their respective owners. This Data Sheet is proprietary to Teridian Semiconductor Corporation (TSC) and sets forth design goals for the described product. The data sheet is subject to change. TSC assumes no obligation regarding future manufacture, unless agreed to in writing. If and when manufactured and sold, this product is sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement and limitation of liability. Teridian Semiconductor Corporation (TSC) reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that a data sheet is current before placing orders. TSC assumes no liability for applications assistance. Teridian Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618 TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com Rev. 1.6 25