AD13280AZ

Dual-Channel, 12-Bit, 80 MSPS ADC with Analog Input Signal Conditioning AD13280 FEATURES APPLICATIONS Dual 80 MSPS, minimum sample rate Channel-to-channel matching, ±1% gain error 90 dB channel-to-channel isolation DC-coupled signal conditioning 80 dB spurious-free dynamic range Selectable bipolar inputs (±1 V and ±0.5 V ranges) Integral single-pole, low-pass Nyquist filter Twos complement output format 3.3 V compatible outputs 1.85 W per channel Radar processing (optimized for I/Q baseband operation) Phased array receivers Multichannel, multimode receivers GPS antijamming receivers Communications receivers PRODUCT HIGHLIGHTS 1. 2. 3. 4. Guaranteed sample rate of 80 MSPS. Input signal conditioning; gain and impedance match. Single-ended, differential, or off-module filter option. Fully tested/characterized full channel performance. FUNCTIONAL BLOCK DIAGRAM AMP-IN-A-2 AMP-IN-B-2 AMP-IN-A-1 AMP-IN-B-1 AMP-OUT-B AMP-OUT-A A–IN B+IN A+IN B–IN AD13280 DROUTA D0A (LSB) DROUTB D1A D2A TIMING D4A D5A D6A D7A D8A 9 VREF DROUT VREF DROUT 12 12 100Ω OUTPUT TERMINATORS TIMING ENCODEA ENCODEA D9A D10A D11B (MSB) 5 100Ω OUTPUT TERMINATORS D10B D9B D8B 7 3 ENCODEB D7B D11A (MSB) D0B D1B D2B (LSB) D3B D4B D5B D6B 02386-001 D3A ENCODEB Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2002–2008 Analog Devices, Inc. All rights reserved. AD13280 TABLE OF CONTENTS Features .............................................................................................. 1 Input and Output Stages................................................................ 13 Applications....................................................................................... 1 Theory of Operation ...................................................................... 14 Product Highlights ........................................................................... 1 Using the Single-Ended Input .................................................. 14 Functional Block Diagram .............................................................. 1 Using the Differential Input...................................................... 14 Revision History ............................................................................... 2 Applications Information .............................................................. 15 General Description ......................................................................... 3 Encoding the AD13280 ............................................................. 15 Specifications..................................................................................... 4 Jitter Consideration.................................................................... 15 Timing Diagram ........................................................................... 6 Power Supplies ............................................................................ 16 Absolute Maximum Ratings............................................................ 7 Output Loading .......................................................................... 16 Explanation of Test Levels ........................................................... 7 Evaluation Board ............................................................................ 17 ESD Caution.................................................................................. 7 Layout Information.................................................................... 17 Pin Configuration and Function Descriptions............................. 8 Bill of Materials List for Evaluation Board.............................. 24 Typical Performance Characteristics ........................................... 10 Outline Dimensions ....................................................................... 25 Terminology .................................................................................... 12 Ordering Guide .......................................................................... 26 REVISION HISTORY 4/08—Rev. B to Rev. C Updated Outline Dimensions ....................................................... 25 Changes to the Ordering Guide.................................................... 26 8/02—Rev. 0 to Rev. A Edits to Specifications .......................................................................2 Packages Updated........................................................................... 19 11/05—Rev. A to Rev. B Updated Format..................................................................Universal Changes to Features and Product Highlights ............................... 1 Changes to General Description .................................................... 3 Changes to Table 1............................................................................ 4 Changes to Figure 3.......................................................................... 8 Changes to Theory of Operation.................................................. 14 Changes to Equation 1 ................................................................... 15 Changes to Table 5.......................................................................... 18 Changes to Figure 21...................................................................... 19 Changes to Figure 22...................................................................... 20 Changes to Figure 23...................................................................... 21 Changes to Figure 28 and Figure 29............................................. 24 Updated Outline Dimensions ....................................................... 25 Changes to the Ordering Guide.................................................... 26 Rev. C | Page 2 of 28 AD13280 GENERAL DESCRIPTION The AD13280 is a complete, dual-channel, signal processing solution that includes on-board amplifiers, references, ADCs, and output termination components to provide optimized system performance. The AD13280 has on-chip track-and-hold circuitry and uses an innovative multipass architecture to achieve 12-bit, 80 MSPS performance. The AD13280 uses innovative high density circuit design and laser-trimmed thin-film resistor networks to achieve exceptional channel matching, impedance control, and performance while maintaining excellent isolation and providing for significant board area savings. Multiple options are provided for driving the analog input, including single-ended, differential, and optional series filtering. The AD13280 also offers users a choice of analog input signal ranges to further minimize additional external signal conditioning, while remaining general purpose. The AD13280 operates with ±5.0 V for the analog signal conditioning with a separate 5.0 V supply for the analog-to-digital conversion and 3.3 V digital supply for the output stage. Each channel is completely independent, allowing operation with independent encode and analog inputs and maintaining minimal crosstalk and interference. The AD13280 is available in a 68-lead, ceramic gull wing package. The components are manufactured using the Analog Devices, Inc., high speed complementary bipolar process (XFCB). Rev. C | Page 3 of 28 AD13280 SPECIFICATIONS AVCC = +5 V, AVEE = −5 V, DVCC = +3.3 V; applies to each ADC with front-end amplifier, unless otherwise noted. Table 1. Parameter RESOLUTION DC ACCURACY 1 No Missing Codes Offset Error Offset Error Channel Match Gain Error 2 Gain Error Channel Match SINGLE-ENDED ANALOG INPUT Input Voltage Range AMP-IN-X-1 AMP-IN-X-2 Input Resistance AMP-IN-X-1 AMP-IN-X-2 Capacitance Analog Input Bandwidth 3 DIFFERENTIAL ANALOG INPUT Analog Signal Input Range A+IN to A–IN and B+IN to B−IN 4 Input Impedance Analog Input Bandwidth ENCODE INPUT (ENCODE, ENCODE)1 Differential Input Voltage Differential Input Resistance Differential Input Capacitance SWITCHING PERFORMANCE Maximum Conversion Rate 5 Minimum Conversion Rate5 Aperture Delay (tA) Aperture Delay Matching Aperture Uncertainty (Jitter) ENCODE Pulse Width High at Max Conversion Rate ENCODE Pulse Width Low at Max Conversion Rate Output Delay (tOD) Encode, Rising to Data Ready, Rising Delay SNR1, 6 Analog Input @ 10 MHz Analog Input @ 21 MHz Temperature Test Level Min Full 25°C Full Full 25°C Full 25°C Max Min IV I VI VI I VI I VI VI −2.2 −2.2 −1.0 −3 −5.0 −1.5 −3.0 −5 Full Full V V Full Full 25°C Full IV IV V V Full 25°C Full V V V Full 25°C 25°C IV V V 0.4 Full Full 25°C 25°C 25°C 25°C 25°C Full Full VI IV V IV V IV IV V V 80 25°C Min Max 25°C Min Max I II II I II II Rev. C | Page 4 of 28 AD13280AZ Typ 12 Guaranteed ±1.0 ±1.0 ±0.1 −1.0 ±2.0 ±0.5 ±1.0 ±1.0 Max Unit Bits +2.2 +2.2 +1.0 +1 +5.0 +1.5 +3.0 +5 % FS % FS % % FS % FS % % % ±0.5 ±1.0 99 198 100 200 4.0 143 V V 101 202 7.0 ±1 618 50 V Ω MHz 10 2.5 V p-p kΩ pF 30 4.75 4.75 66.5 64.5 66.3 66.5 64 66.3 Ω Ω pF MHz 0.9 250 0.3 6.25 6.25 5 8.5 70 70 500 8 8 MSPS MSPS ns ps ps rms ns ns ns ns dBFS dBFS dBFS dBFS dBFS dBFS AD13280 Parameter Analog Input @ 37 MHz SINAD1, 7 Analog Input @ 10 MHz Analog Input @ 21 MHz Analog Input @ 37 MHz SPURIOUS-FREE DYNAMIC RANGE1, 8 Analog Input @ 10 MHz Analog Input @ 21 MHz Analog Input @ 37 MHz SINGLE-ENDED ANALOG INPUT Pass-Band Ripple to 10 MHz Pass-Band Ripple to 25 MHz DIFFERENTIAL ANALOG INPUT Pass-Band Ripple to 10 MHz Pass-Band Ripple to 25 MHz TWO-TONE IMD REJECTION9 fIN = 9.1 MHz and 10.1 MHz (f1 and f2 are −7 dBFS) fIN = 19.1 MHz and 20.7 MHz (f1 and f2 are −7 dBFS) fIN = 36 MHz and 37 MHz (f1 and f2 are −7 dBFS) CHANNEL-TO-CHANNEL ISOLATION10 TRANSIENT RESPONSE DIGITAL OUTPUTS11 Logic Compatibility DVCC = 3.3 V Logic 1 Voltage Logic 0 Voltage DVCC = 5 V Logic 1 Voltage Logic 0 Voltage Output Coding POWER SUPPLY AVCC Supply Voltage12 I (AVCC) Current AVEE Supply Voltage12 I (AVEE) Current DVCC Supply Voltage12 Temperature 25°C Min Max Test Level I II II Min 63 61.5 63 25°C Min Max 25°C Min Max 25°C Min Max I II II I II II I II II 66 63.5 66 64 63 64 54 53 54 25°C Min Max 25°C Min Max 25°C Min Max I II II I II II I II II 75 70 75 68 67 67 56 55 55 25°C 25°C AD13280AZ Typ 65 Max 69 Unit dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS 68.5 59 80 dBFS 75 dBFS 62 dBFS V V 0.07 0.12 dB dB 25°C 25°C V V 0.3 0.82 dB dB 25°C Min Max 25°C 25°C 25°C 25°C I II II V V IV V 80 dBc 77 60 dBc dBc dB ns 75 71 74 90 25 CMOS Full Full I I Full Full V V Full Full Full Full Full IV I IV I IV Rev. C | Page 5 of 28 2.5 DVCC − 0.2 0.2 0.5 DVCC − 0.3 0.35 Twos complement 4.85 −5.25 3.135 5.0 313 −5.0 38 3.3 5.25 364 −4.75 49 3.465 V V V V V mA V mA V AD13280 Parameter I (DVCC) Current ICC (Total) Supply Current per Channel Power Dissipation (Total) Power Supply Rejection Ratio (PSRR) Temperature Full Full Full Full Test Level I I I V Min AD13280AZ Typ 34 375 3.7 0.01 Max 46 459 4.3 Unit mA mA W % FSR/% VS All ac specifications tested by driving ENCODE and ENCODE differentially. Single-ended input: AMP-IN-x-1 = 1 V p-p, AMP-IN-x-2 = GND. Gain tests are performed on the AMP-IN-x-1 input voltage range. 3 Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB. 4 For differential input: +IN = 1 V p-p and −IN = 1 V p-p (signals are 180 Ω out of phase). For single-ended input: +IN = 2 V p-p and –IN = GND. 5 Minimum and maximum conversion rates allow for variation in encode duty cycle of 50% ± 5%. 6 Analog input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 80 MSPS. SNR is reported in dBFS, related back to converter full scale. 7 Analog input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 80 MSPS. SINAD is reported in dBFS, related back to converter full scale. 8 Analog input signal at –1 dBFS; SFDR is the ratio of converter full scale to worst spur. 9 Both input tones at –7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third-order intermodulation product. 10 Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B channel. 11 Digital output logic levels: DVCC = 3.3 V, CLOAD = 10 pF. Capacitive loads >10 pF degrades performance. 12 Supply voltage recommended operating range. AVCC may be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range AVCC = 5.0 V to 5.25 V. 1 2 TIMING DIAGRAM tA N + 3 N AIN N+ 1 N + 2 tENC ENCODE, ENCODE tENCH N N+ 4 tENCL N+1 N+2 N+3 N + 4 tE_DR N –3 N – 2 N– 1 N 02386-012 D[11:0] tOD DRY Figure 2. Rev. C | Page 6 of 28 AD13280 ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS Table 2. Parameter ELECTRICAL1 AVCC Voltage AVEE Voltage DVCC Voltage Analog Input Voltage Analog Input Current Digital Input Voltage (ENCODE) ENCODE, ENCODE Differential Voltage Digital Output Current ENVIRONMENTAL1 Operating Temperature Range (Case) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) 1 Ratings I. 100% production tested. 0 V to 7 V −7 V to 0 V 0 V to 7 V VEE to VCC −10 mA to +10 mA 0 to VCC 4 V max −10 mA to +10 mA II. 100% production tested at 25°C, and sample tested at specified temperatures. AC testing done on a sample basis. III. Sample tested only. IV. Parameter guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. 100% production tested with temperature at 25°C, and sample tested at temperature extremes. −40°C to +85°C 175°C 300°C −65°C to +150°C Typical thermal impedance for ES package: θJC 2.2°C/W; θJA 24.3°C/W. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. C | Page 7 of 28 AD13280 D4B DGNDB D5B D6B D7B D8B D9B AGNDB DV CC B D11B (MSB) D10B ENCODEB AGNDB ENCODEB AVCCB AVEEB AGNDB PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 AGNDB 61 AMP-IN-B-2 62 43 DGNDB 42 D3B AMP-IN-B-1 63 AMP-OUT-B 64 41 D2B 40 D1B B+IN 65 39 D0B (LSB) 38 NC B–IN 66 AGNDB 67 AGNDB 68 SHIELD 1 PIN 1 IDENTIFIER AGNDA 2 AGNDA 3 37 NC AD13280 36 DROUTB TOP VIEW (Not to Scale) 35 SHIELD A–IN 4 A+IN 5 AMP-OUT-A 6 34 DROUTA 33 D11A (MSB) 32 D10A D9A 30 D8A 29 D7A 31 AMP-IN-A-1 7 AMP-IN-A-2 8 AGNDA 9 28 D6A 27 DGNDA D4A D5A DGNDA 02386-002 NC = NO CONNECT D3A D2A D1A D0A (LSB) NC NC AGNDA DV CCA ENCODEA AGNDA ENCODEA AV EEA AV CCA AGNDA 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Figure 3. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1, 35 2, 3, 9, 10, 13, 16 4 5 6 7 8 11 12 14 15 17 18, 19, 37, 38 20 to 25, 28 to 33 26, 27 34 36 39 to 42, 45 to 52 43, 44 53 Mnemonic SHIELD AGNDA A−IN A+IN AMP-OUT-A AMP-IN-A-1 AMP-IN-A-2 AVEEA AVCCA ENCODEA ENCODEA DVCCA NC D0A to D11A DGNDA DROUTA DROUTB D0B to D11B DGNDB DVCCB Description Internal Ground Shield Between Channels. A Channel Analog Ground. A and B grounds should be connected as close to the device as possible. Inverting Differential Input (Gain = +1). Noninverting Differential Input (Gain = +1). Single-Ended Amplifier Output (Gain = +2). Analog Input for A Side ADC (Nominally ±0.5 V). Analog Input for A Side ADC (Nominally ±1.0 V). A Channel Analog Negative Supply Voltage (Nominally −5.0 V or −5.2 V). A Channel Analog Positive Supply Voltage (Nominally +5.0 V). Complement of ENCODEA. Differential input. Encode Input. Conversion initiated on rising edge. A Channel Digital Positive Supply Voltage (Nominally +5.0 V/+3.3 V). No Connect. Digital Outputs for ADC A. D0 (LSB). A Channel Digital Ground. Data Ready A Output. Data Ready B Output. Digital Outputs for ADC B. D0 (LSB). B Channel Digital Ground. B Channel Digital Positive Supply Voltage (Nominally +5.0 V/+3.3 V). Rev. C | Page 8 of 28 AD13280 Pin No. 54, 57, 60, 61, 67, 68 55 56 58 59 62 63 64 65 66 Mnemonic AGNDB ENCODEB ENCODEB AVCCB AVEEB AMP-IN-B-2 AMP-IN-B-1 AMP-OUT-B B+IN B−IN Description B Channel Analog Ground. A and B grounds should be connected as close to the device as possible. Encode Input. Conversion initiated on rising edge. Complement of ENCODEB. Differential input. B Channel Analog Positive Supply Voltage (Nominally +5.0 V). B Channel Analog Negative Supply Voltage (Nominally −5.0 V or −5.2 V). Analog Input for B Side ADC (Nominally ±1.0 V). Analog Input for B Side ADC (Nominally ±0.5 V). Single-Ended Amplifier Output (Gain = +2). Noninverting Differential Input (Gain = +1). Inverting Differential Input (Gain = +1). Rev. C | Page 9 of 28 AD13280 TYPICAL PERFORMANCE CHARACTERISTICS 0 0 ENCODE = 80MSPS AIN = 5MHz (–1dBFS) SNR = 69.4dBFS SFDR = 81.9dBc –10 –20 –20 –30 –40 –40 –50 –50 –60 –60 dB –70 3 –80 2 –90 4 –70 6 2 –90 –100 –110 –120 5 10 15 20 25 30 35 40 –130 02386-003 0 FREQUENCY (MHz) 0 5 10 25 30 35 40 35 40 0 –30 –20 –30 –40 –50 –50 –60 –60 dB –40 –70 –80 –90 –90 –100 –100 –110 –110 –120 –120 10 15 20 25 30 35 40 FREQUENCY (MHz) –130 02386-004 5 2 3 –70 –80 0 ENCODE = 80MSPS AIN = 37MHz (–1dBFS) SNR = 68.38dBFS SFDR = 57.81dBc –10 0 5 10 5 6 4 15 20 25 30 FREQUENCY (MHz) Figure 5. Single Tone @ 18 MHz 02386-007 ENCODE = 80MSPS AIN = 18MHz (–1dBFS) SNR = 69.79dBFS SFDR = 76.81dBc –20 dB 20 Figure 7. Single Tone @ 10 MHz 0 –10 Figure 8. Single Tone @ 37 MHz 0 0 ENCODE = 80MSPS AIN = 9MHz AND 10MHz (–7dBFS) SFDR = 82.77dBc –10 –20 –30 ENCODE = 80MSPS AIN = 19MHz AND 20MHz (–7dBFS) SFDR = 74.41dBc –10 –20 –30 –40 –50 –50 –60 –60 dB –40 –70 –70 –80 –80 –90 –90 –100 –100 –110 –110 –120 –120 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40 02386-005 dB 15 FREQUENCY (MHz) Figure 4. Single Tone @ 5 MHz –130 4 02386-006 –110 –130 5 6 –100 –120 –130 3 –80 5 Figure 6. Two Tone @ 9 MHz and 10 MHz –130 0 5 10 15 20 25 30 FREQUENCY (MHz) Figure 9. Two Tone @ 19 MHz and 20 MHz Rev. C | Page 10 of 28 35 40 02386-008 dB –30 ENCODE = 80MSPS AIN = 10MHz (–1dBFS) SNR = 69.19dBFS SFDR = 79.55dBc –10 AD13280 3 3.0 ENCODE = 80MSPS DNL MAX = 0.688 CODES DNL MIN = 0.385 CODES 2.5 ENCODE = 80MSPS INL MAX = 0.562 CODES INL MIN = 0.703 CODES 2 2.0 1 LSB LSB 1.5 1.0 0.5 0 –1 0 0 512 1024 1536 2048 2560 3072 3584 4096 02386-009 –1.0 Figure 10. Differential Nonlinearity –1 ENCODE = 80MSPS ROLL-OFF = 0.0459dB –3 –5 –6 –7 –8 –9 1.0 3.5 6.0 8.5 11.0 13.5 16.0 18.5 21.0 FREQUENCY (MHz) 23.5 26.0 02386-010 dBFS –4 –10 0 512 1024 1536 2048 2560 3072 Figure 12. Integral Nonlinearity 0 –2 –3 Figure 11. Pass-Band Ripple to 25 MHz Rev. C | Page 11 of 28 3584 4096 02386-011 –2 –0.5 AD13280 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Aperture Delay The delay between a differential crossing of the ENCODEA signal and the ENCODEA signal and the instant at which the analog input is sampled. Maximum Conversion Rate The encode rate at which parametric testing is performed. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance The real and complex impedances measured at each analog input port. The resistance is measured statically, and the capacitance and differential input impedances are measured with a network analyzer. Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage from the other pin, which is 180 degrees out of phase. Peak-to-peak differential is computed by rotating the input phase 180 degrees and taking the peak measurement again. The difference is then computed between both peak measurements. Differential Nonlinearity The deviation of any code from an ideal 1 LSB step. ENCODE Pulse Width/Duty Cycle Pulse width high is the minimum amount of time that the ENCODE pulse should be left in a Logic 1 state to achieve the rated performance. Pulse width low is the minimum time the ENCODE pulse should be left in a low state. At a given clock rate, these specifications define an acceptable encode duty cycle. Harmonic Distortion The ratio of the rms signal amplitude to the rms value of the worst harmonic component. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line determined by a least square curve fit. Output Propagation Delay The delay between a differential crossing of the ENCODEA signal and the ENCODEA signal and the time at which all output data bits are within valid logic levels. Overvoltage Recovery Time The amount of time required for the converter to recover to 0.02% accuracy after an analog input signal of the specified percentage of full scale is reduced to midscale. Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise-and-Distortion (SINAD) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc. SINAD can be reported in dB (that is, degrades as signal level is lowered) or in dBFS (always related back to converter full scale). Signal-to-Noise Ratio (SNR) (Without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. SNR can be reported in dB (that is, degrades as signal level is lowered) or in dBFS (always related back to converter full scale). Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. Transient Response The time required for the converter to achieve 0.02% accuracy when a one-half full-scale step function is applied to the analog input. Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product; reported in dBc. Rev. C | Page 12 of 28 AD13280 INPUT AND OUTPUT STAGES LOADS AVCC AVCC AVCC 10kΩ 10kΩ 10kΩ 10k Ω AVCC ENCODE ENCODE AMP-IN-X-2 100 Ω AMP-IN-X-1 02386-014 02386-013 TO AD8045 100Ω LOADS Figure 15. ENCODE Inputs Figure 13. Single-Ended Input Stage DVCC DVCC CURRENT MIRROR CURRENT MIRROR DVCC DVCC VREF VREF CURRENT MIRROR 02386-015 CURRENT MIRROR Figure 14. DR Digital Output Stage Figure 16. Digital Output Stage Rev. C | Page 13 of 28 D0–D11 02386-016 100Ω DROUT AD13280 THEORY OF OPERATION The AD13280 is a high dynamic range 12-bit, 80 MHz pipeline delay (three pipelines) analog-to-digital converter (ADC). The custom analog input section provides input ranges of 1 V p-p and 2 V p-p and input impedance configurations of 50 Ω, 100 Ω, and 200 Ω. The AD13280 employs four monolithic Analog Devices components per channel (AD8045, AD8138, AD8031, and a custom ADC IC), along with multiple passive resistor networks and decoupling capacitors to fully integrate a complete 12-bit analog-to-digital converter (ADC). In the single-ended input configuration, the input signal is passed through a precision laser-trimmed resistor divider, allowing the user to externally select operation with a full-scale signal of ±0.5 V or ±1.0 V by choosing the proper input terminal for the application. The result of the resistor divider is to apply a full-scale input of approximately 0.4 V to the noninverting input of the internal AD8045 amplifier. The AD13280 analog input includes an AD8045 amplifier featuring an innovative architecture that maximizes the dynamic range capability on the amplifier inputs and outputs. The AD8045 amplifier provides a high input impedance and gain for driving the AD8138 in a single-ended to differential amplifier configuration. The AD8138 has a −3 dB bandwidth at 300 MHz and delivers a differential signal with the lowest harmonic distortion available in a differential amplifier. The AD8138 differential outputs help balance the differential inputs to the custom ADC, maximizing the performance of the device. The AD8031 provides the buffer for the internal reference analog-to-digital converter. The internal reference voltage of the custom ADC is designed to track the offsets and drifts and is used to ensure matching over an extended temperature range of operation. The reference voltage is connected to the output common-mode input on the AD8138. This reference voltage sets the output common mode on the AD8138 at 2.4 V, which is the midsupply level for the ADC. The custom ADC has complementary analog input pins, AIN and AIN. Each analog input is centered at 2.4 V and should swing ±0.55 V around this reference. Because AIN and AIN are 180 degrees out of phase, the differential analog input signal is 2.2 V peak-to-peak. Both analog inputs are buffered prior to the first track-and-hold. USING THE SINGLE-ENDED INPUT The AD13280 has been designed with user ease of operation in mind. Multiple input configurations have been included onboard to allow the user a choice of input signal levels and input impedance. The standard inputs are ±0.5 V and ±1.0 V. The user can select the input impedance of the AD13280 on any input by using the other inputs as alternate locations for the GND. The following is a summary of the impedance options available at each input location: AMP-IN-x-1 = 100 Ω when AMP-IN-x-2 is open. AMP-IN-x-1 = 50 Ω when AMP-IN-x-2 is shorted to GND. AMP-IN-x-2 = 200 Ω when AMP-IN-x-1 is open. Each channel has two analog inputs: AMP-IN-A-1 and AMP-IN-A-2 or AMP-IN-B-1 and AMP-IN-B-2. Use AMP-IN-A-1 or AMP-IN-B-1 when an input of ±0.5 V full scale is desired. Use AMP-IN-A-2 or AMP-IN-B-2 when ±1 V full scale is desired. Each channel has an AMP-OUT that must be tied to either a noninverting or inverting input of a differential amplifier with the remaining input grounded. For example, Side A, AMP-OUT-A (Pin 6) must be tied to A+IN (Pin 5) with A−IN (Pin 4) tied to ground for noninverting operation or AMP-OUT-A (Pin 6) tied to A−IN (Pin 4) with A+IN (Pin 5) tied to ground for inverting operation. USING THE DIFFERENTIAL INPUT Each channel of the AD13280 is designed with two optional differential inputs, A+IN, A−IN and B+IN, B−IN. The inputs provide system designers with the ability to bypass the AD8045 amplifier and drive the AD8138 directly. The AD8138 differential ADC driver can be deployed in either a single-ended or differential input configuration. The differential analog inputs have a nominal input impedance of 620 Ω and nominal fullscale input range of 1.2 V p-p. The AD8138 amplifier drives a differential filter and the custom analog-to-digital converter. The differential input configuration provides the lowest evenorder harmonics and signal-to-noise (SNR) performance improvement of up to 3 dB (SNR = 73 dBFS). Exceptional care was taken in the layout of the differential input signal paths. The differential input transmission line characteristics are matched and balanced. Equal attention to system level signal paths must be provided in order to realize significant performance improvements. The custom ADC digital outputs drive 100 Ω series resistors (see Figure 16). The result is a 12-bit, parallel digital CMOScompatible word, coded as a twos complement. Rev. C | Page 14 of 28 AD13280 APPLICATIONS INFORMATION ENCODING THE AD13280 JITTER CONSIDERATION The AD13280 encode signal must be a high quality, extremely low phase noise source to prevent degradation of performance. Maintaining 12-bit accuracy at 80 MSPS places a premium on encode clock phase noise. SNR performance can easily degrade 3 dB to 4 dB with 37 MHz input signals when using a high jitter clock source. See Analog Devices Application Note AN-501, Aperture Uncertainty and ADC System Performance, for complete details. For optimum performance, the AD13280 must be clocked differentially. The encode signal is usually ac-coupled into the ENCODE and ENCODE pins via a transformer or capacitors. These pins are biased internally and require no additional bias. The signal-to-noise ratio for any ADC can be predicted. When normalized to ADC codes, Equation 1 accurately predicts the SNR based on three terms. These are jitter, average DNL error, and thermal noise. Each of these terms contributes to the noise within the converter. Figure 17 shows one preferred method for clocking the AD13280. The clock source (low jitter) is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the transformer secondary limit clock excursions into the AD13280 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to the other portions of the AD13280 and limits the noise presented to the ENCODE inputs. A crystal clock oscillator can also be used to drive the RF transformer if an appropriate limited resistor (typically 100 Ω) is placed in series with the primary. T1-4T For a 12-bit analog-to-digital converter like the AD13280, aperture jitter can greatly affect the SNR performance as the analog frequency is increased. The chart below shows a family of curves that demonstrates the expected SNR performance of the AD13280 as jitter increases. The chart is derived from Equation 1. For a complete discussion of aperture jitter, consult Analog Devices Application Note AN-501, Aperture Uncertainty and ADC System Performance. ENCODE AD13280 02386-017 ENCODE HSMS2812 DIODES 71 AIN = 5MHz 70 69 Figure 17. Crystal Clock Oscillator—Differential Encode 68 AIN = 10MHz 67 66 SNR (–dBFS) If a low jitter ECL/PECL clock is available, another option is to ac-couple a differential ECL/PECL signal to the encode input pins as shown below. A device that offers excellent jitter performance is the MC100LVEL16 (or within the same family) from Motorola. VT 65 AIN = 20MHz 64 63 62 61 AIN = 37MHz 60 0.1µF 59 ENCODE 2.6 2.8 3.0 1.4 1.6 1.8 2.0 2.2 2.4 Figure 19. SNR vs. Jitter 02386-018 VT 0.6 0.8 1.0 1.2 0.0 0.2 CLOCK JITTER (ps) ENCODE 0.1µF 0.4 58 AD13280 ECL/PECL Figure 18. Differential ECL for Encode Rev. C | Page 15 of 28 02386-019 100Ω where: fANALOG is the analog input frequency. tJ rms is the rms jitter of the encode (rms sum of encode source and internal encode circuitry). ε is the average DNL of the ADC (typically 0.50 LSB). N is the number of bits in the ADC. VNOISE rms is the analog input of the ADC (typically 5 LSB). 3.6 3.8 4.0 0.1µF 1/ 2 (1) 3.2 3.4 CLOCK SOURCE 2 ⎡ ⎡1 + ε ⎤ 2 ⎛ VNOISE rms ⎞ ⎤ ⎟ SNR = − 20 × log ⎢ ⎢ N ⎥ + (2 × π × f ANALOG × t J rms )2 + ⎜⎜ N ⎟ ⎥ ⎢⎣ ⎣ 2 ⎦ ⎝ 2 ⎠ ⎥⎦ AD13280 POWER SUPPLIES OUTPUT LOADING Care should be taken when selecting a power source. Linear supplies are strongly recommended. Switching supplies tend to have radiated components that may be received by the AD13280. Each of the power supply pins should be decoupled as close as possible to the package using 0.1 μF chip capacitors. Care must be taken when designing the data receivers for the AD13280. The digital outputs drive an internal series resistor (for example, 100 Ω) followed by a gate like 75LCX574. To minimize capacitive loading, there should be only one gate on each output pin. An example of this is shown in the evaluation board schematic (see Figure 20). The digital outputs of the AD13280 have a constant output slew rate of 1 V/ns. The AD13280 has separate digital and analog power supply pins. The analog supplies are denoted AVCC, and the digital supply pins are denoted DVCC. AVCC and DVCC should be separate power supplies because the fast digital output swings can couple switching current back into the analog supplies. Note that AVCC must be held within 5% of 5 V. The AD13280 is specified for DVCC = 3.3 V because this is a common supply for digital ASICs. A typical CMOS gate combined with a PCB trace has a load of approximately 10 pF. Therefore, as each bit switches, 10 mA (10 pF × 1 V ÷ 1 ns) of dynamic current per bit flows in or out of the device. A full-scale transition can cause up to 120 mA (12 bits × 10 mA/bit) of transient current through the output stages. These switching currents are confined between ground and the DVCC pin. Standard TTL gates should be avoided because they can appreciably add to the dynamic switching currents of the AD13280. It should also be noted that extra capacitive loading increases output timing and invalidates timing specifications. Digital output timing is guaranteed with 10 pF loads. Rev. C | Page 16 of 28 AD13280 EVALUATION BOARD The AD13280 evaluation board (see Figure 20) is designed to provide optimal performance for evaluation of the AD13280 analog-to-digital converter. The board encompasses everything needed to ensure the highest level of performance for evaluating the AD13280. The board requires an analog input signal, encode clock, and power supply inputs. The clock is buffered on-board to provide clocks for the latches. The digital outputs and out clocks are available at the standard 40-pin connectors J1 and J2. The schematics of the evaluation board (Figure 21, Figure 22, and Figure 23) represent a typical implementation of the AD13280. The pinout of the AD13280 is very straightforward and facilitates ease of use and the implementation of high frequency/high resolution design practices. It is recommended that high quality ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. All capacitors can be standard, high quality ceramic chip capacitors. Care should be taken when placing the digital output runs. Because the digital outputs have such a high slew rate, the capacitive loading on the digital outputs should be minimized. Circuit traces for the digital outputs should be kept short and should connect directly to the receiving gate. Internal circuitry buffers the outputs of the ADC through a resistor network to eliminate the need to externally isolate the device from the receiving gate. 02386-020 Power to the analog supply pins is connected via banana jacks. The analog supply powers the associated components and the analog section of the AD13280. The digital outputs of the AD13280 are powered via banana jacks with 3.3 V. Contact the factory if additional layout or applications assistance is required. LAYOUT INFORMATION Figure 20. Evaluation Board Mechanical Layout Rev. C | Page 17 of 28 AD13280 J13 SMA E68 AGNDA J9 SMA J6 SMA E67 AGNDB E66 J8 SMA LIDA J3 SMA E50 U8 C16 0.1µF DGNDB 61 AGNDB 62 AMP-IN-B-2 AMP-IN-B-1 E81 E83 AMP-OUT-B 63 64 E84 B+IN E40 L3 +5VAA U1 C20 0.1µF AGNDB DGNDB 55 54 53 52 51 50 49 48 47 46 45 44 AGNDB ENCODEB ENCODEB AGNDB AGNDB OUT_3.3VDB C18 0.1µF D11B C37 0.1µF D10B D9B DGNDB D8B D7B D6B D5B D4B DGNDB DGNDB 43 D2B D3B 42 D3B 56 U1 C21 0.1µF +5VAB AGNDB Figure 21. Evaluation Board Rev. C | Page 18 of 28 47Ω –5VAA ±20% BJ2 @100MHz 1 C11 10µF AGNDA L4 1 C4 10µF 57 DGNDB 47Ω +5VAB ±20% BJ5 @100MHz DUT_3.3VDB 58 E65 E48 1 C3 10µF DGNDB 59 –5VAB C33 0.1µF AGNDB +5VAB C17 C38 0.1µF 0.1µF AGNDB E55 47Ω +3VAA ±20% BJ6 @100MHz DUT_3.3VDA D2B 41 D0B(LSB) D1B 40 D0B D1B NC 39 NC1B 38 NC DRBOUT AGNDA L2 37 SHIELD DRAOUT D4B 60 L5 –5VAA U1 C32 0.1µF AGNDA AGNDA 47Ω –5VAB ±20% BJ1 @100MHz 1 C19 10µF AGNDB L6 U1 C31 0.1µF –5VAB AGNDB 02386-021 1 C30 10µF 36 NC0B DGNDA 35 DGNDA DROUTA D5A 47Ω ±20% @100MHz +3VDB E79 D5B DGNDA BJ9 65 E82 D4A 47Ω ±20% @100MHz L1 B–IN E78 D6B DGNDA U7 C12 0.1µF 66 E80 D7B D3A LIDB 1 C29 10µF 67 D2A E56 BJ10 AGNDB D8B DROUTB D1A NC = NO CONNECT +3VDA AGNDB 1 68 SHIELD AGNDA 2 E76 E75 3 A–IN AGNDA A+IN 4 E77 E71 8 7 AMP-IN-A-1 D9B D11A(MSB) 26 D10B NC 27 DGNDA 25 D11B(MSB) D0A(LSB) 34 D5A 24 NC D11A D4A 23 DVCCB AD13280AZ D10A D3A 22 U1 DVCCA 33 D2A 21 AGNDB D10A D1A AGNDA D9A DGNDA 20 AVEEB ENCODEB 32 D0A 19 AGNDB ENCODEA D9A NC1A 18 AGNDB AGNDB ENCODEB D7A NC0A 17 E86 AGNDB ENCODEA 30 C10 0.1µF E85 AGNDB D7A OUT_3.3VDA 16 AGNDB AGNDA D6A AGNDA 15 E54 E52 AVCCB 29 ENCODEA AGNDB J7 SMA AVCCA D6A ENCODEA 14 AMP-IN-A-2 9 AGNDA 13 AVEEA DGNDA 12 AGNDA C36 0.1µF 11 AGNDA 28 AGNDA 10 AGNDA AGNDA –5VAA C9 0.1µF AGENDA +5VAA C34 C35 0.1µF 0.1µF 5 E74 E70 AGNDA AMP-OUT-A E69 AGNDA 6 E72 E49 D8A AGNDA E73 E53 E51 31 J4 SMA D8A AGNDA J14 SMA AD13280 U8 25 26 R48 0Ω DGNDA NC0A DGNDA NC1A DUT_3.3VDA (LSB) D0A D1A DGNDA D2A D3A D4A D5A DGNDA D6A D7A DUT_3.3VDA D8A D9A DGNDA D10A (MSB) D11A 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 R7 50Ω 48 LATCHB E58 LE2 OE2 115 O15 114 O14 GND GND 113 O13 112 O12 VCC VCC 111 O11 110 O10 GND GND 19 O9 18 O8 17 O7 16 O6 GND GND 15 O5 14 O4 VCC VCC O3 13 O2 12 GND GND 11 O1 10 O0 LE1 OE1 24 DGNDA R18, DNI R17, DNI 23 22 R16, DNI 20 R40, DNI DUT_3.3VDA 18 R44, 100Ω 17 R45, 100Ω 16 R46, 100Ω 14 R15, 100Ω 13 R14, 100Ω 12 R13, 100Ω DGNDA 10 R24, 100Ω 9 R23, 100Ω 8 DUT_3.3VDA R22, 100Ω 6 R21, 100Ω 4 DGNDA R20, 100Ω R19, 100Ω 3 2 1 F3A C15 10µF B10A B9A B8A DGNDA B0A (LSB) B7A B1A B6A B2A B3A B4A B5A R5 50Ω E61 E60 B4A E59 B3A B2A B1A B6A (LSB) B0A F3A B7A F2A 7 5 (MSB) B11A F2A B5A DGNDA 15 11 F1A 3.3VDA DGNDA 21 19 J1 H40DM F0A BUFLATA DROUTA R47 0Ω F1A B8A F0A B9A DGNDA 1 40 2 39 3 38 4 37 5 36 6 35 7 34 8 33 9 32 10 31 11 30 12 29 13 28 14 27 15 26 16 25 17 24 18 23 19 22 20 21 B10A DGNDA B11A (MSB) DGNDA 74LCX16374 U7 26 R50 0Ω DGNDB NC0B DGNDB NC1B DUT_3.3VDB (LSB) D0B D1B DGNDB D2B D3B D4B D5B DGNDB D6B D7B DUT_3.3VDB D8B D9B DGNDB D10B (MSB) D11B 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 R8 50Ω 48 LE2 OE2 115 O15 114 O14 GND GND 113 O13 112 O12 VCC VCC 111 110 O11 O10 GND GND 19 O9 18 O8 17 O7 16 O6 GND GND 15 14 O5 O4 VCC VCC 13 O3 12 O2 GND GND 11 O1 10 O0 LE1 OE1 24 DGNDB R11, DNI R10, DNI 23 22 R30, DNI 20 R29, DNI 18 DUT_3.3VDB R28, 100Ω R27, 100Ω 17 16 R26, 100Ω 14 R12, 100Ω 13 R9, 100Ω 12 R25, 100Ω DGNDB 10 R36, 100Ω 9 R35, 100Ω 8 7 DUT_3.3VDB 5 4 DGNDB 2 1 R32, 100Ω R31, 100Ω 3 F3B C14 10µF B10B B9B B8B DGNDB B0B (LSB) B7B B1B B6B B2B B3B B4B B5B R2 50Ω E64 E63 B4B E62 B3B B2B B1B B6B (LSB) B0B B7B F3B F2B R34, 100Ω R33, 100Ω 6 (MSB) B11B F2B B5B DGNDB 15 11 F1B 3.3VDB DGNDB 21 19 J2 H40DN F0B B8B B9B B10B F1B F0B DGNDB 1 40 2 39 3 38 4 37 5 36 6 35 7 34 8 33 9 32 10 31 11 30 12 29 13 28 14 27 15 26 16 25 17 24 18 23 19 22 20 21 DGNDB B11B (MSB) DGNDB 02386-022 25 BUFLATB DROUTB R49 0Ω LATCHB 74LCX16374 E57 Figure 22. Evaluation Board Rev. C | Page 19 of 28 AD13280 5 2 +5VAA 6 OUT ERR 1 ADP3330 U5 IN SD GND 4 AGNDA AGNDA J5 ENCODE SMA 1 C1 0.1µF 2 3 R1 50Ω AGNDA 4 AGNDA D DB QB 5 BJ4 8 VCC R3 100Ω 1 D0 VCC D0 3 D1 4 D1 R4 100Ω DGNDA DGNDA Q0 U4 Q1 GND DGNDA 8 +3.3VDA 7 6 LATCHA E23 E19 BUFLATA 5 MC100EPT23 NC = NO CONNECT OUT ERR DGNDA SD GND 4 AGNDB J10 ENCODE SMA 1 C22 0.1µF 2 3 R54 50Ω AGNDB 4 AGNDB AGNDB Q U11 QB VBB VEE 7 1 2 NC D 3 DB 4 VBB VCC U9 Q QB VEE ENCODEB 6 8 AGNDB +3.3VDB 6 MC10EP16 NC = NO CONNECT C26 0.1µF 1 2 DGNDB AGNDA D0 VCC D0 Q0 3 D1 4 D1 R6 100Ω DGNDB U10 Q1 GND 8 Figure 23. Evaluation Board Rev. C | Page 20 of 28 DGNDB +3.3VDA 7 6 E37 E30 E2 E35 E13 E46 E4 AGNDB SO1 SO2 SO3 SO4 SO5 SO6 LATCHB E24 E22 BUFLATB 5 MC100EPT23 NC = NO CONNECT E18 E28 E26 E20 E31 E43 E41 E9 E34 E5 AGNDA DGNDB R37 100Ω 7 5 C28 0.1µF R51 100Ω AGNDB DGNDB E38 E29 E1 E36 E14 E45 E3 ENCODEB 5 E8 E47 DGNDA C24 0.1µF +3.3VB R38 33kΩ DGNDB C25 0.1µF R39 33kΩ C23 0.1µF R53 25Ω D DB 8 MC10EP16 NC = NO CONNECT DGNDB J11 SMA VCC NC R52 100Ω C27 0.47µF E11 E39 E17 E27 E25 E21 E32 E44 E42 E10 E33 E6 1 AGNDB E16 E12 AGNDB ADP3330 2 IN U6 6 E15 E7 DGNDA 5 NR DGNDA 1 DGND C5 0.1µF 2 +5VAB DGNDB 1 BJ8 7 D Q U3 6 3 DB QB 4 5 VBB VEE 3 AGNDA 1 DGNDB +3.3VDA MC10EP16 NC = NO CONNECT AGNDB BJ7 AGNDA 2 AGNDA ENCODEA DGNDA C6 0.1µF NC 1 R56 33kΩ R55 33kΩ 1 BJ3 ENCODEA C8 0.1µF R43 100Ω AGNDA MC10EP16 NC = NO CONNECT C2 0.1µF R41 25Ω 6 VEE VBB C7 0.1µF +3.3VA 7 Q U2 DGNDA J12 SMA 8 VCC NC R42 100Ω C13 0.47µF DGNDB 02386-023 3 NR 02386-024 AD13280 02386-025 Figure 24. Top Silk Figure 25. Top Layer Rev. C | Page 21 of 28 02386-026 AD13280 02386-027 Figure 26. GND1 Figure 27. GND2 Rev. C | Page 22 of 28 02386-028 AD13280 02386-029 Figure 28. Bottom Silk Figure 29. Bottom Layer Rev. C | Page 23 of 28 AD13280 BILL OF MATERIALS LIST FOR EVALUATION BOARD Table 4. Qty 2 1 2 10 2 4 28 Component Name 74LCX16374MTD AD13280AZ ADP3330 BJACK BRES0805 BRES0805 CAP2 2 2 6 4 2 8 CAP2 H40DM IND2 MC10EP16 MC100EPT23 POLCAP2 4 6 32 RES2 RES2 RES2 12 4 4 1 SMA Standoff Screws PCB Reference U7, U8 U1 U5, U6 BJ1 to BJ10 R41, R53 R38, R39, R55, R56 C1, C2, C5 to C10, C12, C16 to C18, C20 to C26, C28, C31 to C38 C13, C27 J1, J2 L1 to L6 U2, U3, U9, U11 U4, U10 C3, C4, C11, C14, C15, C19, C29, C30 R47 to R50 R1, R2, R5, R7, R8, R54 R3, R4, R6, R9, R12 to R15, R19 to R28, R31 to R37, R42, R43, R44 to R46, R51, R52 J3 to J14 Value Description Latch AD13280 Regulator Banana jacks 0805 SM resistor 0805 SM resistor 0805 SM capacitor Manufacturing Part Number 74LCX16374MTD (Fairchild) AD13280AZ ADP3330ART-3.3RL7 108-0740-001 (Johnson Components) ERJ-6GEYJ 240V (Panasonic) ERJ-6GEYJ 333V (Panasonic) GRM 40X7R104K025BL 10 μF 0805 SM capacitor 2 × 20, 40-pin male connector SM inductor Clock drivers ECL/TTL clock drivers Tantalum polar capacitor VJ1206U474MFXMB (Vishay) TSW-120-08-G-D 2743019447 MC10EP16D (ON Semiconductor) SY100EP23L (ON Semiconductor) T491C106M016AT (Kemet) 0Ω 50 Ω 100 Ω 0805 SM resistor 0805 SM resistor 0805 SM resistor ERJ-6GEY OR 00V (Panasonic) ERJ-6GEYJ 510V (Panasonic) ERJ-6GEYJ 101V (Panasonic) SMA connectors Standoff Screws (standoff ) AD13280 evaluation board 142-0701-201 313-2477-016 (Johnson Components) MPMS 004 0005 PH (Building Fasteners) GS03361 25 Ω 33 kΩ 0.1 μF 0.47 μF 47 Ω Rev. C | Page 24 of 28 AD13280 OUTLINE DIMENSIONS 2.00 (50.80) TYP 0.035 (0.889) MAX 0.350 (8.89) TYP 0.040 (1.02) × 45° DETAIL A PIN 1 TOE DOWN ANGLE 0–8 DEGREES 0.800 (20.32) BSC 0.010 (0.254) 0.960 (24.38) 0.950 (24.13) SQ 0.940 (23.88) TOP VIEW (PINS DOWN) 30° 0.050 (1.27) 0.020 (0.508) DETAIL A ROTATED 90° CCW 0.040 (1.02) R TYP 0.235 (5.97) MAX 0.015 (0.30) × 45° 3 PLS 0.020 (0.508) 0.017 (0.432) 0.014 (0.356) 0.055 (1.40) 0.050 (1.27) 0.045 (1.14) 022608-B 0.010 (0.25) 0.008 (0.20) 0.007 (0.18) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 30. 68-Lead Ceramic Leaded Chip Carrier with Nonconductive Tie-Bar [CLCC] (ES-68-1) Dimensions shown in inches and (millimeters) 0.010 (0.25) 0.008 (0.20) 0.007 (0.18) 0.235 (5.97) MAX 0.960 (24.38) 0.950 (24.13) SQ 0.940 (23.88) 9 61 10 60 PIN 1 TOE DOWN ANGLE 0–8 DEGREES 1.070 (27.18) MIN TOP VIEW 0.800 (20.32) BSC 1.190 (30.23) 1.180 (29.97) SQ 1.170 (29.72) (PINS DOWN) 0.010 (0.254) 44 26 30° 43 27 0.060 (1.52) 0.050 (1.27) 0.040 (1.02) 0.020 (0.508) DETAIL A ROTATED 90° CCW DETAIL A 0.175 (4.45) MAX 0.055 (1.40) 0.050 (1.27) 0.045 (1.14) 0.020 (0.508) 0.017 (0.432) 0.014 (0.356) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 31. 68-Lead Ceramic Leaded Chip Carrier [CLCC] (ES-68-C) Dimensions shown in inches and (millimeters) Rev. C | Page 25 of 28 012908-A 0.050 (1.27) AD13280 ORDERING GUIDE Model AD13280AZ 2 AD13280AF AD13280/PCB 1 2 Temperature Range 1 −25°C to +85°C −25°C to +85°C Package Description 68-Lead Ceramic Leaded Chip Carrier [CLCC] 68-Lead Ceramic Leaded Chip Carrier with Nonconductive Tie-Bar [CLCC] Evaluation Board with AD13280AZ Referenced temperature is case temperature. Z is a package indicator; the part is not RoHS compliant. Rev. C | Page 26 of 28 Package Option ES-68-C ES-68-1 AD13280 NOTES Rev. C | Page 27 of 28 AD13280 NOTES ©2002–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02386–0–4/08(C) Rev. C | Page 28 of 28