AD15452BBC

12-Bit 65 MSPS Quad A/D Converter with Integrated Signal Conditioning AD15452 FEATURES 12-bit, 65 MSPS, quad, analog-to-digital converter Differential input with 100 Ω input impedance Full-scale analog input: 296 mV p-p 200 MHz, 3 dB bandwidth SNR @ −9 dBFS 64 dBFS (70 MHz AIN) 64 dBFS (140 MHz AIN) SFDR @ −9 dBFS 81 dBFS (70 MHz AIN) 73 dBFS (140 MHz AIN) 475 mW per channel Quad LVDS outputs Data clock output provided Offset binary output data format PRODUCT HIGHLIGHTS 1. Quad, 12-bit, 65 MSPS, analog-to-digital converter with integrated analog signal conditioning optimized for antijam global positioning system receiver (AJ-GPS) applications. 2. Packaged in a space saving 81-lead, 10 mm x 10 mm chip scale package ball grid array (CSP_BGA) and specified over the industrial temperature range (−40°C to +85°C). GENERAL DESCRIPTION The AD15452 is a quad, 12-bit, 65 MSPS, analog-to-digital converter (ADC). It features a differential front-end amplification circuit followed by a sample-and-hold amplifier and multistage pipeline analog-to-digital converter. It is designed to operate with a 3.3 V analog supply and a 3.3 V digital supply. Each input is fully differential. The input signals are ac-coupled and terminated in 100 Ω input impedances. The full-scale differential signal input range is 296 mV p-p. Four separate 12-bit digital output signals provide data flow from the ADCs. The digital output data is presented in offset binary format. A single-ended clock input is used to control all internal conversion cycles. The AD15452 is optimized for applications in antijam global positioning receivers and is suited for communications applications. APPLICATIONS Antijam GPS receivers Wireless and wired broadband communications Communications test equipment FUNCTIONAL BLOCK DIAGRAM D+A IN_A LPF D–A D–C LPF D+C IN_C PDOWN CLK IN_B LPF D–B D–D LPF IN_D Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. 05155-001 D+B D+D AD15452 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Product Highlights ........................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics............................................................. 3 Timing Diagram ........................................................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Terminology ...................................................................................... 8 Typical Performance Characteristics ........................................... 10 Theory of Operation ...................................................................... 13 Analog Inputs ............................................................................. 13 Voltage Reference ....................................................................... 13 Clock Input and Considerations .............................................. 13 Digital Outputs ........................................................................... 13 Timing ......................................................................................... 14 DTP Pin ....................................................................................... 14 Power-Down Mode.................................................................... 14 Power Supplies ............................................................................ 14 Outline Dimensions ....................................................................... 15 Ordering Guide .......................................................................... 15 REVISION HISTORY 10/05—Rev. 0: Initial Version Rev. 0 | Page 2 of 16 AD15452 SPECIFICATIONS ELECTRICAL CHARACTERISTICS @ AVDD = DRVDD = PLLVDD = 3.3 V, Encode = 65 MSPS, AIN = −9 dBFS differential input, TA = 25°C, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error MATCHING CHARACTERISTICS Offset Error Gain Error INPUT REFERRED NOISE ANALOG INPUT Input Range Input Resistance 1 Input Capacitance1 CLOCK INPUTS High Level Input Voltage (VIH) Low Level Input Voltage (VIL) High Level Input Current (IIH) Low Level Input Current (IIL) Input Capacitance (CIN) POWER-DOWN INPUT Logic 1 Voltage Logic 0 Voltage Input Capacitance DIGITAL OUTPUTS (LVDS) Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding CLOCK Maximum Conversion Rate Minimum Conversion Rate Clock Pulse Width High (tEH) Clock Pulse Width Low (tEL) OUTPUT PARAMETERS Propagation Delay (tpd) Rise Time (tR) 2 Fall Time (tF)2 FCO Propagation Delay (tFCO) DCO Propagation Delay (tDCO) DCO to Data Delay (tDATA) DCO − FCO Delay (tFRAME) Data to Data Skew Wake-Up Time Pipeline Latency Full 25°C 25°C Full Full Full Full Full Full Full Full 25°C 25°C Full Full Full Full Full Full Full Full Full Full IV I I V V V V V V V IV V V IV IV IV IV V IV IV V VI VI 260 1.15 Offset binary Full Full Full Full Full Full Full Full Full Full Full Full 25°C Full VI IV VI VI VI V V V V IV IV IV V IV 65 10 6.2 6.2 3.3 6.5 250 250 6.5 tFCO + tSAMPLE/24 tSAMPLE/24 tSAMPLE/24 ±100 250 10 7.9 MSPS MSPS ns ns ns ps ps ns ns ps ps ps ns Cycles 2 −10 −10 2 2 0.8 2 440 1.35 0.8 +10 +10 Temp Test Level Min Typ 12 Guaranteed Max Unit Bits −5 −12.5 ±0.35 ±0.5 ±10 ±290 ±2 ±1.2 0.82 296 100 2.5 +5 +12.5 % FSR % FSR LSB LSB ppm/oC ppm/oC % FSR % FSR LSB rms mV p-p Ω pF V V μA μA pF V V pF mV V tSAMPLE/24 − 250 tSAMPLE/24 − 250 tSAMPLE/24 + 250 tSAMPLE/24 + 250 ±250 Rev. 0 | Page 3 of 16 AD15452 Parameter APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter) POWER SUPPLIES Supply Voltages AVDD DRVDD Supply Currents IAVDD IDRVDD Total Power Dissipation Power-Down Dissipation SIGNAL-TO-NOISE RATIO fINPUT = 70 MHz fINPUT = 110 MHz fINPUT = 140 MHz SINAD fINPUT = 70 MHz fINPUT = 110 MHz fINPUT = 140 MHz THD fINPUT = 70 MHz fINPUT = 110 MHz fINPUT = 140 MHz SPURIOUS-FREE DYNAMIC RANGE fINPUT = 70 MHz fINPUT = 110 MHz fINPUT = 140 MHz CROSSTALK 1 2 Temp 25°C 25°C Test Level V Min Typ 1.8