AD1555BPZRL

a 24-Bit
- ADC with Low Noise PGA AD1555/AD1556 high dynamic range measurement applications. The AD1555 outputs a ones-density bitstream proportional to the analog input. When used in conjunction with the AD1556 digital filter/ decimator, a high performance ADC is realized. FEATURES AD1555 Fourth Order
- Modulator Large Dynamic Range 116 dB Min, 120 dB Typical @ 1 ms 117 dB Typical @ 0.5 ms Low Input Noise: 80 nV rms @ 4 ms with Gain of 34,128 Low Distortion: –111 dB Max, –120 dB Typical Low Intermodulation: 122 dB Sampling Rate at 256 kSPS Very High Jitter Tolerance No External Antialias Filter Required Programmable Gain Front End Input Range: 2.25 V Robust Inputs Gain Settings: 1, 2.5, 8.5, 34, 128 Common-Mode Rejection (DC to 1 kHz) 93 dB Min, 101 dB Typical @ Gain of 1 77 mW Typical Low Power Dissipation Standby Modes AD1556 FIR Digital Filter/Decimator Serial or Parallel Selection of Configuration Output Word Rates: 250 SPS to 16 kSPS 6.2 mW Typ Low Power Dissipation 70 W in Standby Mode Reference Design and Evaluation Board with Software Available The continuous-time analog modulator input architecture avoids the need for an external antialias filter. The programmable gain front end simplifies system design, extends the dynamic range, and reduces the system board area. Low operating power and standby modes makes the AD1555 ideal for remote battery-powered data acquisition systems. The AD1555 is fabricated on Analog Devices’ BiCMOS process that has high performance bipolar devices along with CMOS transistors. The AD1555 and AD1556 are packaged, respectively, in 28-lead PLCC and 44-lead MQFP packages and are specified from –55°C to +85°C (AD1556 and AD1555 B Grade) and from 0°C to 85°C (AD1555 A Grade). 0 fIN = 24.4Hz SNR = 116.7dB THD = –120.6dB –20 AMPLITUDE – dBr –40 –60 –80 –100 –120 –140 –160 APPLICATIONS Seismic Data Acquisition Systems Chromatography Automatic Test Equipment –180 –200 0 50 100 150 200 250 300 350 FREQUENCY – Hz 400 450 500 Figure 1. FFT Plot, Full-Scale AIN Input, Gain of 1 GENERAL DESCRIPTION The AD1555 is a complete sigma-delta modulator, combined with a programmable gain amplifier intended for low frequency, FUNCTIONAL BLOCK DIAGRAM REFIN REFCAP2 REFCAP1 AGND3 PGA0...PGA4 H/S ERROR CB0...CB4 MODE CONTROL LOGIC REF DIVIDER PGA CONTROL CONFIGURATION REGISTER INPUT SHIFT REGISTER DIN SCLK OVERVOLTAGE DETECTION DAC MFLG CS STATUS REGISTER R/W CSEL PGA AIN (+) AIN (–) LOOP FILTER MUX DATA OUTPUT MUX DIGITAL FILTER INPUT MUX CLOCK GENERATION AD1555 TIN (–) PGAOUT MODIN AGND2 +VA –VA VL DGND MCLK DOUT DRDY MDATA TIN (+) AGND1 TDATA CLOCK DIVIDER DATA REGISTER RSEL AD1556 CLKIN SYNC BW0...BW2 RESET PWRDN GND VL REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 AD1555/AD1556 (+VA = +5 V; –VA = –5 V; VL = 5 V; AGND = DGND = 0 V; MCLK = 256 kHz; TA = TMIN to MAX, unless otherwise noted.) AD1555–SPECIFICATIONS T Parameter Notes PGA Gain Settings 1, 2.5, 8.5, 34, 128 AC ACCURACY Dynamic Range1 Total Harmonic Distortion2 Jitter Tolerance3 Intermodulation Distortion 4 DC ACCURACY Absolute Gain Error5 Gain Stability Over Temperature 5 Offset5, 6 Offset Drift5, 6 ANALOG INPUT Full-Scale Nondifferential Input Input Impedance Full-Scale Differential Input Differential Input Impedance Common-Mode Range Common-Mode Rejection Ratio Power Supply Rejection Ratio 7 AIN to TIN Crosstalk Isolation Differential Input Current TEMPERATURE RANGE8 Specified Performance REFERENCE INPUT Input Voltage Range Input Current Min PGA Gain of 1 PGA Gain of 2.5 PGA Gain of 8.5 PGA Gain of 34 PGA Gain of 128 PGA Gain of 1 PGA Gain of 2.5 PGA Gain of 8.5 PGA Gain of 34 PGA Gain of 128 AD1555BP Typ Max 116.5 116 114 104.5 120 119.5 117.5 109.5 98 –120 –116 –116 –115 –108 Min AD1555AP Typ Max 116 115.5 114 104.5 –111 –108 –106 –101 120 119.5 117.5 109.5 98 –120 –116 –116 –115 –108 300 PGA Gain of 1 300 122 PGA Gain of 1, 2.5 PGA Gain of 8.5 PGA Gain of 34 –3.5 –4.5 –10 122 +3.5 +4.5 +10 –3.5 –4.5 –10 ± 15 –60 6 All PGA Gain 20 VCM = ±2.25 V, fIN = 200 Hz PGA Gain of 1 PGA Gain of 2.5 PGA Gain of 8.5, 34 PGA Gain of 128 93 95 95.5 fIN = 200 Hz TMIN to TMAX 101 102 108 108 50 130 130 –55 % % % ppm/°C mV µV/°C ± 2.25 ± 2.25 V k⍀ V ± 2.25 MΩ V 20 ± 2.25 See Table I 140 ± 2.25 See Table I 140 91 91.5 94.5 +85 0 3.010 2.990 +0.8 VL + 0.3 +10 +10 0.4 –0.3 2.0 –10 –10 dB dB dB dB dB dB dB dB dB dB ps dB +3.5 +4.5 +10 ± 15 –60 6 ± 2.25 MODIN MODIN PGA Gain of 1 Other PGA Gain Settings AIN, TIN Inputs –107 –107 –105 –101 Unit 101 102 108 108 50 130 130 dB dB dB dB dB dB nA 85 °C 3.010 V µA +0.8 VL + 0.3 +10 +10 0.4 V V µA µA V V 9 DIGITAL INPUTS OUTPUTS VIL VIH IIL IIH VOL VOH 2.990 –0.3 2.0 –10 –10 ISINK = +2 mA ISOURCE = –2 mA 2.4 –2– 3.0 130 2.4 3.0 130 REV. B AD1555/AD1556 Parameter Notes Min POWER SUPPLIES Recommended Operating Conditions +VA –VA VL Quiescent Currents I(+VA)10 I(–VA)10 I(VL) Power Dissipation10 AD1555BP Typ Max 4.75 –5.25 4.75 PGA in Standby Mode11 In Power-Down Mode11, 12 Reference Input = 3 V Reference Input = 0 V 5 –5 5 5.25 –4.75 5.25 8 8 30 77 56 10 9.5 42 96 70 Min AD1555AP Typ Max 4.75 –5.25 4.75 650 250 Unit 5 –5 5 5.25 –4.75 5.25 V V V 8 8 30 77 56 10 9.5 42 96 70 mA mA µA mW mW µW µW 650 250 NOTES 1 Tested at the output word rate FO = 1 kHz. FO is the AD1556 output word rate, the inverse of the sampling rate. See Tables I, Ia, Ib for other output word rates. 2 Tested with a full-scale input signal at approximately 24 Hz. 3 This parameter is guaranteed by design. 4 Tested at the output word rate FO = 1 kHz with input signals of 30 Hz and 50 Hz, each 6 dB down full scale. 5 This specification is for the AD1555 only and does not include the errors from external components as, for instance, the external reference. 6 This offset specification is referred to the modulator output. 7 Characterized with a 100 mV p-p sine wave applied separately to each supply. 8 Contact factory for extended temperature range. 9 Recommended Reference: AD780BR. 10 Specified with analog inputs grounded. 11 See Table III for configuration conditions. 12 Specified with MCLK input grounded. Specifications subject to change without notice. AD1556–SPECIFICATIONS (V = 2.85 V to 5.25 V; CLKIN = 1.024 MHz; T = T L Parameter FILTER PERFORMANCES Pass-Band Ripple Stop-Band Attenuation A Notes Min POWER SUPPLIES Specified Performance VL Quiescent Currents I(VL) Power Dissipation Max Unit +0.05 –135 –86 dB dB dB +0.8 VL + 0.3 +10 +10 +0.5 V V µA µA V V 5.25 V 5 8.5 mA mW µW +85 °C See Table II –0.3 +2.0 –10 –10 ISINK = +2 mA ISOURCE = –2 mA VL – 0.6 2.85 4 6.2 70 VL = 3.3 V, FO = 1 kHz In Power-Down Mode –55 Contact factory for extended temperature range. Specifications subject to change without notice. REV. B AD1556AS Typ –0.05 TEMPERATURE RANGE* Specified Performance, TMIN to TMAX * to TMAX unless otherwise noted.) All Filters Except FO =16 kHz FO =16 kHz Filters Characteristics DIGITAL INPUTS OUTPUTS VIL VIH IIL IIH VOL VOH MIN –3– AD1555/AD1556 Table I. Dynamic and Noise Typical Performances Input and Gain MODIN PGA = 1 (0 dB) PGA = 2.5 (8 dB) PGA = 8.5 (19 dB) PGA = 34 (31 dB) PGA = 128 (42 dB) Input Range Dynamic Range FO = 16 kHz (1/16 ms) FO = 8 kHz (1/8 ms) FO = 4 kHz (1/4 ms) FO = 2 kHz (1/2 ms) FO = 1 kHz (1 ms) FO = 500 Hz (2 ms) FO = 250 Hz (4 ms) Equivalent Input Noise FO = 16 kHz (1/16 ms) FO = 8 kHz (1/8 ms) FO = 4 kHz (1/4 ms) FO = 2 kHz (1/2 ms) FO = 1 kHz (1 ms) FO = 500 Hz (2 ms) FO = 250 Hz (4 ms) 1.6 V rms 1.6 V rms 636 mV rms 187 mV rms 47 mV rms 12.4 mV rms 40 dB 69 dB 98 dB 117 dB 120 dB 123 dB 126 dB 40 dB 69 dB 98 dB 117 dB 120 dB 123 dB 126 dB 40 dB 69 dB 98 dB 116.5 dB 119.5 dB 122.5 dB 125.5 dB 40 dB 69 dB 98 dB 114.5 dB 117.5 dB 120 dB 123 dB 40 dB 69 dB 97 dB 106.5 dB 109.5 dB 112.5 dB 115.5 dB 40 dB 69 dB 91 dB 95 dB 98 dB 101 dB 104 dB 15.5 mV rms 560 µV rms 20 µV rms 2.25 µV rms 1.59 µV rms 1.13 µV rms 797 nV rms 15.5 mV rms 560 µV rms 20 µV rms 2.25 µV rms 1.59 µV rms 1.13 µV rms 797 nV rms 6.17 mV rms 220 µV rms 8 µV rms 952 nV rms 674 nV rms 477 nV rms 338 nV rms 1.84 mV rms 65.5 µV rms 2.36 µV rms 353 nV rms 250 nV rms 187 nV rms 133 nV rms 470 µV rms 16.4 µV rms 661 nV rms 225 nV rms 159 nV rms 113 nV rms 80 nV rms 138 µV rms 4.5 µV rms 351 nV rms 223 nV rms 159 nV rms 111 nV rms 79 nV rms Table Ia. Minimum Dynamic Performances (AD1555AP Only)* Input and Gain MODIN PGA = 1 (0 dB) PGA = 2.5 (8 dB) PGA = 8.5 (19 dB) PGA = 34 (31 dB) FO = 1 kHz (1 ms) FO = 500 Hz (2 ms) FO = 250 Hz (4 ms) 116 119 122 116 119 122 115.5 118.5 121.5 114 117 120 104.5 107.5 110.5 * Not tested in production. Guaranteed by design. Table Ib. Minimum Dynamic Performances (AD1555BP Only)* Input and Gain MODIN PGA = 1 (0 dB) PGA = 2.5 (8 dB) PGA = 8.5 (19 dB) PGA = 34 (31 dB) FO = 1 kHz (1 ms) FO = 500 Hz (2 ms) FO = 250 Hz (4 ms) 116.5 119.5 122.5 116.5 119.5 122.5 116 119 121 114 117 120 104.5 107.5 110.5 * Not tested in production. Guaranteed by design. Table II. Filter Characteristics Output Word Rate FO (Sampling Rate in ms) Pass Band (Hz) –3 dB Frequency (Hz) Stop Band (Hz) Group Delay (ms) 16000 Hz (1/16 ms) 8000 Hz (1/8 ms) 4000 Hz (1/4 ms) 2000 Hz (1/2 ms) 1000 Hz (1 ms) 500 Hz (2 ms) 250 Hz (4 ms) 6000 3000 1500 750 375 187.5 93.75 6480 3267.5 1634 816.9 408.5 204.2 101.4 8000 4000 2000 1000 500 250 125 0.984 3 6 12 24 48 93 –4– REV. B AD1555/AD1556 (+VA = +5 V  5%; –VA = –5 V  5%; AD1555 VL = 5 V  5%, AD1556 VL = 2.85 V to 5.25 V; L A MIN to TMAX, unless otherwise noted) TIMING SPECIFICATIONS CLKIN = 1.024 MHz; AGND = DGND = 0 V; C = 50 pF; T = T Symbol Min Typ Max Unit CLKIN Frequency CLKIN Duty Cycle Error MCLK Output Frequency1 fCLKIN 0.975 45 1.024 1.075 55 MHz % SYNC Setup Time SYNC Hold Time CLKIN Rising to MCLK Output Falling on SYNC CLKIN Falling to MCLK Output Rising CLKIN Falling to MCLK Output Falling MCLK Input Falling to MDATA Falling MCLK Input Rising to MDATA and MFLG Valid TDATA Setup Time after SYNC TDATA Hold Time t1 t2 t3 t4 t5 t6 t7 t8 t9 10 10 20 20 20 30 100 5 5 ns ns ns ns ns ns ns ns ns RESET Setup Time RESET Hold Time t10 t11 15 15 ns ns CLKIN Falling to DRDY Rising CLKIN Rising to DRDY Falling2 CLKIN Rising to ERROR Falling t12 t13 t14 RSEL to Data Valid RSEL Setup to SCLK Falling DRDY to Data Valid DRDY High Setup to SCLK Falling R/W to Data Valid R/W High Setup to SCLK Falling CS to Data Valid CS Low Setup to SCLK Falling SCLK Rising to DOUT Valid SCLK High Pulsewidth SCLK Low Pulsewidth SCLK Period SCLK Falling to DRDY Falling2 CS High or R/W Low to DOUT Hi-Z t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 R/W Low Setup to SCLK Falling CS Low Setup to SCLK Falling Data Setup Time to SCLK Falling Data Hold Time after SCLK Falling R/W Hold Time after SCLK Falling t29 t30 t31 t32 t33 1 fCLKIN/4 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 25 10 25 10 25 10 25 25 25 70 20 20 10 10 10 10 10 ns ns ns ns ns Specifications subject to change without notice. 1.6mA IOL 1.4V CL 50pF 500A IOH Figure 2. Load Circuit for Digital Interface Timing REV. B ns ns ns 10 NOTES 1 The gain of the modulator is proportional to f CLKIN and MCLK frequency. 2 With DRDYBUF low only. When DRDYBUF is high, this timing also depends on the value of the external pull-down resistor. TO OUTPUT PIN 20 20 50 –5– AD1555/AD1556 CLKIN t2 t1 SYNC t3 t4 t5 MCLK (FS) MDATA DATA VALID DATA VALID t6 t8 t7 t9 VALID TDATA VALID Figure 3. AD1555/AD1556 Interface Timing t 11 t 10 RESET t1 t2 CLKIN SYNC t 12 t 13 t 12 DRDY t 14 ERROR Figure 4. AD1556 RESET, DRDY, and Overwrite Timings –6– REV. B AD1555/AD1556 t 15 RSEL t 16 t 17 DRDY t 18 t 27 t 19 R/W t 20 CS t 21 t 22 t 28 MSB DOUT MSB–1 LSB+1 HI-Z LSB t 23 SCLK t 24 t 26 t 25 Figure 5. Serial Read Timing CS t 29 R/W t 30 t 33 t 24 SCLK t 32 t 31 DIN MSB t 25 t 26 MSB–1 LSB+1 Figure 6. Serial Write Timing REV. B –7– LSB AD1555/AD1556 ABSOLUTE MAXIMUM RATINGS 1 Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C Analog Inputs Pins 7, 8, 23, 24, 25, 28 . . . . . . –VA – 0.3 V to +VA + 0.3 V AIN(+), AIN(–) DC Input Current . . . . . . . . . . . ± 100 mA AIN(+), AIN(–) 2 µs Pulse Input Current . . . . . . . . ± 1.5 A Supply Voltages +VA to –VA . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +14 V +VA to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V –VA to AGND . . . . . . . . . . . . . . . . . . . . . . . –7 V to +0.3 V VL to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V Ground Voltage Differences DGND, AGND1, AGND2, AGND3 . . . . . . . . . . . ± 0.3 V Digital Inputs . . . . . . . . . . . . . . . . . . . . –0.3 V to VL + 0.3 V Internal Power Dissipation2 AD1555 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8 W AD1556 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8 W NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air: 28-lead PLCC: θJA = 36°C/W, θJC = 20°C/W 44-lead MQFP: θJA = 36°C/W, θJC = 14°C/W ORDERING GUIDE Model AD1555AP AD1555APRL AD1555BP AD1555BPRL AD1556AS AD1556ASRL EVAL-AD1555/AD1556EB AD1555/56-REF Temperature Range* 0°C to 85°C 0°C to 85°C –55°C to +85 °C –55°C to +85 °C –55°C to +85 °C –55°C to +85 °C Package Description Plastic Lead Chip Carrier Plastic Lead Chip Carrier Plastic Lead Chip Carrier Plastic Lead Chip Carrier Plastic Quad Flatpack Plastic Quad Flatpack Package Option P-28A P-28A P-28A P-28A S-44A S-44A Evaluation Board Reference Design *Contact factory for extended temperature range. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1555/AD1556 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –8– WARNING! ESD SENSITIVE DEVICE REV. B AD1555/AD1556 PIN CONFIGURATION 1 28 27 26 +VA MODIN 2 AGND2 3 PGAOUT 4 AGND1 –VA +VA 28-Lead PLCC (P-28A) PIN 1 AIN(+) 5 25 REFIN 24 REFCAP2 AIN(–) 6 TIN(+) 7 23 REFCAP1 AD1555 TOP VIEW 22 AGND3 (Not to Scale) 21 –VA TIN(–) 8 NC 9 NC = NO CONNECT (DO NOT CONNECT THIS PIN) 17 18 MCLK 16 DGND 15 MDATA 14 CB3 12 13 CB4 19 V L MFLG 20 –V A CB1 11 CB2 CB0 10 DGND MCLK MDATA RESETD MFLG CB4 CB2 CB3 CB0 CB1 VL 44-Lead MQFP (S-44A) 44 43 42 41 40 39 38 37 36 35 34 33 NC NC 1 PGA0 2 PGA1 3 PIN 1 IDENTIFIER 32 CLKIN 31 SYNC 30 TDATA PGA2 4 PGA3 5 AD1556 PGA4 6 TOP VIEW (Not to Scale) BW0 7 29 CSEL 28 NC 27 NC 26 PWRDN BW1 8 BW2 9 25 RESET H/S 10 24 DGND VL 11 23 DGND NC = NO CONNECT REV. B –9– VL NC ERROR DIN RSEL R/W CS DRDY DOUT SCLK DGND 12 13 14 15 16 17 18 19 20 21 22 AD1555/AD1556 AD1555 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 2 AGND1 PGAOUT 3, 26 4, 20, 21 5 6 7 8 9 10–14 +VA –VA AIN(+) AIN(–) TIN(+) TIN(–) NC CB0–CB4 15 16 17 MFLG DGND MDATA 18 MCLK 19 22 23 VL AGND3 REFCAP1 24 25 REFCAP2 REFIN 27 28 AGND2 MODIN Analog Ground Programmable Gain Amplifier Output. The output of the on-chip programmable gain amplifier is available at this pin. Refer to Table III for PGA gain settings selection. Positive Analog Supply Voltage. +5 V nominal. Negative Analog Supply Voltage. –5 V nominal. Mux Input. Noninverting signal to the PGA mux input. Refer to Table III for input selection. Mux Input. Inverting signal to the PGA mux input. Refer to Table III for input selection. Mux Input. Noninverting test signal to the PGA mux input. Refer to Table III for input selection. Mux Input. Inverting test signal to the PGA mux input. Refer to Table III for input selection. Pin for Factory Use Only. This pin must be kept not connected for normal operation. Modulator Control. These input pins control the mux selection, the PGA gain settings, and the standby modes of the AD1555. When used with the AD1556, these pins are generally directly tied to the CB0–CB4 output pins of the AD1556. CB0–CB2 are generally used to set the PGA gain or cause it to enter in the PGA standby mode (refer to Table III). CB3 and CB4 select the mux input voltage applied to the PGA as described in Table III. Modulator Error. Digital output that is pulsed high if an overrange condition occurs in the modulator. Digital Ground Modulator Output. The bitstream generated by the modulator is output in a return-to-zero data format. The data is valid for approximately one-half a MCLK cycle. Refer to Figure 3. Clock Input. The clock input signal, nominally 256 kHz, provides the necessary clock for the Σ-∆ modulator. When this input is static, AD1555 is in the power-down mode. Positive Digital Supply Voltage. 5 V Nominal. Analog Ground. Used as the ground reference for the REFIN pin. DAC Reference Filter. The reference input is internally divided and available at this pin to provide the reference for the ⌺-⌬ modulator. Connect an external 22 µF (5 V min) tantalum capacitor from REFCAP1 to AGND3 to filter the external reference noise. Reference Filter. The reference input is internally divided and available at this pin. Reference Input. This input accepts a 3 V level that is internally divided to provide the reference for the Σ-∆ modulator. Analog Ground. Modulator Input. Analog input to the modulator. Normally, this input is directly tied to PGAOUT output. AD1556 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1, 21, 27, 28, 33 2–6 NC No Connect PGA0–PGA4 7–9 BW0–BW2 10 H/S 11, 22, 44 12, 23, 24, 34 13 VL DGND SCLK PGA and MUX Control Inputs. Sets the logic level of CB0-CB4 output pins respectively and the state of the corresponding bit in the configuration register upon RESET or when in hardware mode. Refer to Table III. Output Rate Control Inputs. Sets the digital filter decimation rate and the state of the corresponding bit in the configuration register upon RESET or when in hardware mode. Refer to the Filter Specifications and Table VI. Hardware/Software Mode Select. Determines how the device operation is controlled. In hardware mode, H/S is high, the state of hardware pins set the mode of operation. When H/S is low, a write sequence to the Configuration Register or a previous write sequence sets the device operation. Positive Digital Supply Voltage. 3.3 V or 5 V nominal. Digital Ground Serial Data Clock. Synchronizes data transfer to either write data on the DIN input pin or read data on the DOUT output pin. –10– REV. B AD1555/AD1556 AD1556 PIN FUNCTION DESCRIPTIONS (continued) Pin No. Mnemonic Description 14 DOUT 15 DRDY 16 CS 17 R/W 18 RSEL 19 DIN 20 ERROR 25 RESET 26 PWRDN 29 CSEL 30 31 TDATA SYNC 32 CLKIN 35 MCLK 36 MDATA 37 38 RESETD MFLG 43–39 CB0–CB4 Serial Data Output. DOUT is used to access the conversion results or the contents of the Status Register, depending on the logic state of the RSEL pin. At the beginning of a read operation, the first data bit is output (MSB first). The data changes on the rising edge of SCLK and is valid on the SCLK falling edge. Data Ready. A logic high output indicates that data is ready to be accessed from the Output Data Register. DRDY goes low once a read operation is complete. When selected, the DRDY output pin has a type buffer that allows wired-OR connection of multiple AD1556s. Chip Select. When set low the serial data interface pins DIN, DOUT, R/W, and SCLK are active; a logic high disables these pins and sets the DOUT pin to Hi-Z. Read/Write. A read operation is initiated if R/W is high and CS is low. A low sets the DOUT pin to Hi-Z and allows a write operation to the device via the DIN pin. Register Select. When set high, the Conversion Data Register contents are output on a read operation. A low selects the Status Register. Serial Data Input. Used during a write operation. Loads the Configuration Register via the Input Shift Register. Data is loaded MSB first and must be valid on the falling edge of SCLK. Error Flag. A logic low output indicates an error condition occurred in the modulator or digital filter. When ERROR goes low the ERROR bit in the status register is set high. The ERROR output pin has an open drain type buffer with an internal 100 kΩ typical pull-up that allows wired-OR connection of multiple AD1556s. Chip Reset. A logic high input clears any error condition in the status register and sets the configuration register to the state of the corresponding hardware pins. On power-up, this reset state is entered. Power-Down Hardware Control. A logic high input powers down the filter. The convolution cycles in the digital filter and the MCLK signal are stopped. All registers retain their data and the serial data interface remains active. The power-down mode is entered on the first falling edge of CLKIN after PWRDN is taken high. When exiting the power-down mode, a SYNC must be applied to resume filter convolutions. Filter Input Select. Selects the source for input to the digital filter. A logic high selects the TDATA input, a low selects MDATA as the filter input. Test Data. Input to digital filter for user test data. Synchronization Input. The SYNC input clears the AD1556 filter in order to synchronize the start of the filter convolutions. The SYNC event is initiated on the first CLKIN rising edge after the SYNC pin goes high. The SYNC input can also be applied synchronously to the AD1556 decimation rate without resetting the convolution cycles. Clock Input. The clock input signal, nominally 1.024 MHz, provides the necessary clock for the AD1556. This clock frequency is divided by four to generate the MCLK signal for the AD1555. Modulator Clock. Provides the modulator sampling clock frequency. The modulator always samples at one-fourth the CLKIN frequency. Modulator Data. This input receives the ones-density bit stream from the AD1555 for input to the digital filter. Decimator Reset. A logic high resets the decimator of the digital filter. Modulator Error. The MFLG input is used to detect if an overrange condition occurred in the modulator. Its logic level is sensed on the rising edge of CLKIN. When overrange condition detected, ERROR goes low and updates the status register. Modulator Control. These output control pins represent a portion of the data loaded into the AD1556 Configuration Register. CB0–CB2 are generally used to set the PGA gain or cause it to enter in the PGA standby mode (Refer to Table III). CB3 and CB4 select the mux input voltage applied to the PGA as described in Table III. REV. B –11– AD1555/AD1556 TERMINOLOGY OFFSET DYNAMIC RANGE The offset is the difference between the ideal midscale input voltage (0 V) and the actual voltage producing the midscale output code (code 000000H) at the output of the AD1556. The offset specification is referred to the output. This offset is intentionally set at a nominal value of –60 mV (see Sigma-Delta Modulator section). The value for offset is expressed in mV. Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together in the bandwidth from 3 Hz to the Nyquist frequency FO/2. The value for dynamic range is expressed in decibels. SIGNAL-TO-NOISE RATIO (SNR) SNR is the ratio of the rms value of the full-scale signal to the total rms noise in the bandwidth from 3 Hz to the Nyquist frequency FO/2. The value for SNR is expressed in decibels. OFFSET ERROR DRIFT The change of the offset over temperature. It is expressed in mV. GAIN ERROR TOTAL HARMONIC DISTORTION (THD) THD is the ratio of the rms sum of all the harmonic components up to Nyquist frequency FO/2 to the rms value of a full-scale input signal. The value for THD is expressed in decibels. The gain error is the ratio of the difference between the actual gain and the ideal gain to the ideal gain. The actual gain is the ratio of the output difference obtained with a full-scale analog input (± 2.25 V) to the full-scale span (4.5 V) after correction of the effects of the external components. It is expressed in %. INTERMODULATION DISTORTION (IMD) IMD is the ratio of the rms sum of two sine wave signals of 30 Hz and 50 Hz which are each 6 dB down from full scale to the rms sum of all intermodulation components within the bandwidth from 1 Hz to the Nyquist frequency FO/2. The value for IMD is expressed in decibels. GAIN ERROR STABILITY OVER TEMPERATURE The change of the gain error over temperature. It is expressed in %. –12– REV. B Typical Performance Characteristics– AD1555/AD1556 0 130 fIN = 24.4Hz SNR = 116.7dB THD = –120dB –20 120 DYNAMIC RANGE – dB AMPLITUDE – dBr –40 G=1 –60 –80 –100 –120 –140 –160 G = 2.5 110 G = 34 G = 8.5 G = 128 100 90 –180 –200 0 50 100 150 200 250 300 350 FREQUENCY – Hz 400 450 80 –55 500 TPC 1. FFT (2048 Points) Full-Scale MODIN Input 5 25 45 65 TEMPERATURE – C 85 105 125 TPC 4. Dynamic Range vs. Temperature 35 0 fIN = 24.4Hz SNR = 105.8dB THD = –114.9dB –20 –40 30 –60 NUMBER OF UNITS AMPLITUDE – dBr –15 –35 –80 –100 –120 –140 25 20 15 10 –160 5 –180 –200 0 50 100 150 200 250 300 350 FREQUENCY – Hz 400 450 0 –122 500 TPC 2. FFT (2048 Points) Full-Scale AIN Input, Gain of 34 –119 –118 DYNAMIC RANGE – dB –117 –116 TPC 5. Dynamic Range Distribution (272 Units) 0 150 fIN = 24.4Hz SNR = 68.2dB THD = –120dB –20 –40 G = 34 140 G=1 –60 130 CMRR – dB AMPLITUDE – dBr –121 –80 –100 –120 G = 2.5 120 110 –140 G = 128 –160 G = 8.5 100 –180 –200 0 500 1000 1500 2000 2500 FREQUENCY – Hz 3000 3500 90 –55 4000 –15 5 25 45 65 85 105 125 TEMPERATURE – C TPC 3. FFT (16384 Points) Full-Scale AIN Input, Gain of 1 REV. B –35 TPC 6. Common-Mode Rejection vs. Temperature –13– AD1555/AD1556 20 0.20 18 0.15 16 AMPLITUDE – dB NUMBER OF UNITS 0.10 14 12 10 8 0.05 0.00 –0.05 6 –0.10 4 –0.15 2 0 –128 –0.20 –120 –113 –105 CMRR – dB –98 –90 0 50 100 150 200 250 FREQUENCY – Hz TPC 7. Common-Mode Rejection Distribution (272 Units) TPC 10. AD1556 Pass Band Ripple, FO = 500 Hz (2 ms) 120 0.20 G = 8.5 0.15 115 G = 34 0.10 105 AMPLITUDE – dB CMRR – dB 110 G = 128 G = 2.5 100 G=1 0.05 0.00 –0.05 –0.10 95 –0.15 90 –0.20 0 100 200 300 400 500 600 700 800 900 0 1000 100 FREQUENCY – Hz TPC 8. Common-Mode Rejection vs. Frequency 300 400 500 TPC 11. AD1556 Pass Band Ripple, FO = 1 kHz (1 ms) 0.20 0.20 0.15 0.15 0.10 0.10 AMPLITUDE – dB AMPLITUDE – dB 200 FREQUENCY – Hz 0.05 0.00 –0.05 0.05 0.00 –0.05 –0.10 –0.10 –0.15 –0.15 –0.20 –0.20 0 25 50 75 100 125 0 FREQUENCY – Hz 200 400 600 800 1000 FREQUENCY – Hz TPC 9. AD1556 Pass Band Ripple, FO = 250 Hz (4 ms) TPC 12. AD1556 Pass Band Ripple, FO = 2 kHz (1/2 ms) –14– REV. B 0.20 0.20 0.15 0.15 0.10 0.10 AMPLITUDE – dB AMPLITUDE – dB AD1555/AD1556 0.05 0.00 –0.05 0.00 –0.05 –0.10 –0.10 –0.15 –0.15 –0.20 –0.20 0 500 1000 1500 2000 0 FREQUENCY – Hz 0.15 0.10 0.05 0.00 –0.05 –0.10 –0.15 –0.20 1000 2000 3000 4000 FREQUENCY – Hz TPC 14. AD1556 Pass Band Ripple, FO = 8 kHz (1/8 ms) REV. B 4000 6000 8000 TPC 15. AD1556 Pass Band Ripple, FO = 16 kHz (1/16 ms) 0.20 0 2000 FREQUENCY – Hz TPC 13. AD1556 Pass Band Ripple, FO = 4 kHz (1/4 ms) AMPLITUDE – dB 0.05 –15– AD1555/AD1556 The AD1555 operates from a dual analog supply (± 5 V), while the digital part of the AD1555 operates from a +5 V supply. The AD1556 operates from a single 3.3 V or 5 V supply. Each device exhibits low power dissipation and can be configured for standby mode. CIRCUIT DESCRIPTION The AD1555/AD1556 chipset is a complete sigma-delta 24-bit A/D converter with very high dynamic range intended for the measurement of low frequency signals up to a few kHz such as those in seismic applications. The AD1555 contains an analog multiplexer, a fully differential programmable gain amplifier and a fourth order sigma-delta modulator. The analog multiplexer allows selection of one fully differential input from two different external inputs, an internal ground reference or an internal full-scale voltage reference. The fully differential programmable gain amplifier (PGA) has five gain settings of 1, 2.5, 8.5, 34, and 128, which allow the part to handle a total of five different input ranges: 1.6 V rms, 636 mV rms, 187 mV rms, 47 mV rms, and 12.4 mV rms that are programmed via digital input pins (CB0 to CB4). The modulator that operates nominally at a sampling frequency of 256 kHz, outputs a bitstream whose ones-density is proportional to its input voltage. This bitstream can be filtered using the AD1556, which is a digital finite impulse low pass filter (FIR). The AD1556 outputs the data in a 24-bit word over a serial interface. The cutoff frequency and output rate of this filter can be programmed via an on-chip register or by hardware through digital input pins. The dynamic performance and the equivalent input noise vary with gain and output rate as shown in Table I. The use of the different PGA gain settings allows enhancement of the total system dynamic range up to 146 dB (gain of 34 or 128 and FO = 250 Hz). AC SINE TEST SOURCE Figure 7 illustrates a typical operating circuit. MULTIPLEXER AND PROGRAMMABLE GAIN AMPLIFIER (PGA) Analog Inputs The AD1555 has two sets of fully differential inputs AIN and TIN. The common-mode rejection capability of these inputs generally surpasses the performance of conventional programmable gain amplifiers. The very high input impedance, typically higher than 140 MΩ, allows direct connection of the sensor to the AD1555 inputs, even through serial resistances. Figure 7 illustrates such a configuration. The passive filter between the sensor and the AD1555 is shown here as an example. Other filter structures could be used, depending on the specific requirements of the application. Also, the Johnson noise (√4 k TRB) of the serial resistance should be taken into consideration. For instance, a 1 kΩ serial resistance reduces by approximately 1.3 dB the dynamic performance of a system using a gain setting of 128 at an output word rate FO = 500 Hz. For applications where the sensor inputs must be protected against severe DC TEST SOURCE UNUSED AD1555 PINS MUST BE LEFT UNCONNECTED; UNUSED AD1556 INPUT PINS MUST BE TIED TO DGND OR VL. 3 +5V 3 14 –5V ADG609 100nF 100nF DB DA 4 15 15 9 TEM AD780 +VIN P 6 VOUT GND O/P 28 25 MFLG MDATA TO OTHER AD1555s T1 15 MFLG 17 R2 R4 MCLK TDATA SCLK DIN MCLK DOUT +5V VL 6 19 DGND AGND1 AGND2 3, 26 1 DRDY 15 100nF AIN (–) +VA RSEL MDATA C1 C2 R/W CB0...CB4 18 AD1555 AIN (+) C3 T2 CS 5 TIN (–) SENSOR: GEOPHONE, HYDROPHONE... 32 22 CB0...CB4 8 ERROR SYNC 16 4, 20, 21 RESETD –5V 10F 100nF 100nF 17 18 30 13 19 14 15 20 TO OTHER AD1556s RESET +5V 16 AD1556 10F –VA 27 SERIAL DATA INTERFACE ADSP-21xxx OR P CLOCK SOURCE 1.024MHz 23 TIN (+) 5 100nF 8 PGAOUT MODIN REFIN REFCAP1 AGND3 7 R3 +5V 22F 8 2 R1 2 H/S VL 10F 11, 22, 44 31 25 HARDWARE CONTROL 37 10 DGND 100nF 12, 23, 24, 34 VDIG Figure 7. Typical Operating Circuit –16– REV. B AD1555/AD1556 external stresses such as lightning, the inputs AIN are specifically designed to ease the design. The external voltage spike is generally clamped by devices T1 and T2 at about hundred volts (for instance, devices T1 and T2 can be gas discharge tubes) and then generates a pulsed current in the serial resistances (R1, R3, and R2, R4). The AD1555 AIN inputs, using robust internal clamping diodes to the analog supply rails, can handle this huge pulsed input current (1.5 A during 2 ␮s) without experiencing any destructive damages or latch-up, whether or not the AD1555 is powered on. Meanwhile, enough time should be left between multiple spikes to avoid excessive power dissipation. AIN (+) AIN (–) 50 50 S1(–) TIN (+) TIN (–) 100 100 S2(–) 500 S3(+) S3(–) REFIN 7.5k REFCAP2 22.5k The multiplexer, which exhibits a break-before-make switching action, allows various combinations. S2(+) 500 Programming the AD1555 The different hardware events of the AD1555 as multiplexer inputs selection, programmable gain settings, and power-down modes are selectable using the control pins bus CB0 to CB4 according to the Table III. This table is only valid when MCLK is toggling; otherwise, the AD1555 is powered down. When used in combination with the AD1556, this control bus could either be loaded by hardware (H/S pin high) or via the serial interface of the AD1556 (H/S pin low). S1(+) AGND3 S4(+) S4(–) AD1555 Figure 8. Simplified AD1555 Input Multiplexer When the ground input is selected, S3(+) and S3(–) are closed, all the other switches are opened, and the inputs of the programmable gain amplifier are shorted through an accurate internal 1 kΩ resistor. This combination allows accurate calibration of the offset of the AD1555 for each gain setting. Also, a system noise calibration can be done using the internal 1 kΩ resistor as a noise reference. Table III. PGA Input and Gain Control CB4 CB3 CB2 CB1 CB0 Description 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 1 1 0 1 0 X X X X 1 1 0 1 1 X Ground Input with PGA Gain of 1 Ground Input with PGA Gain of 2.5 Ground Input with PGA Gain of 8.5 Ground Input with PGA Gain of 34 Ground Input with PGA Gain of 128 Test Inputs TIN(+) and TIN(–) with PGA Gain of 1 Test Inputs TIN(+) and TIN(–) with PGA Gain of 2.5 Test Inputs TIN(+) and TIN(–) with PGA Gain of 8.5 Test Inputs TIN(+) and TIN(–) with PGA Gain of 34 Test Inputs TIN(+) and TIN(–) with PGA Gain of 128 Signal Inputs AIN(+) and AIN(–) with PGA Gain of 1 Signal Inputs AIN(+) and AIN(–) with PGA Gain of 2.5 Signal Inputs AIN(+) and AIN(–) with PGA Gain of 8.5 Signal Inputs AIN(+) and AIN(–) with PGA Gain of 34 Signal Inputs AIN(+) and AIN(–) with PGA Gain of 128 VREF Input with PGA Gain of 1 Sensor Test 1: Signal inputs AIN(+) and AIN(–) with AIN(+) and AIN(–) inputs tied respectively to TIN(+) and TIN(–) inputs and with PGA Gain of 1. Sensor Test 2: Signal inputs TIN(+) and TIN(–) with AIN(–) input tied to TIN(–) input and with PGA Gain of 1. PGA Powered Down Chip Powered Down REV. B –17– AD1555/AD1556 When the VREF input is selected, S4(+) and S4(–) are closed, all the other switches are opened, and a reference voltage (2.25 V) equal to half of the full-scale range is sampled. In this combination, the gain setting is forced to be the gain of 1. SIGMA-DELTA MODULATOR The AD1555 sigma-delta modulator achieves its high level of performance, notably in dynamic range and distortion, through the use of a switched-capacitor feedback DAC in an otherwise continuous-time design. Novel circuitry eliminates the subtle distortion normally encountered when these disparate types are connected together. As a result, the AD1555 enjoys many of the benefits of both design techniques. When the signal input is selected, S1(+) and S1(–) are closed, all the other switches are opened, and the differential input signal between AIN(+) and AIN(–) is sampled. This is the main path for signal acquisition. When the test input is selected, S2(+) and S2(–) are closed, all the other switches are opened, and the differential input signal between TIN(+) and TIN(–) is sampled. This combination allows acquisition of a test signal or a secondary channel with the same level of performance as with AIN inputs. By applying known voltages to these inputs, it is also possible to calibrate the gain for each gain setting. When the Sensor Test 1 is selected, S1(+), S1(–), S2(+), and S2(–) are closed, all the other switches are opened, and the gain setting is forced to be the gain of 1. In this configuration, a source between TIN(+) and TIN(–) may be applied to the sensor to determine its impedance or other characteristics. The total internal serial resistance between each AIN input and the PGA inputs, nominally 66 Ω, slightly affects these measurements. The total internal serial resistance between each TIN input and the PGA inputs is nominally 116 Ω. When the Sensor Test 2 is selected, S1(+), S2(+), and S2(–) are closed, all the other switches are opened. This configuration could be used to test the sensor isolation. Power-Down Modes of the AD1555 The AD1555 has two power-down modes. The multiplexer and programmable gain amplifier can be powered down by the CB2–CB0 setting of “101.” The entire chip is powered down by either CB2–CB1 set to “11” or by keeping the clock input MCLK at a fixed level high or low. Less shutdown current flows with MCLK low. The least power dissipation is achieved when the external reference is shut down eliminating the current through the 30 kΩ nominal load at REFIN. When in power-down, the multiplexer is switched to the “ground input.” DAC FS RIN 20k MODIN LOOP FILTER Because of the switched-capacitor feedback, this modulator is much less sensitive to timing jitter than is the usual continuoustime design that relies on the duty cycle of the clock to control a switched-current feedback DAC. Unlike its fully switched-capacitor counterparts, the modulator input circuitry is nonsampling, consisting simply of an internal, low temperature coefficient resistor connected to the summing node of the input integrator. Among the advantages of this continuous-time architecture is a relaxation of requirements for the antialias filter; in fact, the output of the programmable gain amplifier, PGAOUT, may be tied directly to the input of the modulator MODIN without any external filter. Another advantage is that the gain may be adjusted to accommodate a higher input range by adding an external series resistor at MODIN. The modulator of the AD1555 is fourth order, which very efficiently shapes the quantization noise so that it is pushed toward the higher frequencies (above 1 kHz) as shown in TPC 3. This high frequency noise is attenuated by the AD1556 digital filter. However, when the output word rate (OWR) of the AD1556 is higher than 4 kHz (–3 dB frequency is higher than 1634 Hz), the efficiency of this filtering is limited and slightly reduces the dynamic range, as shown in the Table I. Hence, when possible, an OWR of 2 kHz or lower is generally preferred. Sigma-delta modulators have the potential to generate idle tones that occur for dc inputs close to ground. To prevent this undesirable effect, the AD1555 modulator offset is set to about –60 mV. In this manner, any existing idle tones are moved out of the band of interest and filtered out by the digital filter. Also, sigma-delta modulators may oscillate when the analog input is overranged. To avoid any instability, the modulator of the AD1555 includes circuitry to detect a string of 16 identical bits (“0” or “1”). Upon this event, the modulator is reset by discharging the integrator and loop filter capacitors and MFLG is forced high. After 1.5 MCLK cycles, MFLG returns low. MDATA INTEGRATOR COMPARATOR Figure 9. Sigma-Delta Modulator Block Diagram –18– REV. B AD1555/AD1556 DIGITAL FILTERING The AD1556 is a digital finite impulse response (FIR) linear phase low pass filter and serves as the decimation filter for the AD1555. It takes the output bitstream of the AD1555, filters and decimates it by a user-selectable choice of seven different filters associated with seven decimation ratios, in power of 2 from 1/16 to 1/1024. With a nominal bit rate of 256 kbits/s at the AD1556 input, the output word rate (the inverse of the sampling rate) ranges from 16 kHz (1/16 ms) to 250 Hz (4 ms) in powers of 2. The AD1556 filter achieves a maximum pass band flatness of ± 0.05 dB for each decimation ratio and an out-ofband attenuation of –135 dB maximum for each decimation ratio except 1/16 (OWR = 16 kHz) at which the out-of-band attenuation is –86 dB maximum. Table II gives for each filter the pass band frequency, the –3 dB frequency, the stop-band frequency, and the group delay. The pass band frequency is 37.5% of the output word rate, and the –3 dB frequency is approximately 41% of the output word rate. The noise generated by the AD1556, even that due to the word truncation, has a negligible impact on the dynamic range performance of the AD1555/AD1556 chipset. Although dedicated to the AD1555, the AD1556 can also be used as a very efficient and low power, low pass, digital filter of a bitstream generated by other ⌺-⌬ modulators. Architecture The functional block diagram of the filter portion of the AD1556 is given in Figure 10. The basic architecture is a two-stage filter. The second stage has a decimation ratio of 4 for all filters except at the output word rate of 250 Hz, where the decimation ratio is 8. Each filter is a linear phase equiripple FIR implemented by summing symmetrical pairs of data samples and then convoluting by multiplication and accumulation. The input bitstream at 256 kHz enters the first filter and is multiplied by the 26-bit wide coefficients tallied in Table IV. Due to the symmetry of the filter, only half of the coefficients are stored in the internal ROM and each is used twice per convolution. Because the multiplication uses a 1-bit input data, the convolution for the first stage is implemented with a single accumulator 29-bits wide to avoid any truncation in the accumulation process. The output of the first-stage filter is decimated with the ratios given in Table IV and then are stored in an internal RAM which truncates the accumulator result to 24 bits. The second-stage filter architecture is similar to the first stage. The main difference is the use of a true multiplier. The multiplier, the accumulator, and the output register, which are respectively 32-bits, 35-bits and 24-bits wide, introduce some truncation that does not affect the overall dynamic performance of the AD1555/AD1556 chipset. Filter Coefficients As indicated before, each stage for each filter uses a different set of coefficients. These coefficients are provided with the EVAL-AD1555/AD1556EB, the evaluation board for the AD1555 and the AD1556. FIRST-STAGE FILTER INPUT DATA STORAGE 1 MODULATOR BITSTREAM 1-BIT WIDE AT 256kbits/s SECOND-STAGE FILTER FIRST-STAGE FILTER 29-BIT ACCUMULATOR 24 SECOND-STAGE FILTER INPUT DATA STORAGE 24 32 MULTIPLIER 35-BIT ACCUMULATOR 24 RAM 364 BY 24 BITS RAM 1024 BY 1 BIT 26 26 FIRST-STAGE FILTER COEFFICIENTS SECOND-STAGE FILTER INPUT COEFFICIENTS ROM 1008 BY 26 BITS ROM 333 BY 26 BITS Figure 10. AD1556 Filter Functional Block Diagram Table IV. Filter Definition Output Word Rate FO (Hz) (Sampling Rate [ms]) Decimation Ratio First Stage Second Stage Number of Coefficients First Stage Second Stage 16000 [1/16 ms] 8000 [1/8 ms] 4000 [1/4 ms] 2000 [1/2 ms] 1000 [1 ms] 500 [2 ms] 250 [4 ms] 4 8 16 32 64 128 128 32 64 128 256 512 1024 1024 REV. B 4 4 4 4 4 4 8 –19– 118 184 184 184 184 184 364 AD1555/AD1556 RESET Operation Configuring and Interfacing the AD1556 The RESET pin initializes the AD1556 in a known state. RESET is active on the next CLKIN rising edge after the RESET input is brought high as shown in Figure 4. The reset value of each bit of the configuration and the status registers are indicated in Table V and Table VIII. The filter memories are not cleared by the reset. Filter convolutions begin on the next CLKIN rising edge after the RESET input is returned low. A RESET operation is done on power-up, independent of the RESET pin state. The AD1556 configuration can be loaded either by hardware (H/S pin high) or via the serial interface of the AD1556 (H/S pin low). To operate with the AD1556, the CLKIN clock must be kept running at the nominal frequency of 1.024 MHz. Table V gives the description of each bit of the configuration register and Table VI defines the selection of the filter bandwidth. When the software mode is selected (H/S pin low), the configuration register is loaded using the pins DIN, SCLK, CS, and R/W. In this mode, when RESET is active, the configuration register mimics the selection of the hardware pins. The AD1556 and the AD1555 can be put in power-down by software. In multiple ADCs applications where absolute synchronization—even below the noise floor—is required, RESETD, which resets the decimator, can be tied to RESET to ensure this synchronization. The DRDYBUF bit controls the operating mode of the DRDY output pin. When the DRDYBUF bit is low, the DRDY is a conventional CMOS push-pull output buffer as shown in Figure 11. When the DRDYBUF bit is high, the DRDY output pin is an open drain PMOS pull-up as shown in Figure 11. Many DRDY pins may be connected with an external pull-down resistor in a wired OR to minimize the interconnection between the AD1556s and the microprocessor in multichannel applications. The DRDY pin is protected against bit contention. Power-Down Operation The PWRDN pin puts the AD1556 in a power-down state. PWRDN is active on the next CLKIN rising edge after the PWRDN input is brought high. While in this state, MCLK is held at a fixed level and the AD1555 is therefore powered down too. The serial interface remains active allowing read and write operations of the AD1556. The configuration and status registers maintain their content during the power-down state. SYNC Operation SYNC is used to create a relationship between the analog input signal and the output samples of the AD1556. The SYNC event does two things: • It synchronizes the AD1555 clock, MCLK, to the AD1556 clock, CLKIN, as shown in Figure 3. • It clears the filter and then initiates the filter convolution. Exactly one sampling rate delay later, the DRDY pin goes high. A SYNC event occurs on the next CLKIN rising edge after the SYNC input is brought high as shown in Figure 3. The DRDY output goes high on the next falling edge of CLKIN. SYNC may be applied once or kept high, or applied synchronously at the output word rate, all with the same effect. By connecting DRDY to RSEL directly, and applying 48 SCLK cycles, both data and status can be read sequentially, data register first. Table VI. Filter Bandwidth Selection BW2 BW1 BW0 Output Rate (ms) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 4 2 1 1/2 1/4 1/8 1/16 Reserved Table V. Configuration Register Data Bits Bit Number Name DB15 (MSB) DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (LSB) X X X X PWRDN CSEL X BW2 BW1 BW0 DRDYBUF CB4 CB3 CB2 CB1 CB0 Description Power-Down Mode Select TDATA Input Filter Bandwidth Selection Filter Bandwidth Selection Filter Bandwidth Selection DRDY Output Mode PGA Input Select PGA Input Select PGA Gain Select PGA Gain Select PGA Gain Select –20– RESET State X X X X PWRDN CSEL X BW2 BW1 BW0 0 (Push-Pull) PGA4 PGA3 PGA2 PGA1 PGA0 REV. B AD1555/AD1556 DRDYBUF = 0 DRDYBUF = 1 VL VL TO OTHER AD1556s TO THE MICROPROCESSOR DRDY AD1556 DRDY AD1556 TO THE MICROPROCESSOR VL DGND DRDY AD1556 DGND Figure 11. DRDY Output Pin Configuration When operating with a nominal MCLK frequency of 256 kHz, the AD1555 is designed to output a ones-density bitstream from 0.166 to 0.834 on its MDATA output pin corresponding to an input voltage from –2.25 V to +2.25 V on the MODIN pin. The AD1556 computes a 24-bit two’s complement output whose codes range from decimal –6,291,456 to +6,291,455 as shown in Table VII. Table VII. Output Coding Analog Input MODIN Hexa Decimal ~ ~ ~ ~ ~ ~ ~ 5FFFFF 558105 4C00E8 000000 B3FF17 AA7EFA A00000 +6291455 +5603589 +4980968 0 –4980969 –5603590 –6291456 Output Code *Input out of range. STATUS Register The AD1556 status register contains 24 bits that capture potential error conditions and readback the configuration settings. The status register mapping is defined in Table VIII. The ERROR bit is the logical OR of the other error bits, OVWR, MFLG, and ACC. ERROR and the other error bits are reset low after completing a status register read operation or upon RESET. The ERROR bit is the inverse of the ERROR output pin. The OVWR bit indicates if an unread conversion result is overwritten in the output data register. If a data read was started but not completed when new data is loaded into the output data register, the OVWR bit is set high. The MFLG status bit is set to the state of the MFLG input pin on the rising edge of CLKIN. MFLG will remain set high as long as the MFLG bit is set. The MFLG status bit will not change during power-down or RESET. REV. B The FLSTL bit indicates the digital filter has settled and the conversion results are an accurate representation of the analog input. FLSTL is set low on RESET, at power-up, and upon exiting the power-down state. FLSTL also goes low when SYNC sets the start of the filter’s convolution cycle, when changes are made to the device setting with the hardware pins CB0–CB4, BW0–BW2, or CSEL, and when the MFLG status bit is set high. When FLSTL is low the OVWR, MFLG, ACC, and DRNG status bits will not change. The DRNG bit is used to indicate if the analog input to the AD1555 is outside its specified operating range. The DRNG bit is set high whenever the AD1556 digital filter computes four consecutive output samples that are greater than decimal +6,291455 or all less than –6,291456. Layout Analog Input and Digital Output Data Format +2.526 V* +2.25 V +2 V 0V –2 V –2.25 V –2.526 V* The ACC bit is set high and the data output is clipped to either +FS (0111 . . . ) or –FS (1000 . . . ) if an underflow or overflow has occurred in the digital filter. The AD1555 has very good immunity to noise on the power supplies. However, care should still be taken with regard to grounding layout. The printed circuit board that houses the AD1555 and the AD1556 should be designed so the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. Digital and analog ground planes should be joined in only one place, preferably underneath the AD1555, or at least as close as possible to the AD1555. If the AD1555 is in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at one point only, a star ground point, which should be established as close as possible to the AD1555. It is recommended to avoid running digital lines under the device since these will couple noise onto the die. The analog ground plane should be allowed to run under the AD1555 to avoid noise coupling. Fast switching signals such as MDATA and MCLK should be shielded with digital ground to avoid radiating noise to other sections of the board and should never run near analog signal paths. Crossover of digital and analog signals should be avoided. Traces on different but close layers of the board should run at right angles to each other. This will reduce the effect of feedthrough through the board. The power supply lines to the AD1555 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Good decoupling is also important to lower the supplies impedance resent to the AD1555 and reduce the magnitude of the supply spikes. Decoupling ceramic capacitors, typically 100 nF, should be placed on power supply pins +VA, –VA, and VL close to, and ideally right up against these pins and their corresponding ground pins. Additionally, low ESR 10 µF capacitors should be located in the vicinity of the ADC to further reduce low frequency ripple. The VL supply of the AD1555 can either be a separate supply or come from the analog supply VA. When the system digital supply is noisy, or fast switching digital signals are present, it is recommended, if no separate supply is available, to connect the VL digital supply to the analog supply VA through an RC filter as shown in Figure 7. –21– AD1555/AD1556 Table VIII. Status Register Data Bits Bit Number Name Description RESET State DB23 (MSB) DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (LSB) ERROR OVWR MFLG X ACC DRDY FLSTL DRNG X X X X PWRDN CSEL X BW2 BW1 BW0 X CB4 CB3 CB2 CB1 CB0 Detects One of the Following Errors Read Sequence Overwrite Error Modulator Flag Error 0 0 MFLG X 0 0 0 0 X X X X PWRDN CSEL X BW2 BW1 BW0 X PGA4 PGA3 PGA2 PGA1 PGA0 Accumulator Error Data Ready Filter Settled Output Data Not within AD1555 Range Power-Down Mode Select TDATA Input Filter Bandwidth Selection Filter Bandwidth Selection Filter Bandwidth Selection PGA Input Select PGA Input Select PGA Gain Select PGA Gain Select PGA Gain Select The AD1555 has three different ground pins: AGND1, AGND2, and AGND3 plane, depending on the configuration. AGND1 should be a star point and be connected to the analog ground point. AGND2 should be directly tied to AGND1. A low impedance trace should connect in the following order: AGND3, the low side of the reference decoupling capacitor on REFCAP1, the ground of the reference voltage, and return to AGND1. Evaluating the AD1555/AD1556 Performance Performances of the AD1555/AD1556 can be evaluated with the evaluation board EVAL-AD1555/AD1556EB. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the PC printer port. –22– REV. B AD1555/AD1556 OUTLINE DIMENSIONS Dimensions shown in inches and (mm) 28-Lead PLCC (P-28A) 0.180 (4.57) 0.165 (4.19) 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 0.056 (1.42) 0.042 (1.07) 4 5 26 25 PIN 1 IDENTIFIER 11 12 0.021 (0.53) 0.013 (0.33) 0.050 (1.27) BSC TOP VIEW (PINS DOWN) 0.020 (0.50) R 0.025 (0.63) 0.015 (0.38) 0.032 (0.81) 0.026 (0.66) 19 18 0.430 (10.92) 0.390 (9.91) 0.040 (1.01) 0.025 (0.64) 0.456 (11.58) SQ 0.450 (11.43) 0.495 (12.57) SQ 0.485 (12.32) 0.110 (2.79) 0.085 (2.16) 44-Lead MQFP (S-44A) 0.530 (13.45) SQ 0.510 (12.95) 0.398 (10.10) SQ 0.390 (9.90) 0.096 (2.45) MAX 0.041 (1.03) 0.029 (0.73) 44 34 1 33 SEATING PLANE 0.315 (8.00) REF TOP VIEW (PINS DOWN) 0.010 (0.25) MAX 0.009 (0.23) 0.005 (0.13) 0.083 (2.10) 0.077 (1.95) REV. B 11 23 22 12 0.031 (0.80) BSC –23– 0.018 (0.45) 0.012 (0.30) –24– PRINTED IN U.S.A. C02053–0–5/02(B)