AD1819

a AC’97 FEATURES Fully Compliant AC’97 Analog I/O Component 48-Terminal LQFP Package Multibit Converter Architecture for Improved S/N Ratio >90 dB 16-Bit Stereo Full-Duplex Codec Four Analog Line-Level Stereo Inputs for Connection from LINE, CD, VIDEO, and AUX Two Analog Line-Level Mono Inputs for Speakerphone and PC BEEP Mono MIC Input Switchable from Two External Sources High Quality CD Input with Ground Sense Stereo Line Level Output Mono Output for Speakerphone Power Management Support AC’97 SoundPort® Codec AD1819B ENHANCED FEATURES Support for Multiple Codec Communications DSP 16-Bit Serial Port Format Variable 7 kHz to 48 kHz Sampling Rate with 1 Hz Resolution Supports Modem Sample Rates and Filtering Phat™ Stereo 3D Stereo Enhancement VHDL and Verilog Models of Serial Port Available FUNCTIONAL BLOCK DIAGRAM CS0 CS1 CHAIN_IN CHAIN_CLK AD1819B MIC1 MIC2 LINE_IN AUX CD VIDEO PHONE_IN SYNC AC LINK 0dB/ 20dB MASTER/SLAVE SYNCHRONIZER PGA SELECTOR 16-BIT A/D CONVERTER PGA 16-BIT A/D CONVERTER RESET G A M G A M G A M G A M G A M G A M G A M SAMPLE RATE GENERATORS BIT_CLK SDATA_OUT LINE_OUT_L MONO_OUT LINE_OUT_R MV MV MV A M PHAT STEREO 16-BIT D/A CONVERTER SDATA_IN PHAT STEREO G = GAIN A = ATTENUATE M = MUTE MV = MASTER VOLUME G A M 16-BIT D/A CONVERTER OSCILLATORS PC_BEEP XTALO XTALI SoundPort is a registered trademark of Analog Devices, Inc. Phat is a trademark of Analog Devices, Inc. R EV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 AD1819B PRODUCT OVERVIEW The AD1819B SoundPort Codec is designed to meet all requirements of the Audio Codec ’97, Component Specification, Revision 1.03, © 1996, Intel Corporation, found at www.Intel.com. In addition, the AD1819B supports multiple codec configurations (up to three per AC-Link), a DSP serial mode, variable sample rates, modem sample rates and filtering, and built-in Phat Stereo 3D enhancement. The AD1819B is an analog front end for high performance PC audio, modem, or DSP applications. The AC’97 architecture defines a 2-chip audio solution comprising a digital audio controller, plus a high quality analog component that includes Digital-to-Analog Converters (DACs), Analog-to-Digital Converters (ADCs) mixer and I/O. The main architectural features of the AD1819B are the high quality analog mixer section, two channels of Σ∆ ADC conversion, two channels of Σ∆ DAC conversion and Data Direct Scrambling (D2S) rate generators. The AD1819B’s left channel ADC and DAC are compatible for modem applications supporting irrational sample rates and modem filtering requirements. FUNCTIONAL DESCRIPTION Each channel of the ADC is independent, and can process left and right channel data at different sample rates. All programmed sample rates from 7 kHz to 48 kHz have a resolution of 1 Hz. The AD1819B also supports irrational V.34 sample rates. Sample Rates and D2S The AD1819B default mode sets the codec to operate at 48 kHz sample rates. The converter pairs may process left and right channel data at different sample rates. The AD1819B sample rate generator allows the codec to instantaneously change and process sample rates from 7 kHz to 48 kHz with a resolution of 1 Hz. The in-band integrated noise and distortion artifacts introduced by rate conversions are below –90 dB. The AD1819B uses a 4-bit D/A structure and Data Directed Scrambling (D2S) to enhance noise immunity on motherboards and in PC enclosures, and to suppress idle tones below the device’s quantization noise floor. The D2S process pushes noise and distortion artifacts caused by errors in the multibit D/A conversion process to frequencies beyond the audible range of the human ear and then filters them. Digital-to-Analog Signal Path This section overviews the functionality of the AD1819B and is intended as a general introduction to the capabilities of the device. Detailed reference information may be found in the descriptions of the Indexed Control Registers. The codec contains a stereo pair of Σ∆ ADCs. Inputs to the ADC may be selected from the following analog signals: telephony (PHONE_IN), mono microphone (MIC1 or MIC2), stereo line (LINE_IN), auxiliary line input (AUX), stereo CD ROM (CD), stereo audio from a video source (VIDEO) and post-mixed stereo or mono line output (LINE_OUT). Analog Mixing Analog Inputs The analog output of the DAC may be gained or attenuated from +12 dB to –34.5 dB in 1.5 dB steps, and summed with any of the analog input signals. The summed analog signal enters the Master Volume stage where each channel of the mixer output may be attenuated from 0 dB to –46.5 dB in 1.5 dB steps or muted. Host-Based Echo Cancellation Support The AD1819B supports time correlated I/O data format by presenting mic data on the left channel of the ADC and the mono summation of left and right output on the right channel. The ADC is splittable; left and right ADC data can be sampled at different rates. Telephony Modem Support PHONE_IN, MIC1 or MIC2, LINE_IN, AUX, CD and VIDEO can be mixed in the analog domain with the stereo output from the DACs. Each channel of the stereo analog inputs may be independently gained or attenuated from +12 dB to –34.5 dB in 1.5 dB steps. The summing path for the mono inputs (PHONE_IN, MIC1, and MIC2 to LINE_OUT) duplicates mono channel data on both the left and right LINE_OUT. Additionally, the PC attention signal (PC_BEEP) may be mixed with the line output. A switch allows the output of the DACs to bypass the Phat Stereo 3D enhancement. Analog-to-Digital Signal Path The AD1819B contains a V.34-capable analog front end for supporting host-based and data pump modems. The modem DAC typical dynamic range is 90 dB over a 4.2 kHz analog output passband where FS = 12.8 kHz. The left channel of the ADC and DAC may be used to convert modem data at the same sample rate in the range between 7 kHz and 48 kHz. All programmed sample rates have a resolution of 1 Hz. The AD1819B supports irrational V.34 sample rates with 8/7 and 10/7 selectable sample rate multiplier coefficients. Differences Between the AD1819A and AD1819B The selector sends left and right channel signals to the programmable gain amplifier (PGA). The PGA following the selector allows independent gain for each channel entering the ADC from 0 dB to +22.5 dB in 1.5 dB steps. The voltage reference (VREF) of the AD1819B remains active while RESET is asserted. This eliminates the audible artifacts associated with the RESET LO to HI transitions that can occur during a Windows boot (power-up) or Windows warm restart (reset). –2– REV. 0 SPECIFICATIONS STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED AD1819B 25 5.0 5.0 48 1008 20 Hz to 20 kHz 2.0 0.8 4.0 1.0 °C V V kHz Hz V V V V DAC Test Conditions Calibrated 0 dB Attenuation Input 0 dB 10 kΩ Output Load Mute Off ADC Test Conditions Calibrated 0 dB Gain Input –3 dB Relative to Full Scale Line Input Selected Min Typ 1 2.83 0.1 0.283 1 2.83 10 15 Max Units V rms V p-p V rms V p-p V rms V p-p kΩ pF Temperature Digital Supply (VDD) Analog Supply (VCC) Sample Rate (FS) Input Signal Analog Output Passband VIH (AC-Link) VIL (AC-Link) VIH (CS0, CS1, CHAIN_IN) VIL (CHAIN_CLK) ANALOG INPUT Parameter Input Voltage (RMS Values Assume Sine Wave Input) LINE_IN, AUX, CD, VIDEO, PHONE_IN, PC_BEEP MIC1, MIC2 with +20 dB Gain (M20 = 1) MIC1, MIC2 with 0 dB Gain (M20 = 0) Input Impedance* Input Capacitance* PROGRAMMABLE GAIN AMPLIFIER—ADC Parameter Step Size (0 dB to 22.5 dB) PGA Gain Range Span ANALOG MIXER— INPUT GAIN/AMPLIFIERS/ATTENUATORS Min Typ 1.5 22.5 Max Units dB dB Parameter Min Typ Max Units dB dB dB dB dB dB Dynamic Range (–60 dB Input THD+N, Referenced to Full Scale, A-Weighted) CD to LINE_OUT 90 Other to LINE_OUT* Step Size (+12 dB to –34.5 dB): (All Steps Tested) MIC, LINE_IN, AUX, CD, VIDEO, PHONE_IN, DAC Input Gain/Attenuation Range MIC, LINE_IN, AUX, CD, VIDEO, PHONE_IN, DAC Step Size (0 dB to –45 dB): (All Steps Tested) PC_BEEP Input Gain/Attenuation Range: PC_BEEP DIGITAL DECIMATION AND INTERPOLATION FILTERS* 90 1.5 46.5 3.0 45 Parameter Passband Passband Ripple Transition Band Stopband Stopband Rejection Group Delay Group Delay Variation Over Passband *Guaranteed, not tested. Specifications subject to change without notice. Min 0 0.4 × FS 0.6 × FS –74 Typ Max 0.4 × FS ± 0.09 0.6 × FS Units Hz dB Hz Hz dB sec µs ∞ 12/FS 0.0 REV. 0 – 3– AD1819B–SPECIFICATIONS ANALOG-TO-DIGITAL CONVERTERS Parameter Resolution Total Harmonic Distortion (THD) Dynamic Range (–60 dB Input THD+N Referenced to Full Scale, A-Weighted) Signal-to-Intermodulation Distortion* (CCIF Method) ADC Crosstalk* Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) Line to Other Gain Error (Full-Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) ADC Offset Error DIGITAL-TO-ANALOG CONVERTERS Min Typ 16 Max 0.02 –74 Units Bits % dB dB dB 84 87 85 –100 –90 –90 –85 ± 10 ± 0.5 ±5 dB dB % dB mV Parameter Resolution Total Harmonic Distortion (THD) LINE_OUT Dynamic Range (–60 dB Input THD+N Referenced to Full Scale, A-Weighted) Signal-to-Intermodulation Distortion* (CCIF Method) Gain Error (Full-Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) DAC Crosstalk* (Input L, Zero R, Measure LINE_OUT_R; Input R, Zero L, Measure LINE_OUT_L) Total Out-of-Band Energy (Measured from 0.6 × FS to 20 kHz)* MASTER VOLUME Min Typ 16 Max 0.02 –74 Units Bits % dB dB dB % dB dB dB dB 85 90 85 ± 10 ± 0.5 –80 –40 Parameter Step Size (0 dB to –46.5 dB) LINE_OUT_L, LINE_OUT_R, MONO_OUT Output Attenuation Range Span Mute Attenuation of 0 dB Fundamental* ANALOG OUTPUT Min Typ 1.5 46.5 Max Units dB dB dB 75 Parameter Full-Scale Output Voltage Output Impedance* External Load Impedance Output Capacitance* External Load Capacitance VREF VREF Current Drive VREFOUT VREFOUT Current Drive Mute Click (Muted Output Minus Unmuted Midscale DAC Output)* *Guaranteed, not tested. Specifications subject to change without notice. Min Typ 1 2.83 Max Units V rms V p-p Ω kΩ pF pF V µA V mA mV 800 10 15 2.00 2.25 2.25 ±5 5 100 2.50 100 – 4– REV. 0 AD1819B STATIC DIGITAL SPECIFICATIONS Parameter High-Level Input Voltage (VIH): Digital Inputs Low-Level Input Voltage (VIL) High-Level Output Voltage (VOH), IOH = 2 mA Low-Level Output Voltage (VOL), IOL = 2 mA Input Leakage Current Output Leakage Current POWER SUPPLY Min 0.4 × DVDD 0.5 × DVDD –10 –10 Typ Max 0.2 × DVDD 0.2 × DVDD 10 10 Units V V V V µA µA Parameter Power Supply Range—Analog Power Supply Range—Digital Power Supply Current Power Dissipation Analog Supply Current Digital Supply Current Power Supply Rejection (100 mV p-p Signal @ 1 kHz)* (At Both Analog and Digital Supply Pins, Both ADCs and DACs) CLOCK SPECIFICATIONS* Min 4.5 4.5 Typ Max 5.5 5.5 Units V V mA mW mA mA dB 120 600 60 60 –40 Parameter Input Clock Frequency Recommended Clock Duty Cycle POWER-DOWN STATES Min 40 Typ 24.576 50 Max 60 Units MHz % Parameter ADCs and Input Mux Power-Down DACs Power-Down Analog Mixer Power-Down (VREF and VREFOUT On) Analog Mixer Power-Down (VREF and VREFOUT Off) Digital Interface Power-Down* Internal Clocks Disabled* ADC and DAC Power-Down VREF Standby Mode* Total Power-Down RESET (Low) *Guaranteed, not tested. Specifications subject to change without notice. Set Bits PR0 PR1 PR1, PR2 PR0, PR1, PR3 PR4 PR0, PR1, PR4, PR5 PR0, PR1 PR0, PR1, PR2, PR4, PR5 PR0, PR1, PR2, PR3, PR4, PR5 Min Typ 110 100 54 47 120 85 85 55 220 250 Max Units mA mA mA mA mA mA mA mA µA µA REV. 0 –5– AD1819B TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE) Parameter RESET Active Low Pulsewidth RESET Inactive to BIT_CLK Start-Up Delay SYNC Active High Pulsewidth SYNC Low Pulsewidth SYNC Inactive to BIT_CLK Start-Up Delay BIT_CLK Frequency BIT_CLK Period BIT_CLK Output Jitter* BIT_CLK High Pulsewidth BIT_CLK Low Pulsewidth SYNC Frequency SYNC Period Setup to Falling Edge of BIT_CLK Hold from Falling Edge of BIT_CLK BIT_CLK Rise Time BIT_CLK Fall Time SYNC Rise Time SYNC Fall Time SDATA_IN Rise Time SDATA_IN Fall Time SDATA_OUT Rise Time SDATA_OUT Fall Time End of Slot 2 to BIT_CLK, SDATA_IN Low Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT) Rising Edge of RESET to HI-Z Delay *Output Jitter is directly dependent on crystal input jitter. Symbol tRST_LOW tRST2CLK tSYNC_HIGH tSYNC_LOW tSYNC2CLK tCLK_PERIOD tCLK_HIGH tCLK_LOW tSYNC_PERIOD tSETUP tHOLD tRISE CLK tFALL CLK tRISE SYNC tFALL SYNC tRISE DIN tFALL DIN tRISE DOUT tFALL DOUT tS2_PDOWN tSETUP2RST tOFF Min 1.0 162.8 0.0814 162.8 Typ Max Units µs ns µs µs ns MHz ns ps ns ns kHz µs ns ns ns ns ns ns ns ns ns ns µs ns ns 1.3 19.5 12.288 81.4 32.56 32.56 40.7 40.7 48.0 20.8 750 48.84 48.84 15.0 15.0 4 4 4 4 4 4 4 4 1.0 15 25 tRST_LOW RESET tRST2CLK BIT_CLK Figure 1. Cold Reset tSYNC_HIGH SYNC BIT_CLK tRST2CLK Figure 2. Warm Reset tCLK_LOW BIT_CLK tCLK_HIGH tCLK_PERIOD tSYNC_LOW SYNC tSYNC_HIGH tSYNC_PERIOD Figure 3. Clock Timing –6– REV. 0 AD1819B tSETUP SYNC BIT_CLK SYNC SDATA_OUT BIT_CLK SLOT 1 SLOT 2 SDATA_OUT WRITE TO 0x26 DATA PR4 DON’T CARE tHOLD tS2_PDOWN SDATA_IN NOTE: BIT_CLK NOT TO SCALE Figure 4. Data Setup and Hold BIT_CLK Figure 6. AC-Link, Link Low Power Mode Timing tRISECLK tFALLCLK RESET SYNC tRISESYNC SDATA_IN tFALLSYNC SDATA_OUT tSETUP2RST SDATA_IN, BIT_CLK HI-Z tRISEDIN SDATA_OUT tFALLDIN tOFF Figure 7. ATE Test Mode tFALLDOUT tRISEDOUT Figure 5. Signal Rise and Fall Time ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE Parameter Power Supplies Analog (AVDD) Digital (DVDD) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Ambient Temperature (Operating) Storage Temperature Min –0.3 –0.3 –0.3 –0.3 –40 –65 Max 6.0 6.0 ± 10.0 AVDD + 0.3 DVDD + 0.3 +85 +150 Units Model V V mA V V °C °C Temperature Range Package Description Package Option* AD1819BJST –40°C to +85° C 48-Terminal LQFP ST-48 *ST = Thin Quad Flatpack. ENVIRONMENTAL CONDITIONS *Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Ambient Temperature Rating TAMB = TCASE – (P D × θCA) TCASE = Case Temperature in °C PD = Power Dissipation in W θCA = Thermal Resistance (Case-to-Ambient) θJA = Thermal Resistance (Junction-to-Ambient) θJC = Thermal Resistance (Junction-to-Case) Package LQFP JA JC CA 76.2°C/W 17°C/W 59.2°C/W CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1819B features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. 0 –7– AD1819B PIN CONFIGURATION 48-Terminal LQFP (ST-48) CHAIN_CLK MONO_OUT CHAIN_IN AVSS2 48 47 46 45 44 43 42 41 40 39 38 37 DVDD1 1 XTL_IN 2 XTL_OUT 3 DVSS1 4 SDATA_OUT 5 BIT_CLK 6 DVSS2 7 SDATA_IN 8 DVDD2 9 SYNC 10 RESET 11 PC_BEEP 12 13 14 15 16 17 18 19 20 21 22 23 24 PIN 1 IDENTIFIER NC AVDD2 CS1 CS0 NC NC NC NC 36 35 34 33 LINE_OUT_R LINE_OUT_L CX3D RX3D FILT_L FILT_R AFILT2 AFILT1 AD1819B TOP VIEW (Not to Scale) 32 31 30 29 28 VREFOUT 27 VREF 26 25 AVSS1 AVDD1 PHONE_IN AUX_L AUX_R MIC1 VIDEO_R CD_L VIDEO_L CD_GND CD_R MIC2 LINE_IN_L NC = NO CONNECT PIN FUNCTION DESCRIPTIONS Digital I/O Pin Name XTL_IN XTL_OUT SDATA_OUT BIT_CLK SDATA_IN SYNC RESET LQFP 2 3 5 6 8 10 11 I/O I O I O/I* O I I Description 24.576 MHz Crystal or Clock Input 24.576 MHz Crystal Output Serial Data Output. Serial, Time Division Multiplexed, AD1819B Input Stream Bit Clock Input, 12.288 MHz Serial Data Clock. Daisy Chain Output Clock Serial Data Input. Serial, Time Division Multiplexed, AD1819B Output Stream 48 kHz Fixed Rate Sample Sync Clock Reset. AC-Link Master Hardware Reset *Input if the AD1819B is configured as Slave 1 or Slave 2. Daisy Chain Connections Pin Name CS0 CS1 CHAIN_IN CHAIN_CLK LQFP 45 46 47 48 I/O I I I I/O* Description Daisy Chain Codec Select Daisy Chain Codec Select Daisy Chain Data Input 24.576 MHz Buffered Clock Input/Output *Output when configured as Master. Input when configured as Slave 1 or Slave 2. LINE_IN_R –8– REV. 0 AD1819B Analog I/O These signals connect the AD1819B component to analog sources and sinks, including microphones and speakers. Pin Name PC_BEEP PHONE_IN AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND CD_R MIC1 MIC2 LINE_IN_L LINE_IN_R LINE_OUT_L LINE_OUT_R MONO_OUT Filter/Reference LQFP 12 13 14 15 16 17 18 19 20 21 22 23 24 35 36 37 I/O I I I I I I I I I I I I I O O O Description PC Beep. PC Speaker Beep Pass-Through Phone. From Telephony Subsystem Speakerphone or Handset Auxiliary Input Left Channel Auxiliary Input Right Channel Video Audio Left Channel Video Audio Right Channel CD Audio Left Channel CD Audio Analog Ground Sense for Differential CD Input CD Audio Right Channel Microphone 1. Desktop Microphone Input Microphone 2. Second Microphone Input Line In Left Channel Line In Right Channel Line Out Left Channel Line Out Right Channel Monaural Output to Telephony Subsystem Speakerphone Pin Name VREF VREFOUT AFILT1 AFILT2 FILT_R FILT_L RX3D CX3D LQFP 27 28 29 30 31 32 33 34 I/O O O O O O O O I Description Voltage Reference Filter Voltage Reference Output 5 mA Drive (Intended for Mic Bias) Antialiasing Filter Capacitor—ADC Right Channel Antialiasing Filter Capacitor—ADC Left Channel AC-Coupling Filter Capacitor—ADC Right Channel AC-Coupling Filter Capacitor—ADC Left Channel 3D Phat Stereo Enhancement—Capacitor 3D Phat Stereo Enhancement—Capacitor Power and Ground Signals Pin Name DVDD1 DVSS1 DVSS2 DVDD2 AVDD1 AVSS1 AVDD2 AVSS2 No Connects LQFP 1 4 7 9 25 26 38 42 I/O I I I I I I I I Description Digital VDD—5.0 V Digital GND Digital GND Digital VDD—5.0 V Analog VDD—5.0 V Analog GND Analog VDD—5.0 V Analog GND Pin Name NC NC NC NC NC LQFP 39 40 41 43 44 I/O Description No Connect No Connect No Connect No Connect No Connect REV. 0 –9– AD1819B MIC1 MS MIC2 0dB/20dB M20 0x0E 0x20 LS/RS (0) LS (4) RS (4) GM 0x1C LIM LS (3) IM RS (3) S E LS (1) L RS (1) E C LS (2) T RS (2) O GM 0x1C LS/RS (7) R RIM LS (5) IM LS/RS (6) RS (5) RESET LINE_IN AUX CD VIDEO PHONE_IN GM 0X1C LIM IM 16-BIT ADC STEREO MIX (L) MONO MIX STEREO MIX (R) GM 0X1C RIM IM 16-BIT ADC 0x1A SYNC GA 0x0C PHV M 0x0C PHM M 0x0E MCM M 0x10 LM M 0x16 AM M 0x12 CM M 0x14 VM GAM 0x18 LOV OM SDATA_IN 16-BIT DAC SR1 0x7A LPBK 0x20 GA 0x0E GA 0x10 MCV LLV RLA GA 0x16 LAV RAV GA 0x12 LCV RCV GA 0x14 LVV RVV SR0 0x78 AC LINK 0X74 BIT_CLK SDATA_OUT M 0x02 A 0x02 LMV A 0x06 MMV A 0x02 RMV 3D 0x22 DP LINE_OUT_L MM M 0x06 0 1 MIX 0x20 3D 0x22 DP MONO_OUT MMM M 0x02 0x20 POP GAM 0x18 ROV OM 16-BIT DAC LINE_OUT_R MM GA 0x0A PCV M 0x0A PC_BEEP PCM G = GAIN A = ATTENUATE M = MUTE MV = MASTER VOLUME AD1819B OSCILLATORS XTL_OUT XTL_IN Figure 8. Block Diagram Register Map –10– REV. 0 AD1819B Indexed Control Registers Reg Num 00h 02h 04h 06 h 08h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 1Eh 20h 22h 24h 26h 28h Name Reset Master Volume Reser ved Master Volume Mono Reser ved PC Beep Volume Phone Volume Mic Volume Line In Volume CD Volume Video Volume Aux Volume PCM Out Vol Record Select Record Gain Reser ved General Purpose 3D Control Reser ved Power-Down Contr/Stat Reser ved D15 X MM X MMM X PCM PHM MCM LM CVM VM AM OM X IM X POP X X X X D14 SE4 X X X X X X X X X X X X X X X X X X X X D13 SE3 LMV5 X X X X X X X X X X X X X X 3D X X PR5 X D12 SE2 LMV4 X X X X X X LLV4 LCV4 LVV4 LAV4 LOV4 X X X X X X PR4 X D11 SE1 LMV3 X X X X X X LLV3 LCV3 LVV3 LAV3 LOV3 X LIM3 X X X X PR3 X D10 SE0 LMV2 X X X X X X LLV2 LCV2 LVV2 LAV2 LOV2 LS2 LIM2 X X X X PR2 X D9 ID9 LMV1 X X X X X X LLV1 LCV1 LVV1 LAV1 LOV1 LS1 LIM1 X MIX X X PR1 X D8 ID8 LMV0 X X X X X X LLV0 LCV0 LVV0 LAV0 LOV0 LS0 LIM0 X MS X X PR0 X D7 ID7 X X X X X X X X X X X X X X X LPBK X X X X D6 ID6 X X X X X X M20 X X X X X X X X X X X X X D5 ID5 RMV5 X MMV5 X X X X X X X X X X X X X X X X X D4 ID4 RMV4 X MMV4 X PCV3 PHV4 MCV4 RLV4 RCV4 RVV4 RAV4 ROV4 X X X X X X X X D3 ID3 RMV3 X MMV2 X PCV2 PHV3 MCV3 RLV3 RCV3 RVV3 RAV3 ROV3 X RIM3 X X DP3 X REF X D2 ID2 RMV2 X MMV2 X PCV1 PHV2 MCV2 RLV2 RCV2 RVV2 RAV2 ROV2 RS2 RIM2 X X DP2 X ANL X D1 ID1 RMV1 X MMV1 X PCV0 PHV1 MCV1 RLV1 RCV1 RVV1 RAV1 ROV1 RS1 RIM1 X X DP1 X DAC X D0 ID0 RMV0 X MMV0 X X PHV0 MCV0 RLV0 RCV0 RVV0 RAV0 ROV0 RS0 RIM0 X X DP0 X ADC X Default 0400h 8000h X 8000h X 8000h 8008h 8008h 8808h 8808h 8808h 8808h 8808h 0000h 8000h X 0000h 0000h X 0000h X 72h 74 h Reser ved Serial Configuration X SLOT 16 X REGM 2 X REGM 1 X REGM 0 X DRQE N X DLRQ 2 X DLRQ 1 X DLRQ 0 X X X X X X X X X X X DRRQ 2 X DRRQ 1 X DRRQ 0 X 7000h 76h 78h 7Ah 7Ch 7Eh Misc Control Bits Sample Rate 0 Sample Rate 1 Vendor ID1 Vendor ID2 DACZ SR015 SR115 F7 T7 X SR014 SR114 F6 T6 X SR013 SR113 F5 T5 X SR012 SR112 F4 T4 X SR011 SR111 F3 T3 DLSR SR010 SR110 F2 T2 X SR09 SR19 F1 T1 ALSR SR08 SR18 F0 T0 MOD EN SR07 SR17 S7 REV7 SRX1 0D7 SR06 SR16 S6 REV6 SRX8 D7 SR05 SR15 S5 REV5 X SR04 SR14 S4 REV4 X SR03 SR13 S3 REV3 DRSR SR02 SR12 S2 REV2 X SR01 SR11 S1 REV1 ARSR SR00 SR10 S0 REV0 0000h BB80h BB80h 4144h 5303h NOTES 1. All registers not shown and bits containing an X are reserved. 2. Odd register addresses are aliased to the next lower even address. 3. Reserved registers should not be written. 4. Zeros should be written to reserved bits. REV. 0 –11– AD1819B Reset (Index 00h) Reg Num 00h Name Reset D15 X D14 SE4 D13 SE3 D12 SE2 D11 SE1 D10 SE0 D9 ID9 D8 ID8 D7 ID7 D6 ID6 D5 ID5 D4 ID4 D3 ID3 D2 ID2 D1 ID1 D0 ID0 Default 0400h Note: Writing any value to this register performs a register reset, which cause all registers to revert to their default values (except 74h, which controls the serial configuration). Reading this register returns the ID code of the part and a code for the type of 3D Stereo Enhancement. ID [9:0] Identify Capability. The ID field decodes the capabilities of AD1819B on the following: Bit ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ID9 Function Dedicated Mic PCM in Channel Modem Line Codec Support Bass and Treble Control Simulated Stereo (Mono to Stereo) Headphone Out Support Loudness (Bass Boost) Support 18-Bit DAC Resolution 20-Bit DAC Resolution 18-Bit ADC Resolution 20-Bit ADC Resolution AD1819B* 0 0 0 0 0 0 0 0 0 0 *The AD1819B contains none of the optional features identified by these bits. SE [4:0] Stereo Enhancement. The 3D stereo enhancement field identifies the Analog Devices 3D Phat Stereo enhancement. Master Volume (Index 02h) Reg Num 02h Name Master Volume D15 MM D14 X D13 LMV5 D12 LMV4 D11 LMV3 D10 LMV2 D9 LMV1 D8 LMV0 D7 X D6 X D5 RMV5 D4 RMV4 D3 RMV3 D2 RMV2 D1 RMV1 D0 RMV0 Default 8000h RMV [4:0] RMV5 LMV [4:0] LMV5 MM Right Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of –46.5 dB. Right Master Volume Maximum Attenuation. Forces RMV [4:0] to all “1s,” –46.5 dB. Left Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of –46.5 dB. Left Master Volume Maximum Attenuation. Forces LMV [4:0] to all “1s,” –46.5 dB. Master Volume Mute. When this bit is set to “1,” the left and right channels are muted. MM 0 0 0 1 xMV5 . . . xMV0 00 0000 01 1111 1x xxxx xx xxxx Function 0 dB Attenuation –46.5 dB Attenuation –46.5 dB Attenuation ∞ dB Attenuation Master Volume Mono (Index 06h) Reg Num 06h Name Master Volume Mono D15 MMM D14 X D13 X D12 X D11 X D10 X D9 X D8 X D7 X D6 X D5 MMV5 D4 MMV4 D3 MMV3 D2 MMV2 D1 MMV1 D0 MMV0 Default 8000h MMV [4:0] MMV5 MMM Mono Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of –46.5 dB. Mono Master Volume Maximum Attenuation –46.5 dB. Mono Master Volume Mute. When this bit is set to “1,” the mono channel is muted. –12– REV. 0 AD1819B MMM 0 0 0 1 PC Beep (Index 0Ah) Reg Num 0Ah Name PC Beep Volume D15 PCM D14 X D13 X D12 X D11 X D10 X D9 X D8 X D7 X D6 X D5 X D4 PCV3 D3 PCV2 D2 PCV1 D1 PCV0 D0 X Default 8000h MMV5 . . . MMV0 00 0000 01 1111 1x xxxx xx xxxx Function 0 dB Attenuation –46.5 dB Attenuation –46.5 dB Attenuation ∞ dB Attenuation PCV [3:0] PC Beep Volume Control. The least significant bit represents 3 dB attenuation. This register controls the output from 0 dB to a maximum attenuation of –45 dB. The PC Beep is routed to the Left and Right Line outputs even when AD1819B is in a RESET State. This is so that Power-On Self Test (POST) codes can be heard by the user in case of a hardware problem with the PC. PC Beep Mute. When this bit is set to “1,” the channel is muted. PCM 0 0 1 PCV3 . . . PCV0 0000 1111 xxxx Function 0 dB Attenuation –45 dB Attenuation –∞ dB Attenuation PCM Phone Volume (Index 0Ch) Reg Num 0Ch Name Phone Volume D15 PHM D14 X D13 X D12 X D11 X D10 X D9 X D8 X D7 X D6 X D5 X D4 PHV4 D3 PHV3 D2 PHV2 D1 PHV1 D0 PHV0 Default 8008h PHV [4:0] PHM Phone Volume. Allows setting the Phone Volume Attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled. Phone Mute. When this bit is set to “1,” the channel is muted. Mic Volume (Index 0Eh) Reg Num 0Eh Name Mic Volume D15 MCM D14 X D13 X D12 X D11 X D10 X D9 X D8 X D7 X D6 M20 D5 X D4 MCV4 D3 MCV3 D2 MCV2 D1 MCV1 D0 MCV0 Default 8008h MCV [4:0] M20 Mic Volume Gain. Allows setting the Mic Volume attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled. Microphone +20 dB Gain Block 0 = Disabled; Gain = 0 dB. 1 = Enabled; Gain = +20 dB. Mic Mute. When this bit is set to “1,” the channel is muted. MCM Line In Volume (Index 10h) Reg Num 10h Name LINE_IN Volume D15 LM D14 X D13 X D12 LLV4 D11 LLV3 D10 LLV2 D9 LLV1 D8 LLV0 D7 X D6 X D5 X D4 RLV4 D3 RLV3 D2 RLV2 D1 RLV1 D0 RLV0 Default 8808h RLV [4:0] LLV [4:0] LM Right Line In Volume. Allows setting the Line In right channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled. Left Line In Volume. Allows setting the Line In left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled. Line In Mute. When this bit is set to “1,” the channel is muted. REV. 0 –13– AD1819B CD Volume (Index 12h) Reg Num 12h Name CD Volume D15 CVM D14 X D13 X D12 LCV4 D11 LCV3 D10 LCV2 D9 LCV1 D8 LCV0 D7 X D6 X D5 X D4 RCV4 D3 RCV3 D2 RCV2 D1 RCV1 D0 RCV0 Default 8808h RCV [4:0] LCV [4:0] CVM Right CD Volume. Allows setting the CD right channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled. Left CD Volume. Allows setting the CD left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled. CD Volume Mute. When this bit is set to “1,” the channel is muted. Video Volume (Index 14h) Reg Num 14h Name Video Volume D15 VM D14 X D13 X D12 LVV4 D11 LVV3 D10 LVV2 D9 LVV1 D8 LVV0 D7 X D6 X D5 X D4 RVV4 D3 RVV3 D2 RVV2 D1 RVV1 D0 RVV0 Default 8808h RVV [4:0] LVV [4:0] VM Right Video Volume. Allows setting the Video right channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled. Left Video Volume. Allows setting the Video left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled. Video Mute. When this bit is set to “1,” the channel is muted. Aux Volume (Index 16h) Reg Num 16h Name Aux Volume D15 AM D14 X D13 X D12 LAV4 D11 LAV3 D10 LAV2 D9 LAV1 D8 LAV0 D7 X D6 X D5 X D4 RAV4 D3 RAV3 D2 RAV2 D1 RAV1 D0 RAV0 Default 8808h RAV [4:0] LAV [4:0] AM Right Aux Volume. Allows setting the Aux right channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled. Left Aux Volume. Allows setting the Aux left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled. Aux Mute. When this bit is set to “1,” the channel is muted. PCM Out Volume (Index 18h) Reg Num 18h Name PCM Out Volume D15 OM D14 X D13 X D12 LOV4 D11 LOV3 D10 LOV2 D9 LOV1 D8 LOV0 D7 X D6 X D5 X D4 ROV4 D3 ROV3 D2 ROV2 D1 ROV1 D0 ROV0 Default 8808h ROV [4:0] LOV [4:0] OM Right PCM Out Volume. Allows setting the PCM right channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled. Left PCM Out Volume. Allows setting the PCM left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled. PCM Out Volume Mute. When this bit is set to “1,” the channel is muted. Volume Table (Index 0Ch to 18h) Mute 0 0 0 1 x4 . . . x0 00000 01000 11111 xxxxx Function +12 dB Gain 0 dB Gain –34.5 dB Gain –∞ dB Gain –14– REV. 0 AD1819B Record Select Control (Index 1Ah) Reg Num 1Ah Name Record Select D15 X D14 X D13 X D12 X D11 X D10 LS2 D9 LS1 D8 LS0 D7 X D6 X D5 X D4 X D3 X D2 RS2 D1 RS1 D0 RS0 Default 0000h RS [2:0] LS [2:0] Right Record Select. Left Record Select. Used to select the record source independently for right and left. See table for legend. The default value is 0000h, which corresponds to Mic in. RS2 . . . RS0 0 1 2 3 4 5 6 7 LS2 . . . LS0 0 1 2 3 4 5 6 7 Right Record Source MIC CD_R VIDEO_R AUX_R LINE_IN_R Stereo Mix (R) Mono Mix PHONE_IN Left Record Source MIC CD_L VIDEO_L AUX_L LINE_IN_L Stereo Mix (L) Mono Mix PHONE_IN Record Gain (Index 1Ch) Reg Num 1Ch Name Record Gain D15 IM D14 X D13 X D12 X D11 LIM3 D10 LIM2 D9 LIM1 D8 LIM0 D7 X D6 X D5 X D4 X D3 RIM3 D2 RIM2 D1 RIM1 D0 RIM0 Default 8000h RIM [3:0] LIM [3:0] IM Right Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB and the range is 0 dB to +22.5 dB. Left Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB and the range is 0 dB to +22.5 dB. Input Mute. 0 = Unmuted, 1 = Muted or –∞ dB gain. IM 0 0 1 xIM3 . . . xIM0 1111 0000 xxxxx Function +22.5 dB Gain 0 dB Gain – ∞ dB Gain General Purpose (Index 20h) Reg Num 20h Name General Purpose D15 POP D14 X D13 3D D12 X D11 X D10 X D9 MIX D8 MS D7 LPBK D6 X D5 X D4 X D3 X D2 X D1 X D0 X Default 0000h LPBK MS Loopback Control. ADC/DAC digital loopback mode. MIC Select. 0 = MIC1. 1 = MIC2. –15– REV. 0 AD1819B MIX Mono Output Select. 0 = Mix. 1 = Mic. Phat Stereo Enhancement. 0 = Phat Stereo is off. 1 = Phat Stereo is on. PCM Output Path. The POP bit controls the optional PCM out 3D bypass path (the pre- and post3D PCM outpaths are mutually exclusive). 0 = Pre-3D. 1 = Post-3D. The register should be read before writing to generate a mask for only the bit(s) that need to be changed. The default value is 0000h. 3D POP 3D Control (Index 22h) Reg Num 22h* Name 3D Control D15 X D14 X D13 X D12 X D11 X D10 X D9 X D8 X D7 X D6 X D5 X D4 X D3 DP3 D2 DP2 D1 DP1 D0 DP0 Default 0000h DP [2:0] Depth Control. Sets 3D “Depth” Phat Stereo enhancement according to table below. DP3 . . . DP0 0 1 14 15 Depth 0% 6.67% 93.33% 100% Power-Down Control/Status (Index 26h) Reg Num 26h Name Power-Down Cntrl/Stat D15 X D14 X D13 PR 5 D12 PR4 D11 PR3 D10 PR2 D9 PR1 D8 PR0 D7 X D6 X D5 X D4 X D3 REF D2 ANL D1 DAC D0 ADC Default 0000h ADC DAC ANL REF PR [5:0] Ready Bits: The ready bits are read only, writing to REF, ANL, DAC, ADC will have no effect. These bits indicate the status for the AD1819B subsections. If the bit is a one then that subsection is “ready.” Ready is defined as the subsection able to perform in its nominal state. ADC section ready to transmit data. DAC section ready to accept data. Analog gainuators, attenuators, and mixers ready. Voltage References, VREF and V REFOUT up to nominal level. Power-Down Bits. Bits 0 and 1 are to be used individually rather than in combination with each other. The last bit PR3 can be used in combination with PR2 or by itself. Power-Down State ADCs and Input Mux Power-Down DACs Power-Down Analog Mixer Power-Down (VREF and VREFOUT On) Analog Mixer Power-Down (VREF and VREFOUT Off) AC-Link Interface Power-Down Internal Clocks Disabled ADC and DAC Power-Down VREF Standby Mode Total Power-Down Set Bits PR0 PR1 PR1, PR2 PR0, PR1, PR3 PR4 PR0, PR1, PR4, PR5 PR0, PR1 PR0, PR1, PR2, PR4, PR5 PR0, PR1, PR2, PR3, PR4, PR5 –16– REV. 0 AD1819B Serial Configuration (Index 74h) Reg Num 74h Name Serial Configuration D15 SLOT 16 D14 REGM 2 D13 REGM 1 D12 REGM 0 D11 DRQE N D10 DLRQ 2 D9 DLRQ 1 D8 DLRQ 0 D7 X D6 X D5 X D4 X D3 X D2 DRRQ 2 D1 DRRQ 1 D0 Default DRRQ 7000h 0 DRRQ0 DRRQ1 DRRQ2 DLRQ0 DLRQ1 DLRQ2 DRQEN REGM0 REGM1 REGM2 SLOT16 Master AC’97 Codec DAC Right Request. Slave 1 Codec DAC Right Request. Slave 2 Codec DAC Right Request. Master AC’97 Codec DAC Left Request. Slave 1 Codec DAC Left Request. Slave 2 Codec DAC Left Request. Fills idle status slots with DAC request reads, and stuffs DAC requests into LSB of output address slot. (AC-Link Slot 1.) Master Codec Register Mask. Slave 1 Codec Register Mask. Slave 2 Codec Register Mask. Enable 16-Bit Slots. If your system uses only a single AD1819B, you can ignore the register mask and the slave 1/slave 2 request bits. If you write to this register, write ones to all of the register mask bits. The request bits are read-only. The codec asserts each request bit when the corresponding DAC channel can accept data in the next frame. These bits are snapshots of the codec state taken when the current frame began (effectively, on the rising edge of SYNC), but they also take notice of DAC samples sent in the current frame. If you set the DRQEN bit, the AD1819B will fill all otherwise unused AC-Link status address and data slots with the contents of register 74h. That makes it somewhat simpler to access the information, because you don’t need to continually issue AC-Link read commands to get the register contents. Also, the DAC requests are reflected in Slot 1, Bits (11 . . . 6). These bits are active Lo. SLOT16 makes all AC-Link slots 16 bits in length, formatted into 16 slots. Miscellaneous Control Bits (Index 76h) Reg Num 76h Name Misc Control Bits D15 DACZ D14 X D13 X D12 X D11 X D10 DLSR D9 X D8 ALSR D7 MOD EN D6 SRX10 D7 D5 SRX8 D7 D4 X D3 X D2 DRSR D1 X D0 ARSR Default 0000h ARSR ADC Right Sample Generator Select. Connects right ADC channel to SR0 or SR1. 0 = SR0 Selected. 1 = SR1 Selected. DAC Right Sample Generator Select. Connects right DAC channel to SR0 or SR1. 0 = SR0 Selected. 1 = SR1 Selected. Multiply SR1 Rate by 8/7. Multiply SR1 Rate by 10/7. SRX10D7 and SRX8D7 are mutually exclusive; SRX10D7 has priority if both are set. Modem Filter Enable (left channel only). Change only when DACs are powered down. ADC Left Sample Generator Select. Connects left ADC channel to SR0 or SR1. 0 = SR0 Selected. 1 = SR1 Selected. DAC Left Sample Generator Select. Connects left DAC channel to SR0 or SR1. 0 = SR0 Selected. 1 = SR1 Selected. Zero-Fill (vs. repeat sample) if DAC is starved. DRSR SRX8D7 SRX10D7 MODEN ALSR DLSR DACZ REV. 0 –17– AD1819B Sample Rate 0 (Index 78h) Reg Num 78h Name Sample Rate 0 D15 SR015 D14 SR014 D13 SR013 D12 SR012 D11 SR011 D10 SR010 D9 SR09 D8 SR08 D7 SR07 D6 SR06 D5 SR05 D4 SR04 D3 SR03 D2 SR02 D1 SR01 D0 SR00 Default BB80h SR0 [15:0] Writing to this register allows the user to program the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hz increments. Programming a value greater than 48 kHz or less than 7 kHz may cause unpredictable results. Sample Rate 1 (Index 7Ah) Reg Num 7Ah Name Sample Rate 1 D15 SR115 D14 SR114 D13 SR113 D12 SR112 D11 SR111 D10 SR110 D9 SR19 D8 SR18 D7 SR17 D6 SR16 D5 SR15 D4 SR14 D3 SR13 D2 SR12 D1 SR11 D0 SR10 Default BB80h SR1 [15:0] Writing to this register allows the user to program the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hz increments. The sample rate may be multiplied by 8/7 or 10/7 by setting Bits D6 and D5 in Register 76h. Vendor ID (Index 7Ch–7Eh) Reg Num 7Ch Name Vendor ID1 D15 F7 D14 F6 D13 F5 D12 F4 D11 F3 D10 F2 D9 F1 D8 F0 D7 S7 D6 S6 D5 S5 D4 S4 D3 S3 D2 S2 D1 S1 D0 S0 Default 4144h S [7:0] F [7:0] Reg Num 7Eh Name Vendor ID2 This register is ASCII encoded to “A.” This register is ASCII encoded to “D.” D15 T7 D14 T6 D13 T5 D12 T4 D11 T3 D10 T2 D9 T1 D8 T0 D7 REV7 D6 REV6 D5 REV5 D4 REV4 D3 REV3 D2 REV2 D1 REV1 D0 REV0 Default 5303h T [7:0] REV [7:0] This register is ASCII encoded to “S.” Revision Register field contains the revision number. These bits are read-only and should be verified before accessing vendor-defined features. DIGITAL INTERFACE AD1819B AC-Link Digital Serial Interface Protocol The AD1819B incorporates an AC'97 5-pin digital serial interface that links it to a digital controller. AC-Link is a bidirectional, fixed rate, serial PCM digital stream. It handles multiple input, and output audio streams, as well as control register accesses employing a time division multiplexed (TDM) scheme. The AC-Link architecture divides each audio frame into 12 outgoing and 12 incoming data streams, up to 20-bit sample resolution. The AD1819B uses 16-bit samples. The data streams include: AC ’97 Protocol • TAG • Control Control Register Write Port • Status Control Register Read Port • PCM Playback 2-Channel Composite PCM Output Stream • PCM Record Data 2-Channel Composite PCM Input Stream 1 Input and Output 2 Output Slots 2 Input Slots 2 Output Slots 2 Input Slots Synchronization of all AC-Link data transactions is signaled by the AC’97 controller. The AD1819B drives the serial bit clock onto AC-Link, which the AC’97 controller then qualifies with a synchronization signal to construct audio frames. SYNC, which is fixed at 48 kHz, is derived by dividing down the serial bit clock (BIT_CLK) by 256. The BIT_CLK is fixed at 12.288 MHz. AC-Link serial data is updated on each rising edge of BIT_CLK. The receiver of AC-Link data, the AD1819B for outgoing data and the AC’97 controller for incoming data, samples each serial bit on the falling edge of BIT_CLK. SYNC must remain high for a minimum of 1 BIT_CLK up to a maximum duration of 16 BIT_CLKs at the beginning of each audio frame. The first 16 bits of the audio frame is defined as the “Tag Phase.” The remainder of the audio frame is the “Data Phase.” The AD1819B uses SYNC to define the beginning of the audio frame. –18– REV. 0 AD1819B The AC-Link protocol provides for a special 16-bit time slot (Slot 0) wherein each bit conveys a valid tag for its corresponding time slot within the current audio frame. A “1” in a given bit position of Slot 0 indicates that the corresponding time slot within the current audio frame has been assigned to a data stream, and contains valid data. If a slot is “tagged” invalid, it is the responsibility of the source of the data, (AD1819B for the input stream, AC’97 controller for the output stream), to stuff all bit positions with 0s during that slot’s active time. The AD1819B stuffs all invalid slots with zeros and ignores invalid input slots. Additionally, for power savings, all clock, sync, and data signals can be halted. For multiple codec operations, the AD1819B supports an enhanced mode for communicating with up to two additional codecs. The Slave 1 AD1819B codec uses Slots 5 and 6, while Slave 2 uses Slots 7 and 8 as shown in the following diagram. ENHANCED MODE SLOT # .... 1 2 3 4 5 6 7 8 9 10 11 12 SYNC CMD ADR CMD DATA PCM LEFT PCM LEFT PCM RIGHT PCM RIGHT PCM LEFT PCM LEFT PCM RIGHT PCM RIGHT PCM LEFT PCM LEFT PCM RIGHT PCM RIGHT OUTGOING STREAMS INCOMING STREAMS TAG RSRVD RSRVD RSRVD RSRVD TAG STATUS STATUS ADR DATA RSRVD RSRVD RSRVD RSRVD TAG PHASE SLAVE 1 SLAVE 2 DATA PHASE Figure 9. Standard Bidirectional Audio Frame AC-Link Audio Output Frame (SDATA_OUT) The audio output frame data streams correspond to the multiplexed bundles of all digital output data targeting AD1819B’s DAC inputs and control registers. As briefly mentioned earlier, each audio output frame supports up to twelve 20-bit outgoing data time slots. Slot 0 is a special reserved time slot containing 16 bits that are used for AC-Link protocol infrastructure. Within Slot 0 the first bit is a global bit (SDATA_OUT Slot 0, Bit 15), which flags the validity for the entire audio frame. If the “Valid Frame” bit is a 1, this indicates that the current audio frame contains at least one slot time of valid data. The next 12-bit positions sampled by AC’97 indicate which of the corresponding 12 time slots contain valid data. In this way input DAC data streams of differing sample rates can be transmitted across the AC-Link at its fixed 48 kHz audio frame rate. The following diagram illustrates the time-slot-based AC-Link protocol. TAG PHASE 20.8 s (48kHz) 12.2888MHz 81.4ns BIT_CLK SDATA_IN CODEC READY SLOT(1) SLOT(2) SLOT(12) DATA PHASE SYNC “0” “0” “0” 19 0 19 0 19 0 19 0 END OF PREVIOUS AUDIO FRAME TIME SLOT “VALID” BITS (1) = TIME SLOT CONTAINS VALID PCM DATA SLOT 1 SLOT 2 SLOT 3 SLOT 12 Figure 10. AC-Link Audio Output Frame A new audio output frame begins with a low-to-high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the AD1819B samples the assertion of SYNC. This falling edge marks the time when both sides of AC-Link are aware of the start of a new audio frame. On the next rising edge of BIT_CLK, the AC’97 controller transitions SDATA_OUT into the first bit position of Slot 0 (Valid Frame Bit). Each new bit position is presented to AC-Link on a rising edge of BIT_CLK, and subsequently sampled by AD1819B on the following falling edge of BIT_CLK. This sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned. REV. 0 –19– AD1819B AD1819A SAMPLES SYNC ASSERTION HERE SYNC AC’97 CONTROLLER SAMPLES FIRST SDATA_OUT BIT OF FRAME HERE BIT_CLK SDATA_OUT VALID FRAME END OF PREVIOUS AUDIO FRAME SLOT (1) SLOT (2) Figure 11. Start of an Audio Output Frame SDATA_OUT’s composite stream is MSB justified (MSB first) with all nonvalid slots’ bit positions stuffed with 0s by the AC’97 controller. The AD1819B ignores invalid slots. In the event that there are less than 20 valid bits within an assigned and valid time slot, the AC’97 controller always stuffs all trailing nonvalid bit positions of the 20-bit slot with 0s. The AD1819B ignores unused bits. As an example, consider an 8-bit sample stream being played out to one of the AD1819B’s DACs. The first 8-bit positions are presented to the DAC (MSB justified), followed by the next 12 bit positions, which are stuffed with 0s by the AC’97 controller. When mono audio sample streams are output from the AC’97 controller, it is necessary that BOTH left and right stream time slots be filled with the same data. Slot 1: Command Address Port The command port is used to control features and request status (see Audio Input Frame Slots l and 2) for AD1819B functions including, but not limited to, mixer settings and power management (refer to the control register section of this specification). The control interface architecture supports up to sixty-four 16-bit read/write registers, addressable on even byte boundaries. Only the even registers (00h, 02h, etc.) are valid, odd register (01h, 03h, etc.) accesses are discouraged (defaulting to the preceding even byte boundary—i.e., a read to 01h will return the 16-bit contents of 00h). Note that shadowing of the control register file on the AC’97 controller is an option left open to the implementation of the AC’97 controller. The AD1819B’s control register file is readable as well as writable. Audio output frame Slot 1 communicates control register address, and write/read command information to AD1819B. Command Address Port Bit Assignments: Bit (19) Bit (18:12) Bit (11:0) Read/Write Command Control Register Index Reserved (1 = Read, 0 = Write) (64 16-Bit Locations, Addressed On Even Byte Boundaries) (Stuffed with 0s) The first bit (MSB) sampled by the AD1819B indicates whether the current control transaction is a read or a write operation. The following 7-bit positions communicate the targeted control register address. The trailing 12-bit positions within the slot are reserved. Slot 2: Command Data Port The command data port is used to deliver 16-bit control register write data in the event that the current command port operation is a write cycle (as indicated by Slot 1, Bit 19). Bit (19:4) Bit (3:0) Control Register Write Data Reserved (Stuffed with 0s If Current Operation Is Not a Write) (Stuffed with 0s) If the current command port operation is not a write, the entire slot time should be stuffed with 0s by the AC’97 controller. Slot 3: PCM Playback Left Channel Audio output frame Slot 3 is the composite digital audio left playback stream. In a typical “Games Compatible” PC this slot is composed of standard PCM (.wav) output samples digitally mixed (on the AC’97 controller or host processor) with music synthesis output samples. If a sample stream of resolution less than 20 bits is transferred, the AC’97 controller should stuff all trailing nonvalid bit positions within this time slot with 0s. Slot 4: PCM Playback Right Channel Audio output frame Slot 4 is the composite digital audio right playback stream. In a typical “Games Compatible” PC this slot is composed of standard PCM (.wav) output samples digitally mixed (on the AC’97 controller or host processor) with music synthesis output samples. If a sample stream of resolution less than 20 bits is transferred, the AC’97 controller should stuff all trailing nonvalid bit positions within this time slot with 0s. –20– REV. 0 AD1819B Slot 5–Slot 8: Multicodec Communication • Slot 5 Slave 1 PCM Playback Left Channel • Slot 6 Slave 1 PCM Playback Right Channel • Slot 7 Slave 2 PCM Playback Left Channel • Slot 8 Slave 2 PCM Playback Right Channel Slot 6–Slot 12: Reserved Audio output frame Slot 6 to Slot 12 are reserved for future use and should always be stuffed with 0s by the digital controller. AC-Link Audio Input Frame (SDATA_IN) The audio input frame data streams correspond to the multiplexed bundles of all digital input data targeting the AC’97 controller. As is the case for audio output frame, each AC-Link audio input frame consists of twelve 20-bit time slots. Slot 0 is a special reserved time slot containing 16 bits used for AC-Link protocol infrastructure. Within Slot 0 the first bit is a global bit (SDATA_IN Slot 0, Bit 15) which flags whether or not AD1819B is in the “Codec Ready” state. If the “Codec Ready” bit is a 0, this indicates that AD1819B is not ready for normal operation. This condition is normal following the deassertion of power-on reset, for example, while AD1819B’s voltage references settle. When the AC-Link “Codec Ready” indicator bit is a 1, it indicates that the AC-Link and AD1819B control and status registers are in a fully operational state and all subsections are ready. Prior to any attempts at putting AD1819B into operation the AC’97 controller should poll the first bit in the audio input frame (SDATA_IN Slot 0, Bit 15) for an indication that the AD1819B has asserted “Codec Ready.” Once the AD1819B is sampled, “Codec Ready” is asserted the next 12-bit positions sampled by the AC’97 controller indicate which of the corresponding 12 time slots are assigned to input data streams and that they contain valid data. The following diagram illustrates the time-slot-based AC-Link protocol. TAG PHASE 20.8 s (48kHz) SYNC 12.288MHz 81.4ns BIT_CLK CODEC READY DATA PHASE SDATA_IN SLOT(1) SLOT(2) SLOT(12) “0” “0” “0” 19 0 19 0 19 0 19 0 END OF PREVIOUS AUDIO FRAME TIME SLOT “VALID” BITS (1) = TIME SLOT CONTAINS VALID PCM DATA SLOT 1 SLOT 2 SLOT 3 SLOT 12 Figure 12. AC-Link Audio Input Frame A new audio input frame begins with a low-to-high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the AD1819B samples the assertion of SYNC. This falling edge marks the time when both sides of AC-Link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AD1819B transitions SDATA_IN into the first bit position of Slot 0 (“Codec Ready” bit). Each new bit position is presented to AC-Link on a rising edge of BIT_CLK, and subsequently sampled by the AC’97 controller on the following falling edge of BIT_CLK. This sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams, are time aligned. AD1819A SAMPLES SYNC ASSERTION HERE SYNC AC’97 CONTROLLER SAMPLES FIRST SDATA_IN BIT OF FRAME HERE BIT_CLK SDATA_IN CODEC READY END OF PREVIOUS AUDIO FRAME SLOT (1) SLOT (2) Figure 13. Start of an Audio Input Frame SDATA_IN’s composite stream is MSB justified (MSB first) with all nonvalid bit positions (for assigned and/or unassigned time slots) stuffed with 0s by AD1819B. Slot 0: Tag Phase SDATA_IN The AD1819B is capable of sampling data from 7 kHz to 48 kHz with a resolution of 1 kHz. To enable a sample rate other than the default 48 kHz, set the DRQEN bit (Register 74h Bit 11). This allows DAC request bits (these are low active) to be output on the SDATA_IN stream. The digital controller should monitor the ADC valid bits to determine when the codec has valid data ready to send. REV. 0 –21– AD1819B TAG Phase Bit Assignments: Bit (15) Bit (14) Bit (13) Bit (12) Bit (11) Bit (10) Bit (9) Bit (8) Bit (7) Bit (6:0) Codec Ready Slot 1 Valid Slot 2 Valid Slot 3 Valid/ADC Left Data Is Valid on Slot 3 Slot 4 Valid/ADC Right Data Is Valid on Slot 4 Slot 5 Valid/ADC Left Data Slave 1 Valid on Slot 5 Slot 6 Valid/ADC Right Data Slave 1 Valid on Slot 6 Slot 7 Valid/ADC Left Data Slave 2 Valid on Slot 7 Slot 8 Valid/ADC Right Data Slave 2 Valid on Slot 8 Not Used Slot 1: Status Address Port The status port is used to monitor status for AD1819B functions including, but not limited to, mixer settings and power management. Audio input frame Slot 1’s stream echoes the control register index, for historical reference, for the data to be returned in Slot 2 (assuming that Slots 1 and 2 had been tagged “valid” by the AD1819B during Slot 0). Status Address Port Bit Assignments: Bit (19) Bit (18:12) Bit (11) Bit (10) Bit (9) Bit (8) Bit (7) Bit (6) Bit (5:0) RESERVED Control Register Index DAC Request Slot 3 DAC Request Slot 4 DAC Request Slot 5 DAC Request Slot 6 DAC Request Slot 7 DAC Request Slot 8 RESERVED (Stuffed with 0) (Echo of Register Index for Which Data Is Being Returned) (0 = Request, 1 = No Request) (0 = Request, 1 = No Request) (0 = Request, 1 = No Request); Slave 1 (0 = Request, 1 = No Request); Slave 1 (0 = Request, 1 = No Request); Slave 2 (0 = Request, 1 = No Request); Slave 2 (Stuffed with 0s) The first bit (MSB) generated by the AD1819B is always stuffed with a 0. The following 7-bit positions communicate the associated control register address, and the trailing 12-bit positions are stuffed with 0s by the AD1819B. Slot 2: Status Data Port The status data port delivers 16-bit control register read data. Bit (19:4) Bit (3:0) Control Register Read Data RESERVED (Stuffed with 0s If Tagged “Invalid” by AD1819B) (Stuffed with 0s) If Slot 2 is tagged “invalid” by the AD1819B, the entire slot will be stuffed with 0s by the AD1819B. Slot 3: PCM Record Left Channel Audio input frame Slot 3 is the left channel output of the AD1819B’s input MUX, post-ADC. AD1819B transmits its ADC output data (MSB first), and stuffs the trailing nonvalid bit positions with 0s to fill out its 20-bit time slot. Slot 4: PCM Record Right Channel Audio input frame Slot 4 is the right channel output of the AD1819B’s input MUX, post-ADC. AD1819B transmits its ADC output data (MSB first), and stuffs the trailing nonvalid bit positions with 0s to fill out its 20-bit time slot. Slot 5–Slot 8: Multicodec Communication • Slot 5 Slave 1 PCM Record Left Channel • Slot 6 Slave 1 PCM Record Right Channel • Slot 7 Slave 2 PCM Record Left Channel • Slot 8 Slave 2 PCM Record Right Channel Slot 9–Slot 12: Reserved Audio input frame Slots 9–12 are reserved for future use and are always stuffed with 0s by the AD1819B. AC-Link Low Power Mode The AC-Link signals can be placed in a low power mode. When the AD1819B’s Power-Down Register (26h) is programmed to the appropriate value, both BIT_CLK and SDATA_IN will be brought to a logic low voltage level. –22– REV. 0 AD1819B SYNC BIT_CLK SDATA_OUT SLOT 12 PREVIOUS FRAME TAG WRITE TO 0x26 DATA PR4 SDATA_IN SLOT 12 PREVIOUS FRAME TAG NOTE: BIT_CLK NOT TO SCALE Figure 14. AC-Link Power-Down Timing BIT_CLK and SDATA_IN are transitioned low immediately following the decode of the write to the Power-Down Register (26h) with PR4. When the AC’97 controller driver is at the point where it is ready to program the AC-Link into its low power mode, Slots (1 and 2) must be the only valid stream in the audio output frame. The AC’97 controller should also drive SYNC and SDATA_OUT low after programming AD1819B to this low power “halted” mode. Once AD1819B has been instructed to halt BIT_CLK, a special “wake-up” protocol must be used to bring the AC-Link to the active mode, since normal audio output and input frames can not be communicated in the absence of BIT_CLK. Waking up the AC-Link There are two methods for bringing the AC-Link out of a low power, halted mode. Regardless of the method, it is the AC’97 controller that performs the wake-up task. AC-Link protocol provides for a “Cold AC’97 Reset,” and a “Warm AC’97 Reset.” The current power-down state would ultimately dictate which form of AC’97 reset is appropriate. Unless a “cold” or “register” reset (a write to the Reset Register) is performed, wherein the AD1819B registers are initialized to their default values, registers are required to keep state during all powerdown modes. The Serial Configuration Register (0x74) maintains state during a register reset. Once powered down, reactivation of the AC-Link via reassertion of the SYNC signal may be immediate. When the AD1819B powers up, it indicates readiness via the Codec Ready Bit (Input Slot 0, Bit 15). Cold AC’97 Reset A cold reset is achieved by asserting RESET for at least the minimum specified time. SYNC and SDATA_IN should be held low during the rising edge of RESET. By driving RESET, BIT_CLK and SDATA_IN will be activated, and all AD1819B control registers will be initialized to their default power-on reset values. RESET is an asynchronous AD1819B input. Warm AC’97 Reset A warm AC’97 reset will reactivate the AC-Link without altering the current AD1819B register values. A warm reset is signaled by driving SYNC high for a minimum of 1 µs in the absence of BIT_CLK. Within normal audio frames SYNC is a synchronous AD1819B input. In the absence of BIT_CLK, however, SYNC is treated as an asynchronous input used in the generation of a warm reset to the AD1819B. REV. 0 –23– AD1819B MULTIPLE CODE CONFIGURATION Setting Up Multiple Codecs Configure the Codec Resources The AD1819B may be used with up to two additional AD1819 or AD1819B codecs. In order to configure the codecs as Master, Slave 1 or Slave 2, refer to the following table. CS1 0 0 1 1 0 = Ground; 1 = V DD. Programing REGM (2:0) bits in the Serial Configuration Register (74h) allows the digital controller read write access to all the internal registers on each codec according to the following table. REGM2 REGM1 REGM0 0 1 0 1 0 1 0 1 Read x Master Slave 1 Master Slave 2 Master Slave 1 Master Write x Master Slave 1 Master, Slave 1 Slave 2 Master, Slave 2 Slave 1, Slave 2 Master, Slave 1, Slave 2 CS0 0 1 0 1 Configuration Slave 1 Codec Slave 2 Codec Master Codec AC’97 Mode Codec The XTAL_IN pin on the Slave Codecs “must” be tied to ground and the CHAIN_IN pin “must” be tied to ground on the last codec Slave 1 (on a 2-codec design) or Slave 2 (on a 3-codec design). See Figures 15, 16 and 17. 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 –24– REV. 0 AD1819B APPLICATIONS CIRCUITS The AD1819B has been designed to require a minimum amount of external circuitry. The recommended applications circuits are shown in Figures 15–18. Reference designs for the AD1819B are available and may be obtained by contacting your local Analog Devices’ sales representative or authorized distributor. Example shell programs for establishing a communications path between the AD1819B and an ADSP-21xx DSP are also available. +5AVDD 10 F TANT +5AVDD 10 F TANT +5DVDD 10 F TANT +5DVDD 10 F TANT 100nF 100nF 100nF 100nF 1.37k 4.99k 100nF 100nF PC_BEEP AVDD2 AVSS2 AVDD1 AVSS DVSS1 DVDD1 DVSS2 DVDD2 1F 1F 1F 1F 1F CD_R 1F 1F 1F 1F 1F 1F 1F 1F 7 LINE_IN_R LINE_IN_L RESET MIC1 MIC2 SDATA_OUT SDATA_IN SYNC BIT_CLK DIGITAL CONTROLLER CD_L CD_GND VIDEO_L CS0 VIDEO_R AUX_L AUX_R PHONE_IN MONO_OUT LINE_OUT_R LINE_OUT_L CS1 CHAIN_IN 47 CHAIN_CLK 48 AD1819B DVDD 1F 36 1F 47k 47k 47k AFILT1 AFILT2 FILT_L FILT_R CX3D 34 RX3D 33 VREFOUT 28 VREF 27 XTAL_IN XTAL_OUT 100nF 270pF NP0 270pF NP0 1F 1F 47nF 600Z ANALOG GROUND 2.25VDC 100nF 10 F TANT 22pF NP0 24.576MHz 22pF NP0 DIGITAL GROUND Figure 15. Recommended One Codec Application Circuit REV. 0 –25– AD1819B RESET SDATA_OUT SDATA_IN SYNC RESET SDATA_OUT SDATA_IN SYNC BIT_CLK FL0 DT0 DR0 RFS0 SCLK0 SPORT0 DVDD DIGITAL CONTROLLER (ADSP-2181) AD1819B MASTER BIT_CLK CS0 CS1 CHAIN_IN CHAIN_CLK XTAL_IN XTAL_OUT 24.576MHz 22pF NP0 22pF NP0 RESET SDATA_OUT SDATA_IN SYNC AD1819B SLAVE 1 BIT_CLK CS0 CS1 CHAIN_IN CHAIN_CLK XTAL_IN XTAL_OUT RESET SDATA_OUT SDATA_IN SYNC AD1819B SLAVE 2 BIT_CLK CS0 CS1 CHAIN_IN CHAIN_CLK DVDD XTAL_IN XTAL_OUT Figure 16. Three Codec System Example –26– REV. 0 AD1819B RESET SDATA_OUT SDATA_IN SYNC RESET SDATA_OUT SDATA_IN SYNC BIT_CLK FL0 DT0 DR0 RFS0 SCLK0 SPORT0 DVDD DIGITAL CONTROLLER (ADSP-2181) AD1819B MASTER BIT_CLK CS0 CS1 CHAIN_IN CHAIN_CLK XTAL_IN XTAL_OUT 24.576MHz 22pF NP0 22pF NP0 RESET SDATA_OUT SDATA_IN SYNC AD1819B SLAVE 1 BIT_CLK CS0 CS1 CHAIN_IN CHAIN_CLK XTAL_IN XTAL_OUT Figure 17. Two Codec System Example AD1819B 2.21k * VREFOUT MIC INPUT FB 100pF 10mV RMS (mean) 200Hz < FREQUENCY RESPONSE < 5kHz @ –3dB NOTES: *MAY NEED TO OPTIMIZE TO SUIT MICROPHONE **SELECT MIC1 AND MAX GAIN 20dB +12dB for 10mV RMS MICROPHONE OUTPUT. 100 10nF* NC MIC2 100nF MIC1** Figure 18. Microphone Input REV. 0 –27– AD1819B OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Terminal LQFP (ST-48) C3681–2–10/99 0.063 (1.60) MAX 0.030 (0.75) 0.018 (0.45) SEATING PLANE TOP VIEW (PINS DOWN) 0.354 (9.00) BSC 0.276 (7.0) BSC 48 1 37 36 0.030 (0.75) 0.057 (1.45) 0.018 (0.45) 0.053 (1.35) 0.006 (0.15) 0.002 (0.05) 0° – 7° 0° MIN 0.007 (0.18) 0.004 (0.09) 12 13 25 24 0.0197 (0.5) BSC 0.011 (0.27) 0.006 (0.17) 0.354 (9.00) BSC 0.276 (7.0) BSC –28– REV. 0 PRINTED IN U.S.A.