AD1862N

a FEATURES 120 dB Signal-to-Noise Ratio 102 dB D-Range Performance 1 dB Gain Linearity 1 mA Output Current 16-Pin DIP Package 0.0012% THD + N APPLICATIONS High Performance Compact Disc Players Digital Audio Amplifiers Synthesizer Keyboards Digital Mixing Consoles High Resolution Signal Processing –VS –VS 1 2 Ultralow Noise 20-Bit Audio DAC AD1862* FUNCTIONAL BLOCK DIAGRAM VOLTAGE REFERENCE 16 +VS 15 NR2 14 ADJ 13 NR1 INPUT & DIGITAL OFFSET 12 AGND 20-BIT DAC 11 IOUT 10 RF 9 DGND TRIM 3 +VL 4 CLK 5 LE 6 DATA 7 –VL 8 AD1862 PRODUCT DESCRIPTION The AD1862 is a monolithic 20-bit digital audio DAC. Each device provides a 20-bit DAC, 20-bit serial-to-parallel input register and voltage reference. The digital portion of the AD1862 is fabricated with CMOS logic elements that are provided by Analog Devices’ BiMOS II process. The analog portion of the AD1862 is fabricated with bipolar and MOS devices as well as thin-film resistors. New design, layout and packaging techniques all combine to produce extremely high performance audio playback. The design of the AD1862 incorporates a digital offset circuit which improves low-level distortion performance. Low stress packaging techniques are used to minimize stress-induced parametric shifts. Stress-sensitive circuit elements are located in die areas which are least affected by packaging stress. Laser-trimming of initial linearity error affords extremely low total harmonic distortion. Output glitch is also small, contributing to the overall high level of performance. The noise performance of the AD1862 is excellent. When used with the recommended two external noise-reduction capacitors, it achieves 120 dB signal-to-noise ratio. The serial input port consists of the clock, data and latch enable pins. A serial 20-bit, 2s complement data word is clocked into the DAC, MSB first, by the external data clock. A latch-enable signal transfers the input word from the internal serial input register to the DAC input register. The data clock can function at 17 MHz, allowing 16 × FS operation. The serial input port is compatible with second-generation digital filter chips for consumer audio products such as the NPC SM5813 and SM5818. The AD1862 operates with ± 5 V to ± 12 V supplies for the digital power supplies and ± 12 V supplies for the analog supplies. The digital and analog supplies can be separated for reduced digital crosstalk. Separate analog and digital common pins are also provided. The AD1862 typically dissipates less than 300 mW. The AD1862 is packaged in a 16-pin plastic DIP. The operating range is guaranteed to be –25°C to +70°C. PRODUCT HIGHLIGHTS 1. 120 dB signal-to-noise ratio. (typical) 2. 102 dB D-Range performance. (minimum) 3. ± 1 dB gain linearity @ –90 dB amplitude. 4. 20-bit resolution provides 120 dB of dynamic range. 5. 16 × FS operation. 6. 0.0016% THD+N @ 0 dB signal amplitude. (typical) 7. Space saving 16-pin DIP package. 8. ± 1 mA output current. *Protected by U.S. Patent Numbers: 4,349,811; 4,857,862; 4,855,618; 3,961,326; 4,141,004; 4,902,959. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD1862–SPECIFICATIONS (T at +25 C and A 12 V supplies, see Figure 10 for test circuit schematic) Min Typ Max Units Bits 4.0 0.4 0.8 1.0 –10 V V µA µA MHz % µA dB (%) dB (%) dB (%) dB (%) dB dB dB dB dB mA % kΩ ns kΩ % ±V ±V mA mA mW °C °C °C RESOLUTION DIGITAL INPUTS VIH VIL IIH @ VIH = 4.0 V IIL @ VIL = 0.4 V Maximum Clock Input Frequency ACCURACY Gain Error Midscale Output Error TOTAL HARMONIC DISTORTION + NOISE (EIAJ)1 0 dB, 990.5 Hz AD1862N-J AD1862N –20 dB, 990.5 Hz AD1862N, N-J –60 dB, 990.5 Hz AD1862N, N-J D-Range, –60 dB, A-Weight Filter SIGNAL-TO-NOISE RATIO2: (EIAJ)1 A-Weight Filter AD1862N-J AD1862N GAIN LINEARITY @ –90 dB AD1862N-J AD1862N OUTPUT CURRENT Bipolar Range Tolerance Output Impedance (± 30%) Settling Time FEEDBACK RESISTOR Value Tolerance POWER SUPPLY Voltage Voltage Current VL and –VL VS and –VS +I, VL and VS = 12 V, 17 MHz Clock –I, –VL and –VS = –12 V, 17 MHz Clock 20 2.0 17 ±2 –98 (0.0012) –94 (0.0019) –84 (0.0063) –45 (0.56) 102 113 110 119 119 ±1 ±1 ±1 ±1 2.1 350 3 ±1 4.75 10.8 12.0 12.0 11 13 288 +25 –25 –60 ±2 ±5 –96 (0.0016) –92 (0.0025) –80 (0.01) –42 (0.8) 2 2 13.2 13.2 15 16 372 POWER DISSIPATION VL and VS = 12 V, –VL and –VS = –12 V, 17 MHz Clock TEMPERATURE RANGE Specification Operation Storage +70 +100 NOTES 1 Test Method complies with EIAJ Standard CP-307. 2 The signal-to-noise measurement includes noise contributed by the SE5534A op amp used in the test fixture but does not include the noise contributed by the low pass filter used in the test fixture. Specifications in boldface are tested on all production units at final electrical test. Specifications subject to change without notice. –2– REV. A AD1862 2 –30 –40 –60dB ANALOG OUTPUT ERROR – dB AD1862N-J GAIN LINEARITY 1 THD +N – dB –50 –60 –70 –80 –90 0dB 1 10 FREQUENCY – kHz 20 –1 –20dB –2 – 100 – 80 – 60 – 40 – 20 0 DIGITAL INPUT – dB Figure 1. THD+N vs. Frequency Figure 4. Gain Linearity 400 –30 350 –40 300 –60dB THD +N – dB FULLSCALE MIDSCALE –50 –60 –70 –80 –90 –20dB 0dB –25 0 25 TEMPERATURE – °C 50 75 250 nV/√Hz 200 150 100 –FULLSCALE 50 0 1 10 100 Hz 1k 10k 100k Figure 2. Noise Density Figure 5. THD+N vs. Temperature (1 kHz) Figure 3. Broadband Noise (20 kHz Bandwidth, Midscale) Figure 6. Midscale Differential Linearity REV. A –3– AD1862 ABSOLUTE MAXIMUM RATINGS* VL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +13.2 V –VL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –VS to 0 V VS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +13.2 V –VS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –13.2 to 0 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 to +0.3 V Digital Inputs to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 to VL Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C, 10 sec Storage Temperature . . . . . . . . . . . . . . . . . . –60°C to +100°C *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1862 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE PIN CONFIGURATION PIN DESIGNATIONS Pin –VS 1 –VS 2 TRIM 3 +VL 4 CLK LE DATA –VL 5 6 7 8 16 +VS 15 NR2 Function –VS –VS TRIM +VL CLK LE D –VL DGND RF IOUT AGND NR1 ADJ NR2 +VS Description Bias Capacitor Analog Negative Supply Trim Pot Connection Positive Logic Supply External Clock Input Latch Enable Input Data Input Negative Logic Supply Digital Ground Feedback Resistor Output Current Analog Ground Reference Capacitor Midscale Adjust Bias Capacitor Positive Analog Supply AD1862 TOP VIEW (Not to Scale) 14 ADJ 13 NR1 12 AGND 11 IOUT 10 RF 9 DGND 11 12 13 14 15 16 17 18 19 10 11 12 13 14 15 16 ORDERING GUIDE Model AD1862N AD1862N-J *N = Plastic DIP. Operating Temperature Range –25°C to +70°C –25°C to +70°C THD+N @ FS –92 dB, 0.0025% –96 dB, 0.0016% SNR 110 dB 113 dB Package Option* N-16 N-16 –4– REV. A AD1862 TOTAL HARMONIC DISTORTION + NOISE Total Harmonic Distortion plus Noise (THD+N) is defined as the ratio of the square root of the sum of the squares of the values of the harmonics and noise to the value of the fundamental input frequency. It is usually expressed in percent (%) or decibels (dB). D-RANGE DISTORTION TRIM NR1 ADJ FEEDBACK REGISTER VS VREF AGND NR2 LATCH ENABLE –VL DECODER AND DIGITAL OFFSET CLOCK 20-BIT DAC CURRENT OUTPUT + VL LATCH D-Range Distortion is the ratio of the signal amplitude to the distortion plus noise at –60 dB. In this case, an A-Weight filter is used. The value specified for D-Range performance is the ratio measured plus 60 dB. SETTLING TIME DATA DGND SERIAL INPUT REGISTER Settling Time is the time required for the output to reach and remain within ± 1/2 LSB about its final value, measured from the digital input transition. It is a primary measure of dynamic performance and is usually expressed in nanoseconds (ns). SIGNAL-TO-NOISE RATIO AD1862 Block Diagram FUNCTIONAL DESCRIPTION The Signal-to-Noise Ratio is defined as the ratio of the amplitude of the output with full-scale present to the amplitude of the output when no signal is present. It is expressed in decibels (dB) and measured using an A-Weight filter. GAIN LINEARITY The AD1862 is a high performance, monolithic 20-bit audio DAC. Each device includes a voltage reference, a 20-bit DAC, 20-bit input latch and a 20-bit serial-to-parallel input register. A special digital offset circuit, combined with segmentation circuitry, produces excellent THD+N and D-range performance. Extensive noise-reduction features are utilized to make the noise performance of the AD1862 as high as possible. For example, the voltage reference circuit is a low-noise, 9 volt bandgap cell. This cell supplies the reference voltage to the bipolar offset circuit and the DAC. An external noise-reduction capacitor is connected to NR1 to form a low-pass filter network. Additional noise-reduction techniques are used in the control amplifier of the DAC. By connecting an external noise-reduction capacitor to NR2 output noise contributions from the control portion of the DAC are similarly reduced. The noise-reduction efforts result in a signal-to-noise ratio of 120 dB. The design of the AD1862 uses a combination of segmented decoder, R-2R topology and digital offset to produce low distortion at all signal amplitudes. The digital offset technique shifts the midscale output voltage (0 V) away from the MSB transition of the device. Therefore, small amplitude signals are not affected by an MSB change. An extra DAC cell is included to avoid clipping the output at full scale. The DAC supplies a ± 1 mA output current to an external I-to-V converter. An on-board 3 kΩ feedback resistor is also supplied. Both the output current and feedback resistor are laser-trimmed to ± 2% tolerance, simplifying the selection of external filter and/or deemphasis network components. The input register and serial-to-parallel converter are fabricated with CMOS logic gates. These gates allow the achievement of fast switching speeds and low power consumption. Internal TTLto-CMOS converters are used to insure TTL and 5 V CMOS compatibility. Gain Linearity is a measure of the deviation of the actual output amplitude from the ideal output amplitude. It is determined by measuring the amplitude of the output signal as the amplitude of that output signal is digitally reduced to a low level. A perfect D/A converter exhibits no difference between the ideal and actual amplitudes. Gain linearity is expressed in decibels (dB). MIDSCALE ERROR Midscale Error, or bipolar zero error, is the deviation of the actual analog output from the ideal output when the 2s complement input code representing midscale is loaded in the input register. The AD1862 is a current output D/A converter. Therefore, this error is expressed in µA. REV. A –5– AD1862 Analog Circuit Considerations GROUNDING RECOMMENDATIONS The AD1862 has two ground pins, designated analog ground (AGND) and digital ground (DGND). The analog ground pin is the “high-quality” ground reference for the device. The analog ground pin should be connected to the analog common point in the system. The reference bypass capacitor, the noninverting terminal of the current-to-voltage conversion op amp, and any output loads should be connected to this point. The digital ground pin returns ground current from the digital logic portions of the AD1862 circuitry. This pin should be connected to the digital common point in the system. As illustrated in Figure 7, AGND and DGND should be connected together at one point in the system. tributed by the voltage reference circuitry. The proper choice for this capacitor is a tantalum type with value of 10 µF or more. This capacitor should be connected to the package pins as closely as possible. This will minimize the effects of parasitic inductance of the leads and connections circuit connections. 1 –12V ANALOG SUPPLY 2 3 4 5 6 7 8 16 C2 15 + 14 13 12 11 10 9 + C1 AD1862 TOP VIEW (Not to Scale) 1 2 3 4 5 6 7 8 TOP VIEW (Not to Scale) 16 15 NOTE: PIN 1 IS "HIGH QUALITY" RETURN FOR BIAS CAP. AD1862 14 13 12 11 10 9 DGND AGND Figure 8. Noise Reduction Capacitors Capacitor C2 is connected between the pin labeled NR2 and the negative analog supply, –VS. This capacitor reduces the portion of output noise contributed by the control amplifier circuitry. C2 should be chosen to be a tantalum capacitor with a value of about 1 µF. Again, the connections between the AD1862 and C2 should be made as short as possible. The recommended values for C1 and C2 are 10 µF and 1 µF, respectively. The ratio between C1 and C2 should be approximately 10. Additional noise reduction can be gained by choosing slightly higher values for C1 and C2 such as 22 µF and 2.2 µF. Figure 2 illustrates the noise performance of the AD1862 with 10 µF and 1 µF. EXTERNAL AMPLIFIER CONNECTIONS Figure 7. Grounding and Bypassing Recommendations The AD1862 has four power supply input pins. ± VS provide the supply voltages which operate the linear portions of the DAC including the voltage reference and control amplifier. The ± VS supplies are designed to operate with ± 12 volts. The ± VL supplies operate the digital portions of the chip including the input shift register, the input latching circuitry and the TTL-to-CMOS level shifters. The ± VL supplies are designed to be operated from ± 5 V to ± 12 V supplies subject only to the limitation that –VL may not be more negative than –VS. Decoupling capacitors should be used on all power supply input pins. Good engineering practice suggests that these capacitors be placed as close as possible to the package pins and the common points. The logic supplies, ± VL, should be decoupled to DGND and the analog supplies, ± VS, should be decoupled to AGND. EXTERNAL NOISE REDUCTION COMPONENTS POWER SUPPLIES AND DECOUPLING The AD1862 is a current-output D/A converter. Therefore, an external amplifier, in combination with the on-board feedback resistor, is required to derive an output voltage. Figure 9 illustrates the proper connections for an external operational amplifier. The output of the AD1862 is intended to drive the summing junction of an external current-to-voltage conversion op amp. Therefore, the voltage on the output current pin of the AD1862 should be approximately the same as that on the AGND pin of the device. The on-board 3 kΩ feedback resistor and the ± 1 mA output current typically have ± 1% tolerance or less. This makes the choice of external components very simple and eliminates additional trimming. For example, if a user wishes to derive an output voltage higher than the ± 3 V swing offered by the output current and feedback resistor combination, all that is required is to combine a standard value resistor with the feedback resistor to achieve the appropriate output voltage swing. This technique can be extended to include the choice of elements in the deemphasis network, etc. Two external capacitors are required to achieve low-noise operation. Their correct connection is illustrated in Figure 8. Capacitor C1 is connected between the pin labeled NR1 and analog common. C1 forms a low-pass filter element which reduces noise con- –6– REV. A Testing the AD1862 TOTAL HARMONIC DISTORTION + NOISE The THD figure of an audio DAC represents the amount of undesirable signal produced during reconstruction and playback of an audio waveform. The THD specification, therefore, provides a direct method to classify and choose an audio DAC for a desired level of performance. By combining noise measurement with the THD measurement, a THD+N specification is realized. This specification indicates all of the undesirable signal produced by the DAC, including harmonic products of the test tone as well as noise. Analog Devices tests all AD1862s on the basis of THD+N performance. In this test procedure, a digital data stream representing a 0 dB, –20 dB or –60 dB sine wave is sent to the device under test. The frequency of the waveform is 990.5 Hz. Input data is sent to the AD1862 at an 8 × FS rate (352.8 kHz). The AD1862 under test produces an output current which is converted to an output voltage by an external amplifier. Figure 10 illustrates the recommended test circuit. Deglitchers and trims are not used during this test procedure. The automatic test equipment digitizes 4096 samples of the output test waveform, incorporating 23 complete cycles of the sine wave. A 4096 point FFT is performed on the test data. 1 2 3 4 5 6 7 8 TOP VIEW (Not to Scale) 16 15 AD1862 14 13 12 11 10 9 VOUT Figure 9. External Amplifier Connections Based upon the harmonics of the fundamental 990.5 Hz test tone, and the noise components in the audio band, the total harmonic distortion + noise of the device is calculated. The AD1862 is available in two performance grades. The AD1862N produces a maximum of 0.0025% THD+N at 0 dB signal levels. The higher performance AD1862N-J produces a maximum of 0.0016% THD+N at 0 dB signal levels. SIGNAL-TO-NOISE RATIO The Signal-to-Noise Ratio (SNR) of the AD1862 is tested in the following manner. The amplitude of a 0 dB signal is measured. The device under test is then set to midscale output voltage (0 volts). The amplitude of all noise present to 30 kHz is measured. The SNR is the ratio of these two measurements. The SNR figure for the AD1862 includes the output noise contributed by the NE5534 op amp used in the test fixture but does not include the noise contributed by the low-pass filter used in the test fixture. The AD1862N has a minimum SNR of 110 dB. The higher performance AD1862N-J has a minimum SNR of 113 dB. 12V 0.1µF 1 –12V 12V 2 3 4 17MHz 352.8kHz 0.1µF 5 6 7 8 0.1µF –12V TOP VIEW (Not to Scale) 16 15 0.1µF 10µF + 1µF AD1862 14 13 12 11 + SE5534A ANALOG COMMON 360pF 10 9 DIGITAL COMMON 3-POLE LOW PASS FILTER OUTPUT VOLTAGE Figure 10. Recommended Test Circuit REV. A –7– AD1862 OPTIONAL TRIM ADJUSTMENT The AD1862 includes an external midscale adjust feature. Should an application require improved distortion performance under small and very small signal amplitudes (–60 dB and lower), an adjustment is possible. Two resistors and one potentiometer form the adjustment network. Figure 11 illustrates the correct configuration of the external components. Analog Devices recommends that this adjustment be performed with –60 dB signal amplitudes or lower. Minor performance improvement is achieved with larger signal amplitudes such as –20 dB. Almost no improvement is possible when this adjustment is performed with 0 dB signal amplitudes. – 12V 1 2 3 4 5 6 7 8 TOP VIEW (Not to Scale) 16 15 470kΩ AD1862 14 13 12 11 10 9 100kΩ 470kΩ Figure 11. External Midscale Adjust DIGITAL CIRCUIT CONSIDERATIONS INPUT DATA Data is transmitted to the AD1862 in a bit stream composed of 20-bit words with a serial, 2s complement, MSB first format. Three signals must be present to achieve proper operation. They are the data, clock and latch enable signals. Input data bits are clocked into the input register on the rising edge of the clock signal (CLK). The LSB is clocked in on the 20th clock pulse. When all data bits are loaded, a low going latch enable (LE) pulse updates the DAC input. Figure 12a illustrates the general signal requirements for data transfer for the AD1862. MSB WORD n+1 MSB DATA CLOCK LATCH ENABLE WORD n LSB Figure 12a. Input Data TIMING Figure 12b illustrates the specific timing requirements that must be met in order for the data transfer to be accomplished successfully. The input pins of the AD1862 are both TTL and 5 V CMOS compatible, independent of the power supplies used in the application. The input requirements illustrated in Figure > 60ns >25ns CLK >25ns 12b are compatible with the data outputs provided by popular digital interpolation filter chips used in digital audio playback systems. The AD1862 input clock will run at 17 MHz allowing data to be transferred at a rate of 16 × FS. Of course, it will also function at slower rates such as 2 ×, 4 × or 8 × FS. >60ns >40ns LATCH ENABLE (LE) >40ns >15ns >15ns DATA MSB 1st BIT 2nd BIT INTERNAL DAC INPUT REGISTER UPDATED WITH 20 MOST RECENT BITS LSB (20th BIT) >15ns >40ns WORD NEXT BITS CLOCKED TO SHIFT REGISTER Figure 12b. Timing Requirements –8– REV. A AD1862 The AD1862 is an extremely high performance DAC designed for high-end consumer and professional digital audio applications. Compact disc players, digital preamplifiers, digital musical instruments and sound processors benefit from the extended dynamic range, low THD+Noise and high signal-to-noise ratio. For the first time, the D/A converter is no longer the basic limitation in the performance of a CD player. The performance of professional audio gear, such as mixing consoles, digital tape recorders and multivoice synthesizers can utilize the wide dynamic range and signal-to-noise ratio to achieve greater performance. And, the AD1862’s space saving 16-pin package contributes to compact system design. This permits a system designer to incorporate more voices in multivoice synthesizers, more tracks in multitrack tape recorders and more channels in multichannel mixing consoles. Furthermore, high-resolution signal processing and waveform generation applications are equally well served by the AD1862. HIGH PERFORMANCE CD PLAYER Figure 13 illustrates the application of AD1862s in a high performance CD player. Two AD1862s are used, one for the left channel and one for the right channel. The CXD11XX chip decodes the digital data coming from the read electronics and sends it to the SM5813. Input data is sent to each AD1862 by the SM5813 digital interpolating filter. This device operates at 8 times oversampling. The NE5534 op amps are chosen for current-to-voltage converters due to their low distortion and low noise. The output filters are 5-pole designs. For the purpose of clarity, all bypass capacitors have been omitted from the schematic. 1µF + +V 16 S NR 2 15 ADJ 14 NR 1 13 AGND 12 I OUT 11 NE5534 R F 10 DGND 9 10µF 12V ANALOG SUPPLY 1 2 – VS – VS 3 TRIM 4 +VL 5 6 7 – 5V DIGITAL SUPPLY 8 CLK LE DATA – VL + LOW PASS FILTER LEFT CHANNEL OUTPUT AD1862 – 12V ANALOG SUPPLY 5V DIGITAL SUPPLY 1 – VS 16.9344MHz 2 – VS 3 TRIM SONY CXD1125 1130 1135 XTAI LRCK DATA CKO XTI LRCI SM5813 DIN BCKI WCKO DOR OW20 CKDV XTO DOL BCKO 4 +VL 5 CLK 6 LE 7 DATA 8 – VL +V 16 S NR 2 15 ADJ 14 NR 1 13 AGND 12 I OUT 11 R F 10 DGND 9 NE5534 10µF 12V ANALOG SUPPLY 1µF + + LOW PASS FILTER RIGHT CHANNEL OUTPUT C210 PSSL SLOB AD1862 Figure 13. High Performance 20-Bit 8 × Oversampling CD Player Application REV. A –9– AD1862 HIGH-RESOLUTION SIGNAL PROCESSING Figure 14 illustrates the AD1862 combined with the DSP56000. In high-resolution applications, the combination of the 24-bit architecture of the DSP56000 and the low noise and high resolution of the AD1862 can produce a high-resolution, low-noise system. As shown in Figure 14, the clock signal supplied by the DSP processor must be inverted to be compatible with the input of the AD1862. The exact architecture of the output low-pass filter – 12V ANALOG SUPPLY depends on the sample rate of the output data. In general, the higher the oversampling rate, the fewer number of filter poles are required to prevent aliasing. The 20-bit resolution is particularly suitable for professional audio, mixing or equalization equipment. Its resolution allows 24 dB of equalization to be performed on 16-bit input words without signal truncation. Furthermore, up to sixteen 16-bit input words can be mixed and output directly to the AD1862. In this case, no loss of signal information would be encountered. 12V ANALOG SUPPLY 5V DIGITAL SUPPLY 0.1µF 1 2 – VS – VS + VS 16 NR 2 15 ADJ 14 NR 1 13 AGND 12 I OUT 11 R F 10 DGND 9 0.1µF 10µF 1µF 3 TRIM 0.1µF 4 +VL 5 CLK 6 LE 7 8 – 5V DIGITAL SUPPLY VDD DIGITAL COMMON 0.1µF DATA – VL AD846 LOW PASS FILTER OUTPUT VOLTAGE VCC SCK SC2 STD DSP56001 AD1862 ANALOG COMMON Figure 14. DSP56001 and AD1862 Produce High Resolution Signal Processing System –10– REV. A AD1862 OTHER DIGITAL AUDIO COMPONENTS AVAILABLE FROM ANALOG DEVICES –VS DGND +VL NC CLK LE DATA –VL 1 2 3 4 5 6 7 8 16-BIT LATCH 16-BIT DAC 16 +VS 15 TRIM SERIAL INPUT REGISTER IOUT CONTROL LOGIC AD1856 16-Bit Audio DAC 14 MSB ADJ 13 I OUT 12 AGND 11 SJ 10 RF Complete, No External Components Required 0.0025% THD Low Cost 16-Pin DIP or SOIC Package Standard Pinout AD1856 NC = NO CONNECT 9 VOUT –VS DGND +VL NC CLK LE DATA –VL 1 2 3 4 5 6 7 8 18-BIT LATCH 18-BIT DAC 16 +VS 15 TRIM SERIAL INPUT REGISTER IOUT CONTROL LOGIC 14 MSB ADJ 13 I OUT 12 AGND 11 SJ 10 RF AD1860 18-Bit Audio DAC Complete, No External Components Required 0.002% THD+N 108 dB Signal-to-Noise Ratio 16-Pin DIP or SOIC Package AD1860 NC = NO CONNECT 9 VOUT –VS TRIM MSB IOUT AGND SJ RF VOUT +VL 1 2 3 4 5 6 7 8 9 18-BIT DAC AD1864 REFERENCE REFERENCE 24 +VS 23 TRIM 22 MSB 21 IOUT 20 AGND 19 SJ 18 RF 17 VOUT 16 –VL AD1864 Dual 18-Bit Audio DAC Complete, No External Components 0.002% THD+N 115 dB Channel Separation 24-Pin DIP DR 10 LR 11 CK 12 18-BIT LATCH 18-BIT DAC 18-BIT LATCH 15 DL 14 LL 13 DGND REV. A –11– AD1862 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Plastic DIP (N-16) C1445–7–9/90 –12– REV. A PRINTED IN U.S.A.