AD1866RZ-REEL

a FEATURES Dual Serial Input, Voltage Output DACs Single +5 Volt Supply 0.005% THD+N Low Power –50 mW 115 dB Channel Separation Operates at 83 Oversampling 16-Pin Plastic DIP or SOIC Package APPLICATIONS Multimedia Workstations PC Audio Add-In Boards Portable CD and DAT Players Automotive CD and DAT Players Noise Cancellation Single Supply Dual 16-Bit Audio DAC AD1866 FUNCTIONAL BLOCK DIAGRAM 16-BIT V L 1 DAC LL 2 DL 3 16-BIT SERIAL REGISTER CLK 4 DR 5 LR 6 DGND 7 VBR AD1866 V REF 16-BIT SERIAL REGISTER VREF 16 VBL 15 VS 14 VOL 13 NRL 12 AGND 11 NRR 10 VOR 9 VS 16-BIT DAC 8 PRODUCT DESCRIPTION The AD1866 is a complete dual 16-bit DAC offering excellent performance while requiring a single +5 V power supply. It is fabricated on Analog Devices’ ABCMOS wafer fabrication process. The monolithic chip includes CMOS logic elements, bipolar and MOS linear elements and laser trimmed, thinfilm resistor elements. Careful design and layout techniques have resulted in low distortion, low noise, high channel separation and low power dissipation. The DACs on the AD1866 chip employ a partially segmented architecture. The first three MSBs of each DAC are segmented into 7 elements. The 13 LSBs are produced using standard R-2R techniques. The segments and R-2R resistors are laser trimmed to provide extremely low total harmonic distortion. The AD1866 requires no deglitcher or trimming circuitry. The AD1866 operates on +5 V power supplies. The digital supply, VL, can be separated from the analog supply, VS, for reduced digital feedthrough. Separate analog and digital ground pins are also provided. In systems employing a single +5 volt power supply, VL and VS should be connected together. In battery operated systems, operation will continue even with reduced supply voltage. Typically, the AD1866 dissipates 50 mW. The AD1866 is packaged in either a 16-pin plastic DIP or a 16-pin plastic SOIC package. Operation is guaranteed over the temperature range of –35°C to +85°C and over the voltage supply range of 4.75 V to 5.25 V. PRODUCT HIGHLIGHTS 1. Single supply operation @ +5 V. Each DAC is equipped with a high performance output amplifier. These amplifiers achieve fast settling and high slew rate, producing ± 1 V signals at load currents up to ± 1 mA. The buffered output signal range is 1.5 V to 3.5 V. The 2.5 V reference voltages eliminate the need for “false ground” networks. 2. 50 mW power dissipation. A versatile digital interface allows the AD1866 to be directly connected to all digital filter chips. Fast CMOS logic elements allow for an input clock rate of up to 16 MHz. This allows for operation at 2×, 4×, 8×, or 16× the sampling frequency (where FS = 44.1 kHz) for each channel. The digital input pins of the AD1866 are TTL and +5 V CMOS compatible. 6. Compatible with all digital filter chips. 3. THD+N is 0.005% (typical). 4. Signal-to-Noise Ratio is 95 dB (typical). 5. 115 dB channel separation (typical). 7. 16-pin DIP and 16-pin SOIC packages. 8. No deglitcher required. 9. No external adjustments required. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD1866–SPECIFICATIONS (T = +258C and +5 V supplies unless otherwise noted) A Min RESOLUTION Typ Max 16 DIGITAL INPUTS VIH VIL IIH, VIH = VL IIL, VIL = DGND Maximum Clock Input Frequency Unit Bits 2.4 0.8 1.0 –10.0 13.5 V V µA µA MHz ACCURACY Gain Error Gain Matching Midscale Error Midscale Error Matching Gain Linearity Error ±3 ±3 ± 30 ± 10 ±3 % of FSR % of FSR mV mV dB DRIFT (0°C to +70°C) Gain Drift Midscale Drift ± 100 –130 ppm/°C µV/°C TOTAL HARMONIC DISTORTION + NOISE 0 dB, 990.5 Hz AD1866N AD1866R –20 dB, 990.5 Hz AD1866N AD1866R –60 dB, 990.5 Hz AD1866N AD1866R 0.005 0.005 0.02 0.02 2.0 2.0 CHANNEL SEPARATION (1 kHz, 0 dB) 108 0.01 0.01 % % % % % % 115 dB SIGNAL-TO-NOISE RATIO (With A-Weight Filter) 95 dB D-RANGE (With A-Weight Filter) 90 dB ±1 0.1 ±1 V Ω mA +2.5 350 V Ω OUTPUT Voltage Output Pins (VOL, VOR) Output Range (± 3%) Output Impedance Load Current Bias Voltage Pins (VBL, VBR) Output Range Output Impedance POWER SUPPLY Specification, VL and VS Operation, VL and VS +I, VL and VS = 5 V 4.75 3.5 POWER DISSIPATION TEMPERATURE RANGE Operation Storage –35 –60 5 10 5.25 5.25 14 V V mA 50 70 mW 85 100 °C °C Specifications subject to change without notice. Specifications in boldface are tested on all production units at final electrical –2– REV. 0 Typical Performance–AD1866 6 –30 –35°C 4 –40 GAIN LINEARITY ERROR – dB –60dB THD+N – dB –50 –60 –70 –80 –20dB –90 0dB 5500 –2 70°C –4 125°C 15500 10500 25°C 0 –6 –8 –100 –100 500 0°C 2 20500 –80 –60 –40 FREQUENCY – Hz 20 0 Figure 4. Gain Linearity Error vs. Input Amplitude Figure 1. THD+N vs. Frequency –30 125 –60dB –40 124 –50 THD+N – dB CHANNEL SEPARATION – dB –20 INPUT AMPLITUDE – dB 123 122 –60 –70 –20dB –80 121 –90 0dB –100 120 –75 102 103 104 105 –50 –25 0 25 50 75 100 125 TEMPERATURE – °C FREQUENCY – Hz Figure 5. THD+N vs. Temperature Figure 2. Channel Separation vs. Frequency 80 –30 –40 –60dB 70 PSRR – dB THD+N – dB –50 –60 60 –70 –20dB 50 –80 –90 0dB 40 103 –100 4.4 4.6 4.8 5.0 5.2 SUPPLY VOLTAGE 5.4 5.6 105 Figure 6. Power Supply Rejection Ratio vs. Frequency (Supply Modulation Amplitude at 500 mV p-p) Figure 3. THD+N vs. Supply Voltage REV. 0 104 FREQUENCY – Hz –3– AD1866 *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ABSOLUTE MAXIMUM RATINGS* VL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 6 V VS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 6 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 0.3 V Digital Inputs to DGND . . . . . . . . . . . . . . . . . . . –0.3 V to VL Soldering (10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1866 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. PIN CONFIGURATION 16-BIT V L 1 LL 2 DL 3 CLK 4 DR 5 LR 6 DGND 7 VBR 8 16-BIT SERIAL REGISTER V REF 16-BIT SERIAL REGISTER V REF 16 VBL 15 VS 14 VOL 13 NRL 12 AGND 11 NRR 10 VOR 9 VS 16-BIT DAC ESD SENSITIVE DEVICE PIN DESIGNATIONS AD1866 DAC WARNING! Pin Mnemonic Description 11 12 13 14 15 16 17 18 19 10 11 12 13 14 15 16 VL LL DL CLK DR LR DGND VBR VS VOR NRR AGND NRL VOL VS VBL Digital Supply (+5 V) Left Channel Latch Enable Pin Left Channel Data Input Pin Clock Input Pin Right Channel Data Input Pin Right Channel Latch Enable Pin Digital Common Pin Right Channel Bias Pin Analog Supply (+5 V) Right Channel Output Pin Right Channel Noise Reduction Pin Analog Common Pin Left Channel Noise Reduction Pin Left Channel Output Pin Analog Supply (+5 V) Left Channel Bias Pin ORDERING GUIDE Model Temperature Range Package Description Package Option AD1866N AD1866R AD1866R-REEL –35°C to +85°C –35°C to +85°C –35°C to +85°C Plastic DIP SOIC SOIC N-16 R-16 R-16 –4– REV. 0 Definition of Specifications–AD1866 TOTAL HARMONIC DISTORTION + NOISE FUNCTIONAL DESCRIPTION Total harmonic distortion plus noise (THD+N) is defined as the ratio of the square root of the sum of the squares of the amplitudes of the harmonics and noise to the amplitude of the fundamental input frequency. It is usually expressed in percent (%) or decibels (dB). The AD1866 is a complete, monolithic dual 16-bit digital audio DAC which runs off a single +5 volt supply. As shown in the block diagram, each channel contains a voltage reference, a 16-bit serial-to-parallel input register, a 16-bit input latch, a 16-bit DAC, and an output amplifier. The voltage reference section provides a reference voltage and a false ground voltage for each channel. The low noise bandgap circuits produce reference voltages that are unaffected by changes in temperature, time, and power supply. D-RANGE DISTORTION (EIAJ SPECIFICATION) D-Range distortion is the ratio of the amplitude of the signal at an amplitude of –60 dB to the amplitude of the distortion plus noise. In this case, an A-weight filter is used. The value specified for D-range performance is the ratio measured plus 60 dB. The input registers are fabricated with CMOS logic gates. These gates allow high switching speeds and low power consumption, contributing to the fast digital timing, the low glitch and low power dissipation of the AD1866. SIGNAL-TO-NOISE RATIO The signal-to-noise ratio is defined as the ratio of the amplitude of the output when a full-scale output is present to the amplitude of the output with no signal present. It is expressed in decibels (dB) and measured using an A-weight filter. 16-BIT GAIN LINEARITY Gain linearity is a measure of the deviation of the actual output amplitude from the ideal output amplitude. It is determined by measuring the amplitude of the output signal as the amplitude of that output signal is digitally reduced to a lower level. A perfect D/A converter exhibits no difference between the ideal and actual amplitudes. Gain linearity is expressed in decibels (dB). VL 1 LL 2 DL 3 CLK 4 DR 5 LR 6 DGND 7 VBR 8 AD1866 DAC 16 VBL 16-BIT SERIAL REGISTER 15 VS 14 VOL 13 NRL 12 AGND 11 NRR 10 VOR 9 VS VREF 16-BIT SERIAL REGISTER VREF MIDSCALE ERROR Midscale error, or bipolar zero error, is the deviation of the actual analog output from a voltage at the bias pin when the twos complement input code representing midscale is loaded in the DAC. Midscale error is expressed in mV. 16-BIT DAC AD1866 Functional Block Diagram The 16-bit DAC uses a combination of segmentation and R-2R architecture to achieve good integral and differential linearity. The resistors which form the ladder structure are fabricated with silicon-chromium thin film. Laser trimming of these resistors further reduces linearity error, resulting in low output distortion. The output amplifier uses both MOS and bipolar devices and incorporates an NPN class A output stage. It is designed to produce high slew rate, low noise, low distortion, and optimal frequency response. REV. 0 –5– AD1866–Analog Circuit Considerations GROUNDING RECOMMENDATIONS POWER SUPPLY The AD1866 has two ground pins, designated as AGND (Pin 12) and DGND (Pin 7). The analog ground, AGND, serves as the “high quality” reference ground for analog signals and as a return path for the supply current from the analog portion of the device. The system analog common should be located as close as possible to Pin 12 to minimize any voltage drop which may develop between these two points, although the internal circuit is designed to minimize signal dependence of the analog return current. The digital ground, DGND, returns ground current from the digital logic portion of the device. This pin should be connected to the digital common node in the system. As shown in Figure 7, the analog and digital grounds should be joined at one point in a system. When these two grounds are connected such as at the power supply ground, care should be taken to minimize the voltage difference between the DGND and AGND pins in order to ensure the specified performance. 1 VL 2 AD1866 VBL 16 LL VS 15 3 DL VOL 14 4 CLK NRL 13 5 DR AGND 12 6 LR NRR 11 7 DGND VOR 10 8 VBR VS 9 4.7µF + – 4.7µF POWER SUPPLIES AND DECOUPLING The AD1866 has three power supply input pins. VS (Pins 9 and 15) provide the supply voltages which operate the analog portion of the device including the 16-bit DACs, the voltage references, and the output amplifiers. The VS supplies are designed to operate from a +5 V supply. These pins should be decoupled to the analog ground using a 0.1 µF capacitor. Good engineering practice suggests that the bypass capacitor be placed as close as possible to the package pins. This minimizes the inherent inductive effects of printed circuit board traces. + – (CAPACITOR VALUES ARE 0.1 µF UNLESS OTHERWISE INDICATED) Figure 7. Recommended Circuit Schematic NOISE REDUCTION CAPACITORS The AD1866 has two noise reduction pins, designated as NRL (Pin 13) and NRR (Pin 11). In order to meet specifications, it is required that external noise reduction capacitors be connected from these pins to AGND to reduce the output noise contributed by the voltage reference circuitry. As shown in Figure 7, each of these pins should be bypassed to AGND with a 4.7 µF or larger capacitor. The connections between the capacitors, package pins and AGND should be as short as possible to achieve the lowest noise. VL (Pin 1) operates the digital portions of the chip including the input shift registers and the input latching circuitry. VL is also designed to operate from a +5 V supply. This pin should be bypassed to digital common using a 0.1 µF capacitor, again placed as close as possible to the package pins. Figure 7 illustrates the correct connection of the digital and analog supply bypass capacitors. An important feature of the AD1866 audio DAC is its ability to operate at diminished power supply voltages. This feature is very important in portable battery operated systems. As the batteries discharge, the supply voltage drops. Unlike any other audio DAC, the AD1866 can continue to function at supply voltages as low as 3.5 V. Because of its unique design, the power requirements of the AD1866 diminish as the battery voltage drops, further extending the operating time of the system. USING VBL AND VBR The AD1866 has two bias voltage reference pins, designated as VBR (Pin 8) and VBL (Pin 16). Each of these pins supplies a dc reference voltage equal to the center of the output voltage swing. These bias voltages replace “false ground” networks previously required in single supply audio systems. At the same time, they allow dc coupled systems, improving audio performance. –6– REV. 0 Analog Circuit Considerations–AD1866 AD1866 1 VL VBL 16 2 LL VS + 5V VOR VOL + 5V FALSE GROUND (2.5V) 15 3 DL VOL 14 4 CLK NRL 13 5 DR AGND 12 6 LR NRR 11 7 DGND VOR 10 8 VBR VS 9 +5V VOL +5V VOR + 5V VOR VOL Figure 8b. Circuitry Using Voltage Biases Figure 8a. Schematic Using False Ground DISTORTION PERFORMANCE AND TESTING The THD+N figure of an audio DAC represents the amount of undesirable signal produced during reconstruction and playback of an audio waveform. Therefore, the THD+N specification provides a direct measure to classify and choose an audio DAC for a desired level of performance. Figure 1 illustrates the typical THD+N versus frequency performance of the AD1866. It is evident that the THD+N performance of the AD1866 remains stable at all three amplitude levels through a wide range of frequencies. A load impedance of at least 2 kΩ is recommended for best THD+N performance. Figure 8a illustrates the traditional approach used to generate false ground voltages in single supply audio systems. This circuit requires additional power and circuit board space. The AD1866 eliminates the need for “false ground” circuitry. VBR and VBL generate the required bias voltages previously generated by the “false ground.” As shown in Figure 8b, VBR and VBL may be used as the reference point in each output channel. This permits a dc coupled output signal path. This eliminates ac coupling capacitors and improves low frequency performance. It should be noted that these bias outputs have relatively high output impedance and will not drive output currents larger than 100 µA without degrading the specified performance. REV. 0 Analog Devices tests all AD1866s on the basis of THD+N performance. During the distortion test, a high speed digital pattern generator transmits digital data to each channel of the device under test. Sixteen-bit data is latched into the DAC at 352.8 kHz (8 × FS). The test input code is a digitally encoded 990.5 Hz sine wave with 0 dB, –20 dB, and –60 dB amplitudes. A 4096 point FFT calculates total harmonic distortion + noise, signal-to-noise ratio, and D-range. No deglitchers or external adjustments are used. –7– AD1866–Digital Circuit Considerations CLK DL M S B L S B DR M S B L S B LL LR Figure 9. AD1866 Control Signals INPUT DATA >30ns The digital input port of the AD1866 employs five signals: Data Left (DL), Data Right (DR), Latch Left (LL), Latch Right (LR), and Clock (CLK). DL and DR are the serial inputs for the left and right DACs, respectively. Input data bits are clocked into the input register on the rising edge of CLK. The falling edges of LL and LR cause the last 16 bits which were clocked into the serial registers to be shifted into the DACs, thereby updating the respective DAC outputs. For systems using only a single latch signal, LL and LR may be connected together. For systems using only one DATA signal, DR and DL may be connected together. Data is transmitted to the AD1866 in a bit stream composed of 16-bit words with a serial, twos complement, MSB first format. Left and right channels share the Clock (CLK) signal. DR/DL >40ns CLK >30ns Figure 10 illustrates the specific timing requirements that must be met in order for the data transfer to be accomplished properly. The input pins of the AD1866 are both TTL and +5 V CMOS compatible. >30ns >15ns >67ns LR/LL >40ns Figure 9 illustrates the general signal requirements for data transfer for the AD1866. TIMING >10ns >10ns >40ns Figure 10. AD1866 Input Signal Timing The maximum clock rate of the AD1866 is specified to be at least 13.5 MHz. This clock rate allows data transfer rates of 2×, 4×, 8×, and 16× FS (where FS equals 44.1 kHz). The applications section of this data sheet contains additional guidelines for using the AD1866. –8– REV. 0 Applications of the AD1866 APPLICATIONS OF THE AD1866 In summary, the AD1866 is an excellent choice for multimedia, battery operated portable or automotive digital audio systems. In the following sections, some examples of high performance audio applications featuring the AD1866 are described. The AD1866 is a high performance audio DAC specifically designed for portable and automotive digital audio applications. These market segments have technical requirements fundamentally different than those found in the high-end or home use market segment. Portable equipment must rely on components which require low amounts of power to offer reasonable playback times. Also, battery voltage tends to diminish as the end of the discharge cycle is approached. The AD1866’s ability to operate from a single +5 V supply makes it a good choice for battery operated gear. And, as the battery voltage drops, the power dissipation of the AD1866 drops. This extends the usable battery life. Finally, as the battery supply voltage drops, the bias voltages and signal swings also drop, preventing signal clipping and abrupt degradation of distortion. Figure 3 illustrates how the THD+N performance of the AD1866 remains constant through a wide supply voltage range. AD1866 with the Sony CXD2550P Digital Filter Figure 11 illustrates a 16-bit CD player design incorporating an AD1866 DAC, a Sony CXD2550P digital filter, and 2-pole antialias filters. This high performance, single supply design operates at 8× FS and is suitable for portable and automotive applications. In this design, the CXD2550P filter transmits left and right channel digital data to the AD1866. The left and right latch signals, LL and LR, are both provided by the word clock signal (LRCKO) of the digital filter. The digital data is converted to low distortion output voltages by the output amplifiers on the AD1866. Also, no deglitching circuitry or external adjustments are required. Bypass capacitors, noise reduction capacitors and the antialias filter details are omitted for clarity. Automotive equipment relies on components which are able to consistently perform over a wide range of temperatures. In addition, due to the limited space available in automotive applications, small size is essential. The AD1866 has guaranteed operation between –35°C and +85°C, and the 16-pin DIP or 16-pin SOIC package is particularly attractive where overall size is important. ADDITIONAL APPLICATIONS In addition to CD player designs, the AD1866 is suited for similar applications such as DAT, portable musical instruments, laptop and notebook personal computers, and PC audio I/O boards. The circuit techniques illustrated here are directly applicable in those applications. Figures 12, 13, 14, and 15 show connection diagrams for the AD1866 and several popular digital filter chips from NPC and Yamaha. Each application operates at 8× FS operation. Please refer to the appropriate sections of this data sheet for additional information. Since the AD1866 provides dc bias voltages, the entire signal chain can be dc coupled. This eliminates ac coupling capacitors from the signal path, improving low frequency performance and lowering system cost and size. +5V POWER SUPPLY CXD2550P 1 TEST 2 LEFT CHANNEL OUTPUT AD1866 SLOT 18 1 VL VBL 16 LRCKO 17 2 LL VS 15 NJM2100 6.8kΩ 6.8kΩ 3 DATAL 16 3 DL VOL 14 4 DATAR 15 4 CLK NRL 13 VSS 14 5 DR AGND 12 6 BCKO 13 6 LR NRR 11 7 VSS 12 7 DGND VOR 10 8 VBR VS 9 5 8 9 VDD 11 LRCK LATCH 330 pF 1 8 2 7 3 6 4 5 6.8kΩ 1000 pF 330 pF RIGHT CHANNEL OUTPUT 6.8kΩ 6.8kΩ 6.8kΩ 1000 pF 10 Figure 11. AD1866 with Sony CXD2550P Digital Filter REV. 0 +VS –9– AD1866 1 28 2 27 SM5813 3 BCKO 26 4 WCKO 25 5 DOL 24 6 DOR 23 7 VDD 22 VSS2 21 VSS1 8 +5V POWER SUPPLY 9 20 10 19 AD1866 VL 2 LL VS 15 3 DL VOL 14 4 CLK NRL 13 DR AGND 12 LR NRR 11 5 6 11 18 12 OW18 17 13 OW20 16 14 COB 15 VBL 16 1 7 DGND 8 VBR VOR 10 VS 9 LOWPASS FILTER LOWPASS FILTER LEFT CHANNEL OUTPUT RIGHT CHANNEL OUTPUT Figure 12. AD1866 with NPC SM5813 Digital Filter +5V POWER SUPPLY SM5818AP 1 VDD 16 2 BCKO 15 3 WDCO 4 AD1866 1 VL VBL 16 2 LL VS 15 14 3 DL VOL 14 13 4 CLK NRL 13 5 DOR 12 5 DR AGND 12 6 DOL 11 6 LR NRR 11 7 DGND 8 VBR 7 8 10 V SS OMOD1 9 VOR 10 VS LOW PASS FILTER LOW PASS FILTER LEFT CHANNEL OUTPUT RIGHT CHANNEL OUTPUT 9 Figure 13. AD1866 with NPC SM5818AP Digital Filter –10– REV. 0 Applications–AD1866 +5V POWER SUPPLY YM3434 1 2 16/18 15 3 ST 14 4 AD1866 16 1 VL VBL 16 2 LL VS 15 3 DL VOL 14 NRL 13 VSS 13 5 BCO 12 5 DR AGND 12 6 WCO 11 6 LR NRR 11 DRO 10 7 DGND DLO 9 8 VBR VDD 2 7 8 VDD1 4 CLK VOR 10 VS LOWPASS FILTER LEFT CHANNEL OUTPUT LOWPASS FILTER RIGHT CHANNEL OUTPUT 9 Figure 14. AD1866 with Yamaha YM3434 Digital Filter +5V POWER SUPPLY DI N 1 AD1866 18 1 VL VBL 16 17 2 LL VS 15 16 3 DL VOL 14 BCK 15 BCKO O 4 CLK NRL 13 14 VVD DD D 5 DR AGND 12 WCKO WCK 13 O 6 LR NRR 11 7 DOL DO 12 L 7 DGND VOR 10 8 DOR DO R 8 VBR 2 3 SM5840A/B BCKO 4 5 VSS 6 OW20 9 D G 11 VS 9 10 10 Figure 15. AD1866 with NPC SM5840C Digital Filter REV. 0 –11– LOWPASS FILTER LEFT CHANNEL OUTPUT LOWPASS FILTER RIGHT CHANNEL OUTPUT AD1866 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Plastic DIP (N) Package Plastic SOIC (R) Package 9 0.25 0.31 (6.35) (7.87) 1 9 16 8 0.419 (10.65) 0.299 (7.60) 0.87 (22.1) MAX 0.035 (0.89) 0.18 (4.57) MAX 8 1 0.125 (3.18) MIN 0.18 (4.57) 0.011 (0.28) 0.413 (10.50) 0.3 (7.62) 0.033 (0.84) 0.1 (2.54) 0.104 (2.65) 0.012 (0.3) 0.05 (1.27) REF 0.019 (0.49) 0.030 (0.75) 0.013 (0.32) 0.042 (1.07) PRINTED IN U.S.A. 0.018 (0.46) C1590–10–12/91 16 –12– REV. 0