AD1870

a FEATURES Single 5 V Power Supply Single-Ended Dual-Channel Analog Inputs 92 dB (Typ) Dynamic Range 90 dB (Typ) S/(THD + N) 0.006 dB Decimator Pass-Band Ripple Fourth Order, 64 Oversampling - Modulator Three-Stage, Linear-Phase Decimator 256 fS or 384 fS Input Clock Less than 100 W (Typ) Power-Down Mode Input Overrange Indication On-Chip Voltage Reference Flexible Serial Output Interface 28-Lead SOIC Package APPLICATIONS Consumer Digital Audio Receivers Digital Audio Recorders, Including Portables CD-R, DCC, MD, and DAT Multimedia and Consumer Electronics Equipment Sampling Music Synthesizers LRCK WCLK BCLK DVDD1 DGND1 RDEDGE S/M 384/256 AVDD 1 2 3 4 5 6 7 8 9 Single-Supply 16-Bit - Stereo ADC AD1870* FUNCTIONAL BLOCK DIAGRAM SERIAL OUTPUT INTERFACE CLOCK DIVIDER 28 27 26 THREE-STAGE FIR DECIMATION FILTER THREE-STAGE FIR DECIMATION FILTER 25 CLKIN TAG SOUT DVDD2 24 DGND2 23 RESET MSBDLY RLJUST AGND VINR CAPR1 CAPR2 AGNDR VREFR DAC DAC DAC DAC 22 21 20 19 18 VINL 10 CAPL1 11 CAPL2 12 AGNDL 13 VREFL 14 SINGLE-TODIFFERENTIAL INPUT CONVERTER SINGLE-TODIFFERENTIAL INPUT CONVERTER 17 16 15 VOLTAGE REFERENCE AD1870 PRODUCT OVERVIEW The AD1870 is a stereo, 16-bit oversampling ADC based on sigma-delta ( - ) technology intended primarily for digital audio bandwidth applications requiring a single 5 V power supply. Each single-ended channel consists of a fourth order one-bit noise shaping modulator and a digital decimation filter. An on-chip voltage reference, stable over temperature and time, defines the full-scale range for both channels. Digital output data from both channels are time multiplexed to a single, flexible serial interface. The AD1870 accepts a 256 × fS or a 384 × fS input clock (fS is the sampling frequency) and operates in both serial port Master and Slave Modes. In Slave Mode, all clocks must be externally derived from a common source. Input signals are sampled at 64 × fS onto internally buffered switched capacitors, eliminating external sample-and-hold amplifiers and minimizing the requirements for antialias filtering at the input. With simplified antialiasing, linear phase can be preserved across the pass band. The on-chip single-ended-to-differential signal converters save the board designer from having to provide them externally. The AD1870’s internal differential architecture provides increased dynamic range and excellent power supply rejection characteristics. The AD1870’s proprietary fourth order differential switched-capacitor - modulator architecture *Protected by U.S. Patent Numbers 5055843, 5126653; others pending. shapes the one-bit comparator’s quantization noise out of the audio pass band. The high order of the modulator randomizes the modulator output, reducing idle tones in the AD1870 to very low levels. Because its modulator is single bit, the AD1870 is inherently monotonic and has no mechanism for producing differential linearity errors. The input section of the AD1870 uses autocalibration to correct any dc offset voltage present in the circuit, provided that the inputs are ac-coupled. The single-ended dc input voltage can swing between 0.7 V and 3.8 V typically. The AD1870 antialias input circuit requires four external 470 pF NPO ceramic chip filter capacitors, two for each channel. No active electronics are needed. Decoupling capacitors for the supply and reference pins are also required. The dual-digital decimation filters are triple-stage, finite impulse response filters for effectively removing the modulator’s high frequency quantization noise and reducing the 64 × fS single-bit output data rate to an fS word rate. They provide linear phase and a narrow transition band that properly digitizes 20 kHz signals at a 44.1 kHz sampling frequency. Pass-band ripple is less than 0.006 dB, and stop-band attenuation exceeds 90 dB. (Continued on Page 7) REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 AD1870–SPECIFICATIONS TEST CONDITIONS UNLESS OTHERWISE NOTED 5.0 V 25 °C 12.288 MHz 991.768 Hz –0.5 dB Full Scale Measurement Bandwidth 23.2 Hz to 19.998 kHz Load Capacitance on Digital Outputs 50 pF 2.4 V Input Voltage HI (VIH) Input Voltage LO (VIL) 0.8 V Master Mode, Data I2S-Justified (Refer to Figure 14). Device Under Test (DUT) bypassed and decoupled as shown in Figure 3. DUT is antialiased and ac-coupled as shown in Figure 2. DUT is calibrated. Values in bold typeface are tested; all others are guaranteed but not tested. Supply Voltages Ambient Temperature Input Clock (fCLKIN) [256 × fS] Input Signal ANALOG PERFORMANCE Min Resolution Dynamic Range (20 Hz to 20 kHz, –60 dB Input) Without A-Weight Filter With A-Weight Filter Signal to (THD + Noise) Signal to THD Analog Inputs Single-Ended Input Range (± Full Scale)* Input Impedance at Each Input Pin VREF DC Accuracy Gain Error Interchannel Gain Mismatch Gain Drift Midscale Offset Error (After Calibration) Midscale Drift Crosstalk (EIAJ Method) *VIN p-p = VREF × 1.326. Typ 16 Max Unit Bits dB dB dB dB V kΩ V % dB ppm/°C LSBs LSB/°C dB 89 92 86.5 93 96 90.5 94 VREF ± 1.49 32 2.25 ± 0.5 0.05 115 ±3 –0.2 –110 2.05 2.55 2.5 20 –100 Minimum Input = VREF V –  REF   VREF   × 1.326  2     Maximum Input = VREF + × 1.326  2 –2– REV. A AD1870 DIGITAL I/O Min Input Voltage HI (VIH) Input Voltage LO (VIL) Input Leakage (IIH @ VIH = 5 V) Input Leakage (IIL @ VIL = 0 V) Output Voltage HI (VOH @ IOH = –2 mA) Output Voltage LO (VOL @ IOL = 2 mA) Input Capacitance 2.4 Typ Max 0.8 10 10 Unit V V µA µA V V pF 2.4 0.4 15 DIGITAL TIMING (Guaranteed over –40 °C to +85°C, DVDD = AVDD = 5 V ± 5%. Refer to Figures 17–19.) Min tCLKIN fCLKIN tCPWL tCPWH tRPWL tBPWL tBPWH tDLYCKB tDLYBLR tDLYBWR tDLYBWF tDLYDT tSETLRBS tDLYLRDT tSETWBS tDLYBDT CLKIN Period CLKIN Frequency (1/tCLKIN) CLKIN LO Pulsewidth CLKIN HI Pulsewidth RESET LO Pulsewidth BCLK LO Pulsewidth BCLK HI Pulsewidth CLKIN Rise to BCLK Xmit (Master Mode) BCLK Xmit to LRCK Transition (Master Mode) BCLK Xmit to WCLK Rise BCLK Xmit to WCLK Fall BCLK Xmit to DATA/TAG Valid (Master Mode) LRCK Setup to BCLK Sample (Slave Mode) LRCK Transition to DATA/TAG Valid (Slave Mode) No MSB Delay Mode (for MSB Only) WCLK Setup to BCLK Sample (Slave Mode) Data Position Controlled by WCLK Input Mode BCLK Xmit to DATA/TAG Valid (Slave Mode) All Bits Except MSB in No MSB Delay Mode All Bits in MSB Delay Mode 48 1.28 15 15 50 15 15 Typ 81 12.288 Max 780 20.48 Unit ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns 15 15 10 10 10 10 40 10 40 ns POWER Min Supplies Voltage, Analog and Digital Analog Current Analog Current–Power-Down (CLKIN Running) Digital Current Digital Current–Power-Down (CLKIN Running) Dissipation Operation–Both Supplies Operation–Analog Supply Operation–Digital Supply Power-Down–Both Supplies (CLKIN Running) Power-Down–Both Supplies (CLKIN Not Running) Power Supply Rejection (See TPC 5) 1 kHz 300 mV p-p Signal at Analog Supply Pins 20 kHz 300 mV p-p Signal at Analog Supply Pins Stop Band (>0.55 × fS)—any 300 mV p-p Signal 4.75 Typ 5 43 25 9.3 50 263 216 47 375 375 90 68 110 Max 5.25 52 12 Unit V mA µA mA µA mW mW mW µW µW dB dB dB 315 260 55 REV. A –3– AD1870 TEMPERATURE RANGE Min Specifications Guaranteed Functionality Guaranteed Storage DIGITAL FILTER CHARACTERISTICS Typ +25 Max +85 +100 Unit °C °C °C –40 –60 Min Decimation Factor Pass-Band Ripple Stop-Band* Attenuation 48 kHz fS (at Recommended Crystal Frequencies) Pass Band Stop Band 44.1 kHz fS (at Recommended Crystal Frequencies) Pass Band Stop Band 32 kHz fS (at Recommended Crystal Frequencies) Pass Band Stop Band Other fS Pass Band Stop Band Group Delay Group Delay Variation Typ 64 Max 0.006 Unit dB dB kHz kHz kHz kHz kHz kHz fS fS s µs 90 0 26.4 0 24.25 0 17.6 0 0.55 21.6 20 14.4 0.45 36/fS 0 *Stop band repeats itself at multiples of 64 × fS, where fS is the output word rate. Thus the digital filter will attenuate to 0 dB across the frequency spectrum except for a range ± 0.55 × fS wide at multiples of 64 × fS. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS Min DVDD1 to DGND1 and DVDD2 to DGND2 AVDD to AGND/AGNDL/AGNDR Digital Inputs Analog Inputs AGND to DGND Reference Voltage Soldering (10 sec) 0 0 DGND – 0.3 AGND – 0.3 –0.3 Typ Max Unit V V V V V °C +6 +6 DVDD + 0.3 AVDD + 0.3 +0.3 Indefinite Short Circuit to Ground +300 ORDERING GUIDE Model AD1870AR AD1870AR–REEL EVAL-AD1870EB Temperature –40°C to +85°C –40°C to +85°C Package Description SOIC SOIC Evaluation Board Package Option R-28 R-28 in 13” Reel (1000 pcs.) CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1870 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE –4– REV. A AD1870 PIN FUNCTION DESCRIPTIONS Signal to Total Harmonic Distortion (S/THD) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Input/ Output I/O I/O I/O I I I I I I I O O I O O I O O I I I I I I I O O I Pin Name LRCK WCLK BCLK DVDD1 DGND1 RDEDGE S/M 384/256 AVDD VINL CAPL1 CAPL2 AGNDL VREFL VREFR AGNDR CAPR2 CAPR1 VINR AGND RLJUST MSBDLY RESET DGND2 DVDD2 SOUT TAG CLKIN Description Left/Right Clock Word Clock Bit Clock 5 V Digital Supply Digital Ground Read Edge Polarity Select Slave/Master Select Clock Mode 5 V Analog Supply Left Channel Input Left External Filter Capacitor 1 Left External Filter Capacitor 2 Left Analog Ground Left Reference Voltage Output Right Reference Voltage Output Right Analog Ground Right External Filter Capacitor 2 Right External Filter Capacitor 1 Right Channel Input Analog Ground Right/Left Justify Delay MSB One BCLK Period Reset Digital Ground 5 V Digital Supply Serial Data Output Serial Overrange Output Master Clock The ratio of the rms value of the fundamental input signal to the rms sum of all harmonically related spectral components in the pass band, expressed in decibels. Pass Band The region of the frequency spectrum unaffected by the attenuation of the digital decimator’s filter. Pass-Band Ripple The peak-to-peak variation in amplitude response from equalamplitude input signal frequencies within the pass band, expressed in decibels. Stop Band The region of the frequency spectrum attenuated by the digital decimator’s filter to the degree specified by stop-band attenuation. Gain Error With a near full-scale input, the ratio of actual output to expected output, expressed as a percentage. Interchannel Gain Mismatch With identical near full-scale inputs, the ratio of outputs of the two stereo channels, expressed in decibels. Gain Drift Change in response to a near full-scale input with a change in temperature, expressed as parts-per-million (ppm) per °C. Midscale Offset Error Output response to a midscale dc input, expressed in least significant bits (LSBs). Midscale Drift Change in midscale offset error with a change in temperature, expressed as parts-per-million (ppm) per °C. Crosstalk (EIAJ Method) Ratio of response on one channel with a grounded input to a full-scale 1 kHz sine wave input on the other channel, expressed in decibels. Power Supply Rejection DEFINITIONS Dynamic Range The ratio of a full-scale output signal to the integrated output noise in the pass band (20 Hz to 20 kHz), expressed in decibels (dB). Dynamic range is measured with a –60 dB input signal and is equal to (S/(THD + N)) 60 dB. Note that spurious harmonics are below the noise with a –60 dB input, so the noise level establishes the dynamic range. The dynamic range is specified with and without an A-Weight filter applied. Signal to Total Harmonic Distortion + Noise With no analog input, signal present at the output when a 300 mV p-p signal is applied to the power supply pins, expressed in decibels of full scale. Group Delay Intuitively, the time interval required for an input pulse to appear at the converter’s output, expressed in milliseconds (ms). More precisely, the derivative of radian phase with respect to radian frequency at a given frequency. Group Delay Variation (S/(THD + N)) The ratio of the root-mean-square (rms) value of the fundamental input signal to the rms sum of all other spectral components in the pass band, expressed in decibels. The difference in group delays at different input frequencies. Specified as the difference between the largest and smallest group delays in the pass band, expressed in microseconds (µs). REV. A –5– AD1870–Typical Performance Characteristics 0 –20 –80 –82 –84 –40 –60 –86 –88 d BFS dBFS –90 –92 –94 –96 –80 –100 –120 –98 –140 0 2 4 6 8 10 12 14 16 FREQUENCY – kHz 18 20 22 24 –100 –60 –50 –40 –30 –20 –10 –0.5 INPUT AMPLITUDE – dBFS TPC 1. 1 kHz Tone at –0.5 dBFS (16 k-Point FFT) TPC 4. THD + N vs. Input Amplitude at 1 kHz 0 –20 –60 –65 –70 –40 –75 dBFS d BFS –60 –80 –80 –85 –100 –90 –95 –100 –120 –140 0 2 4 6 8 10 12 14 16 18 20 22 24 FREQUENCY – kHz 0 2 4 6 8 10 12 14 FREQUENCY – kHz 16 18 20 TPC 2. 1 kHz Tone at –10 dBFS (16 k-Point FFT) TPC 5. Power Supply Rejection to 300 mV p-p on AVDD –80 –82 –84 –80 –85 –90 –86 –88 –95 d BFS d BFS –90 –92 –94 –100 –105 –110 –96 –98 –100 0 2 4 6 8 10 12 14 16 18 20 –115 –120 0 2 4 6 FREQUENCY – kHz 8 10 12 14 FREQUENCY – kHz 16 18 20 TPC 3. THD + N vs. Frequency at –0.5 dBFS TPC 6. Channel Separation vs. Frequency at –0.5 dBFS –6– REV. A AD1870 10 0 –10 –20 –30 –40 d BFS –50 –60 –70 –80 –90 - architectures “shape” the quantization noise-transfer function in a nonuniform manner. Through careful design, this transfer function can be specified to high-pass filter the quantization noise out of the audio band into higher frequency regions. The AD1870 also incorporates a feedback resonator from the fourth integrator’s output to the third integrator’s input. This resonator does not affect the signal transfer function but allows the flexible placement of a zero in the noise transfer function for more effective noise shaping. Oversampling by 64 simplifies the implementation of a high performance audio analog-to-digital conversion system. Antialias requirements are minimal; a single pole of filtering will usually suffice to eliminate inputs near fS and its higher multiples. 0.1 0.2 0.3 0.4 0.5 0.6 NORMALIZED fS 0.7 0.8 0.9 1.0 –100 –110 –120 0.0 TPC 7. Digital Filter Signal Transfer Function to fS (Continued from Page 1 ) The flexible serial output port produces data in two’s complement, MSB-first format. The input and output signals are TTL compatible. The port is configured by pin selections. Each 16-bit output word of a stereo pair can be formatted within a 32-bit field of a 64-bit frame as either right-justified, I2S compatible, word clock controlled, or left-justified positions. Both 16-bit samples can also be packed into a 32-bit frame, in left-justified and I2S compatible positions. The AD1870 is fabricated on a single monolithic integrated circuit using a 0.5 µm CMOS double polysilicon, double metal process and is offered in a plastic 28-lead SOIC package. Analog and digital supply connections are separated to isolate the analog circuitry from the digital supply and reduce digital crosstalk. The AD1870 operates from a single 5 V power supply over the temperature range of –40°C to +85°C and typically consumes less than 260 mW of power. THEORY OF OPERATION - Modulator Noise Shaping A fourth order architecture was chosen both to strongly shape the noise out of the audio band and to help break up the idle tones produced in all - architectures. These architectures have a tendency to generate periodic patterns with a constant dc input, a response that looks like a tone in the frequency domain. These idle tones have a direct frequency dependence on the input dc offset and an indirect dependence on temperature and time as it affects the dc offset. The AD1870 suppresses idle tones 20 dB or better below the integrated noise floor. The AD1870’s modulator was designed, simulated, and exhaustively tested to remain stable for any input within a wide tolerance of its rated input range. The AD1870 is designed to internally reset itself should it ever be overdriven, to prevent it from going unstable. It will reset itself within 5 µs at a 48 kHz sampling frequency after being overdriven. Overdriving the inputs will produce a waveform “clipped” to plus or minus full scale. See TPCs 1 through 6 for illustrations of the AD1870’s typical analog performance as measured by an Audio Precision System One. Signal-to-(distortion + noise) is shown under a range of conditions. Note that there is a small variance between the AD1870 analog performance specifications and some of the performance plots. This is because the Audio Precision System One measures THD and noise over a 20 Hz to 24 kHz bandwidth, while the analog performance is specified over a 20 Hz to 20 kHz bandwidth (i.e., the AD1870 performs slightly better than the plots indicate). The power supply rejection graph (TPC 5) illustrates the benefits of the AD1870’s internal differential architecture. The excellent channel separation shown in TPC 6 is the result of careful chip design and layout. Digital Filter Characteristics The stereo, internally differential, analog modulator of the AD1870 employs a proprietary feedforward and feedback architecture that passes input signals in the audio band with a unity transfer function yet simultaneously shapes the quantization noise generated by the one-bit comparator out of the audio band (see Figure 1). Without the - architecture, this quantization noise would be spread uniformly from dc to one-half the oversampling frequency, 64 × fS. VIN DAC MODULATOR BITSTREAM OUTPUT VIN SINGLE-TODIFFERENTIAL CONVERTER The digital decimator accepts the modulator’s stereo bit stream and simultaneously performs two operations on it. First, the decimator low-pass filters the quantization noise that the modulator shaped to high frequencies and filters any other out-ofaudio-band input signals. Second, it reduces the data rate to an output word rate equal to fS. The high frequency bit stream is decimated to stereo 16-bit words at 48 kHz (or other desired fS). The out-of-band one-bit quantization noise and other high frequency components of the bit stream are attenuated by at least 90 dB. The AD1870 decimator implements a symmetric finite impulse response (FIR) filter that possesses a linear phase response. This filter achieves a narrow transition band (0.1 × fS), high stop-band attenuation (>90 dB), and low pass-band ripple (