AD1928

2 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec AD1928 FEATURES PLL-generated or direct master clock Low EMI design 108 dB DAC/107 dB ADC dynamic range and SNR −94 dB THD + N 3.3 V single supply Tolerance for 5 V logic inputs Supports 24 bits and 8 kHz to 192 kHz sample rates Differential ADC input Single-ended DAC output Log volume control with autoramp function SPI® controllable for flexibility Software-controllable clickless mute Software power-down Right-justified, left-justified, I2S-justified, and TDM modes Master and slave modes up to 16-channel input/output 48-lead LQFP GENERAL DESCRIPTION The AD1928 is a high performance, single-chip codec that provides two analog-to-digital converters (ADCs) with differential input and eight digital-to-analog converters (DACs) with single-ended output using the Analog Devices, Inc., patented multibit sigma-delta (Σ-Δ) architecture. An SPI port is included, allowing a microcontroller to adjust volume and many other parameters. The AD1928 operates from 3.3 V digital and analog supplies. The AD1928 is available in a 48-lead (single-ended output) LQFP package. Other members of this family include a differential DAC output and I2C® control port versions. The AD1928 is designed for low EMI. This consideration is apparent in both the system and circuit design architectures. By using the on-board PLL to derive the master clock from the LR clock or from an external crystal, the AD1928 eliminates the need for a separate high frequency master clock and can be used with a suppressed bit clock. The digital-to-analog and analog-to-digital converters are designed using the latest Analog Devices continuous time architectures to further minimize EMI. By using 3.3 V supplies, power consumption is minimized, further reducing emissions. APPLICATIONS Automotive audio systems Home theater systems Set-top boxes Digital audio effects processors FUNCTIONAL BLOCK DIAGRAM DIGITAL AUDIO INPUT/OUTPUT AD1928 SERIAL DATA PORT DAC DAC QUAD DEC FILTER 48kHz/ 96kHz/ 192kHz SDATA OUT SDATA IN CLOCKS TIMING MANAGEMENT AND CONTROL (CLOCK AND PLL) DAC DIGITAL FILTER AND VOLUME CONTROL DAC DAC DAC DAC DAC PRECISION VOLTAGE REFERENCE CONTROL PORT SPI/I2C ANALOG AUDIO OUTPUTS ANALOG AUDIO INPUTS ADC ADC CONTROL DATA INPUT/OUTPUT Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. 06623-001 AD1928 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Test Conditions............................................................................. 3 Analog Performance Specifications ........................................... 3 Crystal Oscillator Specifications................................................. 5 Digital Input/Output Specifications........................................... 5 Power Supply Specifications........................................................ 5 Digital Filters................................................................................. 6 Timing Specifications .................................................................. 6 Absolute Maximum Ratings............................................................ 8 Thermal Resistance ...................................................................... 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Typical Performance Characteristics ........................................... 11 Theory of Operation ...................................................................... 13 Analog-to-Digital Converters (ADCs).................................... 13 Digital-to-Analog Converters (DACs) .................................... 13 Clock Signals............................................................................... 13 Reset and Power-Down ............................................................. 14 Serial Control Port ..................................................................... 14 Power Supply and Voltage Reference....................................... 15 Serial Data Ports—Data Format............................................... 15 Time-Division Multiplexed (TDM) Modes............................ 15 Daisy-Chain Mode ..................................................................... 19 Control Registers ............................................................................ 24 Definitions................................................................................... 24 PLL and Clock Control Registers............................................. 24 DAC Control Registers .............................................................. 25 ADC Control Registers.............................................................. 27 Additional Modes....................................................................... 29 Application Circuits ....................................................................... 30 Outline Dimensions ....................................................................... 31 Ordering Guide .......................................................................... 31 REVISION HISTORY 4/07—Revision 0: Initial Version Rev. 0 | Page 2 of 32 AD1928 SPECIFICATIONS TEST CONDITIONS Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. Supply voltages (AVDD, DVDD) Temperature range 1 Master clock Input sample rate Measurement bandwidth Word width Load capacitance (digital output) Load current (digital output) High level input voltage Low level input voltage 1 3.3 V As specified in Table 1 and Table 2 12.288 MHz (48 kHz fS, 256 × fS mode) 48 kHz 20 Hz to 20 kHz 24 bits 20 pF ±1 mA or 1.5 kΩ to ½ DVDD supply 2.0 V 0.8 V Functionally guaranteed at −40°C to +125°C case temperature. ANALOG PERFORMANCE SPECIFICATIONS Specifications guaranteed at an ambient temperature of 25°C. Table 1. Parameter ANALOG-TO-DIGITAL CONVERTERS ADC Resolution Dynamic Range No Filter (RMS) With A-Weighted Filter (RMS) Total Harmonic Distortion + Noise Full-Scale Input Voltage (Differential) Gain Error Interchannel Gain Mismatch Offset Error Gain Drift Interchannel Isolation CMRR Input Resistance Input Capacitance Input Common-Mode Bias Voltage DIGITAL-TO-ANALOG CONVERTERS Dynamic Range No Filter (RMS) With A-Weighted Filter (RMS) With A-Weighted Filter (Average) Total Harmonic Distortion + Noise Single-Ended Version Full-Scale Output Voltage Gain Error Interchannel Gain Mismatch Offset Error Gain Drift Rev. 0 | Page 3 of 32 Conditions All ADCs 20 Hz to 20 kHz, −60 dB input Min Typ 24 Max Unit Bits dB dB dB V rms % dB mV ppm/°C dB dB dB kΩ pF V 98 100 −1 dBFS −10 −0.25 −10 102 105 −96 1.9 −87 +10 +0.25 +10 100 mV rms, 1 kHz 100 mV rms, 20 kHz 0 100 −110 55 55 14 10 1.5 20 Hz to 20 kHz, −60 dB input 98 100 0 dBFS Two channels running Eight channels running −10 −0.2 −25 −30 104 106 108 −92 −86 0.88 (2.48) dB dB dB dB dB V rms (V p-p) % dB mV ppm/°C −75 +10 +0.2 +25 +30 −4 AD1928 Parameter Interchannel Isolation Interchannel Phase Deviation Volume Control Step Volume Control Range De-emphasis Gain Error Output Resistance at Each Pin REFERENCE Internal Reference Voltage External Reference Voltage Common-Mode Reference Output Conditions Min Typ 100 0 0.375 95 100 FILTR pin FILTR pin CM pin 1.50 1.50 1.50 Max Unit dB Degrees dB dB dB Ω V V V ±0.6 1.32 1.68 Specifications measured at a case temperature of 130°C. Table 2. Parameter ANALOG-TO-DIGITAL CONVERTERS ADC Resolution Dynamic Range No Filter (RMS) With A-Weighted Filter (RMS) Total Harmonic Distortion + Noise Full-Scale Input Voltage (Differential) Gain Error Interchannel Gain Mismatch Offset Error DIGITAL-TO-ANALOG CONVERTERS Dynamic Range No Filter (RMS) With A-Weighted Filter (RMS) With A-Weighted Filter (Average) Total Harmonic Distortion + Noise Single-Ended Version Full-Scale Output Voltage Gain Error Interchannel Gain Mismatch Offset Error Gain Drift REFERENCE Internal Reference Voltage External Reference Voltage Common-Mode Reference Output Conditions All ADCs 20 Hz to 20 kHz, −60 dB input 95 97 −1 dBFS −10 −0.25 −10 20 Hz to 20 kHz, −60 dB input 98 100 0 dBFS Two channels running Eight channels running −10 −0.2 −25 −30 FILTR pin FILTR pin CM pin 104 106 108 −92 −86 0.8775 (2.482) dB dB dB dB dB V rms (V p-p) % dB mV ppm/°C V V V Min Typ 24 102 105 −96 1.9 Max Unit Bits dB dB dB V rms % dB mV −87 +10 +0.25 +10 0 −70 +10 +0.2 +25 +30 −4 1.32 1.50 1.50 1.50 1.68 Rev. 0 | Page 4 of 32 AD1928 CRYSTAL OSCILLATOR SPECIFICATIONS Table 3. Parameter Transconductance Min Typ 3.5 Max Unit mmhos DIGITAL INPUT/OUTPUT SPECIFICATIONS −40°C < TA < +130°C, DVDD = 3.3 V ± 10%. Table 4. Parameter High Level Input Voltage (VIH) Low Level Input Voltage (VIL) Input Leakage High Level Output Voltage (VOH) Low Level Output Voltage (VOL) Input Capacitance Conditions/Comments MCLKI/XI pin IIH @ VIH = 2.4 V IIL @ VIL = 0.8 V IOH = 1 mA IOL = 1 mA Min 2.0 2.2 Typ Max Unit V V V μA μA V V pF 0.8 10 10 DVDD − 0.60 0.4 5 POWER SUPPLY SPECIFICATIONS Table 5. Parameter SUPPLIES Voltage Digital Current Normal Operation Conditions/Comments DVDD AVDD Master clock = 256 fS fS = 48 kHz fS = 96 kHz fS = 192 kHz fS = 48 kHz to 192 kHz Min 3.0 3.0 Typ 3.3 3.3 56 65 95 2.0 74 23 Master clock = 256 fS, 48 kHz 429 185 244 83 1 kHz, 200 mV p-p 20 kHz, 200 mV p-p 50 50 mW mW mW mW dB dB Max 3.6 3.6 Unit V V mA mA mA mA mA mA Power-Down Analog Current Normal Operation Power-Down DISSIPATION Normal Operation All Supplies Digital Supply Analog Supply Power-Down, All Supplies POWER SUPPLY REJECTION RATIO Signal at Analog Supply Pins Rev. 0 | Page 5 of 32 AD1928 DIGITAL FILTERS Table 6. Parameter ADC DECIMATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay DAC INTERPOLATION FILTER Pass Band Mode All modes, typ @ 48 kHz Factor 0.4375 fS 0.5 fS 0.5625 fS 79 22.9844/fS 48 kHz mode, typ @ 48 kHz 96 kHz mode, typ @ 96 kHz 192 kHz mode, typ @ 192 kHz 48 kHz mode, typ @ 48 kHz 96 kHz mode, typ @ 96 kHz 192 kHz mode, typ @ 192 kHz 48 kHz mode, typ @ 48 kHz 96 kHz mode, typ @ 96 kHz 192 kHz mode, typ @ 192 kHz 48 kHz mode, typ @ 48 kHz 96 kHz mode, typ @ 96 kHz 192 kHz mode, typ @ 192 kHz 48 kHz mode, typ @ 48 kHz 96 kHz mode, typ @ 96 kHz 192 kHz mode, typ @ 192 kHz 48 kHz mode, typ @ 48 kHz 96 kHz mode, typ @ 96 kHz 192 kHz mode, typ @ 192 kHz 0.4535 fS 0.3646 fS 0.3646 fS 479 22 35 70 ±0.01 ±0.05 ±0.1 0.5 fS 0.5 fS 0.5 fS 0.5465 fS 0.6354 fS 0.6354 fS 70 70 70 25/fS 11/fS 8/fS 521 115 42 24 48 96 26 61 122 Min Typ 21 ±0.015 24 27 Max Unit kHz dB kHz kHz dB μs kHz kHz kHz dB dB dB kHz kHz kHz kHz kHz kHz dB dB dB μs μs μs Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay TIMING SPECIFICATIONS −40°C < TA < +130°C, DVDD = 3.3 V ± 10%. Table 7. Parameter INPUT MASTER CLOCK (MCLK) AND RESET tMH Condition Comments Min Max Unit MCLK duty cycle fMCLK tPDR tPDRR PLL Lock Time 256 fS VCO Clock Output Duty Cycle MCLK frequency RST low RST recovery MCLK and LR clock input MCLKO/XO pin DAC/ADC clock source = PLL clock @ 256 fS, 384 fS, 512 fS, and 768 fS DAC/ADC clock source = direct MCLK @ 512 fS (bypass on-chip PLL) PLL mode, 256 fS reference Direct 512 fS mode Reset to active output 40 40 6.9 15 4096 60 60 13.8 27.6 % % MHz MHz ns tMCLK ms % 10 40 60 Rev. 0 | Page 6 of 32 AD1928 Parameter SPI PORT tCCH tCCL fCCLK tCDS tCDH tCLS tCLH tCLHIGH tCOE tCOD tCOH tCOTS DAC SERIAL PORT tDBH tDBL tDLS tDLH tDLSKEW tDDS tDDH ADC SERIAL PORT tABH tABL tALS tALH tALSKEW tABDD AUXILIARY INTERFACE tAXDS tAXDH tDXDD tXBH tXBL tDLS tDLH Condition CCLK high CCLK low CCLK frequency CIN setup CIN hold CLATCH setup CLATCH hold CLATCH high COUT enable COUT delay COUT hold COUT tristate DBCLK high DBCLK low DLRCLK setup DLRCLK hold DLRCLK skew DSDATA setup DSDATA hold ABCLK high ABCLK low ALRCLK setup ALRCLK hold ALRCLK skew ASDATA delay AAUXDATA setup AAUXDATA hold DAUXDATA delay AUXBCLK high AUXBCLK low AUXLRCLK setup AUXLRCLK hold Comments See Figure 11, except where otherwise noted Min 35 35 fCCLK = 1/tCCP, only tCCP shown in Figure 11 To CCLK rising From CCLK rising To CCLK rising From CCLK falling Not shown in Figure 11 From CCLK falling From CCLK falling From CCLK falling, not shown in Figure 11 From CCLK falling See Figure 24 Slave mode Slave mode To DBCLK rising, slave mode From DBCLK rising, slave mode From DBCLK falling, master mode To DBCLK rising From DBCLK rising See Figure 25 Slave mode Slave mode To ABCLK rising, slave mode From ABCLK rising, slave mode From ABCLK falling, master mode From ABCLK falling To AUXBCLK rising From AUXBCLK rising From AUXBCLK falling 10 10 10 10 10 10 30 30 30 30 10 10 10 5 −8 10 5 10 10 10 5 −8 Max Unit ns ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns +8 +8 18 10 5 18 10 10 10 5 To AUXBCLK rising From AUXBCLK rising Rev. 0 | Page 7 of 32 AD1928 ABSOLUTE MAXIMUM RATINGS Table 8. Parameter Analog (AVDD) Digital (DVDD) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range (Case) Storage Temperature Range Rating −0.3 V to +3.6 V −0.3 V to +3.6 V ±20 mA –0.3 V to AVDD + 0.3 V −0.3 V to DVDD + 0.3 V −40°C to +125°C −65°C to +150°C THERMAL RESISTANCE θJA represents thermal resistance, junction-to-ambient; θJC represents the thermal resistance, junction-to-case. All characteristics are for a 4-layer board. Table 9. Thermal Resistance Package Type 48-Lead LQFP θJA 50.1 θJC 17 Unit °C/W Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. 0 | Page 8 of 32 AD1928 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADC1RN ADC1RP ADC1LN ADC1LP AVDD 48 47 46 45 44 43 42 41 40 39 38 AGND MCLKI/XI MCLKO/XO AGND AVDD OL3 OR3 OL4 OR4 PD/RST AVDD 37 CM NC NC NC NC LF 1 2 3 4 5 6 7 8 9 10 36 35 34 33 AGND FILTR AGND AVDD AGND OR2 OL2 OR1 OL1 CLATCH CCLK DGND AD1928 TOP VIEW (Not to Scale) SINGLE-ENDED OUTPUT 32 31 30 29 28 27 26 25 DSDATA4 11 DGND 12 13 14 15 16 17 18 19 20 21 22 23 24 DLRCLK ALRCLK CIN DBCLK DSDATA3 DSDATA2 DSDATA1 ASDATA1 ADCTDMOUT ABCLK COUT DVDD NC = NO CONNECT Figure 2. Pin Configuration, 48-Lead LQFP Table 10. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Input/Output I I O I I O O O O I I/O I I I/O I/O I I/O I/O I/O O I/O I/O I I/O I I I Mnemonic AGND MCLKI/XI MCLKO/XO AGND AVDD OL3 OR3 OL4 OR4 PD/RST DSDATA4 DGND DVDD DSDATA3 DSDATA2 DSDATA1 DBCLK DLRCLK ASDATA1 ADCTDMOUT ABCLK ALRCLK CIN COUT DGND CCLK CLATCH Description Analog Ground. Master Clock Input/Crystal Oscillator Input. Master Clock Output/Crystal Oscillator Output. Analog Ground. Analog Power Supply. Connect to analog 3.3 V supply. DAC Left 3 Output. DAC Right 3Output. DAC Left 4 Output. DAC Right 4 Output. Power-Down Reset (Active Low). DAC Input 4 (Input to DAC L4 and R4)/DAC TDM Data Output 2/AUX ADC 1 Data Input. Digital Ground. Digital Power Supply. Connect to digital 3.3 V supply. DAC Input 3 (Input to DAC L3 and R3)/DAC TDM Data Input 2/AUX DAC 2 Data Output. DAC Input 2 (Input to DAC L2 and R2)/DAC TDM Data Output 1/AUX ADC 1 Data Input. DAC Input 1 (Input to DAC L1 and R1)/DAC TDM Data Input 1/AUX ADC 2 Data Input. Bit Clock for DACs. LR Clock for DACs. ADC Serial Data Output 1 (ADC L1 and R1)/ADC TDM Data Input/AUX DAC 1 Data Output. ADC TDM Data Output. Bit Clock for ADCs. LR Clock for ADCs. Control Data Input (SPI). Control Data Output (SPI). Digital Ground. Control Clock Input (SPI). Latch Input for Control Data (SPI). Rev. 0 | Page 9 of 32 06623-002 AD1928 Pin No. 28 29 30 31 32 33 34 35 36 37 38 39 to 42 43 44 45 46 47 48 Input/Output O O O O I I I O I I O I I I I I O I Mnemonic OL1 OR1 OL2 OR2 AGND AVDD AGND FILTR AGND AVDD CM NC ADC1LP ADC1LN ADC1RP ADC1RN LF AVDD Description DAC Left 1 Output. DAC Right 1 Output. DAC Left 2 Output. DAC Right 2 Output. Analog Ground. Analog Power Supply. Connect to analog 3.3 V supply. Analog Ground. Voltage Reference Filter Capacitor Connection. Bypass with 10 μF||100 nF to AGND. Analog Ground. Analog Power Supply. Connect to analog 3.3 V supply. Common-Mode Reference Filter Capacitor Connection. Bypass with 47 μF||100 nF to AGND. No Connect. Must be tied to common mode, Pin 38. Alternately, ac-coupled to ground. ADC Left 1 Positive Input. ADC Left 1 Negative Input. ADC Right 1 Positive Input. ADC Right 1 Negative Input. PLL Loop Filter. Return to AVDD. Analog Power Supply. Connect to analog 3.3 V supply. Rev. 0 | Page 10 of 32 AD1928 TYPICAL PERFORMANCE CHARACTERISTICS 0.10 0.08 0.06 MAGNITUDE (dB) 0 0.04 MAGNITUDE (dB) –50 0.02 0 –0.02 –0.04 –0.06 –0.08 –0.10 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 FREQUENCY (Hz) 06623-003 –100 –150 0 12 24 FREQUENCY (kHz) 36 48 Figure 3. ADC Pass-Band Filter Response, 48 kHz 0 –10 –20 Figure 6. DAC Stop-Band Filter Response, 48 kHz 0.10 0.05 –30 MAGNITUDE (dB) –40 –50 –60 –70 –80 –90 –100 0 5000 10000 15000 20000 25000 30000 35000 40000 FREQUENCY (Hz) 06623-004 MAGNITUDE (dB) 0 –0.05 06623-007 –0.10 0 24 48 FREQUENCY (kHz) 72 96 Figure 4. ADC Stop-Band Filter Response, 48 kHz 0.06 Figure 7. DAC Pass-Band Filter Response, 96 kHz 0 0.04 MAGNITUDE (dB) 0.02 MAGNITUDE (dB) –50 0 –0.02 –100 06623-005 –0.06 –150 0 8 16 FREQUENCY (kHz) 24 0 24 48 FREQUENCY (kHz) 72 96 Figure 5. DAC Pass-Band Filter Response, 48 kHz Figure 8. DAC Stop-Band Filter Response, 96 kHz Rev. 0 | Page 11 of 32 06623-008 –0.04 06623-006 AD1928 0.5 0.4 0.3 –2 MAGNITUDE (dB) MAGNITUDE (dB) 0 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 0 8 16 32 64 06623-009 –4 –6 –8 06623-010 –10 48 64 80 96 FREQUENCY (kHz) FREQUENCY (kHz) Figure 9. DAC Pass-Band Filter Response, 192 kHz Figure 10. DAC Stop-Band Filter Response, 192 kHz Rev. 0 | Page 12 of 32 AD1928 THEORY OF OPERATION ANALOG-TO-DIGITAL CONVERTERS (ADCS) There are two analog-to-digital converter (ADC) channels in the AD1928, configured as a stereo pair with differential inputs. The ADCs can operate at a nominal sample rate of 48 kHz, 96 kHz, or 192 kHz. The ADCs include on-board digital antialiasing filters with 79 dB stop-band attenuation and linear phase response, operating at an oversampling ratio of 128 (48 kHz, 96 kHz, and 192 kHz modes). Digital outputs are supplied through two serial data output pins (one for each stereo pair) and a common frame clock (ALRCLK) and bit clock (ABCLK). Alternatively, one of the TDM modes can be used to access up to 14 channels on a single TDM data line. The ADCs must be driven from a differential signal source for best performance. The input pins of the ADCs connect to internal switched capacitors. To isolate the external driving op amp from the glitches caused by the internal switched capacitors, each input pin should be isolated by using a series-connected, external, 100 Ω resistor together with a 1 nF capacitor connected from each input to ground. This capacitor must be of high quality, for example, ceramic NPO or polypropylene film. The differential inputs have a nominal common-mode voltage of 1.5 V. The voltage at the common-mode reference pin (CM) can be used to bias external op amps to buffer the input signals (see the Power Supply and Voltage Reference section). The inputs can also be ac-coupled and do not need an external dc bias to CM. A digital high-pass filter can be switched in line with the ADCs under serial control to remove residual dc offsets. It has a 1.4 Hz, 6 dB per octave cutoff at a 48 kHz sample rate. The cutoff frequency scales directly with sample frequency. The voltage at CM, the common-mode reference pin, can be used to bias the external op amps that buffer the output signals (see the Power Supply and Voltage Reference section). CLOCK SIGNALS The on-chip phase-locked loop (PLL) can be selected to reference the input sample rate from either of the LRCLK pins or 256, 384, 512, or 768 times the sample rate, referenced to the 48 kHz mode from the MCLKI/XI pin. The default at power-up is 256 × fS from MCLKI/XI. In 96 kHz mode, the master clock frequency stays at the same absolute frequency; therefore, the actual multiplication rate is divided by 2. In 192 kHz mode, the actual multiplication rate is divided by 4. For example, if the AD1928 is programmed in 256 × fS mode, the frequency of the master clock input is 256 × 48 kHz = 12.288 MHz. If the AD1928 is then switched to 96 kHz operation (by writing to the SPI or I2C port), the frequency of the master clock should remain at 12.288 MHz, which, under these conditions, is 128 × fS. In 192 kHz mode, this becomes 64 × fS. The internal clock for the ADCs is 256 × fS for all clock modes. The internal clock for the DACs varies by mode: 512 × fS (48 kHz mode), 256 × fS (96 kHz mode), or 128 × fS (192 kHz mode). By default, the on-board PLL generates this internal master clock from an external clock. A direct 512 × fS (referenced to 48 kHz mode) master clock can be used for either the ADCs or DACs if selected in the PLL and Clock Control 1 register. Note that it is not possible to use a direct clock for the ADCs set to the 192 kHz mode. It is required that the on-chip PLL be used in this mode. The PLL can be powered down in the PLL and Clock Control 0 register. To ensure reliable locking when changing PLL modes, or if the reference clock is unstable at power-on, power down the PLL and then power it back up when the reference clock has stabilized. The internal master clock (MCLK) can be disabled in the PLL and Clock Control 0 register to reduce power dissipation when the AD1928 is idle. The clock should be stable before it is enabled. Unless a standalone mode is selected (see the Serial Control Port section), the clock is disabled by reset and must be enabled by writing to the SPI or I2C port for normal operation. To maintain the highest performance possible, it is recommended that the clock jitter of the internal master clock signal be limited to less than 300 ps rms TIE (time interval error). Even at these levels, extra noise or tones can appear in the DAC outputs if the jitter spectrum contains large spectral peaks. If the internal PLL is not being used, it is best to use an independent crystal oscillator to generate the master clock. In addition, it is especially important that the clock signal should not be passed through an FPGA, CPLD, or other large digital chip (such as a DSP) before being applied to the AD1928. In most cases, this induces clock jitter due to the sharing of common power and DIGITAL-TO-ANALOG CONVERTERS (DACS) The AD1928 digital-to-analog converter (DAC) channels are arranged as four single-ended stereo pairs, providing eight analog outputs for minimum external components. The DACs include on-board digital reconstruction filters with 70 dB stopband attenuation and linear phase response, operating at an oversampling ratio of 4 (48 kHz or 96 kHz modes) or 2 (192 kHz mode). Each channel has its own independently programmable attenuator, adjustable in 255 steps in 0.375 dB increments. Digital inputs are supplied through four serial data input pins (one for each stereo pair) and a common frame clock (DLRCLK) and bit clock (DBCLK). Alternatively, one of the TDM modes can be used to access up to 16 channels on a single TDM data line. Each output pin has a nominal common-mode dc level of 1.5 V and swings ±1.27 V for a 0 dBFS digital input signal. A single op amp, third-order, external, low-pass filter is recommended to remove high frequency noise present on the output pins. The use of op amps with low slew rate or low bandwidth can cause high frequency noise and tones to fold down into the audio band; therefore, exercise care in selecting these components. Rev. 0 | Page 13 of 32 AD1928 ground connections with other unrelated digital output signals. When the PLL is used, jitter in the reference clock is attenuated above a certain frequency depending on the loop filter. available for operation without serial control that is configured at reset using the serial control pins. All registers are set to default, except the internal master clock enable is set to 1 and ADC BCLK and LRCLK master/slave is set by the COUT pin. Standalone mode only supports stereo mode with an I2S data format and 256 fS master clock rate. Refer to Table 11 for details. It is recommended to use a weak pull-up resistor on CLATCH in applications that have a microcontroller. This pullup resistor ensures that the AD1928 recognizes the presence of a microcontroller. The SPI control port of the AD1928 is a 4-wire serial control port. The format is similar to the Motorola® SPI format, except the input data-word is 24 bits wide. The serial bit clock and latch can be completely asynchronous to the sample rate of the ADCs and DACs. Figure 11 shows the format of the SPI signal. The first byte is a global address with a read/write bit. For the AD1928, the address is 0x04, shifted left 1 bit due to the R/W bit. The second byte is the AD1928 register address and the third byte is the data. RESET AND POWER-DOWN The function of the RST pin sets all the control registers to their default settings. To avoid pops, reset does not power down the analog outputs. After RST is deasserted and the PLL acquires lock condition, an initialization routine runs inside the AD1928. This initialization lasts for approximately 256 master clock cycles. The power-down bits in the PLL and Clock Control 0, DAC Control 1, and ADC Control 1 registers power down the respective sections. All other register settings are retained. The reset pin, PD/RST, should be pulled low by an external resistor to guarantee proper startup. SERIAL CONTROL PORT The AD1928 has an SPI control port that permits programming and reading back of the internal control registers for the ADCs, DACs, and clock system. There is also a standalone mode Table 11. Standalone Mode Selection ADC Clocks Slave Master tCLS CLATCH CIN 0 0 COUT 0 1 CCLK 0 0 CLATCH 0 0 tCLH tCOTS tCCP tCCH tCCL CCLK tCDS tCDH CIN D23 D22 D9 D8 D0 COUT tCOE tCOD D9 D8 D0 06623-011 Figure 11. Format of SPI Signal Rev. 0 | Page 14 of 32 AD1928 POWER SUPPLY AND VOLTAGE REFERENCE The AD1928 is designed for 3.3 V supplies. Separate power supply pins are provided for the analog and digital sections. These pins should be bypassed with 100 nF ceramic chip capacitors, as close to the pins as possible, to minimize noise pickup. A bulk aluminum electrolytic capacitor of at least 22 μF should also be provided on the same PC board as the codec. For critical applications, improved performance is obtained with separate supplies for the analog and digital sections. If this is not possible, it is recommended that the analog and digital supplies be isolated by means of a ferrite bead in series with each supply. It is important that the analog supply be as clean as possible. All digital inputs are compatible with TTL and CMOS levels. All outputs are driven from the 3.3 V DVDD supply and are compatible with TTL and 3.3 V CMOS levels. The ADC and DAC internal voltage reference (VREF) is brought out on FILTR and should be bypassed as close as possible to the chip, with a parallel combination of 10 μF and 100 nF. Any external current drawn should be limited to less than 50 μA. The internal reference can be disabled in the PLL and Clock Control 1 register, and FILTR can be driven from an external source. This can be used to scale the DAC output to the clipping level of a power amplifier based on its power supply voltage. The ADC input gain varies by the inverse ratio. The total gain from ADC input to DAC output remains constant. The CM pin is the internal common-mode reference. It should be bypassed as close as possible to the chip, with a parallel combination of 47 μF and 100 nF. This voltage can be used to bias external op amps to the common-mode voltage of the input and output signal pins. The output current should be limited to less than 0.5 mA source and 2 mA sink. TIME-DIVISION MULTIPLEXED (TDM) MODES The AD1928 serial ports also have several different TDM serial data modes. The first and most commonly used configurations are shown in Figure 12 and Figure 13. In Figure 12, the ADC serial port outputs one data stream consisting of two on-chip ADCs and unused slots. In Figure 13, the eight on-chip DAC data slots are packed into one TDM stream. In this mode, both DBCLK and ABCLK are 256 fS. The input/output pins of the serial ports are defined according to the serial mode selected. For a detailed description of the function of each pin in TDM and auxilliary modes, see Table 12. The AD1928 allows systems with more than eight DAC channels to be easily configured by the use of an auxiliary serial data port. The DAC TDM-AUX mode is shown in Figure 14. In this mode, the AUX channels are the last four slots of the TDM data stream. These slots are extracted and output to the AUX serial port. Note that due to the high DBCLK frequency, this mode is available only in the 48 kHz/44.1 kHz/32 kHz sample rate. The AD1928 also allows system configurations with more than two ADC channels, as shown in Figure 15 and Figure 16, which show configurations using 6 ADCs and 14 ADCs, respectively. Again, due to the high ABCLK frequency, this mode is available only in the 48 kHz/44.1 kHz/32 kHz sample rate. Combining the AUX ADC and DAC modes results in a system configuration of 6 ADCs and 12 DACs. The system, then, consists of two external stereo ADCs, two external stereo DACs, and one AD1928. This mode is shown in Figure 17 (combined AUX DAC and ADC modes). LRCLK 256 BCLKs BCLK 32 BCLKs SLOT 1 SLOT 2 SLOT 3 LEFT 1 SLOT 4 RIGHT 1 SLOT 5 SLOT 6 SLOT 7 SLOT 8 SERIAL DATA PORTS—DATA FORMAT The eight DAC channels use a common serial bit clock (DBCLK) and a common left-right framing clock (DLRCLK) in the serial data port. The two ADC channels use a common serial bit clock (ABCLK) and left-right framing clock (ALRCLK) in the serial data port. The clock signals are all synchronous with the sample rate. The normal stereo serial modes are shown in Figure 23. The ADC and DAC serial data modes default to I2S. The ports can also be programmed for left-justified, right-justified, and TDM modes. The word width is 24 bits by default and can be programmed for 16 or 20 bits. The DAC serial formats are programmable according to DAC Control 0 register. The polarity of the DBCLK and DLRCLK is programmable according to the DAC Control 1 register. The ADC serial formats and serial clock polarity are programmable according to ADC Control 1 register. Both DAC and ADC serial ports are programmable to become the bus masters according to the DAC Control 1 register and the ADC Control 2 register. By default, both ADC and DAC serial ports are in slave mode. DATA LRCLK 06623-012 BCLK MSB MSB – 1 MSB – 2 DATA Figure 12. ADC TDM (6-Channel I2S Mode) LRCLK 256 BCLKs BCLK 32 BCLKs SLOT 1 LEFT 1 SLOT 2 RIGHT 1 SLOT 3 LEFT 2 SLOT 4 RIGHT 2 SLOT 5 LEFT 3 SLOT 6 RIGHT 3 SLOT 7 LEFT 4 SLOT 8 RIGHT 4 DATA LRCLK 06623-013 BCLK MSB MSB – 1 MSB – 2 DATA Figure 13. DAC TDM (8-Channel I2S Mode) Rev. 0 | Page 15 of 32 AD1928 Table 12. Pin Function Changes in TDM-AUX Mode Mnemonic ADCTDMOUT ASDATA1 DSDATA1 DSDATA2 DSDATA3 DSDATA4 ALRCLK ABCLK DLRCLK DBCLK Stereo Modes NC ADC1 Data Output DAC1 Data Input DAC2 Data Input DAC3 Data Input DAC4 Data Input ADC LRCLK Input/Output ADC BCLK Input/Output DAC LRCLK Input/Output DAC BCLK Input/Output TDM Modes ADC TDM Data Output ADC TDM Data Input DAC TDM Data Input DAC TDM Data Output DAC TDM Data Input 2 (Dual-Line Mode) DAC TDM Data Output 2 (Dual-Line Mode) ADC TDM Frame Sync Input/Output ADC TDM BCLK Input/Output DAC TDM Frame Sync Input/Output DAC TDM BCLK Input/Output AUX Modes TDM Data Output AUX Data Output 1 (to External DAC 1) TDM Data Input AUX Data Input 1 (from External ADC 1) AUX Data Input 2 (from External ADC 2) AUX Data Output 2 (to External DAC 2) TDM Frame Sync Input/Output TDM BCLK Input/Output AUX LRCLK Input/Output AUX BCLK Input/Output ALRCLK ABCLK AUXILIARY DAC CHANNELS WILL APPEAR AT AUX DAC PORTS DAC L4 DAC R4 AUX L1 AUX R1 AUX L2 AUX R2 DSDATA1 (TDM_IN) UNUSED SLOTS EMPTY EMPTY EMPTY EMPTY DAC L1 DAC R1 8 ON-CHIP DAC CHANNELS DAC L2 DAC R2 DAC L3 DAC R3 32 BITS MSB DLRCLK (AUX PORT) DBCLK (AUX PORT) ASDATA1 (AUX1_OUT) DSDATA4 (AUX2_OUT) LEFT RIGHT MSB MSB 06623-014 MSB MSB Figure 14. 16-Channel DAC TDM-AUX Mode Rev. 0 | Page 16 of 32 AD1928 ALRCLK ABCLK 8 ON-CHIP DAC CHANNELS DSDATA1 (TDM_IN) DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 2 ON-CHIP ADC CHANNELS ADCTDMOUT (TDM_OUT) UNUSED UNUSED ADC L1 ADC R1 AUX L1 4-AUX ADC CHANNELS AUX R1 AUX L2 AUX R2 32 BITS MSB DLRCLK (AUX PORT) DBCLK (AUX PORT) DSDATA2 (AUX1_IN) DSDATA3 (AUX2_IN) LEFT RIGHT MSB MSB 06623-015 MSB MSB Figure 15. 6-Channel AUX ADC Mode ALRCLK ABCLK ADCTDMOUT (TDM_OUT) 2 ON-CHIP ADC CHANNELS UNUSED UNUSED ADC L1 ADC R1 AUXILIARY ADC CHANNELS AUX L1 AUX R1 AUX L2 UNUSED SLOTS AUX R2 UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED 32 BITS MSB DLRCLK (AUX PORT) DBCLK (AUX PORT) DSDATA2 (AUX1_IN) DSDATA3 (AUX2_IN) LEFT RIGHT MSB MSB 06623-016 MSB MSB Figure 16. 14-Channel AUX ADC Mode Rev. 0 | Page 17 of 32 AD1928 ALRCLK ABCLK AUXILIARY DAC CHANNELS WILL APPEAR AT AUX DAC PORTS DAC L4 DAC R4 AUX L1 AUX R1 AUX L2 AUX R2 DSDATA1 (TDM_IN) UNUSED SLOTS EMPTY EMPTY EMPTY EMPTY DAC L1 DAC R1 8 ON-CHIP DAC CHANNELS DAC L2 DAC R2 DAC L3 DAC R3 ADCTDMOUT (TDM_OUT) DLRCLK (AUX PORT) DBCLK (AUX PORT) DSDATA2 (AUX1_IN) DSDATA3 (AUX2_IN) ASDATA1 (AUX1_OUT) DSDATA4 (AUX2_OUT) 2 ON-CHIP ADC CHANNELS UNUSED UNUSED ADC L1 ADC R1 AUXILIARY ADC CHANNELS AUX L1 AUX R1 AUX L2 UNUSED SLOTS AUX R2 UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED LEFT RIGHT MSB MSB MSB MSB MSB MSB 06623-017 MSB MSB Figure 17. Combined AUX DAC and ADC Mode Rev. 0 | Page 18 of 32 AD1928 DAISY-CHAIN MODE The AD1928 also allows a daisy-chain configuration to expand the system to 4 ADCs and 16 DACs (see Figure 18). In this mode, the DBCLK frequency is 512 fS. The first eight slots of the DAC TDM data stream belong to the first AD1928 in the chain and the last eight slots belong to the second AD1928. The second AD1928 is the device attached to the DSP TDM port. To accommodate 16 channels at a 96 kHz sample rate, the AD1928 can be configured into a dual-line TDM mode, as shown in Figure 19. This mode allows a slower DBCLK than normally required by the one-line TDM mode. Again, the first four channels of each TDM input belong to the first AD1928 in the chain and the last four channels belong to the second AD1928. The dual-line TDM mode can also be used to send data at a 192 kHz sample rate into the AD1928, as shown in Figure 20. DLRCLK There are two configurations for the ADC port to work in daisy-chain mode. The first one is with an ABCLK at 256 fS, shown in Figure 21. The second configuration is shown in Figure 22. Note that in the 512 fS ABCLK mode, the ADC channels occupy the first eight slots; the second eight slots are empty. The TDM_IN of the first AD1928 must be grounded in all modes of operation. The input/output pins of the serial ports are defined according to the serial mode selected. See Table 13 for a detailed description of the function of each pin. See Figure 26 for a typical AD1928 configuration with two external stereo DACs and two external stereo ADCs. Figure 23 through Figure 25 show the serial mode formats. For maximum flexibility, the polarity of LRCLK and BCLK are programmable. In these figures, all of the clocks are shown with their normal polarity. The default mode is I2S. DBCLK 8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN DSDATA1 (TDM_IN) OF THE SECOND AD1928 DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 DSDATA2 (TDM_OUT) OF THE SECOND AD1928 THIS IS THE TDM TO THE FIRST AD1928 DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 8 UNUSED SLOTS 32 BITS FIRST AD1928 SECOND AD1928 DSP MSB Figure 18. Single-Line DAC TDM Daisy-Chain Mode (Applicable to 48 kHz Sample Rate, 16-Channel, Two-AD1928 Daisy Chain) Rev. 0 | Page 19 of 32 06623-018 AD1928 DLRCLK DBCLK 8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN DSDATA1 (IN) DSDATA2 (OUT) DSDATA3 (IN) DSDATA4 (OUT) 32 BITS DAC L3 DAC R3 DAC L4 DAC R4 DAC L1 DAC R1 DAC L2 DAC R2 8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN DAC L1 DAC R1 DAC L2 DAC R2 DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 DAC L3 DAC R3 DAC L4 DAC R4 MSB FIRST AD1928 SECOND AD1928 DSP Figure 19. Dual-Line DAC TDM Mode (Applicable to 96 kHz Sample Rate, 16-Channel, Two-AD1928 Daisy Chain, DSDATA3 and DSDATA4 are the Daisy Chain) DLRCLK DBCLK DSDATA1 DAC L1 DAC R1 DAC L2 DAC R2 DSDATA2 DAC L3 DAC R3 DAC L4 DAC R4 32 BITS MSB Figure 20. Dual-Line DAC TDM Mode (Applicable to 192 kHz Sample Rate, 8-Channel Mode) ALRCLK ABCLK 2 ADC CHANNELS OF SECOND IC IN THE CHAIN UNUSED UNUSED ADC L1 ADC R1 2 ADC CHANNELS OF FIRST IC IN THE CHAIN UNUSED UNUSED ADC L1 ADC R1 ADCTDMOUT (TDM_OUT OF THE SECOND AD1928 IN THE CHAIN) ASDATA1 (TDM_IN OF THE SECOND AD1928 IN THE CHAIN) UNUSED UNUSED ADC L1 ADC R1 32 BITS FIRST AD1928 SECOND AD1928 DSP 06623-021 MSB Figure 21. ADC TDM Daisy-Chain Mode (256 fS BCLK, Two-AD1928 Daisy Chain) Rev. 0 | Page 20 of 32 06623-020 06623-019 AD1928 ALRCLK ABCLK ADCTDMOUT (TDM_OUT OF THE SECOND AD1928 IN THE CHAIN) ASDATA1 (TDM_IN OF THE SECOND AD1928 IN THE CHAIN) 2 ADC CHANNELS OF SECOND IC IN THE CHAIN UNUSED UNUSED ADC L1 2 ADC CHANNELS OF FIRST IC IN THE CHAIN ADC R1 ADC R1 UNUSED UNUSED ADC L1 UNUSED UNUSED ADC L1 ADC R1 32 BITS MSB Figure 22. ADC TDM Daisy-Chain Mode (512 fS BCLK, Two-AD1928 Daisy Chain) LRCLK BCLK SDATA MSB LEFT CHANNEL RIGHT CHANNEL LSB MSB LSB LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL LRCLK BCLK SDATA MSB LEFT CHANNEL RIGHT CHANNEL LSB MSB LSB I2S-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL LRCLK BCLK SDATA LEFT CHANNEL RIGHT CHANNEL MSB LSB MSB LSB RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL LRCLK BCLK SDATA MSB LSB MSB LSB DSP MODE—16 BITS TO 24 BITS PER CHANNEL 1/fS 06623-023 NOTES 1. DSP MODE DOES NOT IDENTIFY CHANNEL. 2. LRCLK NORMALLY OPERATES AT fS EXCEPT FOR DSP MODE WHICH, IS 2 × fS. 3. BCLK FREQUENCY IS NORMALLY 64 × LRCLK BUT MAY BE OPERATED IN BURST MODE. Figure 23. Stereo Serial Modes Rev. 0 | Page 21 of 32 06623-022 FIRST AD1928 SECOND AD1928 DSP AD1928 tDBH DBCLK tDBP tDBL tDLS tDLH DLRCLK tDLSKEW DSDATA LEFT-JUSTIFIED MODE tDDS MSB MSB – 1 tDDH DSDATAx I2S-JUSTIFIED MODE tDDS MSB tDDH tDDS tDDS 06623-024 06623-025 DSDATAx RIGHT-JUSTIFIED MODE MSB LSB tDDH tDDH Figure 24. DAC Serial Timing tABH ABCLK tABL tALS ALRCLK tALH tALSKEW ASDATA LEFT-JUSTIFIED MODE tABDD MSB MSB – 1 tABDD ASDATA I2S-JUSTIFIED MODE MSB tABDD ASDATA RIGHT-JUSTIFIED MODE MSB LSB Figure 25. ADC Serial Timing Rev. 0 | Page 22 of 32 AD1928 Table 13. Pin Function Changes in TDM-AUX Mode (Replication of Table 12) Mnemonic ADCTDMOUT ASDATA1 DSDATA1 DSDATA2 DSDATA3 DSDATA4 ALRCLK ABCLK DLRCLK DBCLK Stereo Modes NC ADC1 Data Output DAC1 Data Input DAC2 Data Input DAC3 Data Input DAC4 Data Input ADC LRCLK Input/Output ADC BCLK Input/Output DAC LRCLK Input/Output DAC BCLK Input/Output TDM Modes ADC TDM Data Output ADC TDM Data Input DAC TDM Data Input DAC TDM Data Output DAC TDM Data Input 2 (Dual-Line Mode) DAC TDM Data Output 2 (Dual-Line Mode) ADC TDM Frame Sync Input/Output ADC TDM BCLK Input/Output DAC TDM Frame Sync Input/Output DAC TDM BCLK Input/Output AUX Modes TDM Data Output AUX Data Output 1 (to External DAC 1) TDM Data Input AUX Data Input 1 (from External ADC 1) AUX Data Input 2 (from External ADC 2) AUX Data Output 2 (to External. DAC 2) TDM Frame Sync Input/Output TDM BCLK Input/Output AUX LRCLK Input/Output AUX BCLK Input/Output 30MHz FSYNC-TDM (RFS) SHARC SHARC IS RUNNING IN SLAVE MODE (INTERRUPT-DRIVEN) RxDATA LRCLK AUX ADC 1 BCLK DATA MCLK ADCTDMOUT ALRCLK ABCLK DSDATA1 DBCLK DLRCLK LRCLK AUX ADC 2 BCLK DATA MCLK DSDATA2 DSDATA3 MCLKI/XI TxDATA RxCLK TxCLK 12.288MHz TFS (NC) LRCLK BCLK AUX DATA DAC 1 MCLK AD1928 TDM MASTER AUX MASTER ASDATA1 DSDATA4 LRCLK BCLK AUX DATA DAC 2 MCLK 06623-026 Figure 26. Example of AUX Mode Connection to SHARC® (AD1928 as TDM Master/AUX Master Shown) Rev. 0 | Page 23 of 32 AD1928 CONTROL REGISTERS DEFINITIONS The format is the same for I2C and SPI ports. The global address for the AD1928 is 0x04, shifted left one bit due to the R/W bit. All registers are reset to 0, except for the DAC volume registers that are set to full volume. Note that the first setting in each control register parameter is the default setting. Table 14. Register Format Global Address Bit 23:17 R/W 16 Register Address 15:8 Data 7:0 Table 15. Register Addresses and Functions Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Function PLL and Clock Control 0 PLL and Clock Control 1 DAC Control 0 DAC Control 1 DAC Control 2 DAC individual channel mutes DAC 1L volume control DAC 1R volume control DAC 2L volume control DAC 2R volume control DAC 3L volume control DAC 3R volume control DAC 4L volume control DAC 4R volume control ADC Control 0 ADC Control 1 ADC Control 2 PLL AND CLOCK CONTROL REGISTERS Table 16. PLL and Clock Control 0 Register Bit 0 2:1 Value 0 1 00 01 10 11 00 01 10 11 00 01 10 11 0 1 Function Normal operation Power-down Input 256 (×44.1 kHz or 48 kHz) Input 384 (×44.1 kHz or 48 kHz) Input 512 (×44.1 kHz or 48 kHz) Input 768 (×44.1 kHz or 48 kHz) XTAL oscillator enabled 256 × fS VCO output 512 × fS VCO output Off MCLKI/XI DLRCLK ALRCLK Reserved Disable: ADC and DAC idle Enable: ADC and DAC active Description PLL power-down MCLKI/XI pin functionality (PLL active), master clock rate setting 4:3 MCLKO/XO pin, master clock rate setting 6:5 PLL input 7 Internal master clock enable Rev. 0 | Page 24 of 32 AD1928 Table 17. PLL and Clock Control 1 Register Bit 0 1 2 3 7:4 Value 0 1 0 1 0 1 0 1 0000 Function PLL clock MCLK PLL clock MCLK Enabled Disabled Not locked Locked Reserved Description DAC clock source select ADC clock source select On-chip voltage reference PLL lock indicator (read only) DAC CONTROL REGISTERS Table 18. DAC Control 0 Register Bit 0 2:1 Value 0 1 00 01 10 11 000 001 010 011 100 101 110 111 00 01 10 11 Function Normal operation Power-down 32 kHz/44.1 kHz/48 kHz 64 kHz/88.2 kHz/96 kHz 128 kHz/176.4 kHz/192 kHz Reserved 1 0 8 12 16 Reserved Reserved Reserved Stereo (normal) TDM (daisy chain) DAC AUX mode (ADC-, DAC-, TDM-coupled) Dual-line TDM Description Power-down Sample rates 5:3 SDATA delay (BCLK periods) 7:6 Serial format Table 19. DAC Control 1 Register Bit 0 2:1 Value 0 1 00 01 10 11 0 1 0 1 0 1 0 1 0 1 Function Latch in midcycle (normal) Latch in at end of cycle (pipeline) 64 (2 channels) 128 (4 channels) 256 (8 channels) 512 (16 channels) Left low Left high Slave Master Slave Master DBCLK pin Internally generated Normal Inverted Description BCLK active edge (TDM in) BCLKs per frame 3 4 5 6 7 LRCLK polarity LRCLK master/slave BCLK master/slave BCLK source BCLK polarity Rev. 0 | Page 25 of 32 AD1928 Table 20. DAC Control 2 Register Bit 0 2:1 Value 0 1 00 01 10 11 00 01 10 11 0 1 00 Function Unmute Mute Flat 48 kHz curve 44.1 kHz curve 32 kHz curve 24 20 Reserved 16 Noninverted Inverted Reserved Description Master mute De-emphasis (32 kHz/44.1 kHz/48 kHz mode only) 4:3 Word width 5 7:6 DAC output polarity Table 21. DAC Individual Channel Mutes Bit 0 1 2 3 4 5 6 7 Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Unmute Mute Unmute Mute Unmute Mute Unmute Mute Unmute Mute Unmute Mute Unmute Mute Unmute Mute Description DAC 1L mute DAC 1R mute DAC 2L mute DAC 2R mute DAC 3L mute DAC 3R mute DAC 4L mute DAC 4R mute Table 22. DAC Volume Controls Bit 7:0 Value 0 1 to 254 255 Function No attenuation −3/8 dB per step Full attenuation Description DAC volume control Rev. 0 | Page 26 of 32 AD1928 ADC CONTROL REGISTERS Table 23. ADC Control 0 Register Bit 0 1 2 3 4 5 7:6 Value 0 1 0 1 0 0 0 1 0 1 00 01 10 11 Function Normal operation Power down Off On Reserved Reserved Unmute Mute Unmute Mute 32 kHz/44.1 kHz/48 kHz 64 kHz/88.2 kHz/96 kHz 128 kHz/176.4 kHz/192 kHz Reserved Description Power-down High-pass filter ADC 1L mute ADC 1R mute Output sample rate Table 24. ADC Control 1 Register Bit 1:0 Value 00 01 10 11 000 001 010 011 100 101 110 111 00 01 10 11 0 1 Function 24 20 Reserved 16 1 0 8 12 16 Reserved Reserved Reserved Stereo TDM (daisy chain) ADC AUX mode (ADC-, DAC-, TDM-coupled) Reserved Latch in midcycle (normal) Latch in at end of cycle (pipeline) Description Word width 4:2 SDATA delay (BCLK periods) 6:5 Serial format 7 BCLK active edge (TDM in) Rev. 0 | Page 27 of 32 AD1928 Table 25. ADC Control 2 Register Bit 0 Value 0 1 0 1 0 1 0 1 00 01 10 11 0 1 0 1 Function 50/50 (allows 32, 24, 20, 16 bit clocks (BCLKs) per channel Pulse (32 BCLKs per channel) Drive out on falling edge (DEF) Drive out on rising edge Left low Left high Slave Master 64 128 256 512 Slave Master ABCLK pin Internally generated Description LRCLK format 1 2 3 5:4 BCLK polarity LRCLK polarity LRCLK master/slave BCLKs per frame 6 7 BCLK master/slave BCLK source Rev. 0 | Page 28 of 32 AD1928 ADDITIONAL MODES The AD1928 offers several additional modes for board-level design enhancements. To reduce the EMI in board-level design, serial data can be transmitted without an explicit BCLK. See Figure 27 for an example of a DAC TDM data transmission mode that does not require high speed DBCLK. This configuration is applicable when the AD1928 master clock is generated by the PLL with the DLRCLK as the PLL reference frequency. To relax the requirement for the setup time of the AD1928 in cases of high speed TDM data transmission, the AD1928 can latch in the data using the falling edge of DBCLK. This effectively dedicates the entire BCLK period to the setup time. This mode is useful in cases where the source has a large delay time in the serial data driver. Figure 28 shows this pipeline mode of data transmission. Both the BCLK-less and pipeline modes are available on the ADC serial data port. DLRCLK 32 BITS INTERNAL DBCLK DSDATAx DLRCLK INTERNAL DBCLK 06623-027 TDM-DSDATAx Figure 27. Serial DAC Data Transmission in TDM Format without DBCLK (Applicable only if PLL locks to DLRCLK. This mode is also available in the ADC serial data port.) DLRCLK DBCLK DATA MUST BE VALID AT THIS BCLK EDGE DSDATAx MSB 06623-028 Figure 28. I2S Pipeline Mode in DAC Serial Data Transmission (Applicable in stereo and TDM, useful for high frequency TDM transmission. This mode is also available in the ADC serial data port.) Rev. 0 | Page 29 of 32 AD1928 APPLICATION CIRCUITS Typical applications circuits are shown in Figure 29 through Figure 32. Figure 29 shows a typical ADC input filter circuit. Recommended loop filters for LR clock and master clock as the 120pF 600Z 100pF 5.76kΩ 2 3 – OP275 + DAC OUT 4.75kΩ 4.75kΩ PLL reference are shown in Figure 30. Output filters for the DAC outputs are shown in Figure 31 and Figure 32 for the noninverting and inverting cases. AUDIO INPUT 5.76kΩ 1 3 2 240pF NPO + OP275 – 1 604Ω 4.7µF + 3.3nF NPO 5.76kΩ 120pF 4.7µF 237Ω + 1nF NPO AUDIO OUTPUT 49.9kΩ 06623-031 ADCxN 270pF NPO 4.99kΩ 4.99kΩ 100pF 6 5 5.76kΩ – OP275 + 7 1nF NPO 4.7µF 237Ω + ADCxP 06623-029 Figure 29. Typical ADC Input Filter Circuit Figure 31. Typical DAC Output Filter Circuit (Single-Ended, Noninverting) LF + LRCLK 39nF 2.2nF 3.32kΩ LF MCLK 5.6nF 390pF 562Ω 06623-030 11kΩ DAC OUT 11kΩ 270pF NPO 68pF NPO 2 3.01kΩ CM 0.1µF 3 – OP275 + 1 604Ω 4.7µF + 2.2nF NPO AUDIO OUTPUT 49.9kΩ 06623-032 AVDD2 AVDD2 Figure 30. Recommended Loop Filters for LRCLK and MCLK PLL Reference Figure 32. Typical DAC Output Filter Circuit (Single-Ended, Inverting) Rev. 0 | Page 30 of 32 AD1928 OUTLINE DIMENSIONS 0.75 0.60 0.45 1.60 MAX 48 1 PIN 1 9.20 9.00 SQ 8.80 37 36 1.45 1.40 1.35 0.15 0.05 TOP VIEW 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY (PINS DOWN) 7.20 7.00 SQ 6.80 12 13 24 25 SEATING PLANE VIEW A COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 33. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters ORDERING GUIDE Model AD1928YSTZ 1 , 2 AD1928YSTZ-RL1, 2 EVAL-AD1928EB EVAL-AD1928EBZ1 1 2 Temperature Range −40°C to +105°C −40°C to +105°C Package Description 48-Lead LQFP 48-Lead LQFP, 13” Reel Evaluation Board Evaluation Board Z = RoHS Compliant Part. Single-ended output; SPI control port. Rev. 0 | Page 31 of 32 051706-A ROTATED 90° CCW VIEW A 0.50 BSC LEAD PITCH 0.27 0.22 0.17 Package Option ST-48 ST-48 AD1928 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, if the system conforms to the I2C Standard Specifications as defined by Philips. ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06623-0-4/07(0) Rev. 0 | Page 32 of 32