Four ADCs/Eight DACs with PLL,
192 kHz, 24-Bit Codec
AD1937
FEATURES
GENERAL DESCRIPTION
PLL-generated clock or direct master clock
Low EMI design
112 dB DAC/107 dB ADC dynamic range and SNR
−96 dB THD + N
Single 3.3 V supply
Tolerance for 5 V logic inputs
Supports 24-bits and 8 kHz to 192 kHz sample rates
Differential ADC input
Differential DAC output
Log volume control with autoramp function
I2C-controllable for flexibility
Software-controllable clickless mute
Software power-down
Right-justified, left-justified, I2S, and TDM modes
Master and slave modes up to 16-channel input/output
Available in a 64-lead LQFP
Qualified for automotive applications
The AD1937 is a high performance, single-chip codec that provides
four analog-to-digital converters (ADCs) with differential input
and eight digital-to-analog converters (DACs) with differential
output, using the Analog Devices, Inc., patented multibit sigmadelta (Σ-Δ) architecture. An I2C® port is included, allowing a
microcontroller to adjust volume and many other parameters.
The AD1937 operates from 3.3 V digital and analog supplies.
The AD1937 is available in a 64-lead (differential output) LQFP.
The AD1937 is designed for low EMI. This consideration is
apparent in both the system and circuit design architectures.
By using the on-board PLL to derive the master clock from the
LR (frame) clock or from an external crystal, the AD1937 eliminates the need for a separate high frequency master clock and
can also be used with a suppressed bit clock. The DACs and
ADCs are designed using the latest Analog Devices continuous
time architecture to further minimize EMI. By using 3.3 V
supplies, power consumption is minimized and further
reduces emissions.
APPLICATIONS
Automotive audio systems
Home theater systems
Set-top boxes
Digital audio effects processors
FUNCTIONAL BLOCK DIAGRAM
DIGITAL AUDIO
INPUT/OUTPUT
AD1937
SERIAL DATA PORT
DAC
DAC
SDATA
OUT
ADC
ANALOG
AUDIO
INPUTS
ADC
ADC
ADC
SDATA
IN
CLOCKS
DIGITAL
FILTER
TIMING MANAGEMENT
AND CONTROL
(CLOCK AND PLL)
DAC
DIGITAL
FILTER
AND
VOLUME
CONTROL
DAC
DAC
ANALOG
AUDIO
OUTPUTS
DAC
DAC
DAC
CONTROL DATA
INPUT/OUTPUT
07414-001
PRECISION
VOLTAGE
REFERENCE
I2C
CONTROL PORT
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2008-2010 Analog Devices, Inc. All rights reserved.
AD1937
TABLE OF CONTENTS
Features .............................................................................................. 1
Analog-to-Digital Converters (ADCs) .................................... 15
Applications ....................................................................................... 1
Digital-to-Analog Converters (DACs) .................................... 15
General Description ......................................................................... 1
Clock Signals ............................................................................... 15
Functional Block Diagram .............................................................. 1
Reset and Power-Down ............................................................. 16
Revision History ............................................................................... 2
I2C Control Port.......................................................................... 16
Specifications..................................................................................... 3
Power Supply and Voltage Reference....................................... 18
Test Conditions ............................................................................. 3
Serial Data Ports—Data Format ............................................... 19
Analog Performance Specifications ........................................... 3
Time-Division Multiplexed (TDM) Modes ............................ 20
Crystal Oscillator Specifications................................................. 5
Daisy-Chain Mode ..................................................................... 23
Digital Specifications ................................................................... 6
Additional Modes ....................................................................... 26
Power Supply Specifications........................................................ 6
Control Registers ............................................................................ 27
Digital Filters ................................................................................. 7
Definitions ................................................................................... 27
Timing Specifications .................................................................. 8
PLL and Clock Control Registers ............................................. 27
Timing Diagrams.......................................................................... 9
DAC Control Registers .............................................................. 28
Absolute Maximum Ratings.......................................................... 10
ADC Control Registers .............................................................. 30
Thermal Resistance .................................................................... 10
Applications Circuits...................................................................... 32
ESD Caution ................................................................................ 10
Outline Dimensions ....................................................................... 33
Pin Configuration and Function Descriptions ........................... 11
Ordering Guide .......................................................................... 33
Typical Performance Characteristics ........................................... 13
Automotive Products ................................................................. 33
Theory of Operation ...................................................................... 15
REVISION HISTORY
6/10—Rev. A to Rev. B
Changes to Table 3 Introductory Text and to Table 3 .................. 4
Changes to Table 5 Introductory Text ........................................... 6
Changes to Table 8 Introductory Text ........................................... 8
3/10—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 33
9/08—Revision 0: Initial Version
Rev. B | Page 2 of 36
AD1937
SPECIFICATIONS
TEST CONDITIONS
Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications.
Table 1.
Parameter
Supply Voltages (AVDD, DVDD)
Temperature
Master Clock
Input Sample Rate
Measurement Bandwidth
Word Width
Load Capacitance (Digital Output)
Load Current (Digital Output)
Input Voltage High
Input Voltage Low
Value
3.3 V
As specified in Table 2 and Table 3
12.288 MHz (48 kHz fS, 256 × fS mode)
48 kHz
20 Hz to 20 kHz
24 bits
20 pF
±1 mA or 1.5 kΩ to ½ DVDD supply
2.0 V
0.8 V
ANALOG PERFORMANCE SPECIFICATIONS
Specifications guaranteed at a TA of 25°C.
Table 2.
Parameter
ANALOG-TO-DIGITAL CONVERTERS
ADC Resolution
Dynamic Range
No Filter (RMS)
With A-Weighted Filter (RMS)
Total Harmonic Distortion + Noise
Full-Scale Input Voltage (Differential)
Gain Error
Interchannel Gain Mismatch
Offset Error
Gain Drift
Interchannel Isolation
CMRR
Input Resistance
Input Capacitance
Input Common-Mode Bias Voltage
DIGITAL-TO-ANALOG CONVERTERS
DAC Resolution
Dynamic Range
No Filter (RMS)
With A-Weighted Filter (RMS)
With A-Weighted Filter (Average)
Conditions/Comments
Min
All ADCs
20 Hz to 20 kHz, −60 dB input
96
98
−1 dBFS
−10
−0.25
−10
100 mV rms, 1 kHz
100 mV rms, 20 kHz
All DACs
20 Hz to 20 kHz, −60 dB input
102
105
Rev. B | Page 3 of 36
Typ
Max
Unit
24
Bits
102
105
−96
1.9
dB
dB
dB
V rms
%
dB
mV
ppm/°C
dB
dB
dB
kΩ
pF
V
0
100
−110
55
55
14
10
1.5
−87
+10
+0.25
+10
24
Bits
107
110
112
dB
dB
dB
AD1937
Parameter
Total Harmonic Distortion + Noise
Full-Scale Output Voltage
Gain Error
Interchannel Gain Mismatch
Offset Error
Gain Drift
Interchannel Isolation
Interchannel Phase Deviation
Volume Control Step
Volume Control Range
De-emphasis Gain Error
Output Resistance at Each Pin
REFERENCE
Internal Reference Voltage
External Reference Voltage
Common-Mode Reference Output
REGULATOR
Input Supply Voltage
Regulated Output Voltage
Conditions/Comments
0 dBFS
Two channels running
Eight channels running
Min
−10
−0.2
−25
−30
Typ
Max
−94
−86
1.76 (4.96)
−76
+10
+0.2
+25
+30
−6
100
0
0.375
95
±0.6
100
Unit
dB
dB
V rms (V p-p)
%
dB
mV
ppm/°C
dB
Degrees
dB
dB
dB
Ω
FILTR pin
FILTR pin
CM pin
1.32
1.50
1.50
1.50
1.68
V
V
V
VSUPPLY pin
VSENSE pin
4.5
3.19
5
3.37
5.5
3.55
V
V
Specifications measured at −40°C < TC < +125°C, AVDD = 3.3 V ± 10%.
Table 3.
Parameter
ANALOG-TO-DIGITAL CONVERTERS
ADC Resolution
Dynamic Range
No Filter (RMS)
With A-Weighted Filter (RMS)
Total Harmonic Distortion + Noise
Full-Scale Input Voltage (Differential)
Gain Error
Interchannel Gain Mismatch
Offset Error
Gain Drift
Interchannel Isolation
CMRR
Input Resistance
Input Capacitance
Input Common-Mode Bias Voltage
DIGITAL-TO-ANALOG CONVERTERS
DAC Resolution
Dynamic Range
No Filter (RMS)
With A-Weighted Filter (RMS)
With A-Weighted Filter (Average)
Total Harmonic Distortion + Noise
Conditions/Comments
−40°C < TC < +125°C, AVDD = 3.3 V ± 10%
Min
Max
All ADCs
20 Hz to 20 kHz, −60 dB
24
Bits
93
95
−1 dBFS
−85
2.05
+10
+0.25
+10
100
1.75
−10
−0.46
−10
−105
100 mV rms, 1 kHz
100 mV rms, 20 kHz
1.45
All DACs
20 Hz to 20 kHz, −60 dB
42
42
By design
By design
1.55
24
dB
dB
dB
−84
−76
Rev. B | Page 4 of 36
dB
dB
dB
V rms
%
dB
mV
ppm/°C
dB
dB
dB
kΩ
pF
V dc
Bits
100
104
109
0 dBFS
Two channels
Eight channels
Units
dB
dB
AD1937
Parameter
Full-Scale Output Voltage
Gain Error
Interchannel Gain Mismatch
Offset Error
Gain Drift
Interchannel Isolation
Interchannel Phase Deviation
Volume Control Step
Volume Control Range
De-emphasis Gain Error
Output Resistance at Each Pin
REFERENCE
Internal Reference Voltage
External Reference Voltage
Common-Mode Reference Output
REGULATOR
Input Supply Voltage
Regulated Output Voltage
−40°C < TC < +125°C, AVDD = 3.3 V ± 10%
Min
Max
1.6
1.9
−10
+10
−0.2
+0.2
−30
+25
−30
+30
−95
By design
By design
By design
By design
By design
Units
V rms (V p-p)
%
dB
mV
ppm/°C
dB
Degrees
dB
dB
dB
Ω
FILTR pin
FILTR pin
CM pin
1.46
1.32
1.45
1.57
1.68
1.56
V dc
V dc
V dc
VSUPPLY pin
VSENSE pin
4.5
3.05
5.5
3.71
V dc
V dc
Conditions/Comments
CRYSTAL OSCILLATOR SPECIFICATIONS
Table 4.
Parameter
Transconductance
Min
Typ
3.5
Rev. B | Page 5 of 36
Max
Unit
mmhos
AD1937
DIGITAL SPECIFICATIONS
−40°C < TC < +125°C, DVDD = 3.3 V ± 10%.
Table 5.
Parameter
INPUT
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
Input Leakage
Input Capacitance
OUTPUT
High Level Output Voltage (VOH)
Low Level Output Voltage (VOL)
Conditions/Comments
Min
MCLKI/MCLKXI pin
2.0
2.2
Typ
IIH @ VIH = 2.4 V
IIL @ VIL = 0.8 V
Max
Unit
0.8
10
10
5
V
V
V
μA
μA
pF
0.4
V
V
IOH = 1 mA
IOL = 1 mA
DVDD − 0.60
Conditions/Comments
Min
Typ
Max
Unit
DVDD
AVDD
VSUPPLY
Master clock = 256 fS
fS = 48 kHz
fS = 96 kHz
fS = 192 kHz
fS = 48 kHz to 192 kHz
3.0
3.0
4.5
3.3
3.3
5.0
3.6
3.6
5.5
V
V
V
POWER SUPPLY SPECIFICATIONS
Table 6.
Parameter
SUPPLIES
Voltage
Digital Current
Normal Operation
Power-Down
Analog Current
Normal Operation
Power-Down
DISSIPATION
Operation
All Supplies
Digital Supply
Analog Supply
Power-Down, All Supplies
POWER SUPPLY REJECTION RATIO
Signal at Analog Supply Pins
56
65
95
2.0
mA
mA
mA
mA
74
23
mA
mA
429
185
244
83
mW
mW
mW
mW
50
50
dB
dB
Master clock = 256 fS, 48 kHz
1 kHz, 200 mV p-p
20 kHz, 200 mV p-p
Rev. B | Page 6 of 36
AD1937
DIGITAL FILTERS
Table 7.
Parameter
ADC DECIMATION FILTER
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Group Delay
DAC INTERPOLATION FILTER
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Group Delay
Mode
All modes, typical @ 48 kHz
Factor
Min
0.4375 × fS
Typ
Max
21
±0.015
24
27
0.5 × fS
0.5625 × fS
kHz
dB
kHz
kHz
dB
μs
79
22.9844 ÷ fS
48 kHz mode, typical @ 48 kHz
96 kHz mode, typical @ 96 kHz
192 kHz mode, typical @ 192 kHz
48 kHz mode, typical @ 48 kHz
96 kHz mode, typical @ 96 kHz
192 kHz mode, typical @ 192 kHz
48 kHz mode, typical @ 48 kHz
96 kHz mode, typical @ 96 kHz
192 kHz mode, typical @ 192 kHz
48 kHz mode, typical @ 48 kHz
96 kHz mode, typical @ 96 kHz
192 kHz mode, typical @ 192 kHz
48 kHz mode, typical @ 48 kHz
96 kHz mode, typical @ 96 kHz
192 kHz mode, typical @ 192 kHz
48 kHz mode, typical @ 48 kHz
96 kHz mode, typical @ 96 kHz
192 kHz mode, typical @ 192 kHz
Rev. B | Page 7 of 36
0.4535 × fS
0.3646 × fS
0.3646 × fS
479
22
35
70
±0.01
±0.05
±0.1
0.5 × fS
0.5 × fS
0.5 × fS
0.5465 × fS
0.6354 × fS
0.6354 × fS
24
48
96
26
61
122
70
70
70
25 ÷ fS
11 ÷ fS
8 ÷ fS
521
115
42
Unit
kHz
kHz
kHz
dB
dB
dB
kHz
kHz
kHz
kHz
kHz
kHz
dB
dB
dB
μs
μs
μs
AD1937
TIMING SPECIFICATIONS
−40°C < TC < +125°C, DVDD = 3.3 V ± 10%.
Table 8.
Parameter
INPUT MASTER CLOCK (MCLK) AND RESET
tMH
Condition
Comments
Min
Max
Unit
MCLK duty cycle
DAC/ADC clock source = PLL clock
@ 256 fS, 384 fS, 512 fS, and 768 fS
DAC/ADC clock source = direct MCLK
@ 512 fS (bypass on-chip PLL)
PLL mode, 256 fS reference
Direct 512 fS mode
40
60
%
40
60
%
6.9
13.8
27.6
MHz
MHz
ns
tMCLK
10
60
ms
%
400
1.3
kHz
μs
μs
μs
μs
μs
ns
ns
ns
μs
10
10
10
−8
5
10
5
ns
ns
ns
ns
ns
ns
ns
tMH
fMCLK
fMCLK
tPDR
tPDRR
PLL
Lock Time
256 fS VCO Clock, Output Duty Cycle,
MCLKO/MCLKXO Pin
I2C
fSCL
tSCLL
tSCLH
tSCS
tSCH
tSSH
tDS
tSR
tSF
tBFT
DAC SERIAL PORT
tDBH
tDBL
tDLS
tDLH
tDDS
tDDH
ADC SERIAL PORT
tABH
tABL
tALS
tALH
tABDD
AUXILIARY INTERFACE
tAXDS
tAXDH
tDXDD
tXBH
tXBL
tDLS
tDLH
MCLK frequency
Low
Recovery
Reset to active output
15
4096
MCLK or LRCLK
40
See Figure 13 and Figure 14
SCL clock frequency
SCL low
SCL high
Setup time (start condition)
Hold time (start condition)
Setup time (stop condition)
Data setup time
SDA and SCL rise time
SDA and SCL fall time
Bus-free time
DBCLK high
DBCLK low
DLRCLK setup
DLRCLK skew
DLRCLK hold
DSDATA setup
DSDATA hold
ABCLK high
ABCLK low
ALRCLK setup
ALRCLK skew
ALRCLK hold
ASDATA delay
AAUXDATA setup
AAUXDATA hold
DAUXDATA delay
AUXBCLK high
AUXBCLK low
AUXLRCLK setup
AUXLRCLK hold
Rev. B | Page 8 of 36
Relevent for repeated start condition
First clock generated after this period
1.3
0.6
0.6
0.6
0.6
100
300
300
Between stop and start
See Figure 2
Slave mode
Slave mode
To DBCLK rising, slave mode
From DBCLK falling, master mode
From DBCLK rising, slave mode
To DBCLK rising
From DBCLK rising
See Figure 3
Slave mode
Slave mode
To ABCLK rising, slave mode
From ABCLK falling, master mode
From ABCLK rising, slave mode
From ABCLK falling, any mode
To AUXBCLK rising
From AUXBCLK rising
From AUXBCLK falling
To AUXBCLK rising
From AUXBCLK rising
10
10
10
−8
5
+8
+8
18
10
5
18
10
10
10
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AD1937
TIMING DIAGRAMS
tDBH
DBCLK
tDBL
tDLH
tDLS
DLRCLK
tDDS
DSDATAx
LEFT-JUSTIFIED
MODE
MSB – 1
MSB
tDDH
tDDS
DSDATAx
I2S-JUSTIFIED
MODE
MSB
tDDH
tDDS
MSB
LSB
tDDH
tDDH
07414-025
tDDS
DSDATAx
RIGHT-JUSTIFIED
MODE
Figure 2. DAC Serial Timing
tABH
ABCLK
tABL
tALH
tALS
ALRCLK
tABDD
ASDATAx
LEFT-JUSTIFIED
MODE
MSB
MSB – 1
tABDD
ASDATAx
I2S-JUSTIFIED
MODE
MSB
ASDATAx
RIGHT-JUSTIFIED
MODE
MSB
Figure 3. ADC Serial Timing
Rev. B | Page 9 of 36
LSB
07414-026
tABDD
AD1937
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 9.
Parameter
Analog (AVDD)
Digital (DVDD)
VSUPPLY
Input Current (Except Supply Pins)
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
Operating Temperature Range (Case)
Storage Temperature Range
Rating
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +6.0 V
±20 mA
–0.3 V to AVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−40°C to +125°C
−65°C to +150°C
θJA represents junction-to-ambient thermal resistance;
θJC represents the junction-to-case thermal resistance.
All characteristics are for a 4-layer board.
Table 10.
Package Type
64-Lead LQFP
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. B | Page 10 of 36
θJA
47
θJC
11.1
Unit
°C/W
AD1937
NC
NC
AVDD
LF
ADC2RN
ADC2RP
ADC2LN
ADC2LP
ADC1RN
ADC1RP
ADC1LN
ADC1LP
CM
AVDD
NC
NC
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1
48
AGND
2
47
FILTR
MCLKO/MCLKXO
3
46
AGND
AGND
4
45
AVDD
AVDD
5
44
AGND
DAC3LP
6
43
DAC2RN
DAC3LN
7
42
DAC2RP
DAC3RP
8
41
DAC2LN
DAC3RN
9
40
DAC2LP
DAC4LP 10
39
DAC1RN
DAC4LN 11
38
DAC1RP
DAC4RP 12
37
DAC1LN
DAC4RN 13
36
DAC1LP
PD/RST 14
35
ADDR1
DSDATA4 15
34
SCL
DGND 16
33
DGND
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DVDD
DSDATA2
DSDATA1
DBCLK
DLRCLK
VSUPPLY
VSENSE
VDRIVE
ASDATA2
ASDATA1
ABCLK
ALRCLK
ADDR0
SDA
DVDD
TOP VIEW
(Not to Scale)
DIFFERENTIAL OUTPUT
DSDATA3
NC = NO CONNECT
AD1937
07414-002
AGND
MCLKI/MCLKXI
Figure 4. Pin Configuration
Table 11. Pin Function Descriptions
Pin No.
1, 4, 44, 46, 48
2
3
5, 45, 51, 62
6
7
8
9
10
11
12
13
14
15
Type 1
I
I
O
I
O
O
O
O
O
O
O
O
I
I/O
Mnemonic
AGND
MCLKI/MCLKXI
MCLKO/MCLKXO
AVDD
DAC3LP
DAC3LN
DAC3RP
DAC3RN
DAC4LP
DAC4LN
DAC4RP
DAC4RN
PD/RST
DSDATA4
16, 33
17, 32
18
I
I
I/O
DGND
DVDD
DSDATA3
19
I/O
DSDATA2
20
21
22
I
I/O
I/O
DSDATA1
DBCLK
DLRCLK
Description
Analog Ground.
Master Clock Input/Crystal Oscillator Input.
Master Clock Output/Crystal Oscillator Output.
Analog Power Supply. Connect this pin to analog 3.3 V supply.
DAC3 Left Positive Output.
DAC3 Left Negative Output.
DAC3 Right Positive Output.
DAC3 Right Negative Output.
DAC4 Left Positive Output.
DAC4 Left Negative Output.
DAC4 Right Positive Output.
DAC4 Right Negative Output
Power-Down Reset (Active Low).
DAC Serial Data Input 4. Data input to DAC4 data in/TDM DAC2 data out (dual-line mode)/
AUX DAC2 data out (to external DAC2).
Digital Ground.
Digital Power Supply. Connect this pin to digital 3.3 V supply.
DAC Serial Data Input 3. Data input to DAC3 data in/TDM DAC2 data in (dual-line mode)/AUX
ADC2 data in (from external ADC2).
DAC Serial Data Input 2. Data input to DAC2 data in/TDM DAC data out/AUX ADC1 data in
(from external ADC1).
DAC Serial Data Input 1. Data input to DAC1 data in/TDM DAC data in/TDM data in.
Bit Clock for DACs. Can be programmed as input or output in all modes.
Frame Clock for DACs. Can be programmed as input or output in all modes.
Rev. B | Page 11 of 36
AD1937
Pin No.
23
24
25
26
Type 1
I
I
O
I/O
Mnemonic
VSUPPLY
VSENSE
VDRIVE
ASDATA2
27
28
29
30
31
34
35
36
37
38
39
40
41
42
43
47
49, 50, 63, 64
52
53
54
55
56
57
58
59
60
61
O
I/O
I/O
I
I/O
I
I
O
O
O
O
O
O
O
O
O
ASDATA1
ABCLK
ALRCLK
ADDR0
SDA
SCL
ADDR1
DAC1LP
DAC1LN
DAC1RP
DAC1RN
DAC2LP
DAC2LN
DAC2RP
DAC2RN
FILTR
NC
CM
ADC1LP
ADC1LN
ADC1RP
ADC1RN
ADC2LP
ADC2LN
ADC2RP
ADC2RN
LF
1
O
I
I
I
I
I
I
I
I
O
Description
5 V Input to Regulator, Emitter of Pass Transistor.
Connect 3.3 V Regulator Output, Collector of Pass Transistor, to This Pin.
Drive for Base of Pass Transistor.
ADC Serial Data Output 2. Data Output from ADC2/TDM ADC data in/AUX DAC1 data out (to
external DAC1).
ADC Serial Data Output 1. Data Output from ADC1/TDM ADC data out/TDM data out.
Bit Clock for ADCs. Can be programmed as input or output in all modes.
Frame Clock for ADCs. Can be programmed as input or output in all modes.
I2C Address Assignment.
Control Data Port (I2C).
Control Clock Port (I2C).
I2C Address Assignment.
DAC1 Left Positive Output.
DAC1 Left Negative Output.
DAC1 Right Positive Output.
DAC1 Right Negative Output.
DAC2 Left Positive Output.
DAC2 Left Negative Output.
DAC2 Right Positive Output.
DAC2 Right Negative Output.
Analog Voltage Reference Filter Capacitor Connection. Bypass with 10 μF||100 nF to AGND.
No Connect.
Common-Mode Reference Filter Capacitor Connection. Bypass with 47 μF||100 nF to AGND.
ADC1 Left Positive Input.
ADC1 Left Negative Input.
ADC1 Right Positive Input.
ADC1 Right Negative Input.
ADC2 Left Positive Input.
ADC2 Left Negative Input.
ADC2 Right Positive Input.
ADC2 Right Negative Input.
PLL Loop Filter, Return to AVDD.
I = input, O = output.
Rev. B | Page 12 of 36
AD1937
TYPICAL PERFORMANCE CHARACTERISTICS
0.10
0
0.08
0.06
MAGNITUDE (dB)
MAGNITUDE (dB)
0.04
0.02
0
–0.02
–0.04
–50
–100
–0.06
–150
0
2
4
6
8
10
12
14
16
07414-003
–0.10
18
FREQUENCY (kHz)
0
12
24
36
48
FREQUENCY (kHz)
Figure 5. ADC Pass-Band Filter Response, 48 kHz
07414-006
–0.08
Figure 8. DAC Stop-Band Filter Response, 48 kHz
0.10
0
–10
–20
0.05
MAGNITUDE (dB)
MAGNITUDE (dB)
–30
–40
–50
–60
–70
0
–0.05
–80
0
5
10
15
20
25
30
35
–0.10
07414-004
–100
40
FREQUENCY (kHz)
0
24
48
72
96
FREQUENCY (kHz)
Figure 6. ADC Stop-Band Filter Response, 48 kHz
07414-007
–90
Figure 9. DAC Pass-Band Filter Response, 96 kHz
0.06
0
MAGNITUDE (dB)
0.02
0
–0.02
–50
–100
–0.06
–150
0
8
16
FREQUENCY (kHz)
24
Figure 7. DAC Pass-Band Filter Response, 48 kHz
0
24
48
72
FREQUENCY (kHz)
Figure 10. DAC Stop-Band Filter Response, 96 kHz
Rev. B | Page 13 of 36
96
07414-008
–0.04
07414-005
MAGNITUDE (dB)
0.04
AD1937
0.5
0
0.4
0.3
–2
MAGNITUDE (dB)
0.1
0
–0.1
–4
–6
–0.2
–8
–0.3
–0.5
0
8
16
32
64
FREQUENCY (kHz)
–10
48
64
80
FREQUENCY (kHz)
Figure 12. DAC Stop-Band Filter Response, 192 kHz
Figure 11. DAC Pass-Band Filter Response, 192 kHz
Rev. B | Page 14 of 36
96
07414-010
–0.4
07414-009
MAGNITUDE (dB)
0.2
AD1937
THEORY OF OPERATION
ANALOG-TO-DIGITAL CONVERTERS (ADCs)
There are four ADC channels in the AD1937 configured as two
stereo pairs with differential inputs. The ADCs can operate at a
nominal sample rate of 48 kHz, 96 kHz, or 192 kHz. The ADCs
include on-board digital antialiasing filters with 79 dB stopband attenuation and linear phase response, operating at an
oversampling ratio of 128 (48 kHz, 96 kHz, and 192 kHz modes).
Digital outputs are supplied through two serial data output
pins (one for each stereo pair): a common frame clock (ALRCLK)
and a common bit clock (ABCLK). Alternatively, the TDM
modes can be used to access up to 16 channels on a single
TDM data line.
The ADCs must be driven from a differential signal source for
best performance. The input pins of the ADCs connect to internal
switched capacitors. To isolate the external driving op amp from
the glitches caused by the internal switched capacitors, each
input pin should be isolated by using a series-connected external
100 Ω resistor and a 1 nF capacitor connected from each input
to ground. Use a high quality capacitor such as a ceramic
NP0/C0G, or polypropylene film.
The differential inputs have a nominal common-mode voltage
of 1.5 V. The voltage at the common-mode reference pin (CM)
can be used to bias external op amps to buffer the input signals
(see the Power Supply and Voltage Reference section). The
inputs can also be ac-coupled and in that case do not need
an external dc bias to CM.
A digital high-pass filter can be switched in line with the
ADCs (ADC Control 0 Register) to remove residual dc offsets.
It has a 1.4 Hz, 6 dB per octave cutoff at a 48 kHz sample rate.
The cutoff frequency scales directly with sample frequency.
DIGITAL-TO-ANALOG CONVERTERS (DACs)
The AD1937 DAC channels are arranged in four stereo pairs,
giving eight analog outputs; the outputs are differential for
improved noise and distortion performance. The DACs include
on-board digital reconstruction filters with 70 dB stop-band
attenuation and linear phase response, operating at an oversampling ratio of 4 (48 kHz or 96 kHz modes) or 2 (192 kHz
mode). Each channel has its own independently programmable
attenuator, adjustable in 255 steps in increments of 0.375 dB.
Digital inputs are supplied through four serial data input pins
(one for each stereo pair), a common frame clock (DLRCLK),
and a common bit clock (DBCLK). Alternatively, one of the
TDM modes can be used to access up to 16 channels on a
single TDM data line.
Each output pin has a nominal common-mode dc level of 1.5 V
and swings ±1.27 V for a 0 dBFS digital input signal. A single
op amp, third-order, external, low-pass filter is recommended
to remove high frequency noise present on the output pins, as
well as to provide a differential-to-single-ended conversion for
the differential output. Note that the use of op amps with low
slew rates or low bandwidth can cause high frequency noise
and tones to fold down into the audio band; exercise care in
selecting these components.
The voltage at CM can be used to bias the external op amps that
buffer the output signals (see the Power Supply and Voltage
Reference section).
CLOCK SIGNALS
The on-chip phase-locked loop (PLL) can be selected to reference the input sample rate from either of the LRCLK pins
or 256×, 384×, 512×, or 768× sample rate s (fS), referenced to
the 48 kHz mode from the MCLKI/MCLKXI pin. The default at
power-up is 256 × fS from the MCLKI/MCLKXI pin. In 96 kHz
mode, the master clock frequency stays at the same absolute
frequency; therefore, the actual multiplication rate is divided
by 2. In 192 kHz mode, the actual multiplication rate is divided
by 4. For example, if the AD1937 is programmed in 256 × fS
mode, the frequency of the master clock input is 256 × 48 kHz
= 12.288 MHz. If the AD1937 is then switched to 96 kHz
operation (by writing to the I2C port), the frequency of the
master clock should remain at 12.288 MHz, which is 128 × fS
in this example. In 192 kHz mode, this becomes 64 × fS.
The internal clock for the ADCs is 256 × fS for all clock modes.
The internal clock for the DACs varies by mode: 512 × fS (48 kHz
mode), 256 × fS (96 kHz mode), or 128 × fS (192 kHz mode). By
default, the on-board PLL generates this internal master clock
from an external clock. A direct 512 × fS (referenced to 48 kHz
mode) master clock can be used for either the ADCs or DACs,
if selected in the PLL and Clock Control 1 register.
Note that it is not possible to use a direct clock for the ADCs
set to the 192 kHz mode. It is required that the on-chip PLL
be used in this mode.
The PLL can be powered down in the PLL and Clock Control 0
Register. To ensure reliable locking when changing PLL modes,
or if the reference clock is unstable at power-on, power down
the PLL and then power it back up after the reference clock has
stabilized.
The internal master clock (MCLK) can be disabled in the
PLL and Clock Control 0 register to reduce power dissipation
when the AD1937 is idle. The clock should be stable before it
is enabled. Unless a standalone mode is selected (see the I2C
Control Port section), the clock is disabled by reset and must
be enabled by writing to the I2C port for normal operation.
Rev. B | Page 15 of 36
AD1937
To maintain the highest performance possible, limit the clock jitter
of the internal master clock signal to less than a 300 ps rms time
interval error (TIE). Even at these levels, extra noise or tones
can appear in the DAC outputs if the jitter spectrum contains
large spectral peaks. If the internal PLL is not used, it is best to
use an independent crystal oscillator to generate the master clock.
In addition, it is especially important that the clock signal not
pass through an FPGA, CPLD, or other large digital chip (such
as a DSP) before being applied to the AD1937. In most cases,
this induces clock jitter due to the sharing of common power
and ground connections with other unrelated digital output
signals. When the PLL is used, jitter in the reference clock is
attenuated above a certain frequency depending on the loop filter.
RESET AND POWER-DOWN
The function of the PD/RST pin sets all the control registers to
their default settings. To avoid audio pops, PD/RST does not
power down the analog outputs. After PD/RST is deasserted
and the PLL acquires lock condition, an initialization routine
runs inside the AD1937. This initialization lasts for approximately 256 master clock cycles. Once the routine is complete,
the registers can be programmed.
The power-down bits in the PLL and Clock Control 0, DAC
Control 1, and ADC Control 1 registers power down their
respective sections. All other register settings are retained.
To guarantee proper startup, the PD/RST pin should be
pulled low by an external resistor.
2
I C CONTROL PORT
The AD1937 has an I2C-compatible control port that permits
programming and reading back the internal control registers
for the ADCs, DACs, and clock system. There is also a standalone mode available for operation without serial control,
configured at reset using the serial control pins. All registers
are set to default except internal MCLK enable, which is set to
1 and ADC BCLK and LRCLK master/slave is set by SDA (see
Table 12 for details).
Table 12. Hardware Selection of Standalone Mode
ADC Clocks
Slave
Master
ADDR0
(Pin 30)
0
0
SDA
(Pin 31)
0
1
SCL
(Pin 34)
0
0
ADDR1
(Pin 35)
0
0
The I2C interface of the AD1937 is a 2-wire interface that
consists of a clock line (SCL) and a data line (SDA). SDA
is bidirectional and the AD1937 drives SDA either to acknowledge the master (ACK) or to send data during a read operation.
The SDA pin for the I2C port is an open-drain collector and
requires a 2 kΩ pull-up resistor. A write or read access occurs
when the SDA line is pulled low while the SCL line is high,
indicated by start in the timing diagrams. SDA is only allowed
to change when SCL is low except when a start or stop condition
occurs, as shown in Figure 13 and Figure 14. The first eight bits
of the data-word consist of the device address and the R/W bit.
The device address consists of an internal built-in address
(0x08) OR’ed with the two address bits, ADDR1 and ADDR0,
and the R/W bit. The two address bits allow four AD1937s to be
used in a system. Tie I2C ADDR0 and ADDR1 low or high and
program the ADDR bits accordingly as 0 or 1. Initiating a write
operation to the AD1937 involves sending a start condition and
then sending the device address with the R/W bit set low. The
AD1937 responds by issuing an acknowledge to indicate that it
has been addressed. The user then sends a second frame telling
the AD1937 which register is required to be written to. Another
acknowledge is issued by the AD1937. Finally, the user can send
another frame with the eight data bits required to be written to
the register. A third acknowledge is issued by the AD1937 after
which the user can send a stop condition to complete the data
transfer.
A read operation requires that the user first write to the
AD1937 to point to the correct register and then read the
data. This is achieved by sending a start condition followed
by the device address frame, with the R/W bit low; the AD1937
returns an acknowledge. The master then sends the register
address frame. Following the acknowledge from the AD1937,
the user must issue a repeated start condition. The next frame
is the device address with the R/W bit set high; the AD1937
returns an acknowledge. On the next frame, the AD1937
outputs the register data on the SDA line; the master should
send an acknowledge. A stop condition completes the read
operation. Figure 13 and Figure 14 show examples of writing
to and reading from the DAC1L volume control register,
Address 0x06 (see Table 28).
Rev. B | Page 16 of 36
AD1937
SCK
SDA
0
0
0
START BY
MASTER (S)
0
1
ADDR1
R/W
ADDR0
0
0
0
ACK. BY
AD1937 (AS)
FRAME 1
CHIP ADDRESS BYTE
0
0
1
1
0
ACK. BY
MASTER (AM)
FRAME 2
REGISTER ADDRESS BYTE
SCK
(CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
MASTER (AM)
FRAME 3
DATA BYTE TO AD1937
STOP BY
MASTER (P)
07414-011
SDA
(CONTINUED)
Figure 13. I2C Write Format
SCK
0
SDA
0
0
START BY
MASTER (S)
0
1
ADDR1
ADDR0
R/W
0
0
ACK. BY
AD1937 (AS)
FRAME 1
CHIP ADDRESS BYTE
0
0
0
1
1
0
ACK. BY
AD1937 (AS)
FRAME 2
REGISTER ADDRESS BYTE
SCL
(CONTINUED)
0
REPEATED START
BY MASTER (S)
0
0
0
1
ADDR1 ADDR0
FRAME 3
CHIP ADDRESS BYTE
R/W
D7
ACK. BY
AD1937 (AS)
Figure 14. I2C Read Format
Rev. B | Page 17 of 36
D6
D5
D4
D3
D2
FRAME 4
REGISTER DATA
D1
D0
ACK. BY
STOP BY
MASTER (AM) MASTER (P)
07414-012
SDA
(CONTINUED)
AD1937
Table 13. I2C Abbreviation Table
Abbreviation
S
P
AM
AS
Condition
Repeated start by master
Stop by master
Acknowledge by master
Acknowledge by AD1937
Table 14. Single Word I2C Write
S
Chip Address, R/W = 0
AS
Register Address
AS
Data Word
AS
P
Table 15. Burst Mode I2C Write
S
Chip Address, R/W = 0
AS
Register Address
AS
Data Word 1
AS
Data Word 2
AS
Data Word N
AS
P
Table 16. Single Word I2C Read
S
Chip Address, R/W = 0
AS
Register Address
AS
S
Chip Address, R/W = 1
AS
Data Word
AM
P
Table 17. Burst Mode I2C Read
S
Chip Address,
R/W = 0
AS
Register
Address
AS
S
Chip Address,
R/W = 1
POWER SUPPLY AND VOLTAGE REFERENCE
The AD1937 is designed for a 3.3 V supply. Separate power
supply pins are provided for the analog and digital sections.
To minimize noise pickup, these pins should be bypassed with
100 nF ceramic chip capacitors placed as close to the pins as
possible. A bulk aluminum electrolytic capacitor of at least
22 μF should also be provided on the same printed circuit
board (PCB) as the codec. For critical applications, improved
performance is obtained with separate supplies for the analog
and digital sections. If this is not possible, it is recommended
that the analog and digital load pins be isolated by means of a
ferrite bead in series with the supply. It is important that the
analog supply be as clean as possible.
The AD1937 includes a 3.3 V regulator driver that only requires
an external pass transistor, a resistor, and bypass capacitors to
turn a 5 V supply into 3.3 V. If the regulator driver is not used,
connect VSUPPLY, VDRIVE, and VSENSE to DGND.
AS
Data
Word 1
AM
Data
Word 2
AM
Data
Word N
AM
P
The ADC and DAC internal analog voltage reference (VREF) is
brought out on the FILTR pin and should be bypassed as close
as possible to the chip with a parallel combination of 10 μF and
100 nF capacitors. Any external current drawn should be limited
to less than 50 μA.
The internal reference can be disabled in the PLL and Clock
Control 1 register, and FILTR can be driven from an external
source. This can be used to scale the DAC output to the clipping
level of a power amplifier based on its power supply voltage.
The ADC input gain varies by the inverse ratio. It is not advisable
to drive the FILTR pin with more than (AVDD/2) V. The total
gain from ADC input to DAC output remains constant.
The CM pin should be bypassed as close as possible to the chip,
with a parallel combination of 47 μF and 100 nF capacitors. This
voltage can be used to bias external op amps to the common-mode
voltage of the input and output signal pins. The output current
should be limited to less than 0.5 mA source and 2 mA sink.
All digital inputs are compatible with TTL and CMOS levels.
All outputs are driven from the 3.3 V DVDD supply and are
compatible with TTL and 3.3 V CMOS levels.
Rev. B | Page 18 of 36
AD1937
24 bits by default and can be set to 16 or 20 bits in the DAC
Control 2 and ADC Control 1 registers. The DAC serial formats
are programmable in the DAC Control 0 register. The polarity of
DBCLK and DLRCLK is programmable in the DAC Control 1 register. The ADC serial format is programmable in ADC Control 1
register. The ABCLK and ALRCLK clock polarities are programmed in ADC Control 2 register. In Figure 2, Figure 3, and
Figure 15 all of the clocks are shown with their normal polarity.
Both DAC and ADC serial ports can be programmed to become
the bus masters according to DAC Control 1 and ADC Control 2
registers. By default, both ADC and DAC serial ports are in the
slave mode.
SERIAL DATA PORTS—DATA FORMAT
The eight DAC channels use a common serial bit clock (DBCLK)
and a common left-right framing clock (DLRCLK) in the serial
data port. The four ADC channels use a common serial bit
clock (ABCLK) and left-right framing clock (ALRCLK) in the
serial data port. The clock signals are all synchronous with the
sample rate. The normal stereo serial modes are shown in
Figure 15.
The ADC and DAC serial data modes default to I2S stereo.
The ports can also be programmed for left-justified stereo,
right-justified stereo, and TDM modes. The word width is
LEFT CHANNEL
LRCLK
RIGHT CHANNEL
BCLK
SDATA
LSB
MSB
LSB
MSB
LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
LEFT CHANNEL
LRCLK
RIGHT CHANNEL
BCLK
SDATA
MSB
LSB
MSB
LSB
I2S-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
LEFT CHANNEL
LRCLK
RIGHT CHANNEL
BCLK
SDATA
MSB
LSB
MSB
LSB
RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL
LRCLK
BCLK
MSB
MSB
LSB
LSB
DSP MODE—16 BITS TO 24 BITS PER CHANNEL
1/fS
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT fS EXCEPT FOR DSP MODE, WHICH IS 2 × fS.
3. BCLK FREQUENCY IS NORMALLY 64 × LRCLK BUT MAY BE OPERATED IN BURST MODE.
Figure 15. Stereo Modes
Rev. B | Page 19 of 36
07414-024
SDATA
AD1937
The I/O pin functions of the serial ports are defined according
to the serial mode that is selected. For a detailed description of
the function of each pin in TDM and TDM/AUX modes, see
Table 18.
TIME-DIVISION MULTIPLEXED (TDM) MODES
The serial ports of the AD1937 have several different TDM
serial data modes. Single-line TDM mode is the most commonly used configuration (see Figure 16 and Figure 17).
These figures show 8-channel configuration; other possible
options are 4- and 16-channel configurations. In Figure 16,
the eight on-chip DAC data slots are packed into one I2S
TDM stream. In this mode, both DBCLK and ABCLK are
256 fS. In Figure 17, the ADC serial port outputs one data
stream consisting of four on-chip ADCs followed by four
unused slots.
The AD1937 allows systems with more than eight DAC channels
to be easily configured by the use of an auxiliary serial data port.
The TDM/AUX mode 16-channel configuration is shown in
Figure 18. In this mode, the AUX channels are the last four
slots of the TDM data stream. These slots are extracted and
output to the AUX serial port. It should be noted that due to
the high DBCLK frequency, this mode is available only in the
48 kHz/44.1 kHz/32 kHz sample rates. An 8-channel DAC
configuration cannot be TDM/AUX because there are no
extra data slots for the AUX packets; this would be singleline TDM mode.
DLRCLK
256 BCLKs
DBCLK
DSDATA
32 BCLKs
SLOT 1
LEFT 1
SLOT 2
RIGHT 1
SLOT 3
LEFT 2
SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8
RIGHT 2 LEFT 3 RIGHT 3 LEFT 4 RIGHT 4
LRCLK
MSB
MSB – 1
MSB – 2
07414-014
BCLK
DATA
Combining the TDM/AUX ADC and DAC modes results in
a system configuration of 8 ADCs and 12 DACs. The system,
then consists of two external stereo ADCs, two external stereo
DACs, and one AD1937. This mode is shown in Figure 21
(combined TDM/AUX DAC and ADC modes).
Figure 16. Single-Line TDM Mode 8-Channel DAC Configuration
ALRCLK
256 BCLKs
ABCLK
ASDATA
32 BCLKs
SLOT 1
LEFT 1
SLOT 2
RIGHT 1
SLOT 3
LEFT 2
SLOT 4
SLOT 5 SLOT 6 SLOT 7 SLOT 8
RIGHT 2
LRCLK
MSB – 1
MSB – 2
07414-013
BCLK
MSB
DATA
The AD1937 also allows system configurations with more
than four ADC channels as shown in Figure 19 (using 8 ADCs)
and Figure 20 (using 16 ADCs). Due to the high ABCLK
frequency, this mode is available only in the 48 kHz/44.1 kHz/
32 kHz sample rates.
Figure 17. Single-Line TDM Mode 8-Channel ADC Configuration
In the TDM/AUX mode, the frame sync (ALRCLK) triggers
the TDM word by crossing the high frequency TDM BCLK
(ABCLK) to 0, similar to the single-line TDM modes (see
Figure 16 and Figure 17). The AUX LRCLK (DLRCLK) runs at
the much slower fS of the AUX port; the AUX BCLK (DBCLK)
runs at 64 × fS. This is shown in the TDM/AUX figures (see
Figure 18 to Figure 21).
Table 18. Pin Function Changes in TDM and TDM/AUX Modes
Mnemonic
ASDATA1
ASDATA2
DSDATA1
DSDATA2
DSDATA3
DSDATA4
ALRCLK
ABCLK
DLRCLK
DBCLK
Stereo Modes
ADC1 data out
ADC2 data out
DAC1 data in
DAC2 data in
DAC3 data in
DAC4 data in
ADC LRCLK in/out
ADC BCLK in/out
DAC LRCLK in/out
DAC BCLK in/out
TDM Modes
TDM ADC data out
TDM ADC data in
TDM DAC data in
TDM DAC data out
TDM DAC2 data in (dual-line mode)
TDM DAC2 data out (dual-line mode)
TDM ADC frame sync in/out
TDM ADC BCLK in/out
TDM DAC frame sync in/out
TDM DAC BCLK in/out
Rev. B | Page 20 of 36
TDM/AUX Modes
TDM data out
AUX DAC1 data out (to external DAC1)
TDM data in
AUX ADC1 data in (from external ADC1)
AUX ADC2 data in (from external ADC2)
AUX DAC2 data out (to external DAC2)
TDM frame sync in/out
TDM BCLK in/out
AUX LRCLK in/out
AUX BCLK in/out
AD1937
ALRCLK
ABCLK
DSDATA1
(TDM DATA IN)
UNUSED SLOTS
EMPTY
EMPTY
EMPTY
AUX DAC CHANNELS
APPEAR AT
AUX DAC PORTS
8 ON-CHIP DAC CHANNELS
EMPTY
DAC1L
DAC1R
DAC2L
DAC2R
DAC3L
DAC3R
DAC4L
DAC4R
AUX1L
AUX1R
AUX2L
AUX2R
32 BITS
MSB
DLRCLK
(AUX LRCLK IN/OUT)
LEFT
RIGHT
ASDATA2
(AUX DAC1 DATA OUT)
MSB
MSB
DSDATA4
(AUX DAC2 DATA OUT)
MSB
MSB
07414-015
DBCLK
(AUX BCLK IN/OUT)
Figure 18. TDM/AUX Mode 16-Channel DAC configuration
ALRCLK
ABCLK
8 ON-CHIP DAC CHANNELS
DSDATA1
(TDM DATA IN)
DACL1
ASDATA1
(TDM DATA OUT)
ADCL1
DACR1
DACL2
DACR2
DACL3
DACR3
ADCR2
AUXL1
AUXR1
4 ON-CHIP ADC CHANNELS
ADCR1
ADCL2
DACL4
DACR4
4 AUX ADC CHANNELS
AUXL2
AUXR2
32 BITS
MSB
DLRCLK
(AUX LRCLK IN/OUT)
LEFT
RIGHT
DSDATA2
(AUX ADC1 DATA IN)
MSB
MSB
DSDATA3
(AUX ADC2 DATA IN)
MSB
MSB
Figure 19. TDM/AUX Mode 8-Channel ADC Configuration
Rev. B | Page 21 of 36
07414-016
DBCLK
(AUX BCLK IN/OUT)
AD1937
ALRCLK
ABCLK
ASDATA1
(TDM DATA OUT)
4 ON-CHIP ADC CHANNELS
ADCL1
ADCR1
ADCL2
ADCR2
AUXILIARY ADC CHANNELS
AUXL1
AUXR1
AUXL2
UNUSED SLOTS
AUXR2 UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED
32 BITS
MSB
DLRCLK
(AUX LRCLK IN/OUT)
LEFT
RIGHT
DSDATA2
(AUX ADC1 DATA IN)
MSB
MSB
DSDATA3
(AUX ADC2 DATA IN)
MSB
MSB
07414-017
DBCLK
(AUX BCLK IN/OUT)
Figure 20. TDM/AUX Mode 16-Channel ADC Configuration
ALRCLK
ABCLK
UNUSED SLOTS
DSDATA1
(TDM DATA IN)
EMPTY
ASDATA1
(TDM DATA OUT)
ADCL1
DLRCLK
(AUX LRCLK IN/OUT)
EMPTY
EMPTY
EMPTY
4 ON-CHIP ADC CHANNELS
ADCR1
ADCL2
AUXILIARY DAC CHANNELS
APPEAR AT
AUX DAC PORTS
8 ON-CHIP DAC CHANNELS
ADCR2
DACL1
DACR1
DACL2
DACR2
DACL3
AUXILIARY ADC CHANNELS
AUXL1
AUXR1
AUXL2
DACR3
DACL4
DACR4
AUXL1
AUXR1
AUXL2
AUXR2
UNUSED SLOTS
AUX R2 UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED
LEFT
RIGHT
DSDATA2
(AUX ADC1 DATA IN)
MSB
MSB
DSDATA3
(AUX ADC2 DATA IN)
MSB
MSB
ASDATA2
(AUX ADC1 DATA OUT)
MSB
MSB
DSDATA4
(AUX DAC2 DATA OUT)
MSB
MSB
Figure 21. Combined TDM/AUX Mode DAC and ADC Configuration
Rev. B | Page 22 of 36
07414-018
DBCLK
(AUX BCLK IN/OUT)
AD1937
There are two configurations for the ADC port to work in
daisy-chain mode. The first configuration is with an ABCLK
at 256 × fS, see Figure 25. The second configuration is with an
ABCLK at 512 × fS, see Figure 26. Note that in the 512 × fS
ABCLK mode, the ADC channels occupy the first eight
slots; the second eight slots are empty. The TDM ADC data
in (ASDATA2) port of the first AD1937 must be grounded
in all modes of operation.
DAISY-CHAIN MODE
The AD1937 also allows a daisy-chain configuration to expand
the system to 16 DACs and 8 ADCs (see Figure 22 to Figure 26).
In this mode, the DBCLK frequency is 512 × fS. The first eight
slots of the TDM DAC data stream belong to the first AD1937
in the chain and the last eight slots belong to the second AD1937.
The second AD1937 is the device attached to the DSP TDM port.
To accommodate 16 channels at a 96 kHz sample rate, the
AD1937 can be configured into a dual-line, TDM mode as
shown in Figure 23. This mode allows a slower DBCLK than
normally required by the one-line TDM mode. The first four
channels of each TDM input belong to the first AD1937 in the
chain and the last four channels belong to the second AD1937.
The I/O pins of the serial ports are defined according to the
serial mode selected. See Table 19 for a detailed description
of the function of each pin. See Figure 27 for a typical AD1937
configuration with two external stereo DACs and two external
stereo ADCs.
The dual-line TDM mode can also be used to send data at a
192 kHz sample rate into the AD1937, as shown in Figure 24.
DLRCLK
DBCLK
8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN
DSDATA1 (TDM ADC DATA IN)
OF THE SECOND AD1937
DAC1L
DAC1R
DAC2L
DSDATA2 (TDM DAC DATA OUT)
OF THE SECOND AD1937;
THIS IS THE TDM
TO THE FIRST AD1937
DAC2R
DAC3L
DAC3R
DAC4L
DAC4R
8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN
DAC1L
DAC1R
DAC2L
DAC2R
DAC3L
DAC3R
DAC4L
DAC4R
DAC1L
DAC1R
DAC2L
DAC2R
DAC3L
DAC3R
DAC4L
DAC4R
8 UNUSED SLOTS
FIRST
AD1937
SECOND
AD1937
DSP
07414-019
32 BITS
MSB
Figure 22. Single-Line Daisy-Chain TDM Mode 16-Channel 48 kHz DAC Configuration
DLRCLK
DBCLK
8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN
DSDATA1
(TDM DAC DATA IN)
DAC1L
DAC1R
DAC2L
DAC2R
DSDATA2
(TDM DAC DATA OUT)
DSDATA3
(TDM DAC2 DATA IN)
DAC3L
DAC3R
DSDATA4
(TDM DAC2 DATA OUT)
DAC4L
DAC4R
8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN
DAC1L
DAC1R
DAC2L
DAC2R
DAC1L
DAC1R
DAC2L
DAC2R
DAC3L
DAC3R
DAC4L
DAC4R
DAC3L
DAC3R
DAC4L
DAC4R
32 BITS
FIRST
AD1937
SECOND
AD1937
07414-020
MSB
DSP
Figure 23. Dual-Line Daisy-Chain TDM Mode16-Channel 96 kHz DAC Configuration
Rev. B | Page 23 of 36
AD1937
DLRCLK
DBCLK
DSDATA1
DAC1L
DAC1R
DAC2L
DAC2R
DSDATA2
DAC3L
DAC3R
DAC4L
DAC4L
07414-021
32 BITS
MSB
Figure 24. Dual-Line Daisy-Chain TDM Mode 8-Channel 192 kHz DAC Configuration
ALRCLK
ABCLK
4 ADC CHANNELS OF SECOND IC IN THE CHAIN
4 ADC CHANNELS OF FIRST IC IN THE CHAIN
ASDATA1 (TDM ADC DATA OUT)
OF THE SECOND AD1937
IN THE CHAIN
ADC1L
ADC1R
ADC2L
ADC2R
ASDATA2 (TDM ADC DATA IN)
OF THE SECOND AD1937
IN THE CHAIN
ADC1L
ADC1R
ADC2L
ADC2R
ADC1L
ADC1R
ADC2L
ADC2R
32 BITS
SECOND
AD1937
DSP
MSB
07414-022
FIRST
AD1937
Figure 25. Single-Line Daisy-Chain TDM Mode 256 × fS ADC Configuration
ALRCLK
ABCLK
4 ADC CHANNELS OF
SECOND IC IN THE CHAIN
ASDATA1 (TDM ADC DATA OUT)
OF THE SECOND AD1937
IN THE CHAIN
ADCL1
ADCR1
ADCL2
ADCR2
ASDATA2 (TDM ADC DATA IN)
OF THE SECOND AD1937
IN THE CHAIN
ADCL1
ADCR1
ADCL2
ADCR2
4 ADC CHANNELS OF
FIRST IC IN THE CHAIN
ADCL1
ADCR1
ADCL2
ADCR2
FIRST
AD1937
SECOND
AD1937
DSP
MSB
Figure 26. Single-Line Daisy-Chain TDM Mode 512 × fS ADC Configuration
Rev. B | Page 24 of 36
07414-023
32 BITS
AD1937
Table 19. Pin Function Changes in TDM and TDM/AUX Modes (Replication of Table 18)
Stereo Modes
ADC1 data out
ADC2 data out
DAC1 data in
DAC2 data in
DAC3 data in
DAC4 data in
ADC LRCLK in/out
ADC BCLK in/out
DAC LRCLK in/out
DAC BCLK in/out
TDM Modes
TDM ADC data out
TDM ADC data in
TDM DAC data in
TDM DAC data out
TDM DAC2 data in (dual-line mode)
TDM DAC2 data out (dual-line mode)
TDM ADC frame sync in/out
TDM ADC BCLK in/out
TDM DAC frame sync in/out
TDM DAC BCLK in/out
TxDATA
TxCLK
TFS (NC)
RxDATA
SHARC
RxCLK
12.288MHz
LRCLK
AUX
ADC 1
LRCLK
BCLK
DATA
MCLK
TDM/AUX Modes
TDM data out
AUX DAC1 data out (to external DAC1)
TDM data in
AUX ADC1 data in (from external ADC1)
AUX ADC2 data in (from external ADC2)
AUX DAC2 data out (to external DAC2)
TDM frame sync in/out
TDM BCLK in/out
AUX LRCLK in/out
AUX BCLK in/out
SHARC IS RUNNING IN SLAVE MODE
(INTERRUPT-DRIVEN)
30MHz
FSYNC-TDM (RFS)
BCLK
ASDATA1 ALRCLK ABCLK DSDATA1
AUX
DATA DAC 1
MCLK
DBCLK
DLRCLK
AD1937
BCLK
DSDATA2
DATA
DSDATA3
TDM MASTER
AUX MASTER
MCLK
MCLKI/MCLKXI
LRCLK
AUX
ADC 2
LRCLK
ASDATA2
DSDATA4
BCLK
AUX
DATA DAC 2
MCLK
Figure 27. Example of TDM/AUX Mode Connection to SHARC® (AD1937 as TDM Master/AUX Master Shown)
Rev. B | Page 25 of 36
07414-027
Mnemonic
ASDATA1
ASDATA2
DSDATA1
DSDATA2
DSDATA3
DSDATA4
ALRCLK
ABCLK
DLRCLK
DBCLK
AD1937
ADDITIONAL MODES
The AD1937 offers several additional modes for board level
design enhancements. To reduce the EMI in board level design,
serial data can be transmitted without an explicit BCLK. See
Figure 28 and Figure 29 for an example of a DAC TDM data
transmission mode that does not require high speed DBCLK.
This configuration is applicable when the AD1937 master
clock is generated by the PLL with the DLRCLK as the PLL
reference frequency.
To relax the requirement for the setup time of the AD1937 in
cases of high speed TDM data transmission, the AD1937 can
latch in the data using the falling edge of DBCLK. This effectively dedicates the entire BCLK period to the setup time. This
mode is useful in cases where the source has a large delay time
in the serial data driver. Figure 30 shows this pipeline mode of
data transmission.
Both the BCLK-less and pipeline modes are available on the
ADC serial data port.
DLRCLK
32 BITS
07414-028
INTERNAL
DBCLK
DSDATAx
Figure 28. Serial DAC Data Transmission in TDM Format Without DBCLK; 2-Channel 64 BCLKs per Frame Mode
(Applicable Only If PLL Locks to DLRCLK; This Mode Is Also Available in the ADC Serial Data Port)
DLRCLK
DBCLK
DSDATAn
07414-029
DATA MUST BE VALID
AT THIS BCLK EDGE
MSB
Figure 29. Serial DAC Data Transmission in TDM Format Without DBCLK; 128 to 512 BCLKs per Frame TDM Mode
(Applicable Only If PLL Locks to DLRCLK; This Mode Is Also Available in the ADC Serial Data Port)
DLRCLK
07414-128
INTERNAL
DBCLK
TDM DSDATAn
Figure 30. I2S Pipeline Mode in DAC Serial Data Transmission
(Applicable in Stereo and TDM, Useful for High Frequency TDM Transmission;
This Mode Is Also Available in the ADC Serial Data Port)
Rev. B | Page 26 of 36
AD1937
CONTROL REGISTERS
DEFINITIONS
The global address for the AD1937 is 0x08 OR’ed with ADDR1 and ADDR0 and one R/W bit; see Figure 13 and Figure 14. The address
bits (Bits[18:17]) setting must correspond to the low/high state of Pin 30 and Pin 35. All registers are reset to 0, except for the DAC
volume registers that are set to full volume.
Note that the first setting in each control register parameter is the default setting.
Table 20. Register Format
Bit
Global Address
R/W
Register Address
Data
23:17
16
15:8
7:0
Table 21. Register Addresses and Functions
Hexadecimal
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
Address
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Function
PLL and Clock Control 0
PLL and Clock Control 1
DAC Control 0
DAC Control 1
DAC Control 2
DAC individual channel mutes
DAC1L volume control
DAC1R volume control
DAC2L volume control
DAC2R volume control
DAC3L volume control
DAC3R volume control
DAC4L volume control
DAC4R volume control
ADC Control 0
ADC Control 1
ADC Control 2
PLL AND CLOCK CONTROL REGISTERS
Table 22. PLL and Clock Control 0 Register (Address 0, 0x00)
Bit
0
2:1
4:3
6:5
7
Value
0
1
00
01
10
11
00
01
10
11
00
01
10
11
0
1
Function
Normal operation
Power-down
Input 256 (× 44.1 kHz or 48 kHz)
Input 384 (× 44.1 kHz or 48 kHz)
Input 512 (× 44.1 kHz or 48 kHz)
Input 768 (× 44.1 kHz or 48 kHz)
XTAL oscillator enabled
256 × fS VCO output
512 × fS VCO output
Off
MCLKI/MCLKXI
DLRCLK
ALRCLK
Reserved
Disable: ADC and DAC idle
Enable: ADC and DAC active
Description
PLL power-down
MCLKI/MCLKXI pin functionality (PLL active), master clock rate setting
MCLKO/MCLKXO pin, master clock rate setting
PLL input
Internal master clock enable
Rev. B | Page 27 of 36
AD1937
Table 23. PLL and Clock Control 1 Register (Address 1, 0x01)
Bit
0
1
2
3
7:4
Value
0
1
0
1
0
1
0
1
0000
Function
PLL clock
MCLK
PLL clock
MCLK
Enabled
Disabled
Not locked
Locked
Reserved
Description
DAC clock source select
ADC clock source select
On-chip voltage reference
PLL lock indicator (read-only)
DAC CONTROL REGISTERS
Table 24. DAC Control 0 Register (Address 2, 0x02)
Bit
0
2:1
5:3
7:6
Value
0
1
00
01
10
11
000
001
010
011
100
101
110
111
00
01
10
11
Function
Normal
Power-down
32 kHz/44.1 kHz/48 kHz
64 kHz/88.2 kHz/96 kHz
128 kHz/176.4 kHz/192 kHz
Reserved
1 cycle (I2S mode)
0 (left-justified mode)
8 cycles (right-justified 24-bit mode)
12 cycles (right-justified 20-bit mode)
16 cycles (right-justified 16-bit mode)
Reserved
Reserved
Reserved
Stereo (normal)
TDM single-line, standalone, and daisy-chain modes
TDM/AUX mode (ADC-, DAC-, TDM-coupled)
TDM dual-line daisy-chain mode
Description
Power-down
Sample rate
DSDATA delay (BCLK periods)
Serial format
Rev. B | Page 28 of 36
AD1937
Table 25. DAC Control 1 Register (Address 3, 0x03)
Bit
0
2:1
3
4
5
6
7
Value
0
1
00
01
10
11
0
1
0
1
0
1
0
1
0
1
Function
Latch in midcycle (normal)
Latch in at end of cycle (pipeline)
64 (2 channels)
128 (4 channels)
256 (8 channels)
512 (16 channels)
Left low
Left high
Slave
Master
Slave
Master
DBCLK pin
Internally generated
Normal
Inverted
Description
DBCLK active edge (TDM_IN)
DBCLKs per frame
DLRCLK polarity
DLRCLK master/slave
DBCLK master/slave
DBCLK source
DBCLK polarity
Table 26. DAC Control 2 Register (Address 4, 0x04)
Bit
0
2:1
4:3
5
7:6
Value
0
1
00
01
10
11
00
01
10
11
0
1
00
Function
Unmute
Mute
Flat
48 kHz curve
44.1 kHz curve
32 kHz curve
24 bits
20 bits
Reserved
16 bits
Noninverted
Inverted
Reserved
Description
Master mute
De-emphasis (32 kHz/44.1 kHz/48 kHz mode only)
Word width
DAC output polarity
Table 27. DAC Individual Channel Mutes Register (Address 5, 0x05)
Bit
0
1
2
3
4
5
6
7
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Function
Unmute
Mute
Unmute
Mute
Unmute
Mute
Unmute
Mute
Unmute
Mute
Unmute
Mute
Unmute
Mute
Unmute
Mute
Description
DAC1L mute
DAC1R mute
DAC2L mute
DAC2R mute
DAC3L mute
DAC3R mute
DAC4L mute
DAC4R mute
Rev. B | Page 29 of 36
AD1937
Table 28. DACxx Volume Controls Registers (Address 6 to Address 13, 0x06 to 0x0D)
Bit
7:0
Value
0
1 to 254
255
Function
No attenuation
−0.375 dB per step
Full attenuation
Description
DAC volume control
ADC CONTROL REGISTERS
Table 29. ADC Control 0 Register (Address 14, 0x0E)
Bit
0
1
2
3
4
5
7:6
Value
0
1
0
1
0
1
0
1
0
1
0
1
00
01
10
11
Function
Normal
Power down
Off
On
Unmute
Mute
Unmute
Mute
Unmute
Mute
Unmute
Mute
32 kHz/44.1 kHz/48 kHz
64 kHz/88.2 kHz/96 kHz
128 kHz/176.4 kHz/192 kHz
Reserved
Description
Power-down
High-pass filter
ADC1L mute
ADC1R mute
ADC2L mute
ADC2R mute
Output sample rate
Table 30. ADC Control 1 Register (Address 15, 0x0F)
Bit
1:0
4:2
6:5
7
Value
00
01
10
11
000
001
010
011
100
101
110
111
00
01
10
11
0
1
Function
24 bits
20 bits
Reserved
16 bits
1 cycle (I2S mode)
0 (left-justified mode)
8 cycles (right-justified 24-bit mode)
12 cycles (right-justified 20-bit mode)
16 cycles (right-justified 16-bit mode)
Reserved
Reserved
Reserved
Stereo
TDM single-line, standalone, and daisy-chain modes
TDM/AUX mode (ADC-, DAC-, TDM-coupled)
Reserved
Latch in midcycle (normal)
Latch in at end of cycle (pipeline)
Rev. B | Page 30 of 36
Description
Word width
ASDATA delay (BCLK periods)
Serial format
ABCLK active edge (TDM_IN)
AD1937
Table 31. ADC Control 2 Register (Address 16, 0x10)
Bit
0
1
2
3
5:4
6
7
Value
0
1
0
1
0
1
0
1
00
01
10
11
0
1
0
1
Function
50/50 (allows 32, 24, 20, or 16 BCLKs per channel)
Pulse (32 BCLKs per channel)
Drive out on falling edge (DEF)
Drive out on rising edge
Left low
Left high
Slave
Master
64 cycles
128 cycles
256 cycles
512 cycles
Slave
Master
ABCLK pin
Internally generated
Rev. B | Page 31 of 36
Description
ALRCLK format
ABCLK polarity
ALRCLK polarity
ALRCLK master/slave
ABCLKs per frame
ABCLK master/slave
ABCLK source
AD1937
APPLICATIONS CIRCUITS
Typical application circuits are shown in Figure 31 through Figure 34. Figure 31 shows a typical ADC input filter circuit. Recommended
loop filters for LRCLK and MCLK as the PLL reference are shown in Figure 32. Output filters for the DAC outputs are shown in Figure 33
and a regulator circuit is shown in Figure 34.
120pF
5.76kΩ
5.76kΩ
2
100pF
3
–
1
OP275
+
68pF
NPO
11kΩ
4.7µF 237Ω
5.76kΩ
+
120pF
DAC
OUTN
ADCxxN
1nF
NPO
11kΩ
100pF
5
5.76kΩ
–
OP275
1nF
NPO
4.7µF 237Ω
7
DAC
OUTP
ADCxxP
+
+
07414-030
6
Figure 31. Typical ADC Input Filter Circuit
5.62kΩ
3.01kΩ
270pF
NPO
2
560pF
NPO
3
1.50kΩ
–
1
OP275
+
604Ω
2.2nF
NPO
150pF
NPO
5.62kΩ
Figure 33. Typical DAC Output Filter Circuit (Differential)
100nF
+
10µF
VSUPPLY
5V
1kΩ
LRCLK
LF
39nF
MCLK
562Ω
AVDD2
FZT953
VSENSE
390pF
3.32kΩ
AVDD2
E
C
5.6nF
2.2nF
B
VDRIVE
3.3V
100nF
07414-031
LF
AUDIO
OUTPUT
07414-032
600Z
Figure 32. Recommended Loop Filters for LRCLK or MCLK as PLL Reference
Rev. B | Page 32 of 36
+
10µF
07414-033
AUDIO
INPUT
Figure 34. Recommended 3.3 V Regulator Circuit
AD1937
OUTLINE DIMENSIONS
0.75
0.60
0.45
12.20
12.00 SQ
11.80
1.60
MAX
64
49
1
48
PIN 1
10.20
10.00 SQ
9.80
TOP VIEW
(PINS DOWN)
0.15
0.05
SEATING
PLANE
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
VIEW A
16
33
32
17
VIEW A
0.50
BSC
LEAD PITCH
ROTATED 90° CCW
0.27
0.22
0.17
COMPLIANT TO JEDEC STANDARDS MS-026-BCD
051706-A
1.45
1.40
1.35
Figure 35. 64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2
AD1937WBSTZ
AD1937WBSTZ-RL
EVAL-AD1937AZ
1
2
Temperature Range
–40°C to +125°C
–40°C to +125°C
Package Description
64-Lead LQFP
64-Lead LQFP, 13” Tape and Reel
Evaluation Board
Package Option
ST-64-2
ST-64-2
Z = RoHS Compliant Part.
W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The AD1937WBSTZ models are available with controlled manufacturing to support the quality and reliability requirements of
automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore,
designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for
use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and
to obtain the specific Automotive Reliability reports for these models.
Rev. B | Page 33 of 36
AD1937
NOTES
Rev. B | Page 34 of 36
AD1937
NOTES
Rev. B | Page 35 of 36
AD1937
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2008-2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07414-0-6/10(B)
Rev. B | Page 36 of 36
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