4 ADC/8 DAC with PLL,
192 kHz, 24-Bit Codec
AD1939
Data Sheet
FEATURES
GENERAL DESCRIPTION
PLL generated or direct master clock
Low EMI design
112 dB DAC/107 dB ADC dynamic range and SNR
−94 dB THD + N
Single 3.3 V supply
Tolerance for 5 V logic inputs
Supports 24-bits and 8 kHz to 192 kHz sample rates
Differential ADC input
Differential DAC output
Log volume control with autoramp function
SPI controllable for flexibility
Software-controllable clickless mute
Software power-down
Right-justified, left-justified, I2S, and TDM modes
Master and slave modes up to 16-channel input/output
64-lead LQFP package
Qualified for automotive applications
The AD1939 is a high performance, single-chip codec that
provides four analog-to-digital converters (ADCs) with
differential input, and eight digital-to-analog converters (DACs)
with differential output using the Analog Devices, Inc. patented
multibit sigma-delta (Σ-Δ) architecture. An SPI port is included,
allowing a microcontroller to adjust volume and many other
parameters. The AD1939 operates from 3.3 V digital and analog
supplies. The AD1939 is available in a 64-lead (differential
output) LQFP package.
The AD1939 is designed for low EMI. This consideration is
apparent in both the system and circuit design architectures.
By using the on-board PLL to derive the master clock from the
LR clock or from an external crystal, the AD1939 eliminates
the need for a separate high frequency master clock and can
also be used with a suppressed bit clock. The DACs and ADCs
are designed using the latest Analog Devices continuous time
architectures to further minimize EMI. By using 3.3 V supplies,
power consumption is minimized, further reducing emissions.
APPLICATIONS
Automotive audio systems
Home Theater Systems
Set-top boxes
Digital audio effects processors
FUNCTIONAL BLOCK DIAGRAM
DIGITAL AUDIO
INPUT/OUTPUT
AD1939
SERIAL DATA PORT
DAC
DAC
SDATA
OUT
ADC
ANALOG
AUDIO
INPUTS
ADC
CLOCKS
DIGITAL
FILTER
ADC
SDATA
IN
TIMING MANAGEMENT
AND CONTROL
(CLOCK AND PLL)
ADC
DAC
DIGITAL
FILTER
AND
VOLUME
CONTROL
DAC
DAC
ANALOG
AUDIO
OUTPUTS
DAC
DAC
DAC
CONTROL DATA
INPUT/OUTPUT
06071-001
PRECISION
VOLTAGE
REFERENCE
SPI
CONTROL PORT
Figure 1.
Rev. E
Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2006–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD1939
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Analog-to-Digital Converters (ADCs) .................................... 13
Applications ....................................................................................... 1
Digital-to-Analog Converters (DACs) .................................... 13
General Description ......................................................................... 1
Clock Signals ............................................................................... 13
Functional Block Diagram .............................................................. 1
Reset and Power-Down ............................................................. 14
Revision History ............................................................................... 2
Serial Control Port ..................................................................... 14
Specifications..................................................................................... 3
Power Supply and Voltage Reference....................................... 15
Test Conditions ............................................................................. 3
Serial Data Ports—Data Format ............................................... 15
Analog Performance Specifications ........................................... 3
Time-Division Multiplexed (TDM) Modes ............................ 15
Crystal Oscillator Specifications................................................. 4
Daisy-Chain Mode ..................................................................... 19
Digital Input/Output Specifications........................................... 5
Control Registers ............................................................................ 24
Power Supply Specifications........................................................ 5
Definitions ................................................................................... 24
Digital Filters ................................................................................. 6
PLL and Clock Control Registers ............................................. 24
Timing Specifications .................................................................. 6
DAC Control Registers .............................................................. 25
Absolute Maximum Ratings............................................................ 8
ADC Control Registers .............................................................. 27
Thermal Resistance ...................................................................... 8
Additional Modes ....................................................................... 29
ESD Caution .................................................................................. 8
Application Circuits ....................................................................... 30
Pin Configuration and Function Descriptions ............................. 9
Outline Dimensions ....................................................................... 31
Typical Performance Characteristics ........................................... 11
Ordering Guide .......................................................................... 31
Theory of Operation ...................................................................... 13
Automotive Products ................................................................. 31
REVISION HISTORY
2/13—Rev. D to Rev. E
Change to tCLH Parameter, Table 7 ................................................... 7
Changes to Serial Control Port Section ........................................14
7/11—Rev. C to Rev. D
Changes to Pin 15, Pin 18, Pin 19, and Pin 20 Descriptions ...... 9
Changes to Pin 26 and Pin 27 Descriptions ................................ 10
9/10—Rev. B to Rev. C
Added Qualified for Automotive Applications to the Features
Section ................................................................................................ 1
Changed Case Temperature from 130°C to 125°C ...................... 4
Changed TA from −40°C to +130°C to −40°C to +105°C ........... 5
Changed TA from −40°C to +130°C to −40°C to +105°C ........... 7
Changes to Ordering Guide .......................................................... 31
Added Automotive Products Section .......................................... 31
Changes to Ordering Guide .......................................................... 31
6/07—Rev. 0 to Rev. A
Deleted I2C References....................................................... Universal
Change to Figure 1 ............................................................................1
Changes to Figure 2 ...........................................................................9
Changes to Table 10 ..........................................................................9
Changes to Table 11 ....................................................................... 14
Changes to Table 12 ....................................................................... 16
Changes to Figure 24 and Figure 25............................................. 22
Changes to Table 13 ....................................................................... 23
Change to Figure 26 ....................................................................... 23
Changes to Table 15 and Table 16 ................................................ 24
Changes to Figure 27 and Figure 28............................................. 29
Change to Figure 30 ....................................................................... 30
Updated Outline Dimensions ....................................................... 31
Changes to Ordering Guide .......................................................... 31
7/06—Revision 0: Initial Version
3/10—Rev. A to Rev. B
Rev. E | Page 2 of 32
Data Sheet
AD1939
SPECIFICATIONS
TEST CONDITIONS
Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications.
Supply voltages (AVDD, DVDD)
Temperature range1
Master clock
Input sample rate
Measurement bandwidth
Word width
Load capacitance (digital output)
Load current (digital output)
Input voltage high
Input voltage low
1
3.3 V
As specified in Table 1 and Table 2
12.288 MHz (48 kHz fS, 256 × fS mode)
48 kHz
20 Hz to 20 kHz
24 bits
20 pF
±1 mA or 1.5 kΩ to ½ DVDD supply
2.0 V
0.8 V
Functionally guaranteed at −40°C to +125°C case temperature.
ANALOG PERFORMANCE SPECIFICATIONS
Specifications guaranteed at an ambient temperature of 25°C.
Table 1.
Parameter
ANALOG-TO-DIGITAL CONVERTERS
ADC Resolution
Dynamic Range
No Filter (RMS)
With A-Weighted Filter (RMS)
Total Harmonic Distortion + Noise
Full-Scale Input Voltage (Differential)
Gain Error
Interchannel Gain Mismatch
Offset Error
Gain Drift
Interchannel Isolation
CMRR
Input Resistance
Input Capacitance
Input Common-Mode Bias Voltage
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range
No Filter (RMS)
With A-Weighted Filter (RMS)
With A-Weighted Filter (Average)
Total Harmonic Distortion + Noise
Conditions/Comments
Min
All ADCs
20 Hz to 20 kHz, −60 dB input
96
98
−1 dBFS
−10
−0.25
−10
100 mV rms, 1 kHz
100 mV rms, 20 kHz
Typ
Max
Unit
24
Bits
102
105
−96
1.9
dB
dB
dB
V rms
%
dB
mV
ppm/°C
dB
dB
dB
kΩ
pF
V
0
100
−110
55
55
14
10
1.5
−87
+10
+0.25
+10
20 Hz to 20 kHz, −60 dB input
102
105
0 dBFS
Two channels running
Eight channels running
Full-Scale Output Voltage
Gain Error
Interchannel Gain Mismatch
Offset Error
Gain Drift
Interchannel Isolation
107
110
112
−94
−86
1.76 (4.96)
−10
−0.2
−25
−30
−6
100
Rev. E | Page 3 of 32
dB
dB
dB
−76
+10
+0.2
+25
+30
dB
dB
V rms (V p-p)
%
dB
mV
ppm/°C
dB
AD1939
Parameter
Interchannel Phase Deviation
Volume Control Step
Volume Control Range
De-emphasis Gain Error
Output Resistance at Each Pin
REFERENCE
Internal Reference Voltage
External Reference Voltage
Common-Mode Reference Output
REGULATOR
Input Supply Voltage
Regulated Output Voltage
Data Sheet
Conditions/Comments
Min
Typ
0
0.375
95
Max
±0.6
100
Unit
Degrees
dB
dB
dB
Ω
FILTR pin
FILTR pin
CM pin
1.32
1.50
1.50
1.50
1.68
V
V
V
VSUPPLY pin
VSENSE pin
4.5
3.19
5
3.37
5.5
3.55
V
V
Min
Typ
Specifications measured at a case temperature of 125°C.
Table 2.
Parameter
ANALOG-TO-DIGITAL CONVERTERS
ADC Resolution
Dynamic Range
No Filter (RMS)
With A-Weighted Filter (RMS)
Total Harmonic Distortion + Noise
Full-Scale Input Voltage (Differential)
Gain Error
Interchannel Gain Mismatch
Offset Error
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range
No Filter (RMS)
With A-Weighted Filter (RMS)
With A-Weighted Filter (Average)
Total Harmonic Distortion + Noise
Full-Scale Output Voltage
Gain Error
Interchannel Gain Mismatch
Offset Error
Gain Drift
REFERENCE
Internal Reference Voltage
External Reference Voltage
Common-Mode Reference Output
REGULATOR
Input Supply Voltage
Regulated Output Voltage
Conditions/Comments
All ADCs
20 Hz to 20 kHz, −60 dB input
93
96
−1 dBFS
−10
−0.25
−10
Max
24
Bits
102
104
−96
1.9
dB
dB
dB
V rms
%
dB
mV
0
−87
+10
+0.25
+10
20 Hz to 20 kHz, −60 dB input
101
104
0 dBFS
Two channels running
Eight channels running
107
110
112
−94
−86
1.76 (4.96)
−10
−0.2
−25
−30
−6
dB
dB
dB
−70
+10
+0.2
+25
+30
dB
dB
V rms (V p-p)
%
dB
mV
ppm/°C
FILTR pin
FILTR pin
CM pin
1.32
1.50
1.50
1.50
1.68
V
V
V
VSUPPLY pin
VSENSE pin
4.5
3.2
5
3.43
5.5
3.65
V
V
CRYSTAL OSCILLATOR SPECIFICATIONS
Table 3.
Parameter
Transconductance
Unit
Min
Typ
3.5
Rev. E | Page 4 of 32
Max
Unit
mmhos
Data Sheet
AD1939
DIGITAL INPUT/OUTPUT SPECIFICATIONS
−40°C < TA < +105°C, DVDD = 3.3 V ± 10%.
Table 4.
Parameter
High Level Input Voltage (VIH)
Conditions/Comments
MCLKI/XI pin
Low Level Input Voltage (VIL)
Input Leakage
High Level Output Voltage (VOH)
Low Level Output Voltage (VOL)
Input Capacitance
IIH @ VIH = 2.4 V
IIL @ VIL = 0.8 V
IOH = 1 mA
IOL = 1 mA
Min
2.0
2.2
Typ
Max
0.4
5
Unit
V
V
V
µA
µA
V
V
pF
0.8
10
10
DVDD − 0.60
POWER SUPPLY SPECIFICATIONS
Table 5.
Parameter
SUPPLIES
Voltage
Digital Current
Normal Operation
Power-Down
Analog Current
Normal Operation
Power-Down
DISSIPATION
Operation
All Supplies
Digital Supply
Analog Supply
Power-Down, All Supplies
POWER SUPPLY REJECTION RATIO
Signal at Analog Supply Pins
Conditions/Comments
Min
Typ
Max
Unit
DVDD
AVDD
VSUPPLY
Master clock = 256 fS
fS = 48 kHz
fS = 96 kHz
fS = 192 kHz
fS = 48 kHz to 192 kHz
3.0
3.0
4.5
3.3
3.3
5.0
3.6
3.6
5.5
V
V
V
56
65
95
2.0
mA
mA
mA
mA
74
23
mA
mA
429
185
244
83
mW
mW
mW
mW
50
50
dB
dB
Master clock = 256 fS, 48 kHz
1 kHz, 200 mV p-p
20 kHz, 200 mV p-p
Rev. E | Page 5 of 32
AD1939
Data Sheet
DIGITAL FILTERS
Table 6.
Parameter
ADC DECIMATION FILTER
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Group Delay
DAC INTERPOLATION FILTER
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Group Delay
Mode
All modes, typical @ 48 kHz
Factor
Min
0.4375 fS
Typ
Max
Unit
21
±0.015
24
27
0.5 fS
0.5625 fS
kHz
dB
kHz
kHz
dB
µs
79
22.9844/fS
48 kHz mode, typical @ 48 kHz
96 kHz mode, typical @ 96 kHz
192 kHz mode, typical @ 192 kHz
48 kHz mode, typical @ 48 kHz
96 kHz mode, typical @ 96 kHz
192 kHz mode, typical @ 192 kHz
48 kHz mode, typical @ 48 kHz
96 kHz mode, typical @ 96 kHz
192 kHz mode, typical @ 192 kHz
48 kHz mode, typical @ 48 kHz
96 kHz mode, typical @ 96 kHz
192 kHz mode, typical @ 192 kHz
48 kHz mode, typical @ 48 kHz
96 kHz mode, typical @ 96 kHz
192 kHz mode, typical @ 192 kHz
48 kHz mode, typical @ 48 kHz
96 kHz mode, typical @ 96 kHz
192 kHz mode, typical @ 192 kHz
0.4535 fS
0.3646 fS
0.3646 fS
479
22
kHz
kHz
kHz
dB
dB
dB
kHz
kHz
kHz
kHz
kHz
kHz
dB
dB
dB
µs
µs
µs
35
70
±0.01
±0.05
±0.1
0.5 fS
0.5 fS
0.5 fS
0.5465 fS
0.6354 fS
0.6354 fS
24
48
96
26
61
122
70
70
70
25/fS
11/fS
8/fS
521
115
42
TIMING SPECIFICATIONS
−40°C < TA < +105°C, DVDD = 3.3 V ± 10%.
Table 7.
Parameter
INPUT MASTER CLOCK (MCLK) AND
RESET
tMH
Condition
Comments
Min
Max
Unit
MCLK duty cycle
DAC/ADC clock source = PLL clock @ 256 fS, 384
fS, 512 fS, and 768 fS
DAC/ADC clock source = direct MCLK @ 512 fS
(bypass on-chip PLL)
PLL mode, 256 fS reference
Direct 512 fS mode
40
60
%
40
60
%
6.9
13.8
27.6
MHz
MHz
ns
tMCLK
10
60
ms
%
tMH
fMCLK
fMCLK
tPDR
tPDRR
PLL
Lock Time
256 fS VCO Clock, Output Duty Cycle,
MCLKO/XO Pin
MCLK frequency
Low
Recovery
Reset to active output
15
4096
MCLK and LRCLK input
40
Rev. E | Page 6 of 32
Data Sheet
Parameter
SPI PORT
tCCH
tCCL
fCCLK
tCDS
tCDH
tCLS
tCLH
tCLHIGH
tCOE
tCOD
tCOH
tCOTS
DAC SERIAL PORT
tDBH
tDBL
tDLS
tDLH
tDLS
tDDS
tDDH
ADC SERIAL PORT
tABH
tABL
tALS
tALH
tALS
tABDD
AUXILIARY INTERFACE
tAXDS
tAXDH
tDXDD
tXBH
tXBL
tDLS
tDLH
AD1939
Condition
CCLK high
CCLK low
CCLK frequency
CIN setup
CIN hold
CLATCH setup
CLATCH hold
CLATCH high
COUT enable
COUT delay
COUT hold
COUT tristate
DBCLK high
DBCLK low
DLRCLK setup
DLRCLK hold
DLRCLK skew
DSDATA setup
DSDATA hold
ABCLK high
ABCLK low
ALRCLK setup
ALRCLK hold
ALRCLK skew
ASDATA delay
AAUXDATA setup
AAUXDATA hold
DAUXDATA delay
AUXBCLK high
AUXBCLK low
AUXLRCLK setup
AUXLRCLK hold
Comments
See Figure 11
Min
Max
35
35
fCCLK = 1/tCCP; only tCCP shown in Figure 11
To CCLK rising
From CCLK rising
To CCLK rising
From CCLK falling
Not shown in Figure 11
From CCLK falling
From CCLK falling
From CCLK falling, not shown in Figure 11
From CCLK falling
See Figure 24
Slave mode
Slave mode
To DBCLK rising, slave mode
From DBCLK rising, slave mode
From DBCLK falling, master mode
To DBCLK rising
From DBCLK rising
See Figure 25
Slave mode
Slave mode
To ABCLK rising, slave mode
From ABCLK rising, slave mode
From ABCLK falling, master mode
From ABCLK falling
To AUXBCLK rising
From AUXBCLK rising
From AUXBCLK falling
To AUXBCLK rising
From AUXBCLK rising
Rev. E | Page 7 of 32
10
10
10
10
10
10
30
30
30
30
10
10
10
5
−8
10
5
10
10
10
5
−8
+8
+8
18
10
5
18
10
10
10
5
Unit
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AD1939
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 8.
Parameter
Analog (AVDD)
Digital (DVDD)
VSUPPLY
Input Current (Except Supply Pins)
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
Operating Temperature Range (Case)
Storage Temperature Range
Rating
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +6.0 V
±20 mA
–0.3 V to AVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−40°C to +125°C
−65°C to +150°C
θJA represents thermal resistance, junction-to-ambient;
θJC represents the thermal resistance, junction-to-case.
All characteristics are for a 4-layer board.
Table 9. Thermal Resistance
Package Type
64-Lead LQFP
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. E | Page 8 of 32
θJA
47
θJC
11.1
Unit
°C/W
Data Sheet
AD1939
51
50
49
AGND
1
48
AGND
MCLKI/XI
2
47
FILTR
MCLKO/XO
3
46
AGND
AGND
4
45
AVDD
AVDD
5
44
AGND
OL3P
6
43
OR2N
OL3N
7
AD1939
42
OR2P
OR3P
8
OL2N
OR3N
TOP VIEW
(Not to Scale)
41
9
40
OL2P
DIFFERENTIAL
OUTPUT
OL4P 10
39
OR1N
OL4N 11
38
OR1P
NC = NO CONNECT
22
23
24
25
26
27
28
29
30
31
32
DVDD
21
CIN
20
COUT
19
ABCLK
18
ALRCLK
DVDD
17
ASDATA1
DGND
VDRIVE
33
ASDATA2
CCLK
DGND 16
VSENSE
34
VSUPPLY
CLATCH
DSDATA4 15
DLRCLK
35
DBCLK
OL1P
PD/RST 14
DSDATA1
OL1N
36
DSDATA2
37
DSDATA3
OR4P 12
OR4N 13
06071-021
52
NC
53
AVDD
54
NC
55
ADC1LP
56
CM
57
ADC1RP
58
ADC1LN
59
ADC1RN
60
ADC2LN
61
ADC2LP
62
ADC2RN
LF
63
ADC2RP
NC
64
AVDD
NC
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. 64-Lead LQFP, Differential Output, Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
In/Out
I
I
O
I
I
O
O
O
O
O
O
O
O
I
I/O
Mnemonic
AGND
MCLKI/XI
MCLKO/XO
AGND
AVDD
OL3P
OL3N
OR3P
OR3N
OL4P
OL4N
OR4P
OR4N
PD/RST
DSDATA4
16
17
18
I
I
I/O
DGND
DVDD
DSDATA3
19
I/O
DSDATA2
20
21
22
I
I/O
I/O
DSDATA1
DBCLK
DLRCLK
Description
Analog Ground.
Master Clock Input/Crystal Oscillator Input.
Master Clock Output/Crystal Oscillator Output.
Analog Ground.
Analog Power Supply. Connect to analog 3.3 V supply.
DAC 3 Left Positive Output.
DAC 3 Left Negative Output.
DAC 3 Right Positive Output.
DAC 3 Right Negative Output.
DAC 4 Left Positive Output.
DAC 4 Left Negative Output.
DAC 4 Right Positive Output.
DAC 4 Right Negative Output
Power-Down Reset (Active Low).
DAC Serial Data Input 4. Data input to DAC4 data in/TDM DAC2 data out (dual-line
mode)/AUX DAC2 data out (to external DAC2).
Digital Ground.
Digital Power Supply. Connect to digital 3.3 V supply.
DAC Serial Data Input 3. Data input to DAC3 data in/TDM DAC2 data in (dual-line
mode)/AUX ADC2 data in (from external ADC2).
DAC Serial Data Input 2. Data input to DAC2 data in/TDM DAC data out/AUX ADC1
data in (from external ADC1).
DAC Serial Data Input 1. Data input to DAC1 data in/TDM DAC data in/TDM data in.
Bit Clock for DACs.
LR Clock for DACs.
Rev. E | Page 9 of 32
AD1939
Data Sheet
Pin No.
23
24
25
26
In/Out
I
I
O
I/O
Mnemonic
VSUPPLY
VSENSE
VDRIVE
ASDATA2
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
O
I/O
I/O
I
I/O
I
I
I
I
O
O
O
O
O
O
O
O
I
I
I
O
I
ASDATA1
ABCLK
ALRCLK
CIN
COUT
DVDD
DGND
CCLK
CLATCH
OL1P
OL1N
OR1P
OR1N
OL2P
OL2N
OR2P
OR2N
AGND
AVDD
AGND
FILTR
AGND
NC
NC
AVDD
CM
53
54
55
56
57
58
59
60
61
62
63
64
I
I
I
I
I
I
I
I
O
I
I
O
ADC1LP
ADC1LN
ADC1RP
ADC1RN
ADC2LP
ADC2LN
ADC2RP
ADC2RN
LF
AVDD
NC
NC
Description
5 V Input to Regulator, Emitter of Pass Transistor.
3.3 V Output of Regulator, Collector of Pass Transistor.
Drive for Base of Pass Transistor.
ADC Serial Data Output 2. Data Output from ADC2/TDM ADC data in/AUX DAC1 data
out (to external DAC1).
ADC Serial Data Output 1. Data Output from ADC1/TDM ADC data out/TDM data out.
Bit Clock for ADCs.
LR Clock for ADCs.
Control Data Input (SPI).
Control Data Output (SPI).
Digital Power Supply. Connect to digital 3.3 V supply.
Digital Ground.
Control Clock Input (SPI).
Latch Input for Control Data (SPI).
DAC 1 Left Positive Output.
DAC 1 Left Negative Output.
DAC 1 Right Positive Output.
DAC 1 Right Negative Output.
DAC 2 Left Positive Output.
DAC 2 Left Negative Output.
DAC 2 Right Positive Output.
DAC 2 Right Negative Output.
Analog Ground.
Analog Power Supply. Connect to analog 3.3 V supply.
Analog Ground.
Voltage Reference Filter Capacitor Connection. Bypass with 10 µF||100 nF to AGND.
Analog Ground.
No Connect.
No Connect.
Analog Power Supply. Connect to analog 3.3 V supply.
Common-Mode Reference Filter Capacitor Connection. Bypass with
47 µF||100 nF to AGND.
ADC1 Left Positive Input.
ADC1 Left Negative Input.
ADC1 Right Positive Input.
ADC1 Right Negative Input.
ADC2 Left Positive Input.
ADC2 Left Negative Input.
ADC2 Right Positive Input.
ADC2 Right Negative Input.
PLL Loop Filter, Return to AVDD.
Analog Power Supply. Connect to analog 3.3 V supply.
No Connect.
No Connect.
Rev. E | Page 10 of 32
Data Sheet
AD1939
TYPICAL PERFORMANCE CHARACTERISTICS
0.10
0
0.08
0.06
MAGNITUDE (dB)
MAGNITUDE (dB)
0.04
0.02
0
–0.02
–0.04
–50
–100
–0.06
–150
0
2
4
6
8
10
12
14
16
06071-002
–0.10
18
FREQUENCY (kHz)
0
12
24
36
48
FREQUENCY (kHz)
Figure 3. ADC Pass-Band Filter Response, 48 kHz
06071-005
–0.08
Figure 6. DAC Stop-Band Filter Response, 48 kHz
0
0.10
–10
–20
0.05
MAGNITUDE (dB)
MAGNITUDE (dB)
–30
–40
–50
–60
–70
0
–0.05
–80
5
10
15
20
25
30
35
–0.10
06071-003
0
40
FREQUENCY (kHz)
0
24
48
72
96
FREQUENCY (kHz)
Figure 4. ADC Stop-Band Filter Response, 48 kHz
06071-006
–90
–100
Figure 7. DAC Pass-Band Filter Response, 96 kHz
0.06
0
MAGNITUDE (dB)
0.02
0
–0.02
–50
–100
–150
–0.06
0
8
16
FREQUENCY (kHz)
24
Figure 5. DAC Pass-Band Filter Response, 48 kHz
0
24
48
72
FREQUENCY (kHz)
Figure 8. DAC Stop-Band Filter Response, 96 kHz
Rev. E | Page 11 of 32
96
06071-007
–0.04
06071-004
MAGNITUDE (dB)
0.04
AD1939
Data Sheet
0.5
0
0.4
0.3
–2
MAGNITUDE (dB)
0.1
0
–0.1
–4
–6
–0.2
–8
–0.3
–0.5
0
8
16
32
64
FREQUENCY (kHz)
–10
48
64
80
FREQUENCY (kHz)
Figure 10. DAC Stop-Band Filter Response, 192 kHz
Figure 9. DAC Pass-Band Filter Response, 192 kHz
Rev. E | Page 12 of 32
96
06071-009
–0.4
06071-008
MAGNITUDE (dB)
0.2
Data Sheet
AD1939
THEORY OF OPERATION
ANALOG-TO-DIGITAL CONVERTERS (ADCS)
There are four analog-to-digital converter (ADC) channels in
the AD1939 configured as two stereo pairs with differential
inputs. The ADCs can operate at a nominal sample rate of 48 kHz,
96 kHz, or 192 kHz. The ADCs include on-board digital antialiasing filters with 79 dB stop-band attenuation and linear
phase response, operating at an oversampling ratio of 128
(48 kHz, 96 kHz, and 192 kHz modes). Digital outputs are
supplied through two serial data output pins (one for each
stereo pair) and a common frame clock (ALRCLK) and bit
clock (ABCLK). Alternatively, one of the TDM modes can be
used to access up to 16 channels on a single TDM data line.
The ADCs must be driven from a differential signal source for
best performance. The input pins of the ADCs connect to internal
switched capacitors. To isolate the external driving op amp from
the glitches caused by the internal switched capacitors, each input pin should be isolated by using a series-connected external
100 Ω resistor together with a 1 nF capacitor connected from
each input to ground. This capacitor must be of high quality, for
example, ceramic NP0 or polypropylene film.
The differential inputs have a nominal common-mode voltage
of 1.5 V. The voltage at the common-mode reference pin (CM)
can be used to bias external op amps to buffer the input signals
(see the Power Supply and Voltage Reference section). The
inputs can also be ac-coupled and do not need an external dc
bias to CM.
A digital high-pass filter can be switched in line with the ADCs
under serial control to remove residual dc offsets. It has a 1.4 Hz,
6 dB per octave cutoff at a 48 kHz sample rate. The cutoff frequency scales directly with sample frequency.
DIGITAL-TO-ANALOG CONVERTERS (DACS)
slew rate or low bandwidth can cause high frequency noise and
tones to fold down into the audio band; exercise care in
selecting these components.
The voltage at CM, the common-mode reference pin, can be
used to bias the external op amps that buffer the output signals
(see the Power Supply and Voltage Reference section).
CLOCK SIGNALS
The on-chip phase-locked loop (PLL) can be selected to
reference the input sample rate from either of the LRCLK pins
or 256, 384, 512, or 768 times the sample rate, referenced to the
48 kHz mode from the MCLKI/XI pin. The default at power-up
is 256 × fS from the MCLKI/XI pin. In 96 kHz mode, the master
clock frequency stays at the same absolute frequency; therefore,
the actual multiplication rate is divided by 2. In 192 kHz mode,
the actual multiplication rate is divided by 4. For example, if a
device in the AD1939 family is programmed in 256 × fS mode, the
frequency of the master clock input is 256 × 48 kHz = 12.288 MHz.
If the AD1939 is then switched to 96 kHz operation (by writing
to the SPI port), the frequency of the master clock should
remain at 12.288 MHz, which is 128 × fS in this example. In
192 kHz mode, this becomes 64 × fS.
The internal clock for the ADCs is 256 × fS for all clock modes.
The internal clock for the DACs varies by mode: 512 × fS (48 kHz
mode), 256 × fS (96 kHz mode), or 128 × fS (192 kHz mode). By
default, the on-board PLL generates this internal master clock
from an external clock. A direct 512 × fS (referenced to 48 kHz
mode) master clock can be used for either the ADCs or DACs if
selected in the PLL and Clock Control 1 register.
Note that it is not possible to use a direct clock for the ADCs set
to the 192 kHz mode. It is required that the on-chip PLL be
used in this mode.
The AD1939 digital-to-analog converter (DAC) channels are
arranged as differential, four stereo pairs giving eight analog
outputs for improved noise and distortion performance. The
DACs include on-board digital reconstruction filters with 70 dB
stop-band attenuation and linear phase response, operating at an
oversampling ratio of 4 (48 kHz or 96 kHz modes) or 2 (192 kHz
mode). Each channel has its own independently programmable
attenuator, adjustable in 255 steps in increments of 0.375 dB.
Digital inputs are supplied through four serial data input pins
(one for each stereo pair) and a common frame clock (DLRCLK)
and bit clock (DBCLK). Alternatively, one of the TDM modes can
be used to access up to 16 channels on a single TDM data line.
The PLL can be powered down in the PLL and Clock Control 0
register. To ensure reliable locking when changing PLL modes,
or if the reference clock is unstable at power-on, power down
the PLL and then power it back up when the reference clock
stabilizes.
Each output pin has a nominal common-mode dc level of 1.5 V
and swings ±1.27 V for a 0 dBFS digital input signal. A single op
amp, third-order, external, low-pass filter is recommended to
remove high frequency noise present on the output pins, as well
as to provide differential-to-single-ended conversion in the case
of the differential output. Note that the use of op amps with low
To maintain the highest performance possible, limit the clock
jitter of the internal master clock signal to less than a 300 ps rms
time interval error (TIE). Even at these levels, extra noise or
tones can appear in the DAC outputs if the jitter spectrum
contains large spectral peaks. If the internal PLL is not used, it is
best to use an independent crystal oscillator to generate the
The internal master clock (MCLK) can be disabled in the PLL
and Clock Control 0 register to reduce power dissipation when
the AD1939 is idle. The clock should be stable before it is
enabled. Unless a standalone mode is selected (see the Serial
Control Port section), the clock is disabled by reset and must be
enabled by writing to the SPI port for normal operation.
Rev. E | Page 13 of 32
AD1939
Data Sheet
master clock. In addition, it is especially important that the
clock signal not pass through an FPGA, CPLD, or other large
digital chip (such as a DSP) before being applied to the
AD1939. In most cases, this induces clock jitter due to the
sharing of common power and ground connections with other
unrelated digital output signals. When the PLL is used, jitter in
the reference clock is attenuated above a certain frequency
depending on the loop filter.
RESET AND POWER-DOWN
The function of the RST pin sets all the control registers to their
default settings. To avoid pops, reset does not power down the
analog outputs. After RST is deasserted and the PLL acquires
lock condition, an initialization routine runs inside the
AD1939. This initialization lasts for approximately 256 master
clock cycles.
The power-down bits in the PLL and Clock Control 0, DAC
Control 1, and ADC Control 1 registers power down the
respective sections. All other register settings are retained. To
guarantee proper startup, the RST pin should be pulled low by
an external resistor.
SERIAL CONTROL PORT
for operation without serial control; standalone is configured at
reset by connecting CIN, CCLK, and CLATCH to ground. In
standalone mode, all registers are set to default, except the
internal MCLK enable, which is set to 1. The ADC, ABCLK, and
ALRCLK clock ports are set to master/slave by the connecting
the COUT pin to either DVDD or ground. Standalone mode
only supports stereo mode with an I2S data format and 256 fS
MCLK rate. Refer to Table 11 for details. If CIN, CCLK, and
CLATCH are not grounded, the AD1939 SPI port is active. It is
recommended to use a weak pull-up resistor on CLATCHin
applications that have a microcontroller. This pull-up resistor
ensures that the AD1939 recognizes the presence of a
microcontroller.
The SPI control port of the AD1939 is a 4-wire serial control
port. The format is similar to the Motorola SPI format except
the input data-word is 24 bits wide. The serial bit clock and
latch can be completely asynchronous to the sample rate of the
ADCs and DACs. Figure 11 shows the format of the SPI signal.
The first byte is a global address with a read/write bit. For the
AD1939, the address is 0x04, shifted left one bit due to the R/W
bit. The second byte is the AD1939 register address and the
third byte is the data.
The AD1939 has an SPI control port that permits programming
and reading back of the internal control registers for the ADCs,
DACs, and clock system. A standalone mode is also available
Table 11. Standalone Mode Selection
ADC Clocks
Slave
Master
CIN
0
0
COUT
0
1
tCLS
CLATCH
0
0
tCLH
tCCH tCCL
tCCP
CLATCH
CCLK
0
0
tCOTS
CCLK
tCDS tCDH
COUT
D23
D22
D9
tCOE
D9
D8
D0
D8
D0
06071-010
CIN
tCOD
Figure 11. Format of the SPI Signal
Rev. E | Page 14 of 32
Data Sheet
AD1939
POWER SUPPLY AND VOLTAGE REFERENCE
The AD1939 is designed for 3.3 V supplies. Separate power
supply pins are provided for the analog and digital sections.
To minimize noise pickup, these pins should be bypassed with
100 nF ceramic chip capacitors placed as close to the pins as
possible. A bulk aluminum electrolytic capacitor of at least
22 μF should also be provided on the same PC board as the
codec. For critical applications, improved performance is
obtained with separate supplies for the analog and digital sections.
If this is not possible, it is recommended that the analog and
digital supplies be isolated by means of a ferrite bead in series
with each supply. It is important that the analog supply be as
clean as possible.
The AD1939 includes a 3.3 V regulator driver that only requires
an external pass transistor and bypass capacitors to make a 5 V
to 3.3 V regulator. If the regulator driver is not used, connect
VSUPPLY, VDRIVE, and VSENSE to DGND.
polarity of DBCLK and DLRCLK is programmable according to
the DAC Control 1 register. The ADC serial formats and serial
clock polarity are programmable according to the ADC Control 1
register. Both DAC and ADC serial ports are programmable to
become the bus masters according to DAC Control 1 register
and ADC Control 2 register. By default, both ADC and DAC
serial ports are in the slave mode.
TIME-DIVISION MULTIPLEXED (TDM) MODES
The AD1939 serial ports also have several different TDM serial
data modes. The first and most commonly used configurations
are shown in Figure 12 and Figure 13. In Figure 12, the ADC
serial port outputs one data stream consisting of four on-chip
ADCs followed by four unused slots. In Figure 13, the eight onchip DAC data slots are packed into one TDM stream. In this
mode, both DBCLK and ABCLK are 256 fS.
LRCLK
256 BCLKs
BCLK
All digital inputs are compatible with TTL and CMOS levels.
All outputs are driven from the 3.3 V DVDD supply and are
compatible with TTL and 3.3 V CMOS levels.
DATA
32 BCLKs
SLOT 1
LEFT 1
SLOT 2
RIGHT 1
SLOT 3
LEFT 2
SLOT 4
RIGHT 2
SLOT 5
SLOT 6
SLOT 7
SLOT 8
LRCLK
The ADC and DAC internal voltage reference (VREF) is brought
out on FILTR and should be bypassed as close as possible to the
chip with a parallel combination of 10 μF and 100 nF. Any
external current drawn should be limited to less than 50 μA.
The internal reference can be disabled in the PLL and Clock
Control 1 register and FILTR can be driven from an external
source. This can be used to scale the DAC output to the clipping
level of a power amplifier based on its power supply voltage.
The ADC input gain varies by the inverse ratio. The total gain
from ADC input to DAC output remains constant.
MSB
MSB–1
MSB–2
06071-016
BCLK
DATA
Figure 12. ADC TDM (8-Channel I2S Mode)
LRCLK
256 BCLKs
BCLK
DATA
32 BCLKs
SLOT 1
LEFT 1
SLOT 2
RIGHT 1
SLOT 3
LEFT 2
SLOT 4
RIGHT 2
SLOT 5
LEFT 3
SLOT 6
RIGHT 3
SLOT 7
LEFT 4
SLOT 8
RIGHT 4
LRCLK
SERIAL DATA PORTS—DATA FORMAT
The eight DAC channels use a common serial bit clock (DBCLK)
and a common left-right framing clock (DLRCLK) in the serial
data port. The four ADC channels use a common serial bit
clock (ABCLK) and left-right framing clock (ALRCLK) in the
serial data port. The clock signals are all synchronous with the
sample rate. The normal stereo serial modes are shown in
Figure 23.
The ADC and DAC serial data modes default to I2S. The ports
can also be programmed for left-justified, right-justified, and
TDM modes. The word width is 24 bits by default and can be
programmed for 16 or 20 bits. The DAC serial formats are
programmable according to the DAC Control 0 register. The
BCLK
MSB
MSB–1
MSB–2
DATA
06071-017
The CM pin is the internal common-mode reference. It should
be bypassed as close as possible to the chip, with a parallel
combination of 47 μF and 100 nF. This voltage can be used to
bias external op amps to the common-mode voltage of the input
and output signal pins. The output current should be limited to
less than 0.5 mA source and 2 mA sink.
Figure 13. DAC TDM (8-Channel I2S Mode)
The I/O pins of the serial ports are defined according to the
serial mode that is selected. For a detailed description of the
function of each pin in TDM and AUX modes, see Table 12.
The AD1939 allows systems with more than eight DAC channels
to be easily configured by the use of an auxiliary serial data port.
The DAC TDM-AUX mode is shown in Figure 14. In this mode,
the AUX channels are the last four slots of the TDM data stream.
These slots are extracted and output to the AUX serial port. It
should be noted that due to the high DBCLK frequency, this mode
is available only in the 48 kHz/44.1 kHz/32 kHz sample rate.
The AD1939 also allows system configurations with more than
four ADC channels as shown in Figure 15 (using 8 ADCs) and
Figure 16 (using 16 ADCs). Again, due to the high ABCLK frequency, this mode is available only in the 48 kHz/44.1 kHz/32 kHz
sample rate.
Rev. E | Page 15 of 32
AD1939
Data Sheet
Combining the AUX ADC and DAC modes results in a system
configuration of 8 ADCs and 12 DACs. The system, then, consists of two external stereo ADCs, two external stereo DACs,
and one AD1939. This mode is shown in Figure 17 (combined
AUX DAC and ADC modes).
Table 12. Pin Function Changes in TDM and AUX Modes
Pin Mnemonic
ASDATA1
ASDATA2
DSDATA1
DSDATA2
DSDATA3
DSDATA4
ALRCLK
ABCLK
DLRCLK
DBCLK
Stereo Modes
ADC1 Data Out
ADC2 Data Out
DAC1 Data In
DAC2 Data In
DAC3 Data In
DAC4 Data In
ADC LRCLK In/ADC LRCLK Out
ADC BCLK In/ADC BCLK Out
DAC LRCLK In/DAC LRCLK Out
DAC BCLK In/DAC BCLK Out
TDM Modes
ADC TDM Data Out
ADC TDM Data In
DAC TDM Data In
DAC TDM Data Out
DAC TDM Data In 2 (Dual-Line Mode)
DAC TDM Data Out 2 (Dual-Line Mode)
ADC TDM Frame Sync In/ADC TDM Frame Sync Out
ADC TDM BCLK In/ADC TDM BCLK Out
DAC TDM Frame Sync In/DAC TDM Frame Sync Out
DAC TDM BCLK In/DAC TDM BCLK Out
AUX Modes
TDM Data Out
AUX Data Out 1 (to Ext. DAC 1)
TDM Data In
AUX Data In 1 (from Ext. ADC 1)
AUX Data In 2 (from Ext. ADC 2)
AUX Data Out 2 (to Ext. DAC 2)
TDM Frame Sync In/TDM Frame Sync Out
TDM BCLK In/TDM BCLK Out
AUX LRCLK In/AUX LRCLK Out
AUX BCLK In/AUX BCLK Out
ALRCLK
ABCLK
DSDATA1
(TDM_IN)
UNUSED SLOTS
EMPTY
EMPTY
EMPTY
AUXILIARY DAC CHANNELS
APPEAR AT
AUX DAC PORTS
8 ON-CHIP DAC CHANNELS
EMPTY
DAC L1
DAC R1
DAC L2
DAC R2
DAC L3
DAC R3
DAC L4
DAC R4
AUX L1
AUX R1
AUX L2
AUX R2
32 BITS
MSB
DLRCLK
(AUX PORT)
LEFT
RIGHT
ASDATA2
(AUX1_OUT)
MSB
MSB
DSDATA4
(AUX2_OUT)
MSB
MSB
Figure 14. 16-Channel DAC TDM-AUX Mode
Rev. E | Page 16 of 32
06071-051
DBCLK
(AUX PORT)
Data Sheet
AD1939
ALRCLK
ABCLK
8 ON-CHIP DAC CHANNELS
DSDATA1
(TDM_IN)
DAC L1
ASDATA1
(TDM_OUT)
ADC L1
DAC R1
DAC L2
DAC R2
DAC L3
DAC R3
ADC R2
AUX L1
AUX R1
4 ON-CHIP ADC CHANNELS
ADC R1
DAC L4
DAC R4
4 AUX ADC CHANNELS
ADC L2
AUX L2
AUX R2
32 BITS
MSB
DLRCLK
(AUX PORT)
LEFT
RIGHT
DSDATA2
(AUX1_IN)
MSB
MSB
DSDATA3
(AUX2_IN)
MSB
MSB
06071-050
DBCLK
(AUX PORT)
Figure 15. 8-Channel AUX ADC Mode
ALRCLK
ABCLK
ASDATA1
(TDM_OUT)
4 ON-CHIP ADC CHANNELS
ADC L1
ADC R1
ADC L2
AUXILIARY ADC CHANNELS
ADC R2 AUX L1
AUX R1
AUX L2
UNUSED SLOTS
AUX R2 UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED
32 BITS
MSB
DLRCLK
(AUX PORT)
LEFT
RIGHT
DBCLK
(AUX PORT)
MSB
DSDATA3
(AUX2_IN)
MSB
MSB
MSB
Figure 16. 16-Channel AUX ADC Mode
Rev. E | Page 17 of 32
06071-052
DSDATA2
(AUX1_IN)
AD1939
Data Sheet
ALRCLK
ABCLK
UNUSED SLOTS
DSDATA1
(TDM_IN)
EMPTY
ASDATA1
(TDM_OUT)
ADC L1
DLRCLK
(AUX PORT)
EMPTY
EMPTY
EMPTY
4 ON-CHIP ADC CHANNELS
ADC R1
ADC L2
AUXILIARY DAC CHANNELS
APPEAR AT
AUX DAC PORTS
8 ON-CHIP DAC CHANNELS
ADC R2
DAC L1
DAC R1
DAC L2
DAC R2
DAC L3
DAC R3
AUXILIARY ADC CHANNELS
AUX L1
AUX R1
AUX L2
DAC L4
DAC R4
AUX L1
AUX R1
AUX L2
AUX R2
UNUSED SLOTS
AUX R2 UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED
LEFT
RIGHT
DSDATA2
(AUX1_IN)
MSB
MSB
DSDATA3
(AUX2_IN)
MSB
MSB
ASDATA2
(AUX1_OUT)
MSB
MSB
DSDATA4
(AUX2_OUT)
MSB
MSB
Figure 17. Combined AUX DAC and ADC Mode
Rev. E | Page 18 of 32
06071-053
DBCLK
(AUX PORT)
Data Sheet
AD1939
There are two configurations for the ADC port to work in
daisy-chain mode. The first one is with an ABCLK at 256 fS
shown in Figure 21. The second configuration is shown in
Figure 22. Note that in the 512 fS ABCLK mode, the ADC
channels occupy the first eight slots; the second eight slots are
empty. The TDM_IN of the first AD1939 must be grounded in
all modes of operation.
DAISY-CHAIN MODE
The AD1939 also allows a daisy-chain configuration to expand
the system to 8 ADCs and 16 DACs (see Figure 18). In this
mode, the DBCLK frequency is 512 fS. The first eight slots of the
DAC TDM data stream belong to the first AD1939 in the chain
and the last eight slots belong to the second AD1939. The second
AD1939 is the device attached to the DSP TDM port.
The I/O pins of the serial ports are defined according to the
serial mode selected. See Table 13 for a detailed description of
the function of each pin. See Figure 26 for a typical AD1939
configuration with two external stereo DACs and two external
stereo ADCs.
To accommodate 16 channels at a 96 kHz sample rate, the
AD1939 can be configured into a dual-line, TDM mode as
shown in Figure 19. This mode allows a slower DBCLK than
normally required by the one-line TDM mode.
Again, the first four channels of each TDM input belong to the
first AD1939 in the chain and the last four channels belong to
the second AD1939.
Figure 23 through Figure 25 show the serial mode formats. For
maximum flexibility, the polarity of LRCLK and BCLK are
programmable. In these figures, all of the clocks are shown with
their normal polarity. The default mode is I2S.
The dual-line TDM mode can also be used to send data at a
192 kHz sample rate into the AD1939 as shown in Figure 20.
DLRCLK
DBCLK
8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN
DSDATA1 (TDM_IN)
OF THE SECOND AD1939
DAC L1
DAC R1
DAC L2
DSDATA2 (TDM_OUT)
OF THE SECOND AD1939
THIS IS THE TDM
TO THE FIRST AD1939
DAC R2
DAC L3
DAC R3
DAC L4
DAC R4
8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN
DAC L1
DAC R1
DAC L2
DAC R2
DAC L3
DAC R3
DAC L4
DAC R4
DAC L1
DAC R1
DAC L2
DAC R2
DAC L3
DAC R3
DAC L4
DAC R4
8 UNUSED SLOTS
FIRST
AD1939
SECOND
AD1939
DSP
MSB
Figure 18. Single-Line DAC TDM Daisy-Chain Mode (Applicable to 48 kHz Sample Rate, 16-Channel, Two-AD1939 Daisy Chain)
Rev. E | Page 19 of 32
06071-054
32 BITS
AD1939
Data Sheet
DLRCLK
DBCLK
8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN
DSDATA1
(IN)
DAC L1
DAC R1
DAC L2
8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN
DAC R2
DSDATA2
(OUT)
DSDATA3
(IN)
DAC L3
DAC R3
DAC L4
DAC R4
DSDATA4
(OUT)
DAC L1
DAC R1
DAC L2
DAC R2
DAC L1
DAC R1
DAC L2
DAC R2
DAC L3
DAC R3
DAC L4
DAC R4
DAC L3
DAC R3
DAC L4
DAC R4
32 BITS
FIRST
AD1939
SECOND
AD1939
06071-055
MSB
DSP
Figure 19. Dual-Line DAC TDM Mode (Applicable to 96 kHz Sample Rate, 16-Channel, Two-AD1939 Daisy Chain); DSDATA3 and DSDATA4 Are the Daisy Chain
DLRCLK
DBCLK
DSDATA1
DAC L1
DAC R1
DAC L2
DAC R2
DSDATA2
DAC L3
DAC R3
DAC L4
DAC R4
06071-058
32 BITS
MSB
Figure 20. Dual-Line DAC TDM Mode (Applicable to 192 kHz Sample Rate, 8-Channel Mode)
ALRCLK
ABCLK
4 ADC CHANNELS OF SECOND IC IN THE CHAIN
ASDATA1 (TDM_OUT
OF THE SECOND AD1939
IN THE CHAIN)
ADC L1
ADC R1
ADC L2
ADC R2
ASDATA2 (TDM_IN
OF THE SECOND AD1939
IN THE CHAIN)
ADC L1
ADC R1
ADC L2
ADC R2
4 ADC CHANNELS OF FIRST IC IN THE CHAIN
ADC L1
ADC R1
ADC L2
ADC R2
32 BITS
SECOND
AD1939
DSP
MSB
Figure 21. ADC TDM Daisy-Chain Mode (256 fS ABCLK, Two-AD1939 Daisy Chain)
Rev. E | Page 20 of 32
06071-056
FIRST
AD1939
Data Sheet
AD1939
ALRCLK
ABCLK
4 ADC CHANNELS OF
SECOND IC IN THE CHAIN
4 ADC CHANNELS OF
FIRST IC IN THE CHAIN
ASDATA1 (TDM_OUT
OF THE SECOND AD1939
IN THE CHAIN)
ADC L1
ADC R1
ADC L2
ADC R2
ASDATA2 (TDM_IN
OF THE SECOND AD1939
IN THE CHAIN)
ADC L1
ADC R1
ADC L2
ADC R2
ADC L1
ADC R1
ADC L2
ADC R2
32 BITS
SECOND
AD1939
DSP
06071-057
FIRST
AD1939
MSB
Figure 22. ADC TDM Daisy-Chain Mode (512 fS ABCLK, Two-AD1939 Daisy Chain)
LEFT CHANNEL
LRCLK
RIGHT CHANNEL
BCLK
SDATA
LSB
MSB
LSB
MSB
LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
LEFT CHANNEL
LRCLK
RIGHT CHANNEL
BCLK
SDATA
LSB
MSB
LSB
MSB
I2S-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
LEFT CHANNEL
LRCLK
RIGHT CHANNEL
BCLK
SDATA
MSB
LSB
MSB
LSB
RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL
LRCLK
BCLK
MSB
MSB
LSB
LSB
DSP MODE—16 BITS TO 24 BITS PER CHANNEL
1/fS
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT fS EXCEPT FOR DSP MODE, WHICH IS 2 × fS.
3. BCLK FREQUENCY IS NORMALLY 64 × LRCLK BUT MAY BE OPERATED IN BURST MODE.
Figure 23. Stereo Serial Modes
Rev. E | Page 21 of 32
06071-013
SDATA
AD1939
Data Sheet
tDBH
DBCLK
tDBL
tDLH
tDLS
DLRCLK
tDDS
DSDATAx
LEFT-JUSTIFIED
MODE
MSB
MSB–1
tDDH
tDDS
DSDATAx
I2S-JUSTIFIED
MODE
MSB
tDDH
tDDS
MSB
LSB
tDDH
tDDH
06071-014
tDDS
DSDATAx
RIGHT-JUSTIFIED
MODE
Figure 24. DAC Serial Timing
tABH
ABCLK
tABL
tALH
tALS
ALRCLK
tABDD
ASDATAx
LEFT-JUSTIFIED
MODE
MSB
MSB–1
tABDD
ASDATAx
I2S-JUSTIFIED
MODE
MSB
ASDATAx
RIGHT-JUSTIFIED
MODE
MSB
Figure 25. ADC Serial Timing
Rev. E | Page 22 of 32
LSB
06071-015
tABDD
Data Sheet
AD1939
Table 13. Pin Function Changes in TDM and AUX Modes (Replication of Table 12)
Stereo Modes
ADC1 Data Out
ADC2 Data Out
DAC1 Data In
DAC2 Data In
DAC3 Data In
DAC4 Data In
ADC LRCLK In/ADC LRCLK Out
ADC BCLK In/ADC BCLK Out
DAC LRCLK In/DAC LRCLK Out
DAC BCLK In/DAC BCLK Out
TDM Modes
ADC TDM Data Out
ADC TDM Data In
DAC TDM Data In
DAC TDM Data Out
DAC TDM Data In 2 (Dual-Line Mode)
DAC TDM Data Out 2 (Dual-Line Mode)
ADC TDM Frame Sync In/ADC TDM Frame Sync Out
ADC TDM BCLK In/ADC TDM BCLK Out
DAC TDM Frame Sync In/DAC TDM Frame Sync Out
DAC TDM BCLK In/DAC TDM BCLK Out
TxDATA
TxCLK
TFS (NC)
RxDATA
SHARC®
RxCLK
12.288MHz
LRCLK
AUX
ADC 1
LRCLK
BCLK
DATA
MCLK
AUX Modes
TDM Data Out
AUX Data Out 1 (to Ext. DAC 1)
TDM Data In
AUX Data In 1 (from Ext. ADC 1)
AUX Data In 2 (from Ext. ADC 2)
AUX Data Out 2 (to Ext. DAC 2)
TDM Frame Sync In/TDM Frame Sync Out
TDM BCLK In/TDM BCLK Out
AUX LRCLK In/AUX LRCLK Out
AUX BCLK In/AUX BCLK Out
SHARC IS RUNNING IN SLAVE MODE
(INTERRUPT-DRIVEN)
30MHz
FSYNC-TDM (RFS)
BCLK
ASDATA1 ALRCLK ABCLK DSDATA1
AUX
DATA DAC 1
MCLK
DBCLK
DLRCLK
LRCLK
AUX
ADC 2
BCLK
DSDATA2
DATA
DSDATA3
MCLK
MCLKI/XI
AD1939
TDM MASTER
AUX MASTER
LRCLK
ASDATA2
DSDATA4
BCLK
AUX
DATA DAC 2
MCLK
Figure 26. Example of AUX Mode Connection to SHARC (AD1939 as TDM Master/AUX Master Shown)
Rev. E | Page 23 of 32
06071-019
Pin Mnemonic
ASDATA1
ASDATA2
DSDATA1
DSDATA2
DSDATA3
DSDATA4
ALRCLK
ABCLK
DLRCLK
DBCLK
AD1939
Data Sheet
CONTROL REGISTERS
DEFINITIONS
The global address for the AD1939 is 0x04, shifted left one bit due to the R/W bit. All registers are reset to 0, except for the DAC volume
registers that are set to full volume.
Note that the first setting in each control register parameter is the default setting.
Table 14. Register Format
Bit
Global Address
R/W
Register Address
Data
23:17
16
15:8
7:0
Table 15. Register Addresses and Functions
Address
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Function
PLL and Clock Control 0
PLL and Clock Control 1
DAC Control 0
DAC Control 1
DAC Control 2
DAC individual channel mutes
DAC L1 volume control
DAC R1 volume control
DAC L2 volume control
DAC R2 volume control
DAC L3 volume control
DAC R3 volume control
DAC L4 volume control
DAC R4 volume control
ADC Control 0
ADC Control 1
ADC Control 2
PLL AND CLOCK CONTROL REGISTERS
Table 16. PLL and Clock Control 0 Register
Bit
0
2:1
4:3
6:5
7
Value
0
1
00
01
10
11
00
01
10
11
00
01
10
11
0
1
Function
Normal operation
Power-down
INPUT 256 (× 44.1 kHz or 48 kHz)
INPUT 384 (× 44.1 kHz or 48 kHz)
INPUT 512 (× 44.1 kHz or 48 kHz)
INPUT 768 (× 44.1 kHz or 48 kHz)
XTAL oscillator enabled
256 × fS VCO output
512 × fS VCO output
Off
MCLKI/XI
DLRCLK
ALRCLK
Reserved
Disable: ADC and DAC idle
Enable: ADC and DAC active
Description
PLL power-down
MCLKI/XI pin functionality (PLL active), master clock rate setting
MCLKO/XO pin, master clock rate setting
PLL input
Internal master clock enable
Rev. E | Page 24 of 32
Data Sheet
AD1939
Table 17. PLL and Clock Control 1 Register
Bit
0
1
2
3
7:4
Value
0
1
0
1
0
1
0
1
0000
Function
PLL clock
MCLK
PLL clock
MCLK
Enabled
Disabled
Not locked
Locked
Reserved
Description
DAC clock source select
ADC clock source select
On-chip voltage reference
PLL lock indicator (read only)
DAC CONTROL REGISTERS
Table 18. DAC Control 0 Register
Bit
0
2:1
5:3
7:6
Value
0
1
00
01
10
11
000
001
010
011
100
101
110
111
00
01
10
11
Function
Normal
Power-down
32 kHz/44.1 kHz/48 kHz
64 kHz/88.2 kHz/96 kHz
128 kHz/176.4 kHz/192 kHz
Reserved
1
0
8
12
16
Reserved
Reserved
Reserved
Stereo (normal)
TDM (daisy chain)
DAC AUX mode (ADC-, DAC-, TDM-coupled)
Dual-line TDM
Description
Power-down
Sample rate
SDATA delay (BCLK periods)
Serial format
Table 19. DAC Control 1 Register
Bit
0
2:1
3
4
5
6
7
Value
0
1
00
01
10
11
0
1
0
1
0
1
0
1
0
1
Function
Latch in mid cycle (normal)
Latch in at end of cycle (pipeline)
64 (2 channels)
128 (4 channels)
256 (8 channels)
512 (16 channels)
Left low
Left high
Slave
Master
Slave
Master
DBCLK pin
Internally generated
Normal
Inverted
Description
BCLK active edge (TDM in)
BCLKs per frame
LRCLK polarity
LRCLK master/slave
BCLK master/slave
BCLK source
BCLK polarity
Rev. E | Page 25 of 32
AD1939
Data Sheet
Table 20. DAC Control 2 Register
Bit
0
2:1
4:3
5
7:6
Value
0
1
00
01
10
11
00
01
10
11
0
1
00
Function
Unmute
Mute
Flat
48 kHz curve
44.1 kHz curve
32 kHz curve
24
20
Reserved
16
Noninverted
Inverted
Reserved
Description
Master mute
De-emphasis (32 kHz/44.1 kHz/48 kHz mode only)
Word width
DAC output polarity
Table 21. DAC Individual Channel Mutes
Bit
0
1
2
3
4
5
6
7
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Function
Unmute
Mute
Unmute
Mute
Unmute
Mute
Unmute
Mute
Unmute
Mute
Unmute
Mute
Unmute
Mute
Unmute
Mute
Description
DAC 1 left mute
DAC 1 right mute
DAC 2 left mute
DAC 2 right mute
DAC 3 left mute
DAC 3 right mute
DAC 4 left mute
DAC 4 right mute
Table 22. DAC Volume Controls
Bit
7:0
Value
0
1 to 254
255
Function
No attenuation
−3/8 dB per step
Full attenuation
Description
DAC volume control
Rev. E | Page 26 of 32
Data Sheet
AD1939
ADC CONTROL REGISTERS
Table 23. ADC Control 0 Register
Bit
0
1
2
3
4
5
7:6
Value
0
1
0
1
0
1
0
1
0
1
0
1
00
01
10
11
Function
Normal
Power down
Off
On
Unmute
Mute
Unmute
Mute
Unmute
Mute
Unmute
Mute
32 kHz/44.1 kHz/48 kHz
64 kHz/88.2 kHz/96 kHz
128 kHz/176.4 kHz/192 kHz
Reserved
Description
Power-down
High-pass filter
ADC 1L mute
ADC 1R mute
ADC 2L mute
ADC 2R mute
Output sample rate
Table 24. ADC Control 1 Register
Bit
1:0
4:2
6:5
7
Value
00
01
10
11
000
001
010
011
100
101
110
111
00
01
10
11
0
1
Function
24
20
Reserved
16
1
0
8
12
16
Reserved
Reserved
Reserved
Stereo
TDM (daisy chain)
ADC AUX mode (ADC-, DAC-, TDM-coupled)
Reserved
Latch in mid cycle (normal)
Latch in at end of cycle (pipeline)
Rev. E | Page 27 of 32
Description
Word width
SDATA delay (BCLK periods)
Serial format
BCLK active edge (TDM in)
AD1939
Data Sheet
Table 25. ADC Control 2 Register
Bit
0
1
2
3
5:4
6
7
Value
0
1
0
1
0
1
0
1
00
01
10
11
0
1
0
1
Function
50/50 (allows 32, 24, 20, or 16 bit clocks (BCLKs)
per channel)
Pulse (32 BCLKs per channel)
Drive out on falling edge (DEF)
Drive out on rising edge
Left low
Left high
Slave
Master
64
128
256
512
Slave
Master
ABCLK pin
Internally generated
Rev. E | Page 28 of 32
Description
LRCLK format
BCLK polarity
LRCLK polarity
LRCLK master/slave
BCLKs per frame
BCLK master/slave
BCLK source
Data Sheet
AD1939
ADDITIONAL MODES
The AD1939 offers several additional modes for board level
design enhancements. To reduce the EMI in board level design,
serial data can be transmitted without an explicit BCLK. See
Figure 27 for an example of a DAC TDM data transmission
mode that does not require high speed DBCLK. This configuration is applicable when the AD1939 master clock is generated
by the PLL with the DLRCLK as the PLL reference frequency.
To relax the requirement for the setup time of the AD1939 in
cases of high speed TDM data transmission, the AD1939 can
latch in the data using the falling edge of DBCLK. This effectively dedicates the entire BCLK period to the setup time. This
mode is useful in cases where the source has a large delay time
in the serial data driver. Figure 28 shows this pipeline mode of
data transmission.
Both the BCLK-less and pipeline modes are available on the
ADC serial data port.
DLRCLK
32 BITS
INTERNAL
DBCLK
DSDATAx
DLRCLK
06071-059
INTERNAL
DBCLK
TDM-DSDATAx
Figure 27. Serial DAC Data Transmission in TDM Format Without DBCLK
(Applicable Only If PLL Locks to DLRCLK, This Mode Is Also Available in the ADC Serial Data Port)
DLRCLK
DBCLK
DSDATAx
06071-060
DATA MUST BE VALID
AT THIS BCLK EDGE
MSB
Figure 28. I2S Pipeline Mode in DAC Serial Data Transmission
(Applicable in Stereo and TDM, Useful for High Frequency TDM Transmission,
This Mode Is Also Available in the ADC Serial Data Port)
Rev. E | Page 29 of 32
AD1939
Data Sheet
APPLICATION CIRCUITS
Typical application circuits are shown in Figure 29 through Figure 32. Figure 29 shows a typical ADC input filter circuit. Recommended
loop filters for LR clock and master clock as the PLL reference are shown in Figure 30. Output filters for the DAC outputs are shown in
Figure 31 and a regulator circuit is shown in Figure 32.
120pF
5.76kΩ
5.76kΩ
100pF
3
11kΩ
–
1
OP275
DAC
OUTN
+
4.7µF 237Ω
5.76kΩ
+
120pF
6
5
OP275
ADCxN
DAC
OUTP
1nF
NPO
1nF
NPO
4.7µF 237Ω
7
270pF
NPO
5.62kΩ
+
2.2nF
AVDD2
604Ω
+
+
AUDIO
OUTPUT
2.2nF
NPO
10µF
5V
1kΩ
E
B
VDRIVE
390pF
562Ω
1
VSUPPLY
5.6nF
3.32kΩ
AVDD2
MCLK
FZT953
C
06071-030
+
LF
39nF
3
–
OP275
1.50kΩ
100nF
LF
2
Figure 31. Typical DAC Output Filter Circuit (Differential)
Figure 29. Typical ADC Input Filter Circuit
LRCLK
68pF
NPO
5.62kΩ
ADCxP
+
3.01kΩ
560pF
NPO
100pF
5.76kΩ
–
11kΩ
06071-031
2
3.3V
VSENSE
100nF
Figure 30. Recommended Loop Filters for LRCLK or MCLK PLL Reference
Rev. E | Page 30 of 32
+
10µF
06071-032
600Z
06071-029
AUDIO
INPUT
Figure 32. Recommended 3.3 V Regulator Circuit
Data Sheet
AD1939
OUTLINE DIMENSIONS
0.75
0.60
0.45
12.20
12.00 SQ
11.80
1.60
MAX
64
49
1
48
PIN 1
10.20
10.00 SQ
9.80
TOP VIEW
(PINS DOWN)
0.15
0.05
SEATING
PLANE
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
VIEW A
16
33
32
17
VIEW A
0.50
BSC
LEAD PITCH
0.27
0.22
0.17
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BCD
051706-A
1.45
1.40
1.35
Figure 33. 64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2
AD1939YSTZ
AD1939YSTZRL
AD1939WBSTZ
AD1939WBSTZ-RL
EVAL-AD1939AZ
1
2
Temperature Range
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
Package Description
64-Lead LQFP
64-Lead LQFP, 13” Tape and Reel
64-Lead LQFP
64-Lead LQFP, 13” Tape and Reel
Evaluation Board
Package Option
ST-64-2
ST-64-2
ST-64-2
ST-64-2
Z = RoHS Compliant Part.
W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The AD1939W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
Rev. E | Page 31 of 32
AD1939
Data Sheet
NOTES
©2006–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06071-0-2/13(E)
Rev. E | Page 32 of 32
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