High Definition Audio
SoundMAX Codec
AD1987
FEATURES
16-, 20-, and 24-bit PCM resolution
Selectable stereo mixer on outputs
3 stereo headphones
Microsoft Vista Premium logo for desktop
95 dB audio outputs, 90 dB audio inputs
Internal 32-bit arithmetic for greater accuracy
Impedance and presence detection on all jacks
Retaskable jacks
4 independent microphone bias pins
Digital and analog PCBeep
C/LFE channel swapping
2 general-purpose digital I/O (GPIO) pins
Advanced power management modes
48-lead LFCSP_VQ package
TE
2 independent stereo ADC pairs
Simultaneous record of up to 4 channels
Independent 8 kHz, 11.025 kHz, 16 kHz, 22.05 kHz, 32 kHz,
44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz sample rates
16-, 20-, and 24-bit PCM resolution
Support for quad microphone arrays
S/PDIF OUTPUT
Supports 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and
192 kHz sample rates
16-, 20-, and 24-bit data; PCM, AC3
Digital PCM gain control
LE
EIGHT 192 kHz DACs
FOUR 96 kHz ADCs
4 independent stereo DAC pairs
7.1 surround sound or 5.1 stereo out plus independent
headphone
Independent 8 kHz, 11.025 kHz, 16 kHz, 22.05 kHz, 32 kHz,
44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz
sample rates
DEDICATED AUXILIARY PINS
B
SO
Stereo CD/auxiliary I/O port w/GND sense
Mono out pin for internal speakers or telephony
S /P D IF T x
H
D
I
N
T
E
R
F
A
C
E
D IG IT A L
P C B E EP
A D 19 87
DAC3
⌺
PO R T F
DAC2
⌺
PO R T G
DAC1
⌺
PO R T D
DAC0
⌺
PORT H
⌺
MONO OUT
⌺
PORT E
⌺
PORT A
⌺
PORT B
⌺
PORT C
O
A
U
D
I
O
S /P D IF O U T
G P IO
⌺
A DC1
ADC0
Figure 1. AD1987 Block Diagram
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
AD1987
TABLE OF CONTENTS
Features ................................................................. 1
Revision History ...................................................... 2
General Description ................................................. 3
Additional Information .......................................... 3
Jack Configuration ................................................ 3
Specifications .......................................................... 4
Test Conditions .................................................... 4
Performance ........................................................ 4
TE
General Specifications ............................................ 4
HD Audio Link Specification ................................... 7
Power-Down States ............................................... 7
Absolute Maximum Ratings .................................... 8
ESD Sensitivity ..................................................... 8
Environmental Conditions ...................................... 8
LE
Pin Configuration and Function Descriptions ................. 9
HD Audio Widgets ................................................ 12
HD Audio Parameters ............................................. 13
Widget Parameters ................................................. 14
Connection List ..................................................... 15
B
SO
Default Configuration Bytes ..................................... 16
Outline Dimensions ............................................... 17
Ordering Guide ..................................................... 17
REVISION HISTORY
3/08—Rev. 0 to Rev. A
Revised notes in Power-Down States ............................ 7
Corrected PCBEEP pin number
AD1987 Pin Descriptions ........................................ 10
O
Corrected VREF_FLT pin number
AD1987 Pin Descriptions ........................................ 10
Rev. A |
Page 2 of 20 |
March 2008
AD1987
GENERAL DESCRIPTION
The jack retasking feature on this product supports various configurations including platforms for 7.1 on 5 jacks, 5.1 on 3 jacks,
and front panel jack retasking.
The AD1987 is available in a 48-lead Pb-free frame chip scale
package in both reels and trays. See Ordering Guide on Page 17.
ADDITIONAL INFORMATION
Port
Port A – Front Panel Headphone
Port B – Front Panel Microphone
Port C – Rear Panel Line-In/SurroundCenter/Side (7.1)
Port D – Rear Panel Front/Headphone
Port E – Rear Panel Microphone
Port F – Rear Panel Surround-Rear (5.1)
Port G – Rear Panel C/LFE
JACK CONFIGURATION
B
SO
Table 1. Desktop Applications with Discrete Jacks (Default
Configuration)
O
HP
x
x
MIC
x
x
x
x
x
LO
x
x
x
x
x
x
x
x
LI
x
x
x
x
x
Rev. A |
MIC
x
x
x
x
Port
Port A – Front Panel Headphone
Port B – Front Panel Microphone
Port C – Rear Panel Line-In/Surround-Rear
(5.1)
Port D – Rear Panel Front/Headphone
Port E – Rear Panel Microphone /C/LFE
The guidelines shown in Table 1 through Table 3 should be
used when selecting ports for particular functions. The symbols
used in this table are defined as: LI = line level input, LO = line
level output, HP = output capable of driving headphone load,
MIC = input supports microphones with MIC bias and boost
amplifier.
Port
Port A – Front Panel Headphone
Port B – Front Panel Microphone
Port C – Rear Panel Line-In
Port D – Rear Panel Front/Headphone
Port E – Rear Panel Microphone
Port F – Rear Panel Surround-Rear (5.1)
Port G – Rear Panel C/LFE
Port H – Rear Panel SurroundCenter/Side (7.1)
HP
x
x
x
LO
x
x
x
LI
x
x
x
x
x
x
x
x
x
Table 3. Desktop Applications with Retasking to Support 5.1
Audio on 3 Jacks
LE
This data sheet provides a general overview of the AD1987
SoundMAX codec’s architecture and functionality. Additional
information on the AD1987 is available in the AD1987 Programmers Reference Manual. Please contact your local Analog
Devices Inc. sales representative for more information. For
information on SoundMAX codecs and software, see Analog
Devices website at http://www.analog.com/soundMAX.
Table 2. Retasking to Support 7.1 Audio on 5 Jacks
TE
The AD1987 audio codec and SoundMAX® software provides
superior HD audio quality that exceeds Vista Premium performance. The AD1987 has eight DACs and four ADCs, three
stereo headphone ports, C/LFE swapping, digital and analog
PCBeep, and S/PDIF output, making the AD1987 the right
choice for desktop PCs where performance is the primary
consideration.
Page 3 of 20 |
March 2008
HP
x
x
MIC
x
x
x
LO
x
x
x
LI
x
x
x
x
x
x
x
x
x
AD1987
SPECIFICATIONS
TEST CONDITIONS
ADC
Test Condition
25°C
3.3 V
3.3 V
5.0 V
48 kHz
1008 Hz
–3.0 dB Full Scale
20 Hz to 20 kHz
10 kΩ Output Load: Line Out Tests
32 Ω Output Load: Headphone Tests
0 dB Gain
TE
Parameter
Temperature
Digital Supply
Analog Supply
MIC_BIAS_IN (via Low-Pass Filter)
Sample Rate fS
Input Signal (Frequency Sine Wave)
Amplitude for THD + N
Analog Output Pass Band
DAC
PERFORMANCE
Typ
Max
LE
Min
B
SO
Parameter
Line Out Drive (10 kΩ loads—DAC to Pin)
Total Harmonic Distortion (THD + N)
Dynamic Range (–60 dB in ref to fS A-Weighted)
Signal-to-Noise Ratio
Headphone Drive (32 Ω loads—DAC to Pin)
Total Harmonic Distortion (THD + N)
Dynamic Range (–60 dB in ref to fS A-Weighted)
Signal-to-Noise Ratio
Input Ports (Mic Boost = 0 dB)
Total Harmonic Distortion (THD + N)
Dynamic Range (–60 dB in ref to fS A-Weighted)
Signal-to-Noise Ratio
Unit
–85
95
95
dB
dB
dB
–83
95
95
dB
dB
dB
–81
90
90
dB
dB
dB
GENERAL SPECIFICATIONS
O
Parameter
DIGITAL DECIMATION AND INTERPOLATION FILTERS1—fS = 8 kHz to 192 kHz
Pass Band
Pass-Band Ripple
Stop Band
Stop-Band Rejection
Group Delay
Group Delay Variation Over Pass Band
ANALOG-TO-DIGITAL CONVERTERS
Resolution
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)2
Interchannel Gain Mismatch (Difference of Gain Errors)
ADC Offset Error1
ADC Crosstalk1
Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L)
Line_In to Other
Rev. A |
Page 4 of 20 |
Min
Typ
0
Max
Unit
0.4 fS
±0.005
Hz
dB
Hz
dB
1/fS
μs
0.6 fS
–100
20
0
24
±0.2
–85
–100
March 2008
±10
±0.5
±5
Bits
%
dB
mV
–80
dB
dB
AD1987
Min
Typ
Max
24
±10
±0.5
–85
–95
1.5
–58.5
0
–80
1.5
–58.5
Mic Boost = +10 dB
Mic Boost = +20 dB
O
Mic Boost = +30 dB
Input Impedance
PCBEEP
Ports B, C, E (Mic Boost = 0 dB)
Port F
Input Capacitance1
Rev. A |
Page 5 of 20 |
March 2008
dB
dB
dB
+12.0
dB
dB
dB
1000
V rms3
V p-p
Ω
kΩ
pF
pF
1.0
2.83
LE
B
SO
Input Voltages—Microphone Boost
Amplifier, Ports B, C, or E
Bits
%
dB
dB
dB
dB
dB
95
–1.5
–34.5
Unit
+22.5
TE
Parameter
DIGITAL-TO-ANALOG CONVERTERS
Resolution
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)1
Interchannel Gain Mismatch (Difference of Gain Errors)
Total Audible Out-of-Band Energy (Measured from 0.6 × fS to 20 kHz)1
DAC Crosstalk (Input L, Zero R, Measure R_OUT; Input R, Zero L, Measure L_OUT)1
DAC VOLUMES
Step Size (DAC-0, DAC-1, DAC-2, DAC-3)
Output Gain/Attenuation Range
Mute Attenuation of 0 dB Fundamental1
ADC VOLUMES
Step Size (ADCSEL-0, ADCSEL-1)
PGA Gain/Attenuation Range
ANALOG MIXER
Signal-to-Noise Ratio Input to Output—Ports B, C, or F, to Port D Output
Step Size: All Mixer Inputs
Input Gain/Attenuation Range: All Mixer Inputs
ANALOG LINE LEVEL OUTPUTS
Full-Scale Output Voltage: Line out drive enabled
Ports A, D, E, F, and Mono Out
Output Impedance1
External Load Impedance1
Output Capacitance1
External Load Capacitance1
ANALOG HP DRIVE OUTPUTS
Full-Scale Output Voltage: Line Out Drive Enabled
Ports A and D (when HP Drive is Enabled)
Output Impedance1
External Load Impedance1
Output Capacitance1
External Load Capacitance1
ANALOG INPUTS
Input Voltages—Ports B, C, or E
Mic Boost = 0 dB
190
10
15
1.0
2.83
0.5
32
15
1000
V rms3
V p-p
Ω
Ω
pF
pF
1
2.83
0.316
0.894
0.1
0.283
0.032
0.089
V rms3
V p-p
V rms3
V p-p
V rms3
V p-p
V rms3
V p-p
23
150
45
5
kΩ
kΩ
kΩ
pF
7.5
AD1987
MIC_BIAS_IN (Pin 33) = +5 V
MIC_BIAS_IN (Pin 33) = +3.3 V
MIC_BIAS-E (When enabled as BIAS)
Min
Typ
High-Z
0
1.65
3.7
3.9
2.86
3.0
V dc
V dc
V dc
V dc
V dc
V dc
VREF Setting = High-Z
VREF Setting = 0 V
VREF Setting = 50%
VREF Setting = 80%
VREF Setting = 100%
High-Z
0
1.65
2.86
3.0
V dc
V dc
V dc
V dc
V dc
1.6
mA
DVIO × 0.60
0
DVIO × 0.72
0
LE
B
SO
O
Guaranteed but not tested.
Measurements reflect main ADC.
3
RMS values assume sine wave input.
2
Unit
VREF Setting = High-Z
VREF Setting = 0 V
VREF Setting = 50%
VREF Setting = 80%
VREF Setting = 100%
VREF Setting = 80%
VREF Setting = 100%
Output Drive Current
VREF Setting = 50%, 80%, or 100%
GPIO 0 and GPIO 1
Input Signal High (VIH)
Input Signal Low (VIL)
Output Signal High (VOH)
IOUT = –500 μA
IOUT = +1500 μA
Output Signal Low (VOL)
Input Leakage Current (Signal High) (IIH)
Input Leakage Current (Signal Low) (IIL)
POWER SUPPLY
Analog (AVDD) 3.3 V ± 5%
Power Supply Range
Power Dissipation
Supply Current
Digital (DVDD) 3.3 V ± 10%
Power Supply Range
Power Dissipation
Supply Current
Digital I/O (DVIO) 3.3 V ± 10%
Power Supply Range
Power Dissipation
Supply Current
Power Supply Rejection (Reference to fS 100 mV p-p Signal @ 1 kHz)1
1
Max
TE
Parameter
MICROPHONE BIAS
MIC_BIAS-B, MIC_BIAS-C
MIC_BIAS_IN (Pin 33) = +5 V or +3.3 V
Rev. A |
Page 6 of 20 |
March 2008
DVIO
DVIO × 0.24
DVIO
DVIO × 0.10
V
V
V
V
μA
μA
–150
–50
3.13
3.30
135
41
3.46
V
mW
mA
2.97
3.30
218
66
3.63
V
mW
mA
2.97
3.30
3.96
1.20
80
3.63
V
mW
mA
dB
AD1987
HD AUDIO LINK SPECIFICATION
HD Audio signals comply with the High Definition Audio Specifications. Please refer to these specifications at:
http://www.intel.com/standards/hdaudio/
POWER-DOWN STATES
1
IAVDD Typ
41
1.2
3
Unit
mA
mA
mA
6
5.3
0
0
5
3.2
2
0.5
mA
mA
mA
mA
Powering down the MIC_BIAS powers down all port MIC_BIAS pins. This disables all microphone bias circuits set to 100% or 50%, setting them to the high-Z state. The
0 Ω and high-Z states remain unaffected by the MIC_BIAS power state.
Test conditions: 30 pF load, 2.0 MHz frequency, 3.3 V AVDD.
O
B
SO
LE
2
IDVDD Typ
66
21
3
TE
Parameter
Function Node in D0, All Nodes Active
Function Node in D3
Codec in RESET
Individual Block Power Savings
DAC Pair Powered Down Saves (Each)
ADC Pair Powered Down Saves (Each)
Mixer Power Control (And Associated Amps) Saves
MIC_BIAS Powered Down Saves1, 2
Rev. A |
Page 7 of 20 |
March 2008
AD1987
ABSOLUTE MAXIMUM RATINGS
ENVIRONMENTAL CONDITIONS
Stresses greater than those listed below may cause permanent
damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above
those indicated in the operational section of this specification is
not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Ambient Temperature Rating
Rating
–0.30 V to +3.65 V
–0.30 V to +3.65 V
–0.30 V to +3.65 V
±10.0 mA
–0.30 V to AVDD +0.3 V
–0.30 V to DVIO +0.3 V
0°C to +70°C
–65°C to +150°C
All measurements per EIA-JESD51 with 2S2P test board per
EIA-JESD51-7.
Table 4. Thermal Resistance
Package
LFCSP_VQ
θJA
97
LE
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device.
O
B
SO
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
Rev. A |
θJC
15
θCA
32
TE
Power Supplies
Digital (DVDD)
Digital I/O (DVIO)
Analog (AVDD)
Input Current (except supply pins)
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
Ambient Temperature (Operating)
Storage Temperature
TAMB = TCASE – (PD × θCA)
TCASE = Case Temperature in °C
PD = Power Dissipation in W
θCA = Thermal Resistance (Case-to-Ambient)
θJA = Thermal Resistance (Junction-to-Ambient)
θJC = Thermal Resistance (Junction-to-Case)
Page 8 of 20 |
March 2008
Unit
°C/W
AD1987
S/PDIF_OUT
GPIO_1/EAPD
PORT-H_R
PORT-H_L
PORT-G_R
PORT-G_L
AVSS
PORT-A_R
MONO_OUT
PORT-A_L
AVDD
MIC_BIAS-A
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48
47
46
45
44
43
42
41
40
39
38
37
1
36
PORT-D_R
GPIO_0
2
35
PORT-D_L
DVIO
3
34
SENSE_B/SRC_A
DVSS
4
33
MIC_BIAS_IN
SDATA_OUT
5
32
RESERVED (NC)
BIT_CLK
6
31
MIC_BIAS-E
30
RESERVED (NC)
29
MIC_BIAS-C
28
MIC_BIAS-B
27
VREF_FLT
26
AVSS
25
AVDD
AD1987JCPZ
TOP VIEW
7
9
SYNC
10
RESET
11
PCBEEP
12
14
15
16
17
18
19
20
CD_R
CD_GND
CD_L
PORT-F_R
PORT-F_L
PORT-E_R
PORT-E_L
SENSE_A/SRC_B
B
SO
13
21
22
23
24
O
Figure 2. AD1987 48-Lead Package and Pinout
Rev. A |
Page 9 of 20 |
March 2008
PORT-C_R
DVDD
PORT-C_L
8
PORT-B_R
SDATA_IN
LE
(Not To Scale)
PORT-B_L
DVSS
TE
DVCORE
AD1987
Table 5. AD1987 Pin Descriptions
Pin No.
Function
Description
5
6
8
10
11
I
I
I/O
I
I
Link Serial Data Output. Clocked on both edges of BIT_CLK.
Link Bit Clock. 24.000 MHz serial data clock.
Link Serial Data Input. AD1987 output stream clocked only on one edge of BIT_CLK.
Link Frame Sync.
Link Reset. Master hardware reset.
2
47
I/O
I/O
S/PDIF_OUT
JACK SENSE
SENSE_A/SRC_B
SENSE_B/SRC_A
ANALOG I/O
PCBEEP
PORT-E_L
PORT-E_R
PORT-F_L
PORT-F_R
CD_L
CD_GND
48
O
General-Purpose Input/Output Pin. Digital signal used to control external circuitry.
General-Purpose Input/Output Pin/EAPD Pin. Digital signal used to control external
circuitry. By default pin is in a high-Z state. When used as EAPD: high-Z = amp on,
DVSS = amp off.
S/PDIF_OUT. Supports S/PDIF output.
13
34
I/O
I/O
JACK Sense A-D Input/Sense B Drive.
JACK Sense E-H Input/Sense A Drive.
12
14
15
16
17
18
19
LI
LI, MIC, LO, SWAP
LI, MIC, LO, SWAP
LO
LO
LI
LI
CD_R
PORT-B_L
PORT-B_R
PORT-C_L
PORT-C_R
PORT-D_L
PORT-D_R
PORT-A_L
MONO_OUT
PORT-A_R
PORT-G_L
PORT-G_R
PORT-H_L
PORT-H_R
FILTER/REFERENCE
MIC_BIAS-B
MIC_BIAS-C
MIC_BIAS-E
VREF_FLT
MIC_BIAS-A
20
21
22
23
24
35
36
39
40
41
43
44
45
46
LI
LI, MIC, HP, LO
LI, MIC, HP, LO
LI, MIC, LO
LI, MIC, LO
LI, HP, LO
LI, HP, LO
LI, MIC, HP, LO
LO
LI, MIC, HP, LO
LO, SWAP
LO, SWAP
LO
LO
Monaural Input From System for Analog PCBeep.
Auxiliary Input/Output Left Channel.
Auxiliary Input/Output Right Channel.
Auxiliary Input/Output Left Channel.
Auxiliary Input/Output Right Channel.
CD Audio Left Channel.
CD-Audio-Analog-Ground-Reference (for Differential CD Input). Must be connected
to AGND via 0.1 μF capacitor if not in use as CD_GND.
CD Audio Right Channel.
Front Panel Stereo MIC/Line-In.
Front Panel Stereo MIC/Line-In.
Rear Panel Stereo MIC/Line-In.
Rear Panel Stereo MIC/Line-In.
Rear Panel Headphone/Line-Out.
Rear Panel Headphone/Line-Out.
Front Panel Headphone/Line-Out.
Monaural Output to Internal Speaker or Telephony Subsystem Speakerphone.
Front Panel Headphone/Line-Out.
Rear Panel C/LFE Output.
Rear Panel C/LFE Output.
Rear Panel Surround Center/Side.
Rear Panel Surround Center/Side.
28
29
31
27
37
O
O
O
O
O
B
SO
LE
TE
Mnemonic
DIGITAL INTERFACE
SDATA_OUT
BIT_CLK
SDATA_IN
SYNC
RESET
DIGITAL I/O
GPIO_0
GPIO_1/EAPD
O
Switchable Microphone Bias. For use with Port B (Pins 21, 22).
Switchable Microphone Bias. For use with Port C (Pins 23, 24).
Switchable Microphone Bias. For use with Port E (Pins 14, 15).
Voltage Reference Filter.
Switchable Microphone Bias. For use with Port A (Pins 39, 41)
All MIC_BIAS pins are capable of:
High-Z, 0 V, 1.65 V, 3.78 V, and 3.95 V (with 5.0 V on Pin 33)
High-Z, 0 V, 1.65 V, 2.86 V, and 3.00 V (with 3.3 V on Pin 33).
1
O
DVCORE
CAUTION: DO NOT APPLY 3.3 V TO THIS PIN!
Filter connection for internal core voltage regulator.
This pin must be connected to filter caps: 10 μF, 1.0 μF, and 0.1 μF connected in
parallel between Pin 1 and DVSS (Pin 4).
The symbols used in this table are defined as: I = Input, O = Output, LI = Line level input, LO = Line level output, HP = Output capable of driving
headphone load, MIC = Input supports microphones with MIC bias and boost amplifier, SWAP = Outputs can swap L/R channels (typically used
to support C/LFE or shared C/LFE function).
Rev. A |
Page 10 of 20 |
March 2008
AD1987
Table 5. AD1987 Pin Descriptions (Continued)
Pin No.
Function
Description
3
I
DVSS
DVDD 3.3 V ±10%
4, 7
9
I
I
AVDD 3.3 V ±5%
25, 38
I
MIC_BIAS_IN
33
I
AVSS
26, 42
I
Digital Supply I/O. Connect to the I/O voltage used for the HD audio controller
signals.
Digital Supply Return (Ground).
Digital Supply Voltage 3.3 V. This is regulated down to Pin 1 to supply the internal
digital core.
CAUTION: DO NOT APPLY 5.0 V TO THESE PINS!
Analog Supply Voltage 3.3 V ONLY.
Note: AVDD supplies should be well regulated and filtered as supply noise degrades
audio performance.
Source for Microphone Bias Boost Circuitry.
Connect this pin to 5.0 V via a low-pass filter. When connected this way, the AD1987
is capable of providing +3.95 V as a mic bias to all of the mic bias pins.
If 5 V is not available, connect this pin to +3.3 V (AVDD) via a low-pass filter. The
AD1987 produces a mic bias voltage relative to the AVDD supply
(typically 3.0 V @ AVDD = 3.3 V).
Analog Supply Return (Ground). AVSS should be connected to DVSS using a
conductive trace under, or close to, the AD1987.
TE
Mnemonic
POWER AND GROUND
DVIO 3.3 V ±10%
O
B
SO
LE
The symbols used in this table are defined as: I = Input, O = Output, LI = Line level input, LO = Line level output, HP = Output capable of driving
headphone load, MIC = Input supports microphones with MIC bias and boost amplifier, SWAP = Outputs can swap L/R channels (typically used
to support C/LFE or shared C/LFE function).
Rev. A |
Page 11 of 20 |
March 2008
AD1987
HD AUDIO WIDGETS
In the following table, node IDs that are not shown are reserved for future use.
Description
Device identification
Designates this device as an audio codec
S/PDIF digital stream output interface
Headphone/surround side (7.1) channel digital/audio converters
Stereo front channel digital/audio converters
Stereo C/LFE channel digital/audio converters
Stereo surround-back (5.1) channel digital/audio converters
Stereo record Channel 1 audio/digital converters
Stereo record Channel 2 audio/digital converters
Selects which ADC drives the S/PDIF mixer
Selects and amplifies/attenuates the input to ADC_0
Selects and amplifies/attenuates the input to ADC_1
Internal digital PCBeep signal
Front panel headphone/microphone jack
Rear panel front/headphone jack
Monaural output pin (internal speakers or telephony system)
Front panel microphone/headphone jack
Rear panel line-in jack
Rear panel surround-rear (5.1) jack
Rear panel mic jack
Analog CD input
Powers down the analog mixer and associated amps
External analog PCBeep signal input
S/PDIF output pin
Mixes the selected ADC with the digital stream to drive S/PDIF out
Selects which source drives the mono out signal
Mixes individually gainable analog inputs
Attenuates the mixer output to drive the port mixers
Mixes the Port A Selected DAC and mixer output amps to drive Port A
Powers down the internal and external VREF circuitry
Rear panel C/LFE jack
Rear panel surround-side (7.1) jack
Mixes DAC_2 and mixer output amps to drive Port E
Mixes DAC_2 and mixer output amps to drive Port G
Mixes DAC_0 and mixer output amps to drive Port H
Mixes DAC_1 and mixer output amps to drive Port D
Mixes DAC_3 and mixer output amps to drive Port F
Mixes the Port B selected DAC and mixer output amps to drive Port B
Mixes the Port C selected DAC and mixer output amps to drive Port C
Mixes the stereo L/R channels to drive mono output
Powers down the internal MIC_BIAS_FILT and all MIC_BIAS Pins
Selects the Port B DAC (0, 1)
Selects the Port C DAC (0, 3)
Selects the Port A DAC (0, 1)
Microphone boost amp for Port A
Microphone boost amp for Port B
Microphone boost amp for Port C
Microphone boost amp for Port E
TE
Type
Root
Function
Audio Output
Audio Output
Audio Output
Audio Output
Audio Output
Audio Input
Audio Input
Audio Selector
Audio Selector
Audio Selector
Beep Generator
Pin Complex
Pin Complex
Pin Complex
Pin Complex
Pin Complex
Pin Complex
Pin Complex
Pin Complex
Power Widget
Pin Complex
Pin Complex
Audio Mixer
Audio Mixer
Audio Mixer
Audio Selector
Audio Mixer
Vendor Defined
Pin Complex
Pin Complex
Audio Mixer
Audio Mixer
Audio Mixer
Audio Mixer
Audio Mixer
Audio Mixer
Audio Mixer
Audio Mixer
Vendor Defined
Audio Selector
Audio Selector
Audio Selector
Audio Selector
Audio Selector
Audio Selector
Audio Selector
LE
Type ID
x
x
0
0
0
0
0
1
1
3
3
3
7
4
4
4
4
4
4
4
4
5
4
4
2
2
2
3
2
F
4
4
2
2
2
2
2
2
2
2
F
3
3
3
3
3
3
3
B
SO
Name
ROOT
FUNCTION
S/PDIF DAC
DAC_0
DAC_1
DAC_2
DAC_3
ADC_0
ADC_1
S/PDIF Mix Selector
ADC Selector 0
ADC Selector 1
Digital Beep
Port A (Headphone)
Port D (Front L/R)
Mono Out
Port B (Front Mic)
Port C (Line In)
Port F (Surr Back)
Port E (Rear Mic)
CD In
Mixer Power Down
Analog PCBeep
S/PDIF Out
S/PDIF Mixer
Mono Out Mixer
Analog Mixer
Mixer Output Atten
Port A Mixer
VREF Power Down
Port G (C/LFE)
Port H (Surr Side)
Port E Mixer
Port G Mixer
Port H Mixer
Port D Mixer
Port F Mixer
Port B Mixer
Port C Mixer
Stereo Mix Down
BIAS Power Down
Port B Out Selector
Port C Out Selector
Port A Out Selector
Port A Boost
Port B Boost
Port C Boost
Port E Boost
O
Node ID
00
01
02
03
04
05
06
08
09
0B
0C
0D
10
11
12
13
14
15
16
17
18
19
1A
1B
1D
1E
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2F
30
31
37
38
39
3A
3C
Rev. A |
Page 12 of 20 |
March 2008
AD1987
HD AUDIO PARAMETERS
Table 6. Root and Function Node Parameters
Node ID
00
01
1
Name
ROOT
FUNCTION
Vendor ID 00
11D41987
01
Revision ID 021 03
00100200
Sub Node
Count 04
00010001
0002003B
Func. Group Audio F.G.
Type 05
Caps 08
GPIO Caps 11
00000001
40000002
00010C0C
Subject to change with silicon stepping.
Table 7. SubSystem ID1
15:8
SKU
00
The default SSID is overwritten by platform BIOS after power-on. It is preserved across HD Audio link reset and verb reset.
O
B
SO
LE
1
31:16
SSID
BFD7
Value
BFD40000
Rev. A |
7:0
Asm ID
00
TE
SubSystem ID
Node ID
Name
01
FUNCTION
Page 13 of 20 |
March 2008
AD1987
WIDGET PARAMETERS
Table 8. Widget Parameters
Output
Processing Amp
Power
Capabilities Capabilities
States 0F 10
12
00000009
00052727
00000009
00000009
00000009
00000009
00000009
00000009
00052727
00052727
00052727
00052727
LE
TE
Pin
Input Amp
Capabilities Capabilities ConnList
0C
0D
Length 0E
80000000
00000001
00000000
00000000
00000000
00000000
00000001
00000001
00000002
00000008
00000008
00000000
0000373F
00000001
0001003F
00000001
00010010
00000001
0000373F
00000001
00003737
00000001
00000017
00000001
00003737
00000001
00000020
00000000
00000002
00000020
00000000
00000010
00000001
80000000
00000002
80000000
00000002
80051F17
00000008
00000001
80000000
00000002
00000008
00000017
00000001
00000017
00000001
80000000
00000002
80000000
00000002
80000000
00000002
80000000
00000002
80000000
00000002
80000000
00000002
80000000
00000002
00000001
00000004
00000002
00000002
00000002
00000001
00000001
00000001
00000001
B
SO
PCM Size,
Rate 0A
000E01FF
000E01E0
000E01FF
000E01FF
000E01FF
000E01FF
000E01FF
000E01FF
Stream
Formats
0B
00000001
00000005
00000001
00000001
00000001
00000001
00000001
00000001
O
Node
ID
01
02
03
04
05
06
08
09
0B
0C
0D
10
11
12
13
14
15
16
17
18
19
1A
1B
1D
1E
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2F
30
31
37
38
39
3A
3C
Widget
Capabilities
09
00000480
00030311
00000405
00000405
00000405
00000405
00100501
00100501
00300301
0030010D
0030010D
0070000C
0040018D
0040058D
0040050C
0040018D
0040018D
0040018D
0040098D
00400001
00500500
00400000
0040030D
00200303
00200103
0020010B
0030010D
00200103
00F00100
0040098D
0040018D
00200103
00200103
00200103
00200103
00200103
00200103
00200103
00200100
00F00100
00300101
00300101
00300101
0030010D
0030010D
0030010D
0030010D
Rev. A |
Page 14 of 20 |
March 2008
00000009
00000009
80053627
80053627
800B0F0F
80000000
80000000
80051F1F
80000000
80000000
80000000
80000000
00000009
80052727
80051F1F
80000000
80000000
00270300
00270300
00270300
00270300
Volume
Knob
Capabilities
13
AD1987
CONNECTION LIST
Table 9. Connection List
0000000C
0000000D
00000908
18BC3938
18BC3938
[4–7]
20123B3B
20123B3B
0
1
NID
1D
I
0C
0D
08
38
38
22
29
2D
2B
2C
2A
26
00002120
20
00000002
00000B01
00002104
12383A39
00000020
00002137
A2209811
00000027
00000028
00002105
00002105
00002103
00002104
00002106
00002130
00002131
0000001E
11171514
00000403
00000603
00000403
00000011
00000014
00000015
00000017
02
01
04
39
20
37
11
27
28
05
05
03
04
06
30
31
1E
14
03
03
03
11
14
15
17
3
I
NID
09
39
39
1
1
3C
3C
I
1A183B3C
O
BC30AE24
4
NID
I
5
NID
I
6
NID
I
18
18
3B
3B
7
NID
I
NID
3B
3B
12
12
20
20
3B
18
1A
2E
30
21
B
SO
00000022
00000029
0000002D
0000002B
0000002C
0000002A
00000026
2
NID
TE
[0–3]
0000001D
LE
Connections
Node ID
02
03
04
05
06
08
09
0B
0C
0D
10
11
12
13
14
15
16
17
18
19
1A
1B
1D
1E
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2F
30
31
37
38
39
3A
3C
1
0B
21
3A
38
21
18
20
1
12
3C
22
24
21
21
21
21
21
21
21
15
04
06
04
Rev. A |
17
Page 15 of 20 |
11
March 2008
1
1
3C
AD1987
DEFAULT CONFIGURATION BYTES
In Table 10, default configuration values are set on codec
power-up only. Default configuration values are not reset by
link or soft reset to preserve modifications by BIOS control.
Table 10. Default Configuration Bytes
31:30
29:28
27:24
23:20
19:16
15:12
8
7:4
3:0
Def. Device
HP Out
Line Out
Speaker
Mic In
Line In
Line Out
Mic In
CD
Other
SPDIF Out
Line Out
Line Out
Conn Type
1/8” Jack
1/8” Jack
ATAPI
1/8” Jack
1/8” Jack
1/8” Jack
1/8” Jack
ATAPI
ATAPI
Optical
1/8” Jack
1/8” Jack
Color
Green
Green
Unknown
Pink
Blue
Black
Pink
Unknown
Unknown
Black
Orange
Grey
JD OR
0
0
1
0
0
0
0
1
1
1
0
0
Def Assn
1
1
F
F
2
1
2
2
F
F
1
1
Sequence
F
0
0
0
1
2
0
E
0
0
1
4
Connectivity
Jack
Jack
Fixed
Jack
Jack
Jack
Jack
Fixed
Fixed
Jack
Jack
Jack
Chasis
External
External
Internal
External
External
External
External
Internal
Internal
External
External
External
Position
Front
Rear
Special 3
Front
Rear
Rear
Rear
Special 3
Special 3
Rear
Rear
Rear
LE
Value
0221401F
01014010
991301F0
02A190F0
01813021
01011012
01A19020
9933012E
99F301F0
014511F0
01016011
01012014
O
B
SO
Name
Port A (Headphone)
Port D (Line Out)
Mono Out
Port B (Front Mic)
Port C (Line In)
Port F (Surr Back)
Port E (Rear Mic)
CD IN
Analog PCBeep
S/PDIF Out
Port G (C/LFE)
Port H (Surr Side)
TE
Location
Rev. A |
Page 16 of 20 |
March 2008
AD1987
OUTLINE DIMENSIONS
Dimensions are shown in millimeters.
7.00
BSC SQ
0.60 MAX
0.60 MAX
37
36
PIN 1
INDICATOR
TOP
VIEW
25
24
12
13
0.25 MIN
5.50
REF
0.80 MAX
0.65 TYP
COPLANARITY
0.08
LE
0.50 BSC
5.25
5.10 SQ
4.95
(BOTTOM VIEW)
0.05 MAX
0.02 NOM
SEATING
PLANE
1
TE
12° MAX
PIN 1
INDICATOR
48
EXPOSED
PAD
6.75
BSC SQ
0.50
0.40
0.30
1.00
0.85
0.80
0.30
0.23
0.18
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
B
SO
Figure 3. 48-Lead, Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad
(CP-48-1)
ORDERING GUIDE
Model
AD1987JCPZ1
AD1987JCPZ-RL1
Package Description
48-Lead LFCSP_VQ
48-Lead LFCSP_VQ, 13” Tape and Reel
Z = RoHS Compliant Part.
O
1
Temperature Range
0°C to 70°C
0°C to 70°C
Rev. A |
Page 17 of 20 |
March 2008
Package Option
CP-48-1
CP-48-1
O
B
SO
LE
TE
AD1987
Rev. A |
Page 18 of 20 |
March 2008
O
B
SO
LE
TE
AD1987
Rev. A |
Page 19 of 20 |
March 2008
O
B
SO
LE
TE
AD1987
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06536-0-3/08(A)
Rev. A |
Page 20 of 20 |
March 2008
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