Automotive Audio Bus (A2B) Transceiver
AD2420/AD2426/AD2427/AD2428/AD2429
A2B BUS FEATURES
A2B TRANSCEIVER FEATURES
Line topology
Single main node, multiple subordinate nodes
Up to 15 m between nodes and up to 40 m overall cable
length (see Table 9)
Communication over distance
Synchronous data
Multichannel I2S/TDM to I2S/TDM
Synchronous clock, phase aligned in all nodes
Low latency node to node communication
Control and status information I2C to I2C
GPIO and interrupt
Bus power or local power subordinate nodes
Configurable with SigmaStudio/SigmaStudio+ graphical
software tool
AEC-Q100 qualified for automotive applications
Configurable A2B bus main node or subordinate node
Programmable via I2C interface
8-bit to 32-bit multichannel I2S/TDM interface
Programmable I2S/TDM data rate
Up to 32 upstream and 32 downstream channels
PDM interface
Programmable PDM clock rate
Up to 4 high dynamic range microphone inputs
Simultaneous reception of I2S data with up to 4 PDM
microphones
Unique ID register for each transceiver
Crossover or straight-through cabling
Programmable settings to optimize EMC performance
IOVDD
SCL
SDA
IRQ/IO0
ADR1/IO1
ADR2/IO2
I2C
DTX0/IO3
DTX1/IO4
DRX0/IO5
DRX1/IO6
I2S/TDM
PDM
DVDD
APPLICATIONS
Audio communication link
Microphone arrays
Beamforming
Hands free and in car communication
Active and road noise cancellation
Audio/video conferencing systems
PLLVDD
VOUT1
PLL
VREG1
VIN
VOUT2
VREG2
BTRXVDD
A2 B
TRX B
(Towards Last
Subordinate Node)
DIAGNOSTICS
PDMCLK/IO7
A2 B
TRX A
(Towards
Main Node)
BCLK
SYNC
VSSN
VSS
BP
BCM
BN
SWP
SENSE
AP
ACM
AN
ATRXVDD
Figure 1. Functional Block Diagram
A2B and the A2B logo are registered trademarks of Analog Devices, Inc.
Rev. D
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AD2420/AD2426/AD2427/AD2428/AD2429
TABLE OF CONTENTS
A2B Bus Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
ESD Caution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
A2B Transceiver Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Test Circuits and Switching Characteristics . . . . . . . . . . . . . . . 21
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Configuration and Function Descriptions . . . . . . . . . . . . . . . 24
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Power Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2
A B Bus Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
I C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Current Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
VREG1 and VREG2 Output Currents . . . . . . . . . . . . . . . . . . . . . . 29
I S/TDM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Current at VIN (IVIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Pulse Density Modulation (PDM) Interface . . . . . . . . . . . . . . . . . 6
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
GPIO Over Distance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Resistance Between Nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data Slot Exchange Between Subordinates . . . . . . . . . . . . . . . . . . 6
Voltage Regulator Current in Main Node or Local
Powered Subordinate Node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Clock Sustain State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Power Dissipation of A2B Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Programmable Settings to Optimize EMC
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Power Analysis of Bus Powered System . . . . . . . . . . . . . . . . . . . . 31
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Reducing Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Designer Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Power Supply Rejection Ratio (PSRR) . . . . . . . . . . . . . . . . . . . . . . 11
VSENSE and Considerations for Diodes . . . . . . . . . . . . . . . . . . . . . . . 33
Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Optional Add On Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Power-Up Sequencing Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 16
Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
A B Bus System Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
PDM Typical Performance Characteristics . . . . . . . . . . . . . . . . 18
Automotive Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
REVISION HISTORY
5/2022—Rev. C to Rev. D
Analog Devices is in the process of updating documentation to
provide terminology and language that is culturally appropriate.
This is a process with a wide scope and will be phased in as
quickly as possible. Thank you for your patience.
Changes to I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Corrected typographical error in Unit column for fSYSBCLK
parameter from kHz to Hz in Table 3,
Clock and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Added tSYSBCLK parameter to Table 3,
Clock and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Added Figure 9, PDM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Added Footnotes 2 and 4 to Table 7, I2S Timing . . . . . . . . . . . . . 14
Clarification to System ESD Rating in Table 9, A2B System
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Rev. D
| Page 2 of 38
Clarified captions for Figure 15, Figure 16, Figure 18, and
Figure 19 in PDM Typical Performance Characteristics . . . .18
Clarifications to Parameter and Conditions columns in Table
11, PDM Interface Performance Specifications . . . . . . . . . . . . . . .19
Clarification to System ESD Rating CON1-A and CON1-B
Terminals in Table 12, Absolute Maximum Ratings . . . . . . . . .20
Clarifications to Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . .20
Clarified captions for Figure 21, Figure 22, Figure 25, and
Figure 26 in Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Corrected graph line symbols for Figure 21 in
Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Clarified captions for Figure 30, Figure 31, Figure 32, and
Figure 33 in Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Changes to Table 15,
AD2420/AD2426/AD2427/AD2428/AD2429 Pin Function
Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
| May 2022
AD2420/AD2426/AD2427/AD2428/AD2429
GENERAL DESCRIPTION
The Automotive Audio Bus (A2B®) provides a multichannel,
I2S/TDM link over distances of up to 15 m between nodes. It
embeds bidirectional synchronous pulse-code modulation
(PCM) data (for example, digital audio), clock, and synchronization signals onto a single differential wire pair. A2B supports a
direct point to point connection and allows multiple, daisychained nodes at different locations to contribute and/or consume time division multiplexed (TDM) channel content.
A2B data stream, which allows direct access of registers and status information on subordinate transceivers, as well as I2C to
I2C communication over distance.
The transceiver can connect directly to general-purpose digital
signal processors (DSPs), field-programmable gate arrays
(FPGAs), application specific integrated circuits (ASICs),
microphones, analog-to-digital converters (ADCs), digital-toanalog converters (DACs), and codecs through a multichannel
I2S/TDM interface. It also provides a pulse density modulation
(PDM) interface for direct connection of up to four PDM digital
microphones.
A2B is a single main node, multiple subordinate node system
where the transceiver at the host controller is the main node.
The main node generates clock, synchronization, and framing
for all subordinate nodes. The main A2B transceiver is programmable over a control port (I2C) for configuration and read back.
An extension of the control port protocol is embedded in the
Finally, the transceiver also supports an A2B bus powering feature, where the main node supplies voltage and current to the
subordinate nodes over the same daisy-chained, twisted pair
wire cable as used for the communication link.
Table 1. Product Comparison Guide
Feature
Main node capable
Number of subordinate nodes discoverable1
Functional TRX blocks
I2S/TDM support
PDM microphone inputs
Max node to node cable length
1
2
AD2420
No
N/A
A only
No
2 mics2
5m
AD2426
No
N/A
A only
No
4 mics
15 m
AD2427
No
N/A
A+B
No
4 mics
15 m
N/A means not applicable.
PDM microphones must be connected to the DRX0/IO5 pin.
Rev. D
| Page 3 of 38
| May 2022
AD2428
Yes
Up to 10
A+B
Yes
4 mics
15 m
AD2429
Yes
Up to 2
B only
Yes
4 mics
5m
AD2420/AD2426/AD2427/AD2428/AD2429
A2B BUS DETAILS
Figure 2 shows a single main node, multiple subordinate node
A2B communications system with the main transceiver controlled by the host. The host generates a periodic
synchronization signal on the I2S/TDM interface at a fixed frequency (typically 48 kHz) to which all A2B nodes synchronize.
Communications along the A2B bus occur in periodic superframes. The superframe frequency is the same as the
synchronization signal frequency, and data is transferred at a bit
rate that is 1024 times faster (typically 49.152 MHz). Each
superframe is divided into periods of downstream transmission,
upstream transmission, and no transmission (where the bus is
not driven). Data is exchanged over the A2B bus in up to 32
equal width slots for both upstream and downstream
transmissions.
The A2B bus also communicates the following control and
status information between nodes:
• I2C to I2C communication
• General-purpose input/output (GPIO)
• Interrupts
I2S/TDM
HOST
DSP
A2B
I2S/TDM
• Data transmitted by the main node transceiver in Superframe M creates Downstream Data M.
• Data transmitted by the subordinate node transceivers in
Superframe N creates Upstream Data N.
I2C
SUBORDINATE
A2B
TRANSCEIVER
• Data received over the I2S/TDM interface by the A2B transceiver is transmitted over the A2B bus in the next
superframe.
I2S/TDM
I2C
• Data on the A2B bus is transmitted over the I2S/TDM interface of an A2B transceiver in the next superframe.
A2B
SUBORDINATE
A2B
TRANSCEIVER
All nodes in an A2B system are sampled synchronously in the
same A2B superframe. Synchronous I2S/TDM downstream data
from the main node arrives at all subordinate nodes in the same
A2B superframe, and the upstream audio data of every node
arrives synchronously in the same I2S/TDM frame at the main
node. The remaining audio phase differences between subordinate nodes can be compensated for by register-programmable
fine adjustment of the SYNC pin signal delay.
Note in Figure 4, both downstream and upstream samples are
named for the frame where they enter the A2B system as follows:
A2B
SUBORDINATE
A2B
TRANSCEIVER
The embedded control and response frames allow the host to
individually address each subordinate transceiver in the system.
The host also enables access to remote peripheral devices that
are connected to the subordinate transceivers via the I2C port
for I2C to I2C communication over distance between multiple
nodes.
There is a sample delay incurred for data moving between the
A2B bus and the I2S/TDM interfaces because data is received
and transmitted over the I2S/TDM every sample period (typically 48 kHz). This timing relationship between samples over
the A2B bus is shown in Figure 4.
MAIN
A2B
TRANSCEIVER
I2C
Downstream, TDM synchronous data is added directly after the
control frame. Every subordinate node can consume some of
the downstream data and add data for downstream nodes. The
last subordinate node transceiver responds after the response
time with a synchronization response frame (SRF). Upstream
synchronous data is added by each node directly after the
response frame. Each node can also consume and/or contribute
upstream data.
• Data transmitted across the A2B bus (main to subordinate
or subordinate to main) has two frames of latency plus any
internal delay that has accumulated in the transceivers as
well as delays due to wire length. Therefore, overall latency
is slightly over two samples (0
ms
tPORST
Minimum Time Required for VVIN to be Held Below VRST to Assert Power on Reset 25
ms
VDVDD
| VIOVDD
tPORST
tVIN
VVIN
MIN VRST
MAX VRSTN
Figure 14. Power-Up Sequencing Timing with Externally Supplied VDVDD and VIOVDD
Rev. D | Page 16 of 38 | May 2022
AD2420/AD2426/AD2427/AD2428/AD2429
A2B BUS SYSTEM SPECIFICATION
Table 9. A2B System Specifications
Parameter
Cable
Maximum Cable Length
AD2428 Main Transceiver System
AD2429 Main Transceiver System
Maximum Number of Nodes
AD2428 Main Transceiver System
AD2429 Main Transceiver System
Maximum Number of Audio Slots
AD2426/AD2427/AD24281
AD2420/AD24291
Number of Audio Channels per
Subordinate Node
Synchronous A2B Data Slot Size
Audio Sampling Frequency
Discovery Time
System Specification
Unshielded, single, twisted pair wire (UTP) with 100 Ω differential impedance. EMC performance
and full functionality under worst-case environmental conditions is confirmed with Leoni Dacar
545 cable (76D00305).
40 m total, 15 m between nodes.
10 m total, 5 m between nodes.
11 nodes (1 main node and 10 subordinate nodes).
Three nodes (1 main node and 2 subordinate nodes).
64 total, up to 32 upstream and 32 downstream slots, depending upon system design.
AD2429: 4 upstream and 2 downstream slots, depending upon system design.
AD2420: 2 upstream slots, depending upon system design.
Individually programmable 0 to 32 upstream channels and 0 to 32 downstream channels.
8, 12, 16, 20, 24, 28, or 32 bits to match I2S/TDM data-word lengths. Same slot size for all nodes.
Upstream and downstream can choose different slot sizes. 12-, 16-, or 20-bit slot sizes can carry
compressed data over the A2B bus for 16-, 20-, or 24-bit I2S/TDM word lengths.
44.1 kHz to 48 kHz. All nodes sample synchronously. Subordinate node transceivers support sample
rates (fS) of 1× (48 kHz), 2× (96 kHz) or 4× (192 kHz), individually configured per subordinate.
To support 2× and 4× sampling rates in subordinates, the main transceiver uses two and four times
the number of I2S/TDM data channels as the 1× sampling frequency (fSYNCM) interface to the host.
Transceivers also support reduced rate sampling for 24 kHz, 12 kHz, 6 kHz, 4 kHz, 3 kHz, 2.4 kHz,
2 kHz, 1.71 kHz, or 1.5 kHz at a low latency 48 kHz superframe rate.
Less than 35 ms per node. Much less than 350 ms for total system startup in a system with 10 nodes.
Includes register initialization.
60 mA. Measured at the negative bias switch.
Maximum Bus Current per Node
Prior to Discovery Completion (IBUSDISC)
Maximum Total Bus Capacitance (CBUSDISC) 70 μF. Capacitance measured between the N and P pins in the CON1-B connector terminal.
Bit Error Detection
Robust error detection for control data and status data with 16-bit cyclic redundancy check (CRC).
Error Correction
Parity and line code error detection on synchronous data slots with audio error correction (repeat
of last known good data).
For 24-bit and 32-bit data channels, single error correction and double error detection (SECDED) of
synchronous data slots is possible.
1
Line Fault Diagnostics
Location and cause of cable fault can be detected for A2B wires shorted to a high voltage (for
example, positive terminal of car battery), shorted to ground (for example, car chassis), wires
shorted to each other, wires reversed or open connection.
System EMI/EMC
Meets or exceeds industry specifications for robustness (ISO 11452-2, ISO 11452-4, ISO 7637-3) and
emissions (CISPR25).
System ESD Rating
Meets ISO 10605 severity levels.
1
See the AD2420/6/7/8/9 Automotive Audio Bus (A2B) Transceiver Technical Reference for more information.
Rev. D | Page 17 of 38 | May 2022
AD2420/AD2426/AD2427/AD2428/AD2429
RMS Time Interval Error (TIE) Jitter
Table 10. SYNC Output RMS TIE Jitter at Each Subordinate
Node
Typ
1.57
1.79
1.91
2.04
2.15
2.27
2.44
2.47
2.58
2.70
Max
5.50
0
–0.1
–0.2
–0.3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–0.4
–0.5
0.0001
0.001
0.01
0.1
1
NORMALIZED FREQUENCY (RELATIVE TO fSYNCM) (Hz)
Figure 16. PDM Frequency Response, fSYNCM = 48 kHz
160
140
120
PDM TYPICAL PERFORMANCE CHARACTERISTICS
Figure 15 through Figure 19 and Table 11 describe typical PDM
performance characteristics.
GROUP DELAY (μs)
Subordinate Node
1
2
3
4
5
6
7
8
9
10
0.1
LEVEL (dBFS)
Clocks in an A2B system are passed from the main node to
Subordinate Node 0, from Subordinate Node 0 to Subordinate
Node 1, and so on. Each transceiver adds self jitter to the incoming jitter, which results in jitter growth from the main node to
the nth subordinate node. Table 10 illustrates typical rms TIE
jitter growth.
100
80
60
20
0
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 17. PDM Group Delay vs. Frequency, fSYNCM = 48 kHz
0
CH1
CH2
–20
–40
20
100
1k
FREQUENCY (Hz)
10k
Figure 15. PDM FFT, fSYNCM = 48 kHz, –60 dBFS Input
20k
THD + N (dBFS)
LEVEL (dBFS)
40
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
–190
–60
–80
–100
–120
–140
0.0001
0.001
0.01
0.1
NORMALIZED FREQUENCY (RELATIVE TO fSYNCM) (Hz)
Figure 18. PDM Total Harmonic Distortion + Noise (THD + N)
vs. Normalized Frequency (Relative to fSYNCM), fSYNCM = 48 kHz
Rev. D | Page 18 of 38 | May 2022
1
AD2420/AD2426/AD2427/AD2428/AD2429
0
–20
MAGNITUDE (dB)
–40
–60
–80
–100
–120
–140
–160
0
0.5
1.0
FREQUENCY (MHz)
1.5
Figure 19. PDM Out of Band Frequency Response (fSYNCM = 48 kHz)
Table 11. PDM Interface Performance Specifications
Parameter
Dynamic Range with A-Weighted Filter
SNR with A-Weighted Filter
Decimation Ratio
Frequency Response
Stop Band
Attenuation
Group Delay
Gain
Start-Up Time1
Bit Width
1
Conditions
20 Hz to 20 kHz, –60 dBFS input
20 Hz to 20 kHz
Default is 64×
DC to 0.45 fSYNCM
Min
64×
–0.1
Typ
120
120
128×
0.566
74
0.02 fSYNCM input signal
PDM to PCM
Internal and output
3.80
0
48
24
Max
256×
+0.01
Unit
dB
dB
dB
fSYNCM
dB
fSYNCM cycles
dB
fSYNCM cycles
Bits
The PDM start-up time is the time for the filters to settle after the PDM block is enabled. It is the time to wait before data is guaranteed to meet the specified performance.
Rev. D | Page 19 of 38 | May 2022
AD2420/AD2426/AD2427/AD2428/AD2429
ABSOLUTE MAXIMUM RATINGS
Stresses at or above those listed in Table 12 can cause permanent damage to the product. This is a stress rating only;
functional operation of the product at these or any other conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum
operating conditions for extended periods may affect product
reliability.
Parameter
Rating
VIN to VSS
–0.7 V to +30 V
Power Supply IOVDD to VSS
–0.3 V to +3.63 V
Power Supply DVDD to VSS
–0.3 V to +1.98 V
Power Supply PLLVDD to VSS
–0.3 V to +1.98 V
Digital Pin Output Voltage Swing
Input Voltage
–0.3 V to +3.63 V
1
–0.3 V to VIOVDD + 0.5 V
2, 3
–0.33 V to +3.63 V
Input Voltage2, 4
2
I C Input Voltage
–0.33 V to +2.10 V
2, 5
–0.33 V to +5.5 V
2
A B Bus Terminal Voltage
AP, AN, BP, and BN Pins
–0.5 V to +4.1 V
SENSE, SWP, VSSN Voltage to VSS
+30 V maximum
Storage Temperature Range
–65°C to +150°C
Junction Temperature While Biased
–40°C to +125°C
ESD Rating HBM
VIN and SWP Pins
±2.5 kV
AP, AN, BP, and BN Pins
±2.5 kV
All Other Pins
±2.5 kV
All Pins
The JESD51 package thermal characteristics in this section are
provided for package comparison and estimation purposes only.
They are not intended for accurate system temperature calculation. System thermal simulation is required for accurate
temperature analysis that accounts for all specific 3D system
design features, including, but not limited to other heat sources,
use of heat sinks, and the system enclosure. Contact Analog
Devices for package thermal models that are intended for use
with thermal simulation tools.
To determine the junction temperature on the application
printed circuit board (PCB), use the following equations:
TJ = TCASE + ΨJT × PD
where:
TJ = junction temperature (°C).
TCASE = case temperature (°C) measured by customer at top center of package.
ΨJT = values in Table 14.
PD = power dissipation.
±1.25 kV
where TA = ambient temperature (°C).
Digital Pin Output Current per Pin Group 15 mA
Applies to BCLK, SYNC, DTX0/IO3, DTX1/DRX1/IO4, DRX0/IO5, DRX1/IO6,
IRQ/IO0, ADR1/IO1, ADR2/IO2, PDMCLK/IO7.
Only applies when the related power supply (VIOVDD) is within specification. When
the power supply is below specification, the range is the voltage being applied to
that power domain ± 0.2 V.
3
Applies when nominal VIOVDD is 3.3 V.
4
Applies when nominal VIOVDD is 1.8 V.
5
Applies to SCL and SDA.
6
CON1-A and CON1-B are connectors.
7
For more information, see the following description and Table 13.
2
THERMAL CHARACTERISTICS
Refer to System ESD
Rating in Table 9.
7
1
Pins in Group
IRQ/IO0, ADR1/IO1, ADR2/IO2
BCLK, SYNC, DTX0/IO3, DTX1/DRX1/IO4, DRX0/IO5,
DRX1/IO6, PMDCLK/IO7
Values of JA are provided for package comparison and PCB
design considerations. Use JA for a first-order approximation
of TJ by the following equation:
ESD Rating FICDM
System ESD Rating CON1-A and CON1-B
Terminals6
Table 13. Total Current Pin Groups
Group
1
2
Table 12. Absolute Maximum Ratings
Power Supply TRXVDD to VSS
Permanent damage can occur if the digital pin output current
per pin group value is exceeded. For example, if three pins from
Group 2 in Table 13 are sourcing or sinking 2 mA each, the total
current for those pins is 6 mA. Up to 9 mA can be sourced or
sunk by the remaining pins in the group without damaging the
device.
TJ = TA + JA × PD
Values of JC are provided for package comparison and PCB
design considerations when an external heat sink is required.
Values of JB are provided for package comparison and PCB
design considerations.
Thermal characteristics of the LFCSP_SS package are shown in
Table 14. See JESD51-13 for detailed parameter definitions.
The junction to board measurement complies with JESD51-8.
The junction to case measurement complies with MIL-STD-883
(Method 1012.1). All measurements use a 2S2P JEDEC test
board.
Rev. D | Page 20 of 38 | May 2022
AD2420/AD2426/AD2427/AD2428/AD2429
Table 14. Thermal Characteristics
8
Conditions
Airflow = 0 m/s
Airflow = 1 m/s
Airflow = 2 m/s
Airflow = 0 m/s
Airflow = 0 m/s
Airflow = 0 m/s
Airflow = 1 m/s
Airflow = 2 m/s
Typical (°C/W)
31.6
28.8
28.1
4.6
14.7
0.20
0.27
0.30
IOVDD = 1.9V @ – 40°C
6
SOURCE CURRENT (mA)
Parameter
JA
JMA
JMA
JC
JB
JT
JT
JT
IOVDD = 1.8V @ 25°C
IOVDD = 1.7V @ 125°C
4
VOH
2
0
– 2.0
– 4.0
VOL
– 6.0
– 8.0
0
The 32-lead LFCSP_SS package requires thermal trace squares
and thermal vias to an embedded ground plane in the PCB. The
exposed paddle must connect to ground for proper operation to
data sheet specifications. Refer to JEDEC standard JESD51-5 for
more information.
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2.0
SOURCE VOLTAGE (V)
Figure 21. Digital I/O Drivers (DS0, 1.8 V IOVDD)
30
IOVDD = 3.6V @ – 40°C
ESD CAUTION
IOVDD = 3.3V @ 25°C
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
SOURCE CURRENT (mA)
20
IOVDD = 3.0V @ 125°C
10
VOH
0
– 10
VOL
– 20
TEST CIRCUITS AND SWITCHING
CHARACTERISTICS
– 30
0
Figure 20 shows a line driver voltage measurement circuit of the
differential line driver and receiver AP/AN and BP/BN pins.
0.5
1.5
1.0
2.5
2.0
3.5
3.0
4.0
SOURCE VOLTAGE (V)
Figure 22. Digital I/O Drivers (DS0, 3.3 V IOVDD)
0
AP/BP
IOVDD = 1.9V @ – 40°C
ȍ
AN/BN
Figure 20. Differential Line Driver Voltage Measurement
OUTPUT DRIVE CURRENTS
Figure 21 through Figure 26 show typical current voltage characteristics for the output drivers of the transceiver. The curves
represent the current drive capability of the output drivers as a
function of output voltage. Drive Strength 0 is DS0, Drive
Strength 1 is DS1, controlled via the PINCFG register.
SOURCE CURRENT (mA)
VOD
– 0.5
IOVDD = 1.8V @ 25°C
– 1.0
IOVDD = 1.7V @ 125°C
– 1.5
– 2.0
– 2.5
– 3.0
– 3.5
VOL
– 4.0
– 4.5
– 5.0
0
Note the following:
0.2
0.4
0.6
0.8
1
1.2
1.4
SOURCE VOLTAGE (V)
Figure 23. I2C Drivers (1.8 V IOVDD)
• I2C pins only support high drive strength (DS1).
• Digital I/Os include BCLK, SYNC, IRQ/IO0, ADR1/IO1,
ADR2/IO2, DTX0/IO3, DTX1/IO4, DRX0/IO5,
DRX1/IO6, PDMCLK/IO7 pins.
Rev. D | Page 21 of 38 | May 2022
1.6
1.8
2.0
AD2420/AD2426/AD2427/AD2428/AD2429
TEST CONDITIONS
0
IOVDD = 3.6V @ – 40°C
–2
IOVDD = 3.0V @ 125°C
–4
SOURCE CURRENT (mA)
All timing parameters in this data sheet were measured under
the conditions described in this section. Figure 27 shows the
measurement point for ac measurements (except output
enable/disable). The measurement point, VMEAS, is VIOVDD/2 for
VIOVDD (nominal) = 3.3 V.
IOVDD = 3.3V @ 25°C
–6
–8
– 10
– 12
VOL
– 14
INPUT
OR
OUTPUT
– 16
VMEAS
VMEAS
– 18
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
SOURCE VOLTAGE (V)
Figure 27. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable)
Figure 24. I2C Drivers (3.3 V IOVDD)
Output Enable Time Measurement
15
Output pins are considered enabled when they make a transition from a high impedance state to the point when they start
driving.
IOVDD = 1.9V @ – 40°C
IOVDD = 1.8V @ 25°C
SOURCE CURRENT (mA)
10
IOVDD = 1.7V @ 125°C
VOH
5
0
–5
The output enable time, tENA, is the interval from the point when
a reference signal reaches a high or low voltage level to the point
when the output starts driving, as shown on the right side of
Figure 28. If multiple pins are enabled, the measurement value
is that of the first pin to start driving.
VOL
– 10
– 15
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2.0
REFERENCE
SIGNAL
SOURCE VOLTAGE (V)
Figure 25. Digital I/O Drivers (DS1, 1.8 V IOVDD)
tDIS
tENA
60
IOVDD = 3.6V @ – 40°C
IOVDD = 3.3V @ 25°C
SOURCE CURRENT (mA)
40
IOVDD = 3.0V @ 125°C
20
VOH
0
OUTPUT STOPS DRIVING
– 20
OUTPUT STARTS DRIVING
HIGH IMPEDANCE STATE
VOL
Figure 28. Output Enable/Disable
–40
Output Disable Time Measurement
– 60
0
0.5
1.0
1.5
2.0
2.5
3.0
SOURCE VOLTAGE (V)
Figure 26. Digital I/O Drivers (DS1, 3.3 V IOVDD)
3.5
4.0
Output pins are considered disabled when they stop driving,
enter a high impedance state, and start to decay from the output
high or low voltage. The output disable time, tDIS, is the interval
from when a reference signal reaches a high or low voltage level
to the point when the output stops driving, as shown on the left
side of Figure 28.
Rev. D | Page 22 of 38 | May 2022
AD2420/AD2426/AD2427/AD2428/AD2429
Capacitive Loading
9
TESTER PIN ELECTRONICS
8
RISE AND FALL TIMES (ns)
Output delays and holds are based on standard capacitive loads
of an average of 6 pF on all pins (see Figure 29). VLOAD is equal
to VIOVDD/2. Figure 30 through Figure 33 show how output rise
time varies with capacitance. The delay and hold specifications
given must be derated by a factor derived from these figures.
The graphs in Figure 30 through Figure 33 cannot be linear outside the ranges shown.
7
6
tRISE
5
tFALL
4
3
2
50:
VLOAD
1
T1
DUT
OUTPUT
45:
DRIVE STRENGTH = 1
0
70:
0
5
10
15
20
25
30
35
40
45
LOAD CAPACITANCE (pF)
ZO = 50:(impedance)
TD = 4.04 r 1.18 ns
50:
Figure 31. Digital I/O Driver Typical Rise and Fall Times (10% to 90%)
vs. Load Capacitance (VIOVDD = 1.8 V, TJ = 25°C)
0.5pF
4pF
2pF
400:
10
9
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, THE SYSTEM CAN INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
Figure 29. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
8
RISE AND FALL TIMES (ns)
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
7
6
tRISE
5
tFALL
4
3
2
1
DRIVE STRENGTH = 0
0
18
10
0
20
30
40
50
60
LOAD CAPACITANCE (pF)
Figure 32. Digital I/O Driver Typical Rise and Fall Times (10% to 90%)
vs. Load Capacitance (VIOVDD = 3.3 V, TJ = 25°C)
14
12
tRISE
10
8
8
tFALL
7
6
4
2
DRIVE STRENGTH = 0
0
0
5
10
15
20
25
30
35
40
45
LOAD CAPACITANCE (pF)
Figure 30. Digital I/O Driver Typical Rise and Fall Times (10% to 90%)
vs. Load Capacitance (VIOVDD = 1.8 V, TJ = 25°C)
RISE AND FALL TIMES (ns)
RISE AND FALL TIMES (ns)
16
6
5
tRISE
4
tFALL
3
2
1
DRIVE STRENGTH = 1
0
0
10
20
30
40
50
60
70
80
90
LOAD CAPACITANCE (pF)
Figure 33. Digital I/O Driver Typical Rise and Fall Times (10% to 90%)
vs. Load Capacitance (VIOVDD = 3.3 V, TJ = 25°C)
Rev. D | Page 23 of 38 | May 2022
AD2420/AD2426/AD2427/AD2428/AD2429
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PLLVDD
DVDD
DVDD
SCL
SDA
IRQ/IO0
ADR1/IO1
ADR2/IO2
1
2
3
4
5
6
7
8
All digital inputs and digital outputs are three-stated with inputs
disabled during reset.
VSS
VIN
VOUT2
SENSE
SWP
VSSN
VSS
VOUT1
The 32-lead LFCSP_SS package pin configuration is shown in
Figure 34. The pin function descriptions are shown in Table 15.
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
EPAD
(PIN 33)
TOP VIEW
17
BCM
BN
BP
BTRXVDD
ATRXVDD
AP
AN
ACM
PDMCLK/IO7
DTX1/IO4
DRX0/IO5
DRX1/IO6
IOVDD
BCLK
SYNC
DTX0/IO3
9 10 11 12 13 14 15 16
PIN 33 IS THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE. THIS PIN MUST BE CONNECTED TO GND.
Figure 34. 32-Lead LFCSP_SS and LFCSP Package Pin Configuration
Table 15. AD2420/AD2426/AD2427/AD2428/AD2429 Pin Function Descriptions
Pin
No.
1
2, 3
42
Pin Name
PLLVDD
DVDD
SCL
Type
PWR
PWR
D_IO
Alternate
Functions1
None
None
None
Description
Power Supply for PLL. PLLVDD can be supplied by VVOUT1.
Power Supply for Digital Core Logic. DVDD can be supplied by VVOUT1.
Serial Clock for I2C Data Transfers. Clock input in an A2B main node. Clock input (I2C target) or
open-drain output (I2C controller) in an A2B subordinate node. This pin uses open-drain I/O cells
and must be pulled up to VI2C_VBUS through a resistor (consult Version 2.1 of the I2C bus specification for the proper resistor value). Connect the pin to ground when the I2C interface is not used.
SDA
D_IO
None
I2C Mode Serial Data. This pin is a bidirectional open-drain input/output and must be pulled up
52
to VI2C_VBUS through a resistor (consult Version 2.1 of the I2C bus specification for the proper
resistor value). Connect the pin to ground if the I2C interface is not used.
62
IRQ/IO0
D_IO
None
Interrupt Request Output. In the main transceiver, event driven interrupt requests towards the
host controller are created.
In subordinate transceivers, this pin indicates mailbox empty/full status to the subordinate node
processor when mailbox interrupts are enabled.
When not serving as an interrupt output pin, this pin serves as a general-purpose I/O pin with
interrupt request input capability. The IRQ/IO0 pin must be initialized to become either an input
or an output. This pin is high impedance by default.
2
7
ADR1/IO1
D_IO
CLKOUT1 The ADR1/IO1 and ADR2/IO2 pins set the I2C target device address during power-on reset; up
to four A2B devices connect to the same I2C bus. The ADR1/IO1 pin is high impedance by default.
The ADR1/IO1 pin can then be initialized to become a general-purpose input/output (GPIO) pin
with interrupt request capability.
This pin can be programmed to become a clock output (CLKOUT1). The clock output can be used
as a main clock for connected ADCs and DACs or to synchronize switching voltage regulators.
In this table, the Type is defined as follows: PWR = power/ground, A_IN = analog input, D_OUT = digital output, A_IO = analog input/output,
D_IO = digital input/output, N/A = not applicable.
Rev. D | Page 24 of 38 | May 2022
AD2420/AD2426/AD2427/AD2428/AD2429
Table 15. AD2420/AD2426/AD2427/AD2428/AD2429 Pin Function Descriptions (Continued)
Pin
No. Pin Name
82
ADR2/IO2
Alternate
Functions1 Description
CLKOUT2 The ADR1/IO1 and ADR2/IO2 pins set the I2C target device address during power-on reset; up
to four A2B devices connect to the same I2C bus. The ADR2/IO2 pin is high impedance by default.
The ADR2/IO2 pin can then be initialized to become a general-purpose input/output (GPIO) pin
with interrupt request capability.
This pin can be programmed to become a clock output (CLKOUT2). The clock output can be used
as a main clock for connected ADCs and DACs or to synchronize switching voltage regulators.
9
IOVDD
PWR
None
Power Supply for Digital Input and Output Pins. The digital output pins are supplied from IOVDD,
which also sets the highest input voltage that is allowed on the digital input pins. Two I/O voltage
ranges are supported (see VIOVDD specifications in the Operating Conditions section). The current
draw of these pins is variable and depends on the loads of the digital outputs. IOVDD can be
powered by either the VOUT1 or VOUT2 internal regulators or by an external supply.
10
BCLK
D_IO
PDMCLK
Bit Clock. Digital input in the main transceiver. Digital output in the subordinate transceiver.
When using the PDM interface in subordinate transceivers, this pin can operate as the clock
output (PDMCLK) for PDM microphones (the PDMCLK/IO7 pin can also be used).
11
SYNC
D_IO
None
Synchronization Signal. Digital input in the main transceiver. Digital output in the subordinate
transceiver.
For the AD2428 and AD2429, the SYNC signal frames a multichannel I2S/TDM data stream.
An A2B main transceiver must have a continuous signal because the A2B main transceiver derives
all clocking information for itself and for the A2B bus from this input.
When this pin stops toggling, the A2B bus resets after a delay. For more information, see Table 3.
2
12
DTX0/IO3
D_IO
None
For the AD2428 and AD2429, serial I2S/TDM data is driven to the DTX0/IO3 pin in multichannel
I2S/TDM format.
This pin serves as the IO3 general-purpose I/O pin when DTX0 function is disabled. The DTX0/IO3
pin is high impedance by default until configured. The pin returns to high impedance when the
chip resets due to a missing synchronization signal or low supply voltage.
For the AD2420, AD2426, and AD2427, this pin is GPIO only (IO3).
132 DTX1/IO4
D_IO
DRX1
For the AD2428 and AD2429, serial I2S/TDM data is driven to the DTX1/IO4 pin in multichannel
I2S/TDM format.
When configured as the alternate DRX1 function, the DTX1/IO4 pin receives data presented in
multichannel I2S/TDM format. This alternate location can be used when the DRX0/IO5 and
DRX1/IO6 pins are used to receive PDM microphone data.
This pin serves as the IO4 general-purpose I/O pin when DTX1 and DRX1 functions are disabled.
The DTX1/IO4 pin is high impedance by default until configured. The pin returns to high
impedance when the chip resets due to a missing synchronization signal or low supply voltage.
For the AD2420, AD2426, and AD2427, this pin is GPIO only (IO4).
142 DRX0/IO5
D_IO
PDM0
For the AD2428 and AD2429, serial I2S/TDM data is received on the DRX0/IO5 pin in multichannel
I2S/TDM format. This pin is an input for microphone data when enabled as a PDM input (PDM0).
This pin serves as the IO5 GPIO pin when DRX0 and PDM0 functions are disabled. The DRX0/IO5
pin is high impedance by default until configured. The pin returns to high impedance when the
chip resets due to a missing synchronization signal or low supply voltage.
For the AD2420, AD2426, and AD2427, the DRX0 function is not supported.
In this table, the Type is defined as follows: PWR = power/ground, A_IN = analog input, D_OUT = digital output, A_IO = analog input/output,
D_IO = digital input/output, N/A = not applicable.
Type
D_IO
Rev. D | Page 25 of 38 | May 2022
AD2420/AD2426/AD2427/AD2428/AD2429
Table 15. AD2420/AD2426/AD2427/AD2428/AD2429 Pin Function Descriptions (Continued)
Pin
No. Pin Name
152 DRX1/IO6
Alternate
Functions1 Description
PDM1
For the AD2428 and AD2429, serial I2S/TDM data is received on the DRX1/IO6 pin in multichannel
I2S/TDM format. This pin is an input for microphone data when enabled as a PDM input (PDM1).
This pin serves as the IO6 GPIO pin when DRX1 and PDM1 functions are disabled. The DRX1/IO6
pin is high impedance by default until configured. The pin returns to high impedance when the
chip resets due to a missing synchronization signal or low supply voltage.
For the AD2420, AD2426, and AD2427, the DRX1 function is not supported.
2
PDMCLK/IO7 D_IO
RRSTRB
PDM Microphone Clock Output.
16
In main mode, the PDM clock output (PDMCLK) is used to clock PDM microphones. This pin runs
at 64× the SYNC frequency regardless of the BCLK rate used by the host.
When using the PDM interface in subordinate mode, this pin can still operate as the clock output
for PDM microphones (PDMCLK), but BCLK can also be used.
When PDM functions are disabled, this pin serves as the IO7 GPIO pin. The PDMCLK/IO7 pin can
also be used as a strobe to indicate when reduced rate data is updated (RRSTRB). The
PDMCLK/IO7 pin is high impedance by default until configured. The pin returns to high
impedance when the chip resets due to a missing synchronization signal or low supply voltage.
17
ACM
A_IN
None
Common-Mode Input for Bidirectional, Differential A2B Line Transceiver A.
18
AN
A_IO
None
Inverted Pin of Bidirectional, Differential A2B Line Driver and Receiver A. Pin 18 is directed
towards the main transceiver. Pin 18 is self biased.
19
AP
A_IO
None
Noninverted Pin of Bidirectional, Differential A2B Line Driver and Receiver A. Pin 19 is directed
towards the main transceiver. Pin 19 is self biased.
20
ATRXVDD
PWR
None
Power Supply for A2B Line Driver and Receiver Circuit. The pins can be supplied by VOUT2.
21
BTRXVDD
PWR
None
Power Supply for A2B Line Driver and Receiver Circuit. The pins can be supplied by VOUT2.
22
BP
A_IO
None
For the AD2427, AD2428, and AD2429, this is the noninverted pin of bidirectional, differential
A2B line driver and Receiver B, which is directed towards the last subordinate. This pin is self
biased.
23
BN
A_IO
None
For the AD2427, AD2428, and AD2429, this is the inverted pin of bidirectional, differential A2B
line driver and Receiver B, which is directed towards the last subordinate. This pin is self biased.
24
BCM
A_IN
None
For the AD2427, AD2428, and AD2429, this is the common-mode input for bidirectional, differential A2B Line Transceiver B.
25
VSS
PWR
None
Power Supply Pin for Return Currents. Connect the VSS pin to a low impedance local VSS ground
plane.
26
VSSN
PWR
None
For the AD2427, AD2428, and AD2429, this is the power supply return current connection for
the next subordinate device. Connect to the inductor that provides the negative bias for the
next subordinate device. The AD2427, AD2428, and AD2429 connect VSSN to the local VSS
potential to sequence power to the next subordinate devices in the chain. VSSN automatically
disconnects under critical fault conditions.
27
SWP
D_OUT None
For the AD2427, AD2428, and AD2429, this is the active low open-drain output to drive the gate
of a PMOS switch. The switch is open (SWP pin is high) by default. The switch can be closed (SWP
pin goes low) to sequence power to the next subordinate devices in the chain. The switch
automatically opens (SWP goes high) under critical fault conditions.
28
SENSE
A_IN
None
Analog input to sense the power supplied to the next subordinate device. For the AD2420,
AD2426, or a last in line AD2427/AD2428/AD2429, connect this pin to local ground through a
33 kΩ pull-down resistor.
29
VOUT2
PWR
None
Second Output of the On-Chip low Dropout Voltage Regulator. The voltage output on this pin
provides a regulated supply to the TRXVDD supply pins. External devices also can be powered
by this supply if the current consumption is within the specification. Decouple VOUT2 to VSS
with a 4.7 μF capacitor.
In this table, the Type is defined as follows: PWR = power/ground, A_IN = analog input, D_OUT = digital output, A_IO = analog input/output,
D_IO = digital input/output, N/A = not applicable.
Type
D_IO
Rev. D | Page 26 of 38 | May 2022
AD2420/AD2426/AD2427/AD2428/AD2429
Table 15. AD2420/AD2426/AD2427/AD2428/AD2429 Pin Function Descriptions (Continued)
Pin
No. Pin Name
30
VIN
Alternate
Functions1 Description
None
Power supply pin that accepts a wide input voltage range (see the VVIN specification in the
Operating Conditions section) for an on-chip low dropout voltage regulator.
31
VSS
PWR
None
Power Supply Pin for Return Currents. Connect the VSS pin to a low impedance local VSS ground
plane.
32
VOUT1
PWR
None
First Output of the On-Chip Low Dropout Voltage Regulator. The voltage output on this pin
provides a regulated supply to the DVDD and PLLVDD power supply pins. External devices can
be powered by this supply if the current consumption is within the specification. Decouple
VOUT1 to VSS with a 4.7 μF capacitor.
33
EPAD
PWR
None
Power Supply Pin for Return Currents. See other VSS pin description in this table. This pin is the
exposed pad on the bottom of the package and must be connected to GND.
In this table, the Type is defined as follows: PWR = power/ground, A_IN = analog input, D_OUT = digital output, A_IO = analog input/output,
D_IO = digital input/output, N/A = not applicable.
1
2
Type
PWR
See the AD2420/6/7/8/9 Automotive Audio Bus A2B Transceiver Technical Reference for more information about configuring pins for alternate functions.
If the listed functions for this pin are not required, do not connect this pin.
Rev. D | Page 27 of 38 | May 2022
AD2420/AD2426/AD2427/AD2428/AD2429
POWER ANALYSIS
This section provides information on power consumption of the
A2B system. The intent of power dissipation calculations is to
assist board designers in estimating power requirements for
power supply and thermal relief designs.
Constant Current
Power dissipation on an A2B node depends on various factors,
such as the required external peripheral supply current and bus
activity. An A2B system can be comprised of a mix of bus powered subordinates and local powered subordinates. A bus
powered subordinate derives power from the A2B bus wires. A
local powered subordinate derives power from separate power
wires. Power estimation for a bus powered system is more complex when compared to a local powered system. For power
analysis, A2B systems with both local and bus powered subordinates must be divided into segments of nodes that draw from
the same power supply.
PLL Supply Current
All currents that are not influenced directly by A2B bus activity
on other nodes fall under the category of constant current.
The PLL supply current is specified as IPLLVDD, which is the static
current in an active transceiver.
VIN Quiescent Current
The VIN quiescent current is specified as the static current
IVINQ. It is independent of the load and does not include any
power drawn from the voltage regulator output pins.
IOVDD Current
The on-chip I2S/TDM/PDM I/O current IIOVDD is based on
dynamic switching currents on the BCLK, SYNC, DTX0, DTX1,
DRX0, and DRX1 pins.
CURRENT FLOW
Figure 35 describe key parameters and equations to calculate
power dissipation on the transceiver. The current flow on an
A2B node incorporates the described current paths.
The dynamic current, due to switching activity on an output
pin, is calculated using the following equation:
Output Dynamic Current = (CPDout + CL) × VIOVDD × f
• Constant current
where:
CPDout = dynamic, transient power dissipation capacitance internal to the transceiver output pins.
CL = total load capacitance that an output pin sees outside the
transceiver.
VIOVDD = voltage on a digital pin.
f = frequency of switching on the pin.
• IPLLVDD — PLL supply current
• IVINQ — VIN quiescent current
• I2C I/O current
• IIOVDD — I2S/TDM/PDM I/O current
• IVEXT1 or IVEXT2 — peripheral supply currents
The dynamic current, due to switching activity on an input pin,
is calculated using the following equation:
• IDVDD — digital logic supply current
2
• ITRXVDD — A B bus TX/RX current
Input Dynamic Current = CPDin × VIOVDD × f
• LVDS transceiver supply currents of A and B transceivers — transmit LVDS TX and receive LVDS RX
where:
CPDin = dynamic, transient power-dissipation capacitance internal to the input pins of the transceiver.
IIOVDD = the sum of input and output dynamic currents of all
pins internally supplied by the IOVDD pin.
f = frequency of switching on the pin.
I2C activity and the resulting I/O current is considered negligible when compared to other currents. Therefore, the on-chip
I2C I/O current is not considered when calculating the current
consumption.
Peripheral
Device(s)
IVEXT2
IVEXT1
IIOVDD
IVIN
IDVDD
IPLLVDD
I VEXT2 + I VEXT1
IOVDD
DVDD
IVOUT1
PLLVDD
VOUT1
IATRXVDD
IVOUT2
1.9V
VIN
VOUT2
ATRXVDD BTRXVDD
VREG1/2
IVINQ
A2B TRANSCEIVER
VSS
IBTRXVDD
3.3V
IVSSN
Figure 35. Current Flow Model
Rev. D | Page 28 of 38 | May 2022
VSSN
AD2420/AD2426/AD2427/AD2428/AD2429
Peripheral Supply Current
Peripheral components that are external to the transceiver also
can be supplied through the voltage regulator outputs of VVOUT1
and VVOUT2. VVOUT1 can supply the current specified as IVEXT1 to
external devices. VVOUT2 can supply the current specified as
IVEXT2 to external devices.
When bus powered, peripheral supply current draw has a direct
impact on other nodes in the system. It is important to stay
within the thermal package limits and not exceed the specification limits of IVSSN and VVIN in any of the A2B bus nodes.
Digital Logic Supply Current
• The number of upstream data bits transmitted in a node =
number of upstream transmitted slots × (bits per slot +
parity bit) where the parity bit = 1. The number of
upstream transmitted slots is the sum of received upstream
slots and locally contributed slots.
• A side upstream transmitter activity level of a node.
(SRF bits + number of transmitted upstream data bits) ÷
1024.
LVDS Transmitter and Receiver Idle Current
The idle current, ITRXVDD_IDLE, depends on ITXVDD and IRXVDD at
0% activity level and A2B bus idle time.
The digital logic supply current IDVDD is a combination of static
current consumption and digital TX/RX current.
• B transceiver idle current. B Transceiver IBTRXVDD_IDLE
LVDS current results from B transceiver idle time.
A2B Bus TX/RX Current
• A transceiver idle current. A Transceiver IATRXVDD_IDLE
LVDS current results from A transceiver idle time.
The level of A2B bus activity directly influences current consumption on both the LVDS transceivers related to A2B
transmitter and receiver processing.
LVDS Transmitter and Receiver Supply Currents
The current ITRXVDD depends on ITXVDD and IRXVDD at 100% activity level and A2B bus activity:
• Downstream LVDS transceiver current
• B transceiver IBTXVDD LVDS TX current results from
downstream TX activity level of the current node.
• A transceiver IARXVDD LVDS RX current results from
downstream activity level of the previous node.
• Upstream LVDS transceiver current
• A transceiver IATXVDD LVDS TX current results from
A side upstream activity level of the current node.
• B transceiver IBRXVDD LVDS RX current results from
upstream activity level of the next in line node.
Downstream/Upstream Activity Level
The activity level for downstream data of TRX B is determined
by the following:
• B transceiver idle time. B transceiver idle time is the time
when both the TX and RX of the B transceiver are idle.
The idle time of the B transceiver is derived by eliminating
the following activity levels from the B transceiver frame
cycle:
• B transceiver downstream activity level of the current
node.
• A transceiver upstream activity level of the next in line
node.
• A transceiver idle time is the time when both the TX and
RX of the A transceiver are idle.
The idle time of the A transceiver is derived by eliminating
the following activity from the A transceiver frame cycle:
• A transceiver upstream activity level of the current
node.
• B transceiver downstream activity level of previous
node.
The sum of the LVDS transceiver currents is
ITRXVDD = IBRXVDD + IBTXVDD + IARXVDD + IATXVDD +
IBTRXVDD_IDLE + IATRXVDD_IDLE
• Header bits for downstream. A2B systems use 64 downstream header bits referred to as a synchronization control
frame (SCF).
VREG1 AND VREG2 OUTPUT CURRENTS
• The number of downstream data bits transmitted in
a node = the number of downstream transmitted slots ×
(bits per slot + parity bit) where the parity bit = 1. The
number of downstream transmitted slots does not include
the locally consumed slots.
IVOUT2 is the current from VVOUT2 which is the sum of the LVDS
transmitter and receiver supply currents, peripheral supply currents, and I/O current.
• B side downstream transmitter activity level of a node.
(SCF bits + number of downstream transmitted data bits) ÷
1024.
The activity level for upstream data of TRX A is determined by
the following:
• Header bits for upstream. (SRF bits + total number of
received downstream data bits) ÷ 1024.
Voltage regulator output currents are governed by the following
equations:
IVOUT2 = ITRXVDD + IIOVDD+ IVEXT2
IVOUT1 is the current from the VOUT1 pin which is the sum of PLL
supply current, IPLLVDD, digital logic supply current IDVDD,
peripheral supply current, IVEXT1, and I2S/TDM/PDM I/O current IIOVDD.
IVOUT1 = IPLLVDD + IVEXT1 + IDVDD + IIOVDD
IIOVDD in a subordinate node can be sourced by either IVOUT1 or
IVOUT2 but not both, depending on whether IIOVDD is supplied
from VVOUT1 or VVOUT2.
Rev. D | Page 29 of 38 | May 2022
AD2420/AD2426/AD2427/AD2428/AD2429
CURRENT AT VIN (IVIN)
IVEXT2 = peripheral supply current from VVOUT2.
VVOUT1 = output voltage from VREG1.
VVOUT2 = output voltage from VREG2.
The current at the VIN pin (IVIN) of the transceiver is the sum of
currents IVOUT1 and IVOUT2 and the quiescent current, shown in
Figure 35 and in the following equation:
RESISTANCE BETWEEN NODES
IVIN = IVOUT1 + IVOUT2 + IVINQ
Figure 36 shows the dc model of a system with a combination of
local and bus powered A2B subordinates.
The A side node current is the line bias current from an earlier
node. In a bus powered node, it is also the power supply current
and a portion of this current supplies the next in line nodes.
A voltage drop of the dc bias is observed between the A2B nodes,
due to resistance and current consumption. Table 16 lists the
causes of the dc resistance between nodes (RBETWEEN) with example resistance values.
IA = IVIN + IB + IVREGPERI
where:
IB = B side current to the next node (= IVSSN return current and
IA of the next in line node).
IVREGPERI = peripheral current supplied from IA by extra voltage
regulator, external to the transceiver (not illustrated in Figure 36
and Figure 37).
Both bias supply and return currents are subject to resistance.
Therefore, some resistance values must be doubled (for example, wire length resistance).
Table 16. Breakdown/Budget of Typical DC Resistance
Between Nodes
POWER DISSIPATION
Resistance
Inductor DC Resistance
Short Circuit Protection Resistor
Positive Bias PMOS Switch
On-Resistance
Negative Bias Switch
On-Resistance RVSSN
Resistance of Connections
Total RSUM
Wire Length Resistance of Cable
The power dissipation of the transceiver is calculated using the
following equation:
Power =
IVIN × VVIN + (IVSSN)2 × RVSSN – IVEXT1 × VVOUT1 – IVEXT2 × VVOUT2
where:
IVIN = current at VIN pin.
VVIN = voltage at VIN pin.
IVSSN = B side current IB to the next node and return current
from the next node. The next node is the node connected to the
B terminal of the current node. See Figure 36.
RVSSN = internal VSSN on resistance (see Table 16).
IVEXT1 = peripheral supply current from VVOUT1.
Main Node
1
Unit
Ω
Ω
Ω
1.2
1
1.2
Ω
0.04
2.39
0.242
Ω
Ω
Ω/m
0.01 4
N/A1 N/A1
0.121 2
N/A means not applicable.
BUS POWER
Subordinate Node 0
Subordinate Node n
Cable
FB
Connections
IB
IA
VNODEM
VNODE0
FB
PMOS
Cable
FB
FB
VNODEn
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