AD260AND-4

a FEATURES IsoLogic™ Circuit Architecture Isolation Test Voltage: To 3.5 kV rms Five Isolated Logic Lines: Available in Six I/O Configurations Logic Signal Bandwidth: 20 MHz (Min), 40 mbps (NRZ) Isolated Power Transformer: 37 V p-p, 1.5 W Max CMV Transient Immunity: 10 kV/␮s Min Waveform Edge Transmission Symmetry: ⴞ1 ns Field and System Output Enable/Three-State Functions Performance Rated Over –25ⴗC to +85ⴗC UL1950, IEC950, EN60950 Certification, Pending High Speed, Logic Isolator with Power Transformer AD260 FUNCTIONAL BLOCK DIAGRAM AD260 LATCH F0 18 TTR IIS STTA ATTE E LINE 0 TR IST AT E LINE 1 TR IST AT E LINE 2 GENERAL DESCRIPTION The AD260 is designed using Analog Devices new IsoLogic circuit architecture to isolate five digital control signals to/ from a microcontroller and its related field I/O components. Six models allow all I/O combinations from five input lines to five output lines, including combinations in between. Every AD260 effectively replaces up to five opto-isolators while also providing the 1.5 W transformer for a 3.5 kV isolated dc-dc power supply circuit. Each line of the AD260 has a bandwidth of 20 MHz (min) with a propagation delay of only 14 ns, which allows for extremely fast data transmission. Output waveform symmetry is maintained to within ± 1 ns of the input so the AD260 can be used to accurately isolate time-based PWM signals. All field or system output pins of the AD260 can be set to a high resistance three-state level by use of the two enable pins. A field output three-stated offers a convenient method of presetting logic levels at power-up by use of pull-up/down resistors. System side outputs being three-stated allows for easy multiplexing of multiple AD260s. The isolation barrier of the AD260 B Grade is 100% tested at 3.5 kV rms (system to field). The barrier design also provides excellent common-mode transient immunity from 10 kV/µs common-mode voltage excursions of field side terminals relative to the system side, with no false output triggering on either side. Each output is updated within nanoseconds by input logic transitions, the AD260 also has a continuous output update feature that automatically updates each output based on the dc level of IsoLogic is a trademark of Analog Devices, Inc. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 1 S0 2 S1 3 S2 E LATCH F1 19 D E LATCH F2 20 D E LATCH F3 21 D LINE 3 E AT IST TR 4 S3 LINE 4 E AT IST TR 5 S4 6 ENABLESYS 7 +5VdcSYS 8 5V RTNSYS 9 DRVA 10 DRVCT 11 DRVB E APPLICATIONS PLC/DCS Analog Input and Output Cards Communications Bus Isolation General Data Acquisition Applications IGBT Motor Drive Controls High Speed Digital I/O Ports D LATCH F4 22 D E ENABLEFLD 17 +5VdcFLD 16 5V RTNFLD 15 PWRAFLD 14 PWRCTFLD 13 PWRBFLD 12 +5Vdc 5Vdc RTN 17V p-p OUT +5Vdc 5Vdc RTN DRIVE +5V CT OUT 17V p-p OUT FIELD DRIVE SYSTEM the input. This guarantees the output is always valid 10 µs after a fault condition or after the power-up reset interval. The AD260 also has an integral center tap transformer for generating isolated power. Typically driven by a 5 V push-pull drive at the primary, it will generate a 37 V p-p output capable of supplying up to 1.5 W. This can then be regulated to the desired voltage, including ± 5 V dc for circuit components and 24 V for a 20 mA loop supply when needed. PRODUCT HIGHLIGHTS Six Isolated Logic Line I/O Configurations Available: The AD260 is available in six pin-compatible versions of I/O configurations to meet a wide variety of requirements. Wide Bandwidth with Minimal Edge Error: The AD260 with IsoLogic affords extremely fast isolation of logic signals due to its 20 MHz bandwidth and 14 ns propagation delay. It maintains a waveform input-to-output edge transition error of typically less than ± 1 ns (total) for positive vs. negative transition. 3.5 kV rms Test Voltage Isolation Rating: The AD260 B Grade is rated to operate at 1.25 kV rms and is 100% production tested at 3.5 kV rms, using a standard ADI test method. High Transient Immunity: The AD260 rejects commonmode transients slewing at up to 10 kV/µs without false triggering or damage to the device. (Continued on page 6) One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 AD260–SPECIFICATIONS (Typical at T = +25ⴗC, +5 V dc A Parameter INPUT CHARACTERISTICS Threshold Voltage Positive Transition (VT+) Negative Transition (VT–) Hysteresis Voltage (VH) Input Capacitance (CIN) Input Bias Current (IIN) SYS, +5 V dcFLD, tRR = 50 ns max unless otherwise noted) Conditions Min Typ Max Units +5 V dcSYS = 4.5 V +5 V dcSYS = 5.5 V +5 V dcSYS = 4.5 V +5 V dcSYS = 5.5 V +5 V dcSYS = 4.5 V +5 V dcSYS = 5.5 V 2.0 3.0 0.9 1.2 0.4 0.5 2.7 3.2 1.8 2.2 0.9 1.0 5 0.5 3.15 4.2 2.2 3.0 1.4 1.5 V V V V V V pF µA Per Input OUTPUT CHARACTERISTICS Output Voltage1 High Level (VOH) Low Level (VOL) Output Three-State Leakage Current +5 V dcSYS = 4.5 V, |IO| = 0.02 mA +5 V dcSYS = 4.5 V, |IO| = 4 mA +5 V dcSYS = 4.5 V, |IO| = 0.02 mA +5 V dcSYS = 4.5 V, |IO| = 4 mA ENABLESYS/FLD @ Logic Low/High Level Respectively 4.4 3.7 50% Duty Cycle, +5 V dcSYS = 5 V tPHL vs. tPLH 20 0.1 0.4 0.5 V V V V µA 1 DYNAMIC RESPONSE (Refer to Figure 2) Max Logic Signal Frequency (fMIN) Waveform Edge Symmetry Error (tERROR) Logic Edge Propagation Delay (tPHL, tPLH) Minimum Pulsewidth (tPWMIN) Max Output Update Delay on Fault or After Power-Up Reset Interval (≈ 30 µs)2 ±1 14 25 25 MHz ns ns ns µs 12 3 ISOLATION BARRIER RATING Operating Isolation Voltage (VCMV) Isolation Rating Test Voltage (VCMV TEST)4 Transient Immunity (VTRANSIENT) Isolation Mode Capacitance (CISO) Capacitive Leakage Current (ILEAD) POWER TRANSFORMER Primary Winding Inductance (LP) Number of Turns (NP) Resistance Max Volt-Seconds (E × t) Recommended Operating Frequency Absolute Min Operating Frequency Secondary Winding Number of Turns (NS) Resistance Insulation Withstand (VCMV TEST) Capacitance Recommended Max Power POWER SUPPLY Supply Voltage (+5 V dcSYS and +5 V dcFLD) Power Dissipation Capacitance Quiescent Supply Current Supply Current AD260A AD260B AD260A AD260B 375 1250 1750 3500 10,000 Total Capacitance, All Lines and Transformer 240 V rms @ 60 Hz Bifilar Wound, Center-Tapped Each Half Each Half Each Half Each Half –25°C to +85°C, Push-Pull Drive –25°C to +85°C, Push-Pull Drive Bifilar Wound, Center-Tapped Each Half Each Half Primary to Secondary Primary to Secondary Rated Performance Rated Performance Operating Effective, per Input, Either Side Effective per Output, Either Side—No Load Each, +5 V dcSYS & FLD All Lines @ 10 MHz (Sum of +5 V dcSYS & FLD) TEMPERATURE RANGE Rated Performance (TA)5 Storage (TSTG) 14 18 2 1 26 0.6 150 75 200 27 300 48 2.3 3,500 5 V rms V rms V rms V rms V/µs pF µA rms mH Turns Ω V × µs kHz kHz Turns Ω V rms pF W 1.0 1.5 4.5 4.0 5.5 5.75 V dc V dc pF pF mA mA +85 +85 °C °C 8 28 4 18 –25 –40 NOTES 1 For best performance, bypass +5 V dc supplies to com. at or near the device (0.01 µF). +5 V dc supplies are also internally bypassed with 0.05 µF. 2 As the supply voltage is applied to either side of the AD260, the internal circuitry will go into a power-up reset mode (all lines disabled) for about 30 µs after the point where +5 V dcSYS & FLD passes above 3.3 V. 3 “Operating” isolation voltage is derived from the Isolation Test Voltage in accordance with such methods as found in VDE-0883 wherein a device will be “hi-pot” tested at twice the operating voltage, plus one thousand volts. Partial discharge testing, with an acceptance threshold of 80 pC of discharge may be considered the same as a hi-pot test (but nondestructive). 4 Partial Discharge at 80 pC THLD. 5 Supply Current will increase slightly, but otherwise the unit will function within specification to – 40°C. Specifications are subject to change without notice. –2– REV. 0 AD260 ABSOLUTE MAXIMUM RATINGS* Parameter Conditions Supply Voltage (+5 V dcSYS & FLD) DC Input Voltage (VIN MAX) DC Output Voltage (V OUT MAX) Clamp Diode Input Current (I IK) Clamp Diode Output Current (I OK) Output DC Current, per Pin (I OUT) DC Current, VCC or GND (ICC or IGND) Storage Temperature (T STG) Lead Temperature (Soldering, 10 sec) Electrostatic Protection (V ESD) Min Typ –0.5 –0.5 –0.5 –25 –25 –25 –50 –40 Referred to +5 V dcSYS & FLD and 5 V RTNSYS & FLD Respectively Referred to +5 V RTNSYS & FLD and 5 V dcSYS & FLD Respectively For VI < –0.5 V or VI > 5 V RTNSYS & FLD +0.5 V For VO < –0.5 V or VO > 5 V RTNSYS & FLD +0.5 V Per MIL-STD-883, Method 3015 4.5 Max Units +6.0 +0.5 +0.5 +25 +25 +25 +50 +85 +300 V V V mA mA mA mA °C °C kV 5 *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. I/O CONFIGURATIONS AVAILABLE PIN CONFIGURATION The AD260 is available in several configurations. The choice of model is determined by the desired number of input vs. output lines. All models have identical footprints with the power and enable pins always being in the same locations. 1 2 PIN FUNCTION DESCRIPTIONS SYSTEM 3 4 5 6 7 Pin Mnemonic 1–5* 6 7 8 9–14 15 16 17 18–22* S0 Through S4 ENABLESYS +5 V dcSYS 5 V RTNSYS 8 9 10 Function Digital Xmt or Rcv from F0 Through F4 System Output Enable/Three-State System Power Supply (+5 V dc Input) System Power Supply Common Not Present On Unit 5 V RTNFLD Field Power Supply Common Field Power Supply (+5 V Input) +5 V dcFLD Field Output Enable/Three-State ENABLEFLD F0 Through F4 Digital Xmt or Rcv from S0 Through S4 11 S0 S1 S2 S3 S4 ENABLESYS +5VdcSYS 5V RTNSYS DRVA DRVCT DRVB BOTTOM VIEW PWRBFLD PWRCTFLD PWRAFLD 5V RTNFLD +5VdcFLD ENABLEFLD F0 F1 F2 F3 F4 *Function of pin determined by model. Refer to Table I. Caution: Use care in handling unit as contaminants on the bottom side of the unit or the circuit card to which it is mounted will lead to reduced breakdown voltage across the isolation barrier. 12 13 14 15 16 17 18 FIELD 19 20 21 22 ORDERING GUIDE Model Number Description Isolation Test Voltage Package Description Package Option AD260AND-0 AD260AND-1 AD260AND-2 AD260AND-3 AD260AND-4 AD260AND-5 0 Inputs, 5 Outputs 1 Input, 4 Outputs 2 Inputs, 3 Outputs 3 Inputs, 2 Outputs 4 Inputs, 1 Output 5 Inputs, 0 Outputs 1.75 kV rms 1.75 kV rms 1.75 kV rms 1.75 kV rms 1.75 kV rms 1.75 kV rms Plastic DIP Plastic DIP Plastic DIP Plastic DIP Plastic DIP Plastic DIP ND-22 ND-22 ND-22 ND-22 ND-22 ND-22 AD260BND-0 AD260BND-1 AD260BND-2 AD260BND-3 AD260BND-4 AD260BND-5 0 Inputs, 5 Outputs 1 Input, 4 Outputs 2 Inputs, 3 Outputs 3 Inputs, 2 Outputs 4 Inputs, 1 Output 5 Inputs, 0 Outputs 3.5 kV rms 3.5 kV rms 3.5 kV rms 3.5 kV rms 3.5 kV rms 3.5 kV rms Plastic DIP Plastic DIP Plastic DIP Plastic DIP Plastic DIP Plastic DIP ND-22 ND-22 ND-22 ND-22 ND-22 ND-22 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD260 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –3– WARNING! ESD SENSITIVE DEVICE AD260 PIN CONFIGURATIONS AD260BND-2 AD260BND-0 AD260-0 F0 18 AD260-2 LATCH TTR RIIS STA ATTE E LINE 0 – OUT TR IST AT E LINE 1 – OUT TR IST AT E LINE 2 – OUT TR IST AT E LINE 3 – OUT TR IST AT E LINE 4 – OUT 1 D F0 18 S0 E LATCH TTRR IIS STA ATTE E LINE 0 – OUT TR IST AT E LINE 1 – OUT TR IST AT E LINE 2 – OUT S1 F1 19 E 3 D S2 F2 20 E D 4 F3 21 S3 D 5 5V RTNFLD 15 PWRAFLD 14 PWRCTFLD 13 PWRBFLD 12 F4 22 S4 D +5Vdc 5Vdc RTN 5Vdc RTN DRIVE 17V p-p OUT +5V CT OUT DRIVE 17V p-p OUT FIELD 6 ENABLESYS 7 +5VdcSYS 8 9 +5VdcFLD 16 5V RTNFLD 15 5V RTNSYS PWRAFLD 14 DRVA PWRCTFLD 13 10 DRVCT PWRBFLD 12 11 DRVB SYSTEM AD260-1 LINE 0 – OUT TR IST AT E LINE 1 – OUT TR IST AT E LINE 2 – OUT TR IST AT E LINE 3 – OUT E AT IST TR 4 S3 LINE 4 – IN E AT IST TR 5 S4 6 ENABLESYS 7 +5VdcSYS 8 5V RTNSYS 9 DRVA +5Vdc +5Vdc 5Vdc RTN 5Vdc RTN 17V p-p OUT DRIVE +5V CT OUT 17V p-p OUT DRIVE FIELD AD260-3 1 D F0 18 S0 E LINE 0 – OUT TR IST AT E LINE 1 – OUT F1 19 S1 E D E S2 F2 20 D 5V RTNFLD 15 PWRAFLD 14 PWRCTFLD 13 PWRBFLD 12 +5Vdc 5Vdc RTN 17V p-p OUT FIELD 1 S0 D 2 S1 E LINE 2 – IN E AT IST TR 3 S2 LINE 3 – IN E AT IST TR 4 S3 LINE 4 – IN E AT IST TR 5 S4 6 ENABLESYS 7 +5VdcSYS 8 5V RTNSYS 9 DRVA LATCH 4 D F3 21 S3 D E E LATCH LINE 4 – IN 5 E AT IST TR F4 22 S4 D E +5Vdc 5Vdc RTN DRIVE +5V CT OUT 17V p-p OUT D E E E ENABLEFLD 17 +5VdcFLD 16 DRVB LATCH 3 D LATCH F4 22 11 LATCH 2 D LATCH F3 21 DRVCT LATCH TTR RIIS STA ATTE E LATCH F2 20 10 SYSTEM LATCH F1 19 S2 AD260BND-3 LATCH TTR RIIS STA ATTE E 3 LINE 3 – IN ENABLEFLD 17 AD260BND-1 F0 18 LATCH D E E E +5Vdc S1 LATCH D ENABLEFLD 17 +5VdcFLD 16 2 E E E LATCH F4 22 D LATCH LATCH F3 21 S0 LATCH 2 D LATCH F2 20 1 E LATCH F1 19 D DRIVE 6 ENABLESYS 7 +5VdcSYS 8 9 10 11 ENABLEFLD 17 +5VdcFLD 16 5V RTNFLD 15 5V RTNSYS PWRAFLD 14 DRVA PWRCTFLD 13 DRVCT PWRBFLD 12 DRVB SYSTEM –4– +5Vdc 5Vdc RTN 17V p-p OUT +5Vdc 5Vdc RTN DRIVE +5V CT OUT 17V p-p OUT FIELD DRIVE 10 DRVCT 11 DRVB SYSTEM REV. 0 AD260 PIN CONFIGURATIONS AD260BND-4 AD260-4 F0 18 TTRR IIS STA ATTE E AD260BND-5 AD260-5 LATCH LINE 0 – OUT 1 D S0 F0 18 D E AT IST TR 2 E AT IST TR 3 E AT IST TR 4 E AT IST TR 5 S1 F1 19 D S2 F2 20 D S3 F3 21 D E 5V RTNFLD 15 PWRAFLD 14 PWRCTFLD 13 PWRBFLD 12 +5Vdc LINE 2 – IN E AT IST TR 3 S2 LINE 3 – IN E AT IST TR 4 S3 5Vdc RTN DRIVE 17V p-p OUT +5V CT OUT DRIVE 17V p-p OUT S4 F4 22 D LINE 4 – IN E AT IST TR 5 S4 6 ENABLESYS 7 +5VdcSYS 8 5V RTNSYS 9 DRVA 10 DRVCT 11 DRVB E +5Vdc 5Vdc RTN FIELD S1 LATCH LINE 4 – IN ENABLEFLD 17 +5VdcFLD 16 2 E LATCH D E AT IST TR LATCH LINE 3 – IN E F4 22 LINE 1 – IN E LATCH D S0 LATCH LINE 2 – IN E F3 21 1 E LATCH D E AT IST TR LATCH LINE 1 – IN E F2 20 LINE 0 – IN E E LATCH F1 19 LATCH D 6 ENABLESYS 7 +5VdcSYS 8 5V RTNSYS 9 DRVA ENABLEFLD 17 +5Vdc +5VdcFLD 16 5Vdc RTN 5V RTNFLD 15 PWRAFLD 14 10 DRVCT PWRCTFLD 13 11 DRVB PWRBFLD 12 SYSTEM +5Vdc 5Vdc RTN 17V p-p OUT DRIVE +5V CT OUT 17V p-p OUT DRIVE FIELD SYSTEM Table I. Pin AD260BND-0 AD260BND-1 AD260BND-2 AD260BND-3 AD260BND-4 AD260BND-5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 S0 (Xmt) S1 (Xmt) S2 (Xmt) S3 (Xmt) S4 (Xmt) ENABLESYS +5 V dcSYS 5 V RTNSYS DRVA DRVCT DRVB PWRBFLD PWRCTFLD PWRAFLD 5 V RTNFLD +5 V dcFLD ENABLEFLD F0 (Rcv) F1 (Rcv) F2 (Rcv) F3 (Rcv) F4 (Rcv) S0 (Xmt) S1 (Xmt) S2 (Xmt) S3 (Xmt) S4 (Rcv) * * * * * * * * * * * * F0 (Rcv) F1 (Rcv) F2 (Rcv) F3 (Rcv) F4 (Xmt) S0 (Xmt) S1 (Xmt) S2 (Xmt) S3 (Rcv) S4 (Rcv) * * * * * * * * * * * * F0 (Rcv) F1 (Rcv) F2 (Rcv) F3 (Xmt) F4 (Xmt) S0 (Xmt) S1 (Xmt) S2 (Rcv) S3 (Rcv) S4 (Rcv) * * * * * * * * * * * * F0 (Rcv) F1 (Rcv) F2 (Xmt) F3 (Xmt) F4 (Xmt) S0 (Xmt) S1 (Rcv) S2 (Rcv) S3 (Rcv) S4 (Rcv) * * * * * * * * * * * * F0 (Rcv) F1 (Xmt) F2 (Xmt) F3 (Xmt) F4 (Xmt) S0 (Rcv) S1 (Rcv) S2 (Rcv) S3 (Rcv) S4 (Rcv) * * * * * * * * * * * * F0 (Xmt) F1 (Xmt) F2 (Xmt) F3 (Xmt) F4 (Xmt) *Pin function is the same on all models, as shown in the AD260BND-0 column. REV. 0 –5– AD260 Edge “fidelity,” or the difference in propagation time for rising and falling edges, is typically less than ± 1 ns. (Continued from page 1) Integral Isolated Power: The AD260 includes an integral, uncommitted and flexible 1 Watt power transformer for developing isolated field power sources. Power consumption, unlike opto-isolators, is a function of operating frequency. Each logic line barrier driver requires about 160 µA per MHz and each receiver 40 µA per MHz plus, of course, 4 mA total idle current (each side). The supply current diminishes slightly with increasing temperature (about –0.03%/°C). Field and System Enable Functions: Both the isolated and nonisolated sides of the AD260 have ENABLE pins that threestate all outputs. Upon reenabling these pins, all outputs are updated to reflect the current input logic level. The total capacitance spanning the isolation barrier is less than 10 pF. CE Certifiable: Simply by adding the external bypass capacitors at the supply pins, the AD260 can attain CE certification in most applications (to the EMC directive) and conformance to the low voltage (safety) directive is assured by the EN60950 certification. The minimum width of a pulse that can be accurately coupled across the barrier is about 25 ns. Therefore the maximum square-wave frequency of operation is 20 MHz. Logic information is sent across the barrier as “set-hi/set-lo” data that is derived from logic level transitions of the input. At power-up or after a fault condition, an output might not represent the state of the respective channel input to the isolator. An internal circuit operates in the background which interrogates all inputs about every 5 µs and in the absence of logic transitions, sends appropriate “set-hi” or “set-lo” data across the barrier. GENERAL ATTRIBUTES The AD260 provides five HCMOS/ACMOS compatible isolated logic lines with ≥ 10 kV/µs common-mode transient immunity. The case design and pin arrangement provides greater than 18 mm spacing between field and system side conductors, providing CSA/IS and IEC creepage spacing consistent with 750 V mains isolation. Recovery time from a fault condition or at power-up is thus between 5 µs and 10 µs. The five unidirectional logic lines have six possible combinations of “ins” and “outs,” or transmitter/receiver pairs; hence there are six AD260 part configurations (see Table I). 3.5kV DATA ISOLATION DATA OUTPUT TRANSMITTER BARRIER RECEIVER BUFFER SCHMITT TRIGGER Each 20 MHz logic line has a Schmidt trigger input and a threestate output (on the other side of the isolation barrier) and 14 ns of propagation delay. A single enable pin on either side of the barrier causes all outputs on that side to go three-state and all inputs (driven pins) to ignore their inputs and retain their last known state. DATA IN D Q ENABLE G OUT ENABLE GATED TRANSPARENT LATCH CONTINUOUS UPDATE CIRCUIT Figure 1. Simplified Block Diagram Note: All unused logic inputs (1–5) should be tied either high or low, but not left floating. PROPAGATION DELAY POSITIVE GOING INPUT THRESHOLD INPUT +3V NEGATIVE GOING INPUT THRESHOLD +2V OUTPUT HYSTERESIS 63% 37% tPD tPD t ff tPHL tPLH EFFECTIVE CIRCUIT MODEL FOR ONE ISOLATED LOGIC LINE SCHMITT TRIGGER DELAY LINE BUFFER 12.5ns 5pF INPUT CAPACITANCE 100V tPD t rr = tff = 100V x CTOTAL OUTPUT CAPACITANCE 5pF OUTPUT CAPACITANCE >0.5ns – NO LOAD = 5.5ns INTO 50pF TOTAL DELAY = (tPLH OR tPHL) = tPD + (trr OR tff) >13ns (NO LOAD), 18ns (50pF LOAD) Figure 2. Typical Timing and Delay Models –6– REV. 0 AD260 The power transformer is designed to operate between 150␣ kHz and 250 kHz and will easily deliver more than 1 W of isolated power when driven push-pull (5 V) on the system side. Different transformer tap, rectifier and regulator schemes will provide combinations of ± 5 V, 15␣ V, 24␣ V or even 30 V or higher. The output voltage when driven with a low voltage-drop drive (@ 5 V push-pull) will be 37 V p-p across the entire secondary. This will drop to 33 V p-p at 4.5 V drive. Application Examples The following is an example of a typical transformer system-side drive circuit and a field-side regulation circuit suitable for use in most general applications. VDD FLD +5V REG +5V ISO 96T CT. ENABLE FLD (PWR-UP ENABLE) +5Vdc 4.7kV 9 15 16 COMP VIN VREF 12 11 52T CT INV NI LM2524 + – I 10 LOGIC/SHUTDOWN (H I ) 1 –5V REG –5V ISO 2 Figure 4. 0.1mF 3.3mF TANT. CL+ CL– 13 4 5 3.3kV RT 6 7 C 14 VOUT @ V(MIN) @ 5V DRIVE 4.5V DRIVE +5Vdc/+4.5Vdc 150mA + T 470pF GND 8 +8.55 7.62 a LOAD 80mA COM a +5Vdc 6 1 52T CT + – SD D1 4 SHUTDOWN (ON/OFF) MAX 253 3.3mF TANT. 8 617.63 FS 2 b – b +5Vdc/+4.5Vdc 150mA 20mA D2 G1 + 15.79 20mA 3 G2 COM 7 Figure 3. System Side Transformer Driver Examples + a – a +5Vdc/+4.5Vdc 150mA 40mA 40mA 68.64 7.72 COM a a + +26.3 23.5 +8.64 7.72 + 20mA +5Vdc/+4.5Vdc 150mA b a 20mA COM "a" DIODES "b" DIODES b IN5818/MBR0530 IN5819/MBR0540 Figure 5. Field Side Power Supply Rectifier Examples REV. 0 –7– AD260 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 0.550 (13.97) MAX 1.500 (38.1) MAX 0.440 (11.18) MAX SIDE VIEW 1 11 0.050 (1.27) 0.160 (4.06) 0.140 (3.56) C3031–8–9/98 22-Lead Plastic DIP (ND-22) 12 END VIEW 22 0.020 3 0.010 (0.508 3 0.254) 22 PLACES 0.100 (2.54) 0.350 (8.89) 0.075 (1.91) PIN 1 0.250 (6.35) BOTTOM VIEW SYSTEM 0.5* (12.2) FIELD 0.050 (1.27) 0.350 (8.89) PRINTED IN U.S.A. * CREEPAGE PATH (SUBTRACT APPROXIMATELY 0.079 (2mm) FOR SOLDER PAD RADII ON PC BOARD. THIS SPACING SUPPORTS THE INTRINSICALLY SAFE RATING OF 750V. WAVE SOLDERING IS NOT RECOMMENDED. –8– REV. 0