AD2S1205YSTZ

12-Bit RDC with Reference Oscillator AD2S1205 FEATURES FUNCTIONAL BLOCK DIAGRAM CRYSTAL REFERENCE PINS AD2S1205 REFERENCE OSCILLATOR (DAC) EXCITATION OUTPUTS VOLTAGE REFERENCE INTERNAL CLOCK GENERATOR SYNTHETIC REFERENCE INPUTS FROM RESOLVER ADC POSITION REGISTER ENCODER EMULATION OUTPUTS ENCODER EMULATION VELOCITY REGISTER MULTIPLEXER DATA BUS OUTPUT APPLICATIONS DATA I/O RESET Automotive motion sensing and control Hybrid-electric vehicles Electric power steering Integrated starter generator/alternator Industrial motor control Process control FAULT DETECTION OUTPUTS FAULT DETECTION TYPE II TRACKING LOOP ADC 06339-001 Complete monolithic resolver-to-digital converter (RDC) Parallel and serial 12-bit data ports System fault detection ±11 arc minutes of accuracy Input signal range: 3.15 V p-p ± 27% Absolute position and velocity outputs 1250 rps maximum tracking rate, 12-bit resolution Incremental encoder emulation (1024 pulses/rev) Programmable sinusoidal oscillator on board Single-supply operation (5.00 V ± 5%) −40°C to +125°C temperature rating 44-lead LQFP 4 kV ESD protection Qualified for automotive applications Figure 1. GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD2S1205 is a complete 12-bit resolution tracking resolver-to-digital converter that contains an on-board programmable sinusoidal oscillator providing sine wave excitation for resolvers. 1. The converter accepts 3.15 V p-p ± 27% input signals on the Sin and Cos inputs. A Type II tracking loop is employed to track the inputs and convert the input Sin and Cos information into a digital representation of the input angle and velocity. The maximum tracking rate is a function of the external clock frequency. The performance of the AD2S105 is specified across a frequency range of 8.192 MHz ± 25%, allowing a maximum tracking rate of 1250 rps. 2. 3. 4. 5. 6. Ratiometric Tracking Conversion. The Type II tracking loop provides continuous output position data without conversion delay. It also provides noise immunity and tolerance of harmonic distortion on the reference and input signals. System Fault Detection. A fault detection circuit can sense loss of resolver signals, out-of-range input signals, input signal mismatch, or loss of position tracking. Input Signal Range. The Sin and Cos inputs can accept differential input voltages of 3.15 V p-p ± 27%. Programmable Excitation Frequency. Excitation frequency is easily programmable to 10 kHz, 12 kHz, 15 kHz, or 20 kHz by using the frequency select pins (the FS1 and FS2 pins). Triple Format Position Data. Absolute 12-bit angular position data is accessed via either a 12-bit parallel port or a 3-wire serial interface. Incremental encoder emulation is in standard A-quad-B format with direction output available. Digital Velocity Output. 12-bit signed digital velocity accessed via either a 12-bit parallel port or a 3-wire serial interface. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved. AD2S1205 TABLE OF CONTENTS Features .............................................................................................. 1 False Null Condition .................................................................. 10 Applications ....................................................................................... 1 On-Board Programmable Sinusoidal Oscillator .................... 11 Functional Block Diagram .............................................................. 1 Synthetic Reference Generation ............................................... 11 General Description ......................................................................... 1 Charge-Pump Output ................................................................ 11 Product Highlights ........................................................................... 1 Connecting the Converter ........................................................ 11 Revision History ............................................................................... 2 Clock Requirements ................................................................... 12 Specifications..................................................................................... 3 Absolute Position and Velocity Output ................................... 12 Absolute Maximum Ratings............................................................ 5 Parallel Interface ......................................................................... 12 ESD Caution .................................................................................. 5 Serial Interface ............................................................................ 14 Pin Configuration and Function Descriptions ............................. 6 Incremental Encoder Outputs .................................................. 16 Resolver Format Signals................................................................... 8 Supply Sequencing and Reset ................................................... 16 Theory of Operation ........................................................................ 9 Circuit Dynamics ........................................................................... 17 Fault Detection Circuit ................................................................ 9 Loop Response Model ............................................................... 17 Monitor Signal .............................................................................. 9 Sources of Error .......................................................................... 18 Loss of Signal Detection .............................................................. 9 Connecting to the DSP .............................................................. 19 Signal Degradation Detection .................................................. 10 Outline Dimensions ....................................................................... 20 Loss of Position Tracking Detection ........................................ 10 Ordering Guide .......................................................................... 20 Responding to a Fault Condition ............................................. 10 Automotive Products ................................................................. 20 REVISION HISTORY 5/10—Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Changes to Input Bias Current Parameter and Input Impedance Parameter ...................................................................... 3 Changes to Table 2 ............................................................................ 5 Changes to Loss of Signal Detection Section ................................ 9 Changes to Connecting the Converter Section and Figure 5 ... 11 Change to t6 Max Value in Table 6 ............................................... 13 Changes to t9 and t10 Max Values Table 7 .................................... 15 Changes to Ordering Guide .......................................................... 20 Added Automotive Products Section .......................................... 20 1/07—Revision 0: Initial Version Rev. A | Page 2 of 20 AD2S1205 SPECIFICATIONS AVDD = DVDD = 5.0 V ± 5% at −40°C to +125°C, CLKIN = 8.192 MHz ± 25%, unless otherwise noted. Table 1. Parameter Sin, Cos INPUTS 1 Voltage Input Bias Current Input Impedance Common-Mode Voltage Phase-Lock Range ANGULAR ACCURACY Angular Accuracy Resolution Linearity INL Linearity DNL Repeatability Hysteresis VELOCITY OUTPUT Velocity Accuracy Resolution Linearity Offset Dynamic Ripple DYNAMIC PERFORMANCE Bandwidth Tracking Rate Min Typ Max Unit Conditions/Comments 2.3 3.15 4.0 V p-p 12 μA MΩ mV peak Degrees Sinusoidal waveforms, Sin − SinLO and Cos − CosLO, differential inputs VIN = 4.5 VDC, CLKIN = 10.24 MHz VIN = 4.5 VDC CMV with respect to REFOUT/2 at 10 kHz Sin/Cos vs. EXC output 0.35 ±11 ±22 12 2 0.3 1 1 2 11 1 0 1 1000 Acceleration Error Settling Time 179° Step Input EXC, EXC OUTPUTS Voltage Center Voltage Frequency EXC/EXC DC Mismatch THD FAULT DETECTION BLOCK Loss of Signal (LOS) Sin/Cos Threshold Angular Accuracy (Worst Case) 100 +44 −44 1 2400 750 1000 1250 30 5.2 4.0 3.34 2.39 3.6 2.47 10 12 15 20 3.83 2.52 35 −58 2.18 2.24 Arc minutes Arc minutes Bits LSB LSB LSB LSB Zero acceleration, Y grade Zero acceleration, W grade Guaranteed no missing codes Zero acceleration, 0 rps to 1250 rps, CLKIN = 10.24 MHz Guaranteed monotonic LSB Bits LSB LSB LSB Zero acceleration Guaranteed by design, 2 LSB maximum Zero acceleration Zero acceleration Hz rps rps rps Arc minutes ms ms CLKIN = 6.144 MHz , guaranteed by design CLKIN = 8.192 MHz , guaranteed by design CLKIN = 10.24 MHz , guaranteed by design At 10,000 rps, CLKIN = 8.192 MHz To within ±11 arc minutes, Y grade, CLKIN = 10.24 MHz To within 1 degree, Y grade, CLKIN = 10.24 MHz V p-p V kHz kHz kHz kHz mV dB 2.3 57 V p-p Degrees Angular Latency (Worst Case) 114 Degrees Time Latency 125 μs Rev. A | Page 3 of 20 Load ±100 μA FS1 = high, FS2 = high, CLKIN = 8.192 MHz FS1 = high, FS2 = low, CLKIN = 8.192 MHz FS1 = low, FS2 = high, CLKIN = 8.192 MHz FS1 = low, FS2 = low, CLKIN = 8.192 MHz First five harmonics DOS and LOT go low when Sin or Cos fall below threshold LOS indicated before angular output error exceeds limit (4.0 V p-p input signal and 2.18 V LOS threshold) Maximum electrical rotation before LOS is indicated (4.0 V p-p input signal and 2.18 V LOS threshold) AD2S1205 Parameter Degradation of Signal (DOS) Sin/Cos Threshold Angular Accuracy (Worst Case) Angular Latency (Worst Case) Time Latency Sin/Cos Mismatch Min Typ Max Unit Conditions/Comments 4.0 4.09 4.2 33 66 125 420 V p-p Degrees Degrees μs mV DOS goes low when Sin or Cos exceeds threshold DOS indicated before angular output error exceeds limit Maximum electrical rotation before DOS is indicated Degrees LOT goes low when internal error signal exceeds threshold; guaranteed by design 385 Loss of Tracking (LOT) Tracking Threshold Time Latency Hysteresis VOLTAGE REFERENCE REFOUT Drift PSRR CHARGE-PUMP OUTPUT (CPO) Frequency Duty Cycle POWER SUPPLY IDD Dynamic ELECTRICAL CHARACTERISTICS VIL, Voltage Input Low VIH, Voltage Input High VOL, Voltage Output Low VOH, Voltage Output High IIL, Low Level Input Current (Non-Pull-Up) IIL, Low Level Input Current (Pull-Up) IIH, High Level Input Current IOZH, High Level Three-State Leakage IOZL, Low Level Three-State Leakage 1 5 1.1 4 2.39 2.47 70 −60 2.52 204.8 50 ms Degrees ±IOUT = 100 μA kHz % Square wave output, CLKIN = 8.192 MHz mA 0.8 4.0 −10 +10 V V V V μA −80 −10 −10 −10 +80 +10 +10 +10 μA μA μA μA 0.4 Guaranteed by design V ppm/°C dB 20 2.0 DOS latched low when Sin/Cos amplitude mismatch exceeds threshold The voltages for Sin, SinLO, Cos, and CosLO relative to AGND must be between 0.2 V and AVDD. Rev. A | Page 4 of 20 +1 mA load −1 mA load SAMPLE, CS, RDVEL, CLKIN, SOE pins RD, FS1, FS2, RESET pins AD2S1205 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage (VDD) Supply Voltage (AVDD) Input Voltage Output Voltage Swing Input Current to Any Pin Except Supplies 1 Operating Temperature Range (Ambient) Storage Temperature Range 1 Rating −0.3 V to +7.0 V −0.3 V to +7.0 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V ±10 mA −40°C to +125°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Transient currents of up to 100 mA do not cause latch-up. Rev. A | Page 5 of 20 AD2S1205 REFBYP AGND Cos CosLO AVDD SinLO Sin AGND EXC EXC 44 43 42 41 40 39 38 37 36 35 34 DVDD 1 33 RESET RD 2 32 FS2 CS 3 31 FS1 SAMPLE 4 30 LOT DOS RDVEL 5 AD2S1205 29 SOE 6 TOP VIEW (Not to Scale) 28 DIR 27 NM 12 13 14 15 16 17 18 19 20 21 22 CLKIN DGND XTALOUT 23 DB0 CPO DB7 11 DB1 24 DB2 A DB8 10 DVDD B 25 DGND 26 9 DB3 8 DB9 DB4 DB10/SCLK DB5 7 DB6 DB11/SO 06339-002 REFOUT PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1, 17 Mnemonic DVDD 2 RD 3 4 CS SAMPLE 5 RDVEL 6 SOE 7 DB11/SO 8 DB10/SCLK 9 to 15 16, 23 DB9 to DB3 DGND 18 to 20 21 DB2 to DB0 XTALOUT 22 CLKIN 24 CPO 25 A Description Digital Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for all digital circuitry on the AD2S1205. The AVDD and DVDD voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Edge-Triggered Logic Input. This pin acts as a frame synchronization signal and output enable. The output buffer is enabled when CS and RD are held low. Chip Select. Active low logic input. The device is enabled when CS is held low. Sample Result. Logic input. Data is transferred from the position and velocity integrators to the position and velocity registers, respectively, after a high-to-low transition on the SAMPLE signal. Read Velocity. Logic input. RDVEL input is used to select between the angular position register and the angular velocity register. RDVEL is held high to select the angular position register and low to select the angular velocity register. Serial Output Enable. Logic input. This pin enables either the parallel or serial interface. The serial interface is selected by holding the SOE pin low, and the parallel interface is selected by holding the SOE pin high. Data Bit 11/Serial Data Output Bus. When the SOE pin is high, this pin acts as DB11, a three-state data output pin controlled by CS and RD. When the SOE pin is low, this pin acts as SO, the serial data output bus controlled by CS and RD. The bits are clocked out on the rising edge of SCLK. Data Bit 10/Serial Clock. In parallel mode this pin acts as DB10, a three-state data output pin controlled by CS and RD. In serial mode this pin acts as the serial clock input. Data Bit 9 to Data Bit 3. Three-state data output pins controlled by CS and RD. Digital Ground. These pins are ground reference points for digital circuitry on the AD2S1205. All digital input signals should be referred to this DGND voltage. Both of these pins can be connected to the AGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Data Bit 2 to Data Bit 0. Three-state data output pins controlled by CS and RD. Crystal Output. To achieve the specified dynamic performance, an external crystal is recommended at the CLKIN and XTALOUT pins. The position and velocity accuracy are guaranteed for a frequency range of 8.192 MHz ± 25%. Clock Input. To achieve the specified dynamic performance, an external crystal is recommended at the CLKIN and XTALOUT pins. The position and velocity accuracy are guaranteed for a frequency range of 8.192 MHz ± 25%. Charge-Pump Output. Analog output. A 204.8 kHz square wave output with a 50% duty cycle is available at the CPO output pin. This square wave output can be used for negative rail voltage generation or to create a VCC rail. Incremental Encoder Emulation Output A. Logic output. This output is free running and is valid if the resolver format input signals applied to the converter are valid. Rev. A | Page 6 of 20 AD2S1205 Pin No. 26 Mnemonic B 27 NM 28 DIR 29 DOS 30 LOT 31 32 33 FS1 FS2 RESET 34 EXC 35 EXC 36, 42 AGND 37 38 39 Sin SinLO AVDD 40 41 43 CosLO Cos REFBYP 44 REFOUT Description Incremental Encoder Emulation Output B. Logic output. This output is free running and is valid if the resolver format input signals applied to the converter are valid. North Marker Incremental Encoder Emulation Output. Logic output. This output is free running and is valid if the resolver format input signals applied to the converter are valid. Direction. Logic output. This output is used in conjunction with the incremental encoder emulation outputs. The DIR output indicates the direction of the input rotation and is high for increasing angular rotation. Degradation of Signal. Logic output. Degradation of signal (DOS) is detected when either resolver input (Sin or Cos) exceeds the specified DOS Sin/Cos threshold. See the Signal Degradation Detection section. DOS is indicated by a logic low on the DOS pin and is not latched when the input signals exceed the maximum input level. Loss of Tracking. Logic output. LOT is indicated by a logic low on the LOT pin and is not latched. See the Loss of Signal Detection section. Frequency Select 1. Logic input. FSI in conjunction with FS2 allows the frequency of EXC/EXC to be programmed. Frequency Select 2. Logic input. FS2 in conjunction with FS1 allows the frequency of EXC/EXC to be programmed. Reset. Logic input. The AD2S1205 requires an external reset signal to hold the RESET input low until VDD is within the specified operating range of 4.5 V to 5.5 V. See the Supply Sequencing and Reset section. Excitiation Frequency. Analog output. An on-board oscillator provides the sinusoidal excitation signal (EXC) and its complement signal (EXC) to the resolver. The frequency of this reference signal is programmable via the FS1 and FS2 pins. Excitation Frequency Complement. Analog output. An on-board oscillator provides the sinusoidal excitation signal (EXC) and its complement signal (EXC) to the resolver. The frequency of this reference signal is programmable via the FS1 and FS2 pins. Analog Ground. These pins are ground reference points for analog circuitry on the AD2S1205. All analog input signals and any external reference signal should be referred to this AGND voltage. Both of these pins should be connected to the AGND plane of a system. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Positive Analog Input of Differential Sin/SinLO Pair. The input range is 2.3 V p-p to 4.0 V p-p. Negative Analog Input of Differential Sin/SinLO Pair. The input range is 2.3 V p-p to 4.0 V p-p. Analog Supply Voltage, 4.75 V to 5.25 V. This pin is the supply voltage for all analog circuitry on the AD2S1205. The AVDD and DVDD voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Negative Analog Input of Differential Cos/CosLO Pair. Positive Analog Input of Differential Cos/CosLO Pair. Reference Bypass. Reference decoupling capacitors should be connected here. Typical recommended values are 10 μF and 0.01 μF. Voltage Reference Output, 2.39 V to 2.52 V. Rev. A | Page 7 of 20 AD2S1205 RESOLVER FORMAT SIGNALS Vr = Vp × Sin(ωt) Vr = Vp × Sin(ωt) R1 S2 S2 Va = Vs × Sin(ωt) × Cos(θ) θ R1 Va = Vs × Sin(ωt) × Cos(θ) θ S4 S4 R2 R2 S3 S1 Vb = Vs × Sin(ωt) × Sin(θ) S3 Vb = Vs × Sin(ωt) × Sin(θ) (A) CLASSICAL RESOLVER 06339-003 S1 (B) VARIABLE RELUCTANCE RESOLVER Figure 3. Classical Resolver vs. Variable Reluctance Resolver A classical resolver is a rotating transformer that typically has a primary winding on the rotor and two secondary windings on the stator. A variable reluctance resolver, on the other hand, has the primary and secondary windings on the stator and no windings on the rotor, as shown in Figure 3; however, the saliency in this rotor design provides the sinusoidal variation in the secondary coupling with the angular position. For both designs, the resolver output voltages (S3 − S1, S2 − S4) are as follows: S3 − S1 = E0 Sin(ωt ) × Sinθ (1) The stator windings are displaced mechanically by 90° (see Figure 3). The primary winding is excited with an ac reference. The amplitude of subsequent coupling onto the secondary windings is a function of the position of the rotor (shaft) relative to the stator. The resolver therefore produces two output voltages (S3 − S1, S2 − S4), modulated by the sine and cosine of the shaft angle. Resolver format signals refer to the signals derived from the output of a resolver, as shown in Equation 1. Figure 4 illustrates the output format. S2 − S4 = E0 Sin(ωt ) × Cosθ where: θ is the shaft angle. Sin(ωt) is the rotor excitation frequency. E0 is the rotor excitation amplitude. S2 – S4 (COSINE) S3 – S1 (SINE) 06339-004 R2 – R4 (REFERENCE) 0° 90° 180° 270° θ Figure 4. Electrical Resolver Representation Rev. A | Page 8 of 20 360° AD2S1205 THEORY OF OPERATION The AD2S1205’s operation is based on a Type II tracking closedloop principle. The digitally implemented tracking loop continually tracks the position and velocity of the resolver without the need for external convert and wait states. As the resolver moves through a position equivalent to the least significant bit weighting, the tracking loop output is updated by 1 LSB. The converter tracks the shaft angle (θ) by producing an output angle (ϕ) that is fed back and compared with the input angle (θ); the difference between the two angles is the error, which is driven towards 0 when the converter is correctly tracking the input angle. To measure the error, S3 − S1 is multiplied by Cosϕ and S2 − S4 is multiplied by Sinϕ to give E0Sin(ωt ) × Sinθ Cosφ for S3 − S1 E0Sin(ωt ) × Cosθ Sinφ for S2 − S4 (2) The difference is taken, giving E 0 Sin(ωt ) × (Sinθ Cosφ − Cosθ Sinφ) (3) This signal is demodulated using the internally generated synthetic reference, yielding E 0 (Sinθ Cosφ − Cosθ Sinφ) (4) Equation 4 is equivalent to E0Sin(θ − ϕ), which is approximately equal to E0(θ − ϕ) for small values of θ − ϕ, where θ − ϕ is the angular error. The value E0(θ − ϕ) is the difference between the angular error of the rotor and the digital angle output of the converter. A phase-sensitive demodulator, some integrators, and a compensation filter form a closed-loop system that seeks to null the error signal. If this is accomplished, ϕ equals the resolver angle, θ, within the rated accuracy of the converter. A Type II tracking loop is used so that constant velocity inputs can be tracked without inherent error. For more information about the operation of the converter, see the Circuit Dynamics section. FAULT DETECTION CIRCUIT The AD2S1205 fault detection circuit can sense loss of resolver signals, out-of-range input signals, input signal mismatch, or loss of position tracking; however, the position indicated by the AD2S1205 may differ significantly from the actual shaft position of the resolver. MONITOR SIGNAL The AD2S1205 generates a monitor signal by comparing the angle in the position register to the incoming Sin and Cos signals from the resolver. The monitor signal is created in a similar fashion to the error signal (described in the Theory of Operation section). The incoming Sinθ and Cosθ signals are multiplied by the Sin and Cos of the output angle, respectively, and then these values are added together: Monitor = ( A1 × Sinθ × Sinφ) + ( A2 × Cosθ × Cosφ) (5) where: A1 is the amplitude of the incoming Sin signal (A1 × Sinθ). A2 is the amplitude of the incoming Cos signal (A2 × Cosθ). θ is the resolver angle. ϕ is the angle stored in the position register. Note that Equation 5 is shown after demodulation with the carrier signal Sin(ωt) removed. Also note that for a matched input signal (that is, a no fault condition), A1 is equal to A2. When A1 is equal to A2 and the converter is tracking (therefore, θ is equal to ϕ), the monitor signal output has a constant magnitude of A1 (Monitor = A1 × (Sin2θ + Cos2θ) = A1), which is independent of the shaft angle. When A1 does not equal A2, the monitor signal magnitude alternates between A1 and A2 at twice the rate of the shaft rotation. The monitor signal is used to detect degradation or loss of input signals. LOSS OF SIGNAL DETECTION Loss of signal (LOS) is detected when either resolver input (Sin or Cos) falls below the specified LOS Sin/Cos threshold. The AD2S1205 detects this by comparing the monitor signal to a fixed minimum value. Without the use of external circuitry, the AD2S1205 can detect the loss of up to three of the four connections from the resolver. The addition of two external 68 kΩ resistors, as outlined in Figure 5, ensures that the loss of all 4 connections, that is, complete removal of the resolver, may also be detected. LOS is indicated by both DOS and LOT latching as logic low outputs. The DOS and LOT pins are reset to the no fault state by a rising edge of SAMPLE. The LOS condition has priority over both the DOS and LOT conditions, as shown in Table 4. LOS is indicated within 57° of the angular output error (worst case). Rev. A | Page 9 of 20 AD2S1205 SIGNAL DEGRADATION DETECTION RESPONDING TO A FAULT CONDITION Degradation of signal (DOS) is detected when either resolver input (Sin or Cos) exceeds the specified DOS Sin/Cos threshold. The AD2S1205 detects this by comparing the monitor signal to a fixed maximum value. In addition, DOS is detected when the amplitudes of the Sin and Cos input signals are mismatched by more than the specified DOS Sin/Cos mismatch. This is identified because the AD2S1205 continuously stores the minimum and maximum magnitude of the monitor signal in internal registers and calculates the difference between these values. DOS is indicated by a logic low on the DOS pin and is not latched when the input signals exceed the maximum input level. When DOS is indicated due to mismatched signals, the output is latched low until a rising edge of SAMPLE resets the stored minimum and maximum values. The DOS condition has priority over the LOT condition, as shown in Table 4. DOS is indicated within 33° of the angular output error (worst case). If a fault condition (LOS, DOS, or LOT) is indicated by the AD2S1205, the output data is presumed to be invalid. Even if a RESET or SAMPLE pulse releases the fault condition and is not immediately followed by another fault, the output data may be corrupted. As discussed previously, there are some fault conditions with inherent latency. If the device fault is cleared, there may be some latency in the resolver’s mechanical position before the fault condition is reindicated. LOSS OF POSITION TRACKING DETECTION Loss of tracking (LOT) is detected when • • • The internal error signal of the AD2S1205 exceeds 5°. The input signal exceeds the maximum tracking rate. The internal position (at the position integrator) differs from the external position (at the position register) by more than 5°. When a fault is indicated, all output pins still provide data, although the data may or may not be valid. The fault condition does not force the parallel, serial, or encoder outputs to a known state. Response to specific fault conditions is a system-level requirement. The fault outputs of the AD2S1205 indicate that the device has sensed a potential problem with either the internal or external signals of the AD2S1205. It is the responsibility of the system designer to implement the appropriate fault-handling schemes within the control hardware and/or algorithm of a given application based on the indicated fault(s) and the velocity or position data provided by the AD2S1205. FALSE NULL CONDITION LOT is indicated by a logic low on the LOT pin and is not latched. LOT has a 4° hysteresis and is not cleared until the internal error signal or internal/external position mismatch is less than 1°. When the maximum tracking rate is exceeded, LOT is cleared only if the velocity is less than the maximum tracking rate and the internal/external position mismatch is less than 1°. LOT can be indicated for step changes in position (such as after a RESET signal is applied to the AD2S1205), or for accelerations of >~65,000 rps2. It is also useful as a built-in test to indicate that the tracking converter is functioning properly. The LOT condition has lower priority than both the DOS and LOS conditions, as shown in Table 4. The LOT and DOS conditions cannot be indicated at the same time. Resolver-to-digital converters that employ Type II tracking loops based on the previously stated error equation (see Equation 4 in the Theory of Operation section) can suffer from a condition known as a false null. This condition is caused by a metastable solution to the error equation when θ − ϕ = 180°. The AD2S1205 is not susceptible to this condition because its hysteresis is implemented external to the tracking loop. As a result of the loop architecture chosen for the AD2S1205, the internal error signal constantly has some movement (1 LSB per clock cycle); therefore, in a metastable state, the converter moves to an unstable condition within one clock cycle. This causes the tracking loop to respond to the false null condition as if it were a 180° step change in input position (the response time is the same, as specified in the Dynamic Performance section of Table 1). Therefore, it is impossible to enter the metastable condition after the start-up sequence if the resolver signals are valid. Table 4. Fault Detection Decoding Condition Loss of Signal (LOS) Degradation of Signal (DOS) Loss of Tracking (LOT) No Fault DOS Pin 0 0 1 1 LOT Pin 0 1 0 1 Order of Priority 1 2 3 Rev. A | Page 10 of 20 AD2S1205 ON-BOARD PROGRAMMABLE SINUSOIDAL OSCILLATOR zero crossing of either the Sin or Cos (whichever signal is larger), which improves phase accuracy, and evaluating the phase of the resolver reference excitation. The synthetic reference reduces the phase shift between the reference and Sin/Cos inputs to less than 10° and can operate for phase shifts of ±45°. An on-board oscillator provides the sinusoidal excitation signal (EXC) and its complement signal (EXC) to the resolver. The frequency of this reference signal is programmable to four standard frequencies (10 kHz, 12 kHz, 15 kHz, or 20 kHz) by using the FS1 and FS2 pins (see Table 5). FS1 and FS2 have internal pull-ups, so the default frequency is 10 kHz. The amplitude of this signal is centered on 2.5 V and has an amplitude of 3.6 V p-p. CHARGE-PUMP OUTPUT Table 5. Excitation Frequency Selection CONNECTING THE CONVERTER Frequency Selection (kHz) 10 12 15 20 FS1 1 1 0 0 FS2 1 0 1 0 The frequency of the reference signal is a function of the CLKIN frequency. By decreasing the CLKIN frequency, the minimum excitation frequency can also be decreased. This allows an excitation frequency of 7.5 kHz to be set when using a CLKIN frequency of 6.144 MHz, and it also decreases the maximum tracking rate to 750 rps. The reference output of the AD2S1205 requires an external buffer amplifier to provide gain and additional current to drive the resolver. See Figure 6 for a suggested buffer circuit. The AD2S1205 also provides an internal synchronous reference signal that is phase locked to its Sin and Cos inputs. Phase errors between the resolver’s primary and secondary windings may degrade the accuracy of the RDC and are compensated for by using this synchronous reference signal. This also compensates for the phase shifts due to temperature and cabling, and it eliminates the need for an external preset phase-compensation circuit. SYNTHETIC REFERENCE GENERATION When a resolver undergoes a high rotation rate, the RDC tends to act as an electric motor and produces speed voltages in addition to the ideal Sin and Cos outputs. These speed voltages are in quadrature to the main signal waveform. Moreover, nonzero resistance in the resolver windings causes a nonzero phase shift between the reference input and the Sin and Cos outputs. The combination of the speed voltages and the phase shift causes a tracking error in the RDC that is approximated by Error = Phase Shift × Rotation Rate Reference Frequency (6) To compensate for the described phase error between the resolver reference excitation and the Sin/Cos signals, an internal synthetic reference signal is generated in phase with the reference frequency carrier. The synthetic reference is derived using the internally filtered Sin and Cos signals. It is generated by determining the A 204.8 kHz square wave output with a 50% duty cycle is available at the CPO pin of the AD2S1205. This square wave output can be used for negative rail voltage generation or to create a VCC rail. Ground is connected to the AGND and DGND pins (see Figure 5). A positive power supply (VDD) of 5 V dc ± 5% is connected to the AVDD and DVDD pins, with typical values for the decoupling capacitors being 10 nF and 4.7 μF. These capacitors are then placed as close to the device pins as possible and are connected to both AVDD and DVDD. If desired, the reference oscillator frequency can be changed from the nominal value of 10 kHz using FS1 and FS2. Typical values for the oscillator decoupling capacitors are 20 pF, whereas typical values for the reference decoupling capacitors are 10 μF and 0.01 μF. As outlined in the Loss of Signal Detection section 68 kΩ resistors between the Sin and SinLO inputs and the Cos and CosLO inputs can be used to ensure loss of signal detection when all four inputs from resolver are disconnected. In this recommended configuration, the converter introduces a VREF/2 offset in the Sin and Cos signal outputs from the resolver. The SinLO and CosLO signals can each be connected to a different potential relative to ground if the Sin and Cos signals adhere to the recommended specifications. Note that because the EXC and EXC outputs are differential, there is an inherent gain of 2×. Figure 6 shows a suggested buffer circuit. Capacitor C1 may be used in parallel with Resistor R2 to filter out any noise that may exist on the EXC and EXC outputs. Care should be taken when selecting the cutoff frequency of this filter to ensure that phase shifts of the carrier caused by the filter do not exceed the phase lock range of the AD2S1205. The gain of the circuit is CarrierGain = − (R2 / R1) × (1 /(1 + R2 × C1 × ω)) (7) R2 ⎞ R2 ⎛ VOUT = ⎜VREF × ⎛⎜1 + ⎞⎟⎟ − ⎛⎜ × (1/(1 + R2× C1× ω))VIN ⎞⎟ ⎝ R1⎠⎠ ⎝ R1 ⎠ ⎝ (8) and where: ω is the radian frequency of the applied signal. VREF, a dc voltage, is set so that VOUT is always a positive value, eliminating the need for a negative supply. Rev. A | Page 11 of 20 AD2S1205 A separate screened twisted pair cable is recommended for analog inputs Sin/SinLO and Cos/CosLO. The screens should terminate to either REFOUT or AGND. To achieve the specified dynamic performance, an external crystal is recommended at the CLKIN and XTALOUT pins. The position and velocity accuracy are guaranteed for a frequency range of 8.192 MHz ± 25%. However, the velocity outputs are scaled in proportion to the clock frequency so that if the clock is 25% greater than the nominal, the full-scale velocity is 25% greater than nominal. The maximum tracking rate, tracking loop bandwidth, and excitation frequency also vary with the clock frequency. R2 S3 S2 CLOCK REQUIREMENTS R1 S1 S4 5V BUFFER CIRCUIT 4.7μF BUFFER CIRCUIT 10nF 10μF 39 38 37 36 35 34 AVDD SinLO Sin AGND EXC EXC 40 Cos DVDD 2 41 CosLO 1 42 ABSOLUTE POSITION AND VELOCITY OUTPUT 68kΩ 31 4 30 5 29 6 27 8 26 9 25 11 14 15 16 17 Data Format DGND 23 18 19 20 21 5V The angular position data represents the absolute position of the resolver shaft as a 12-bit unsigned binary word. The angular velocity data is a 12-bit twos complement word, representing the velocity of the resolver shaft rotating in either a clockwise or counterclockwise direction. 22 8.192 MHz 10nF 20pF 20pF 06339-005 4.7μF The serial output enable pin (SOE) is held high to enable the parallel interface and low to enable the serial interface. In the latter case, Pin DB0 to Pin DB9 are placed into a high impedance state while DB11 is the serial output (SO) and DB10 is the serial clock input (SCLK). 24 DVDD 10 SOE Input 28 AD2S1205 7 13 RESET 33 3 12 The angular position and velocity are represented by binary data and can be extracted via either a 12-bit parallel interface or a 3-wire serial interface that operates at clock rates of up to 25 MHz. 32 DGND Figure 5. Connecting the AD2S1205 to a Resolver C1 R2 12V 12V R1 EXC/EXC (VIN) (VREF ) AD8662 VOUT 06339-017 5V 43 AGND 44 68kΩ REFBYP 10nF 5V Figure 6. Buffer Circuit PARALLEL INTERFACE The angular position and velocity are available on the AD2S1205 in two 12-bit registers, accessed via the 12-bit parallel port. The parallel interface is selected by holding the SOE pin high. Data is transferred from the velocity and position integrators to the position and velocity registers, respectively, after a high-to-low transition on the SAMPLE pin. The RDVEL pin selects whether data from the position or velocity register is transferred to the output register. The CS pin must be held low to transfer data from the selected register to the output register. Finally, the RD input is used to read the data from the output register and to enable the output buffer. The timing requirements for the read cycle are shown in Figure 7. SAMPLE Input Data is transferred from the position and velocity integrators to the position and velocity registers, respectively, after a high-tolow transition on the SAMPLE signal. This pin must be held low for at least t1 to guarantee correct latching of the data. RD should not be pulled low before this time because data will not be ready. The converter continues to operate during the read process. A rising edge of SAMPLE resets the internal registers that contain the minimum and maximum magnitude of the monitor signal. Rev. A | Page 12 of 20 AD2S1205 CS Input RD Input The device is enabled when CS is held low. The 12-bit data bus lines are normally in a high impedance state. The output buffer is enabled when CS and RD are held low. A falling edge of the RD signal transfers data to the output buffer. The selected data is made available to the bus to be read within t6 of the RD pin going low. The data pins return to a high impedance state when the RD pin returns to a high state within t7. When reading data continuously, wait a minimum of t3 after RD is released before reapplying it. RDVEL Input RDVEL input is used to select between the angular position register and the angular velocity register, as shown in Figure 7. RDVEL is held high to select the angular position register and low to select the angular velocity register. The RDVEL pin must be set (stable) at least t4 before the RD pin is pulled low. fCLKIN CLKIN t1 t1 SAMPLE t2 CS t3 t3 RD t5 t5 RDVEL t4 t4 VELOCITY t7 t6 DON'T CARE 06339-007 POSITION DATA t7 t6 Figure 7. Parallel Port Read Timing Table 6. Parallel Port Timing Parameter fCLKIN t1 t2 t3 t4 t5 t6 t7 Description Frequency of clock input SAMPLE pulse width Delay from SAMPLE before RD/CS low RD pulse width Set time RDVEL before RD/CS low Hold time RDVEL after RD/CS low Enable delay RD/CS low to data valid Disable delay RD/CS low to data high-Z Min 6.144 2 × (1/fCLKIN) + 20 6 × (1/fCLKIN) + 20 18 5 7 Typ 8.192 Max 10.24 30 18 Rev. A | Page 13 of 20 Unit MHz ns ns ns ns ns ns ns AD2S1205 SERIAL INTERFACE SAMPLE Input The angular position and velocity are available on the AD2S1205 in two 12-bit registers. These registers can be accessed via a 3-wire serial interface (SO, RD, and SCLK) that operates at clock rates of up to 25 MHz and is compatible with SPI and DSP interface standards. The serial interface is selected by holding the SOE pin low. Data from the position and velocity integrators are first transferred to the position and velocity registers using the SAMPLE pin. The RDVEL pin selects whether data is transferred from the position or velocity register to the output register, and the CS pin must be held low to transfer data from the selected register to the output register. Finally, the RD input is used to read the data that is clocked out of the output register and is available on the serial output pin (SO). When the serial interface is selected, DB11 is used as the serial output pin (SO), DB10 is used as the serial clock input (SCLK), and Pin DB0 to Pin DB9 are placed into the high impedance state. The timing requirements for the read cycle are described in Figure 8. Data is transferred from the position and velocity integrators to the position and velocity registers, respectively, after a high-tolow transition on the SAMPLE signal. This pin must be held low for at least t1 to guarantee correct latching of the data. RD should not be pulled low before this time because data will not be ready. The converter continues to operate during the read process. SO Output The output shift register is 16 bits wide. Data is clocked out of the device as a 16-bit word by the serial clock input (SCLK). The timing diagram for this operation is shown in Figure 8. The 16-bit word consists of 12 bits of angular data (position or velocity, depending on RDVEL input), one RDVEL status bit, and three status bits (a parity bit, a degradation of signal bit, and a loss of tracking bit). Data is clocked out MSB first from the SO pin, beginning with DB15. DB15 through DB4 correspond to the angular information. The angular position data format is unsigned binary, with all 0s corresponding to 0° and all 1s corresponding to 360° − l LSB. The angular velocity data format is twos complement, with the MSB representing the rotation direction. DB3 is the RDVEL status bit, with a 1 indicating position and a 0 indicating velocity. DB2 is DOS, the degradation of signal flag (refer to the Fault Detection Circuit section). Bit 1 is LOT, the loss of tracking flag (refer to the Fault Detection Circuit section). Bit 0 is PAR, the parity bit. The position and velocity data are in odd parity format, and the data readback always contains an odd number of logic highs (1s). CS Input The device is enabled when CS is held low. RD Input The 12-bit data bus lines are normally in a high impedance state. The output buffer is enabled when CS and RD are held low. The RD input is an edge-triggered input that acts as a frame synchronization signal and an output enable. On a falling edge of the RD signal, data is transferred to the output buffer. Data is then available on the serial output pin (SO); however, it is only valid after RD is held low for t9. The serial data is clocked out of the SO pin on the rising edges of SCLK, and each data bit is available at the SO pin on the falling edge of SCLK. However, as the MSB is clocked out by the falling edge of RD, the MSB is available at the SO pin on the first falling edge of SCLK. Each subsequent bit of the data-word is shifted out on the rising edge of SCLK and is available at the SO pin on the falling edge of SCLK for the next 15 clock pulses. The high-to-low transition of RD must occur during the high time of the SCLK to avoid DB14 being shifted on the first rising edge of the SCLK, which would result in the MSB being lost. RD may rise high after the last falling edge of SCLK. If RD is held low and additional SCLKs are applied after DB0 has been read, then 0s will be clocked from the data output. When reading data continuously, wait a minimum of t5 after RD is released before reapplying it. RDVEL Input RDVEL input is used to select between the angular position register and the angular velocity register. RDVEL is held high to select the angular position register and low to select the angular velocity register. The RDVEL pin must be set (stable) at least t4 before the RD pin is pulled low. Rev. A | Page 14 of 20 AD2S1205 fCLKIN CLKIN t1 t1 SAMPLE t2 CS t3 t3 RD t5 t5 RDVEL t4 t4 t6 t6 t7 t7 POSITION SO VELOCITY t8 RD tSCLK SCLK t10 MSB MSB – 1 LSB RDVEL DOS LOT PAR 06339-008 SO t11 t9 Figure 8. Serial Port Read Timing Table 7. Serial Port Timing 1 Parameter Description t8 t9 t10 t11 tSCLK MSB read time RD/CS to SCLK SO enable time RD/CS to DB valid Data access time, SCLK to DB valid Bus relinquish time RD/CS to SO high-Z Serial clock period (25 MHz maximum) 1 t1 to t7 are as defined in Table 6. Rev. A | Page 15 of 20 Min 15 40 Typ Max tSCLK Unit ns 30 30 18 ns ns ns ns AD2S1205 INCREMENTAL ENCODER OUTPUTS The A, B, and NM incremental encoder emulation outputs are free running and are valid if the resolver format input signals applied to the converter are valid. The AD2S1205 emulates a 1024-line encoder, meaning that, in terms of the converter resolution, one revolution produces 1024 A and B pulses. Pulse A leads Pulse B for increasing angular rotation (clockwise direction). The addition of the DIR output negates the need for external A and B direction decode logic. The DIR output indicates the direction of the input rotation and is high for increasing angular rotation. DIR can be considered an asynchronous output that can make multiple changes in state between two consecutive LSB update cycles. This occurs when the direction of the rotation of the input changes but the magnitude of the rotation is less than 1 LSB. The north marker pulse is generated as the absolute angular position passes through zero. The north marker pulse width is set internally for 90° and is defined relative to the A cycle. Figure 9 details the relationship between A, B, and NM. A This compares favorably with encoder specifications, which state fMAX as 20 kHz (photo diodes) to 125 kHz (laser based), depending on the type of light system used. A 1024-line laserbased encoder has a maximum speed of 7300 rpm. The inclusion of A and B outputs allows an AD2S1205 and resolver-based solution to replace optical encoders directly without the need to change or upgrade the user’s existing application software. SUPPLY SEQUENCING AND RESET The AD2S1205 requires an external reset signal to hold the RESET input low until VDD is within the specified operating range of 4.5 V to 5.5 V. The RESET pin must be held low for a minimum of 10 μs after VDD is within the specified range (shown as tRST in Figure 10). Applying a RESET signal to the AD2S1205 initializes the output position to a value of 0x000 (degrees output through the parallel, serial, and encoder interfaces) and causes LOS to be indicated (LOT and DOS pins pulled low), as shown in Figure 10. Failure to apply the correct power-up/reset sequence may result in an incorrect position indication. NM Figure 9. A, B, and NM Timing for Clockwise Rotation Unlike incremental encoders, the AD2S1205 encoder output is not subject to error specifications such as cycle error, eccentricity, pulse and state width errors, count density, and phase ϕ. The maximum speed rating (n) of an encoder is calculated from its maximum switching frequency (fMAX) and its pulses per revolution (PPR). 60 × f MAX n= PPR VDD 1/ 4 × 4.096 MHz = 1.024 MHz (4 Updates = 1 Pulse) (10) For 12 bits, the PPR is 1024. Therefore, the maximum speed (n) of the AD2S1205 with a CLKIN of 8.192 MHz is 1024 The RESET pin is then internally pulled up. (9) The A and B pulses of the AD2S1205 are initiated from the internal clock frequency, which is exactly half the external CLKIN frequency. With a nominal CLKIN frequency of 8.192 MHz, the internal clock frequency is 4.096 MHz. The equivalent encoder switching frequency is 60 × 1,024,000 After a rising edge on the RESET input, the device must be allowed at least 20 ms (shown as tTRACK in Figure 10) for the internal circuitry to stabilize and the tracking loop to settle to the step change of the input position. After tTRACK, a SAMPLE pulse must be applied, which in turn releases the LOT and DOT pins to the state determined by the fault detection circuitry and provides valid position data at the parallel and serial outputs. (Note that if position data is acquired via the encoder outputs, it can be monitored during tTRACK.) = 60,000 rpm 4.75V tRST RESET tTRACK SAMPLE LOT VALID OUTPUT DATA DOS (11) Rev. A | Page 16 of 20 06339-010 06339-009 B n= To achieve the maximum speed of 75,000 rpm, select an external CLKIN of 10.24 MHz to produce an internal clock frequency equal to 5.12 MHz. Figure 10. Power Supply Sequencing and Reset AD2S1205 CIRCUIT DYNAMICS LOOP RESPONSE MODEL θIN k1 × k2 – c 1 – z–1 R2D open-loop transfer function G(z ) = k1 × k2 × I (z ) 2 × C(z ) VELOCITY 1 – az–1 1 – bz–1 c 1 – z–1 θOUT Sin/Cos LOOKUP Figure 11. RDC System Response Block Diagram The RDC is a mixed-signal device that uses two ADCs to digitize signals from the resolver and a Type II tracking loop to convert these to digital position and velocity words. The first gain stage consists of the ADC gain on the Sin/Cos inputs and the gain of the error signal into the first integrator. The first integrator generates a signal proportional to velocity. The compensation filter contains a pole and a zero that are used to provide phase margin and reduce high frequency noise gain. The second integrator is the same as the first and generates the position output from the velocity signal. The Sin/Cos lookup has unity gain. The values for each section are as follows: G( z ) 1 + G( z ) H (z ) = V IN (Vp ) VREF (V) To convert G(z) into the s-plane, an inverse bilinear transformation is performed by substituting the following equation for z: 2 +s z= t 2 −s t k2 = 18 × 10 6 × 2π (13) Substitution yields the open-loop transfer function G(s). k1 × k2(1 − a) G( s ) = × a −b G( s ) ≅ (14) Compensator pole coefficient b= 4085 4096 (15) c= 1 4,096,000 (16) c 1 − z −1 1 − az −1 1 − bz −1 (23) t (1 + b) 2(1 − b) Ka = k1 × k2(1 − a) a −b (17) H (s ) = Compensation filter transfer function C (z ) = K a 1 + st1 × s 2 1 + st 2 Solving for each value gives t1 = 1 ms, t2 = 90 μs, and Ka ≈ 7.4 × 106 s−2. Note that the closed-loop response is described as INT1 and INT2 transfer function I (z ) = (22) where: t (1 + a) t1 = 2(1 − a) t2 = Integrator gain parameter s 2t 2 1 + s × t (1 + a) 2(1 − a) 4 × t (1 + b) s2 1+ s× 2(1 − b) 1 + st + This transformation produces the best matching at low frequencies (f < fSAMPLE). At such frequencies (within the closed-loop bandwidth of the AD2S1205), the transfer function can be simplified to Compensator zero coefficient 4095 a= 4096 (21) where t is the sampling period (1/4.096 MHz ≈ 244 ns). (12) Error gain parameter (20) The closed-loop magnitude and phase responses are that of a second-order low-pass filter (see Figure 12 and Figure 13). ADC gain parameter (k1NOM = 1.8/2.5) k2 = (19) R2D closed-loop transfer function 06339-011 ERROR (ACCELERATION) (18) G( s ) 1 + G( s ) (24) By converting the calculation to the s-domain, it is possible to quantify the open-loop dc gain (Ka). This value is useful to calculate the acceleration error of the loop (see the Sources of Error section). Rev. A | Page 17 of 20 AD2S1205 The step response to a 10° input step is shown in Figure 14. Because the error calculation (see Equation 2) is nonlinear for large values of θ − ϕ, the response time for such large (90° to 180°) step changes in position typically takes three times as long as the response to a small (