AD2S81

a FEATURES Monolithic (BiMOS ll) Tracking R/D Converter Ratiometric Conversion Low Power Consumption: 300 mW Typ Dynamic Performance Set by User Velocity Output ESD Class 2 Protection (2,000 V Min) AD2S81A 28-Lead DIP Package Low Cost AD2S82A 44-Lead PLCC Package 10-, 12-, 14- and 16-Bit Resolution Set by User High Max Tracking Rate 1040 RPS (10 Bits) VCO Output (Inter LSB Output) Data Complement Facility Industrial Temperature Range APPLICATIONS DC Brushless and AC Motor Control Process Control Numerical Control of Machine Tools Robotics Axis Control GENERAL DESCRIPTION Variable Resolution, Monolithic Resolver-to-Digital Converters AD2S81A/AD2S82A AD2S82A FUNCTIONAL BLOCK DIAGRAM DEMOD DEMOD INTEGRATOR I/P O/P I/P AD2S82A SIN I/P SIGNAL GND COS I/P ANALOG GND RIPPLE CLK +12V –12V COMP DATA LOAD A1 SEGMENT SWITCHING A2 PHASE SENSITIVE DETECTOR R-2R DAC INTEGRATOR O/P A3 AC ERROR O/P VCO I/P INHIBIT VCO O/P +5V 16-BIT UP/DOWN COUNTER VCO DATA TRANSFER LOGIC OUTPUT DATA LATCH SC2 SC1 ENABLE BUSY DIR BYTE SELECT DIGITAL GND 16 DATA BITS An analog signal proportional to velocity is also available and can be used to replace a tachogenerator. PRODUCT HIGHLIGHTS Monolithic. A one-chip solution reduces the package size required and increases the reliability. Resolution Set by User. Two control pins are used to select the resolution of the AD2S82A to be 10, 12, 14 or 16 bits allowing the user to use the AD2S82A with the optimum resolution for each application. Ratiometric Tracking Conversion. Conversion technique provides continuous output position data without conversion delay and is insensitive to absolute signal levels. It also provides good noise immunity and tolerance to harmonic distortion on the reference and input signals. Dynamic Performance Set by the User. By selecting external resistor and capacitor values the user can determine bandwidth, maximum tracking rate and velocity scaling of the converter to match the system requirements. The external components required are all low cost, preferred value resistors and capacitors, and the component values are easy to select using the simple instructions given. Velocity Output. An analog signal proportional to velocity is available and is linear to typically one percent. This can be used in place of a velocity transducer in many applications to provide loop stabilization in servo controls and velocity feedback data. Low Power Consumption. Typically only 300 mW. MODELS AVAILABLE The AD2S82A is a monolithic 10-, 12-, 14- or 16-bit tracking resolver-to-digital converter contained in a 44-lead J leaded PLCC package. Two extra functions are provided in the new surface mount package–COMPLEMENT and VCO output. The AD2S81A is a monolithic 12-bit fixed resolution tracking resolver-to-digital converter packaged in a 28-lead DIP. The converters allow users to select their own dynamic performance with external components. This allows the users great flexibility in defining the converter that best suits their system requirements. The AD2S82A allows users to select the resolution to be 10, 12, 14 or 16 bits and to track resolver signals rotating at up to 1040 revs per second (62,400 rpm) when set to 10-bit resolution. The AD2S81A and AD2S82A convert resolver format input signals into a parallel natural binary digital word using a ratiometric tracking conversion method. This ensures high-noise immunity and tolerance of lead length when the converter is remote from the resolver. The output word is in a three-state digital logic form available in two bytes on the 16 output data lines for the AD2S82A and on eight output data lines for the AD2S81A. BYTE SELECT, ENABLE and INHIBIT pins ensure easy data transfer to 8- and 16-bit data buses, and outputs are provided to allow for cycle or pitch counting in external counters. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Information on the models available is given in the Ordering Guide. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 AD2S81A/AD2S82A–SPECIFICATIONS (@ T = +25 C, unless otherwise noted) A Parameter SIGNAL INPUTS Frequency Voltage Level Input Bias Current Input Impedance Maximum Voltage REFERENCE INPUT Frequency Voltage Level Input Bias Current Input Impedance CONTROL DYNAMICS Repeatability Allowable Phase Shift Tracking Rate Conditions Min 400 1.8 1.0 AD2S81A Typ Max 20,000 2.2 150 ±8 20,000 8.0 150 Min 50 1.8 1.0 AD2S82A Typ Max 20,000 2.2 150 ±8 20,000 8.0 150 Units Hz V rms nA MΩ V pk Hz V pk nA MΩ LSB Degrees rps rps rps rps 2.0 60 2.0 60 400 1.0 60 1.0 50 1.0 60 1.0 Bandwidth1 ACCURACY Angular Accuracy (Signals to Reference) 10 Bits 12 Bits 14 Bits 16 Bits User Selectable –10 1 +10 260 –10 1 +10 1040 260 65 16.25 H J K L Monotonicity Guaranteed Monotonic Missing Codes (16-Bit Resolution) J, K L Over Full Range ±1 –22 1 mA Load Mean Value ±8 ±9 30 + 1 LSB 22 + 1 LSB 8 + 1 LSB 4 + 1 LSB 2 + 1 LSB 4 1 arc min arc min arc min arc min Codes Code % FSD % FSD mV µV/°C % FSD V % rms O/P kΩ V mA VELOCITY SIGNAL Linearity Reversion Error DC Zero Offset2 DC Zero Offset Tempco Gain Scaling Accuracy Output Voltage Dynamic Ripple Output Load INPUT/OUTPUT PROTECTION Analog Inputs Analog Outputs DIGITAL POSITION Resolution Output Format Load INHIBIT Sense Time to Stable Data ENABLE3 ENABLE/Disable Time BYTE SELECT3 Sense Logic HI Logic LO Time to Data Available SHORT CYCLE INPUTS4, 5 SC1 0 0 1 1 SC2 0 1 0 1 3 3 ±2 6 10 ± 10.5 1.5 1.0 ±8 ±1 –22 ±9 3 ±2 6 10 ± 10.5 1.5 1.0 Overvoltage Protection Short Circuit O/P Protection 10, 12, 14 and 16 Bidirectional Natural Binary ± 5.6 ±8 ±8 ± 10.4 ± 5.6 ±8 ±8 ± 10.4 3 Logic LO to Inhibit 600 Logic LO Enables Position Output. Logic HI Outputs in High Impedance State 35 110 35 3 LSTTL 600 ns 110 ns MS Byte DB1–DB8, (LS Byte DB9–DB16)4 LS Byte DB1–DB8, (LS Byte DB9–DB16)4 60 Internally Pulled High (100 kΩ ) to +VS 10 Bit 12 Bit 14 Bit 16 Bit Internally Pulled High (100 kΩ ) to +VS; Logic LO Allows Data to Be Loaded into the Counters from the Data Lines 150 300 ns 140 60 140 ns DATA LOAD4, 5 Sense –2– REV. B AD2S81A/AD2S82A Parameter COMPLEMENT 4, 5 Conditions Internally Pulled High (100 kΩ ) to +VS; Logic LO to Activate; No Connect for Normal Operation Logic HI When Position O/P Changing Min AD2S81A Typ Max Min AD2S82A Typ Max Units BUSY3 Sense Width Load DIRECTION3 Sense Max Load RIPPLE CLOCK3 Sense Width Reset Load DIGITAL INPUTS High Voltage, VIH Low Voltage, VIL 200 Use Additional Pull-Up Logic HI Counting Up Logic LO Counting Down 600 1 200 600 1 ns LSTTL 3 Logic HI, All 1s to All 0s All 0s to All 1s Dependent On Input Velocity Before Next Busy 3 LSTTL 300 3 300 3 2.0 0.8 0.8 LSTTL V V INHIBIT, ENABLE DB1–DB16, Byte Select ± VS = ± 10.8 V, VL = 5.0 V INHIBIT, ENABLE DB1–DB16, Byte Select ± VS = ± 13.2 V, VL = 5.0 V INHIBIT, ENABLE DB1–DB16 ± VS = ± 13.2 V, VL = 5.5 V INHIBIT, ENABLE DB1–DB16, Byte Select ± VS = ± 13.2 V, VL = 5.5 V ENABLE = HI SC1, SC2, Data Load ± VS = ± 12.0 V, VL = 5.0 V ENABLE = HI SC1, SC2, Data Load ± VS = ± 12.0 V, VL = 5.0 V DB1–DB16; RIPPLE CLK, DIR ± VS = ± 12.0 V, VL = 4.5 V IOH = 100 µA DB1–DB16, RIPPLE CLK, DIR ± VS = ± 12.0 V, VL = 5.5 V IOL = 1.2 mA DB1–DB16 Only +VS = ± 12.0 V, VL = 5.5 V VOL = 0 V +VS = ± 12.0 V, VL = 5.5 V VOH = 5.0 V 2.0 DIGITAL INPUTS High Current, IIH Low Current, IIL 100 100 100 100 µA µA DIGITAL INPUTS Low Voltage, VIL Low Current, IIL 1.0 –400 1.0 –400 V µA DIGITAL OUTPUTS High Voltage, VOH Low Voltage, VOL 2.4 0.4 2.4 0.4 V V THREE-STATE LEAKAGE Current IL ± 100 ± 100 ± 100 ± 100 µA µA POWER SUPPLIES Voltage Levels +VS –VS +VL Current +IS +IS +IL +10.8 –10.8 +5 ± VS @ ± 12 V ± VS @ ± 13.2 V ± VL @ ± 5.0 V 12 19 0.5 +13.2 –13.2 +13.2 23 30 1.5 +10.8 –10.8 +5 12 19 0.5 +13.2 –13.2 +13.2 23 30 1.5 V V V mA mA mA NOTES 1 Refers to small signal bandwidth. 2 Output offset dependent on value for R6. 3 Refer to timing diagram. 4 AD2S82A only. 5 These pins are referenced to +V S (i.e., HI = +12 V, LO = 0 V). Specifications subject to change without notice. All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. REV. B – 3– AD2S81A/AD2S82A–SPECIFICATIONS (typical @ +25 C unless otherwise noted) Parameter RATIO MULTIPLIER AC Error Output Scaling Conditions 10 Bit 12 Bit 14 Bit 16 Bit Min AD2S81A Typ Max Min AD2S82A Typ Max 177.6 44.4 11.1 2.775 12 w.r.t. REF w.r.t. REF –0.882 –0.9 60 1 –0.918 0.04 150 ±8 63 100 1 60 5 150 12 –0.882 –0.9 60 1 –0.918 0.04 150 ±8 63 100 1 60 5 150 Units mV/Bit mV/Bit mV/Bit mV/Bit mV V rms/V dc V rms/V dc nA MΩ V dB nA/LSB mV nA V MHz kHz/ µA kHz/ µA %/V %/V %/V %/V mV nA nA/°C V % FSD % FSD % FSD %/V of Asymmetry V/LSB 44.4 PHASE SENSITIVE DETECTOR Output Offset Voltage Gain In Phase In Quadrature Input Bias Current Input Impedance Input Voltage INTEGRATOR Open-Loop Gain Dead Zone Current (Hysteresis) Input Offset Voltage Input Bias Current Output Voltage Range VCO Maximum Rate VCO Rate VCO Power Supply Sensitivity Increase Decrease Input Offset Voltage Input Bias Current Input Bias Current Tempco Input Voltage Range Linearity of Absolute Rate Full Range Over 0% to 50% of Full Range Reversion Error Sensitivity of Reversion Error to Symmetry of Power Supplies VCO Output1, 2 POWER SUPPLIES Voltage Levels +VS –VS +VL Current +IS +IS +IL At 10 kHz 57 57 ± VS = ± 10.8 V dc ± VS = ± 12 V dc Positive DIR Negative DIR +VS –VS +VS –VS ±7 1.0 7.1 7.1 1.1 7.9 7.9 +0.5 –8.0 –8.0 +2.0 1 70 –1.22 8.7 8.7 1.0 7.1 7.1 1.1 7.9 7.9 +0.5 –8.0 –8.0 +2.0 1 70 –1.22 8.7 8.7 5 380 ±8