AD2S83IP

a FEATURES Tracking R/D Converter High Accuracy Velocity Output High Max Tracking Rate 1040 RPS (10 Bits) 44-Lead PLCC Package 10-, 12-, 14- or 16-Bit Resolution Set by User Ratiometric Conversion Stabilized Velocity Reference Dynamic Performance Set by User Industrial Temperature Range APPLICATIONS DC and AC Servo Motor Control Process Control Numerical Control of Machine Tools Robotics Axis Control SIN SIG GND COS GND RIPPLE CLOCK +12V –12V A1 Variable Resolution, Resolver-to-Digital Converter AD2S83 FUNCTIONAL BLOCK DIAGRAM REFERENCE I/P HF FILTER C3 R3 OFFSET ADJUST R9 +12V R8 BANDWIDTH SELECTION –12V C1 R1 R2 C2 R4 AC ERROR O/P DEMOD O/P SEGMENT SWITCHING A2 PHASE SENSITIVE DETECTOR INTEGRATOR I/P C5 R5 C4 R – 2R DAC A3 INTEGRATOR O/P R6 VCO I/P VELOCITY SIGNAL AD2S83 16-BIT UP/DOWN COUNTER TRACKING RATE SELECTION C7 OUTPUT DATA LATCH VCO + DATA TRANSFER LOGIC VCO O/P DATA SC1 SC2 ENABLE LOAD 16 DATA BITS BYTE +5V DIG BUSY DIRECTION INHIBIT GND SELECT R7 3K3 C6 390pF GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD2S83 is a monolithic 10-, 12-, 14- or 16-bit tracking resolver-to-digital converter. The converter allows users to select their own resolution and dynamic performance with external components. The converter allows users to select the resolution to be 10, 12, 14 or 16 bits and to track resolver signals rotating at up to 1040 revs per second (62,400 rpm) when set to 10-bit resolution. The AD2S83 converts resolver format input signals into a parallel natural binary digital word using a ratiometric tracking conversion method. This ensures high noise immunity and tolerance of long leads allowing the converter to be located remote from the resolver. The position output from the converter is presented via 3-state output pins which can be configured for operations with 8- or 16-bit bus. BYTE SELECT, ENABLE and INHIBIT pins ensure easy data transfer to 8- and 16-bit data bus, and outputs are provided to allow for cycle or pitch counting in external counters. A precise analog signal proportional to velocity is also available and will replace a tachogenerator. The AD2S83 operates over reference frequencies in the range 0 Hz to 20,000 Hz. High Accuracy Velocity Output. A precision analog velocity signal with a typical linearity of ± 0.1% and reversion error less than ± 0.3% is generated by the AD2S83. The provision of this signal removes the need for mechanical tachogenerators used in servo systems to provide loop stabilization and speed control. Resolution Set by User. Two control pins are used to select the resolution of the AD2S83 to be 10, 12, 14 or 16 bits allowing optimum resolution for each application. Ratiometric Tracking Conversion. This technique provides continuous output position data without conversion delay. It also provides noise immunity and tolerance of harmonic distortion on the reference and input signals. Dynamic Performance Set by the User. By selecting external resistor and capacitor values the user can determine bandwidth, maximum tracking rate and velocity scaling of the converter to match the system requirements. The component values are easy to select using the free component selection software design aid. MODELS AVAILABLE Information on the models available is given in the Ordering Guide. R EV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 AD2S83–SPECIFICATIONS ( Parameter SIGNAL INPUTS (SIN, COS) Frequency1 Voltage Level Input Bias Current Input Impedance REFERENCE INPUT (REF) Frequency Voltage Level Input Bias Current Input Impedance PERFORMANCE Repeatability Allowable Phase Shift Max Tracking Rate Conditions VS = 12 V dc 5%; VL = +5 V dc Min 0 1.8 1.0 0 1.0 10%; TA = –40 C to +85 C) AD2S83 Typ Max 20,000 2.2 150 Units Hz V rms nA MΩ Hz V pk nA MΩ LSB Degree rps rps rps rps 2.0 60 60 1.0 20,000 8.0 150 Bandwidth ACCURACY Angular Accuracy Monotonicity Missing Codes (16-Bit Resolution) VELOCITY SIGNAL LINEARITY2, 3, 4 AD2S83AP 0 kHz–500 kHz 0.5 MHz–1 MHz AD2S83IP 0 kHz–500 kHz 0.5 MHz–1 MHz Reversion Error AD2S83AP AD2S83IP DC Zero Offset5 Gain Scaling Accuracy Output Voltage Dynamic Ripple INPUT/OUTPUT PROTECTION Analog Inputs Analog Outputs DIGITAL POSITION Resolution Output Format Load INHIBIT6 Sense Time to Stable Data ENABLE 6 (Signals to Reference) 10 Bits 12 Bits 14 Bits 16 Bits User Selectable A, I Guaranteed Monotonic A, I –10 1040 260 65 16.25 1 +10 8 +1 LSB 4 arc min Codes –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C 1 mA Load Mean Value Overvoltage Protection Short Circuit O/P Protection 10, 12, 14, and 16 Bidirectional Natural Binary ±8 ± 0.15 ± 0.25 ± 0.25 ± 0.25 ± 0.5 ± 1.0 ±3 ± 1.5 0.25 1.0 0.5 1.0 1.0 1.5 3 1.0 % FSR % FSR % FSR % FSR % O/P % O/P mV % FSR V % rms O/P V mA Bits ± 5.6 ±8 ±8 ± 10.4 3 Logic LO to INHIBIT 240 Logic LO Enables Position Output Logic HI Outputs in High Impedance State 390 490 LSTTL ns ENABLE6/Disable Time BYTE SELECT Sense Logic HI Logic LO Time to Data Available SHORT CYCLE INPUTS SC1 SC2 0 0 0 1 1 0 1 1 6 35 110 ns MS Byte DB1–DB8 LS Byte DB1–DB8 60 Internally Pulled High via 100 kΩ to +VS 10-Bit Resolution 12-Bit Resolution 14-Bit Resolution 16-Bit Resolution 140 ns –2– REV. D AD2S83 Parameter COMPLEMENT Conditions Internally Pulled High via 100 kΩ to +VS. Logic LO to Activate; No Connect for Normal Operation Internally Pulled High via 100 kΩ to +VS. Logic LO Allows Data to be Loaded into the Counters from the Data Lines Logic HI When Position O/P Changing 150 Use Additional Pull-Up (See Figure 2) Logic HI Counting Up Logic LO Counting Down 3 6 Min AD2S83 Typ Max Units DATA LOAD Sense 150 300 ns BUSY6, 7 Sense Width Load DIRECTION6 Sense Max Load RIPPLE CLOCK Sense Width Reset Load DIGITAL INPUTS Input High Voltage, VIH Input Low Voltage, VIL 350 1 ns LSTTL LSTTL Logic HI All 1s to All 0s All 0s to All 1s Dependent on Input Velocity Before Next Busy 300 3 ns LSTTL V 0.8 V INHIBIT, ENABLE DB1–DB16, Byte Select ± VS = ± 11.4 V, VL = 5.0 V INHIBIT, ENABLE DB1–DB16, Byte Select ± VS = ± 12.6 V, VL = 5.0 V INHIBIT, ENABLE DB1–DB16 ± VS = ± 12.6 V, VL = 5.5 V INHIBIT, ENABLE DB1–DB16, Byte Select ± VS = ± 12.6 V, VL = 5.5 V ENABLE = HI SC1, SC2, DATA LOAD ± VS = ± 12.0 V, VL = 5.0 V ENABLE = HI SC1, SC2, DATA LOAD ± VS = ± 12.0 V, VL = 5.0 V DB1–DB16 RIPPLE CLK, DIR ± VS = ± 12.0 V, VL = 4.5 V IOH = 100 µA DB1–DB16 RIPPLE CLK, DIR ± VS = ± 12.0 V, VL = 5.5 V IOL = 1.2 mA 2.0 DIGITAL INPUTS Input High Current, IIH Input Low Current, IIL 100 100 µA µA DIGITAL INPUTS Low Voltage, VIL Low Current, IIL 1.0 –400 V µA DIGITAL OUTPUTS High Voltage, VOH 2.4 V Low Voltage, VOL 0.4 V NOTES 1 Angular accuracy is not guaranteed with R3 in Ω. 1 R 3 × fREF F AD2S83 8. Offset Adjust Offsets and bias currents at the integrator input can cause an additional positional offset at the output of the converter of 1 arc minute typical, 5.3 arc minutes maximum. If this can be tolerated, then R8 and R9 can be omitted from the circuit. If fitted, the following values of R8 and R9 should be used: R 8 = 4.7 MΩ , R 9 = 1 MΩ potentiometer To adjust the zero offset, ensure the resolver is disconnected and all the external components are fitted. Connect the COS pin to the REFERENCE INPUT and the SIN pin to the SIGNAL GROUND and with the power and reference applied, adjust the potentiometer to give all “0s” on the digital output bits. The potentiometer may be replaced with select on test resistors if preferred. DATA TRANSFER BYTE SELECT Input The BYTE SELECT input selects the byte of the position data to be presented at the data output DB1 to DB8. The least significant byte will be presented on data output DB9 to DB16 (with the ENABLE input taken to a logic “LO”) regardless of the state of the BYTE SELECT pin. Note that when the AD2S83 is used with a resolution less than 16 bits the unused data lines are pulled to a logic “LO.” A logic “HI” on the BYTE SELECT input will present the eight most significant data bits on data output DB1 and DB8. A logic “LO” will present the least significant byte on data outputs 1 to 8, i.e., data outputs 1 to 8 will duplicate data outputs 9 to 16. The operation of the BYTE SELECT has no effect on the conversion process of the converter. RIPPLE CLOCK To transfer data the INHIBIT input should be used. The data will be valid 490 ns after the application of a logic “LO” to the INHIBIT. This is regardless of the time when the INHIBIT is applied and allows time for an active BUSY to clear. By using the ENABLE input the two bytes of data can be transferred after which the INHIBIT should be returned to a logic “HI” state to enable the output latches to be updated. BUSY Output As the output of the converter passes through the major carry, i.e., all “1s” to all “0s” or the converse, a positive going edge on the RIPPLE CLOCK (RC) output is initiated indicating that a revolution, or a pitch, of the input has been completed. The minimum pulsewidth of the ripple clock is 300 ns. RIPPLE CLOCK is normally set high before a BUSY pulse and resets before the next positive going edge of the next BUSY pulse. The only exception to this is when DIR changes while the RIPPLE CLOCK is high. Resetting of the RIPPLE clock will only occur if the DIR remains stable for two consecutive positive BUSY pulse edges. If the AD2S83 is being used in a pitch and revolution counting application, the ripple and busy will need to be gated to prevent false decrement or increment (see Figure 2). RIPPLE CLOCK is unaffected by INHIBIT. +5V 10k 1k TO COUNTER (CLOCK) 2N3904 +5V 5K1 IN4148 BUSY NOTE: DO NOT USE ABOVE CCT WHEN INHIBIT IS LOW. 0V The validity of the output data is indicated by the state of the BUSY output. When the input to the converter is changing, the signal appearing on the BUSY output is a series of pulses at TTL level. A BUSY pulse is initiated each time the input moves by the analog equivalent of one LSB and the internal counter is incremented or decremented. INHIBIT Input The INHIBIT logic input only inhibits the data transfer from the up-down counter to the output latches and, therefore, does not interrupt the operation of the tracking loop. Releasing the INHIBIT automatically generates a BUSY pulse to refresh the output data. ENABLE Input IN4148 RIPPLE CLOCK The ENABLE input determines the state of the output data. A logic “HI” maintains the output data pins in the high impedance condition, and the application of a logic “LO” presents the data in the latches to the output pins. The operation of the ENABLE has no effect on the conversion process. Figure 2. Diode Transistor Logic Nand Gate REV. D –9– AD2S83 BUSY VH t1 RIPPLE CLOCK VL t2 VH t4 DATA VH t3 t5 INHIBIT VH VH DIR VL t6 t7 VL t8 INHIBIT ENABLE VZ t9 VL VL t10 DATA VH t11 BYTE SELECT VL VL VH VH DATA t12 t13 VL Figure 3. Digital Timing Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 *ns TMIN* 150 10 470 16 3 70 485 515 – 40 35 60 60 TMAX* 350 25 580 45 25 140 625 670 490 110 110 140 125 Condition BUSY WIDTH VH–VH RIPPLE CLOCK VH to BUSY VH RIPPLE CLOCK VL to Next BUSY VH BUSY VH to DATA VH BUSY VH to DATA VL INHIBIT VH to BUSY VH MIN DIR VH to BUSY VH MIN DIR VH to BUSY VH INHIBIT VL to DATA STABLE ENABLE VL to DATA VH ENABLE VL to DATA VL BYTE SELECT VL to DATA STABLE BYTE SELECT VH to DATA STABLE –10– REV. D AD2S83 DIRECTION Output CIRCUIT FUNCTIONS AND DYNAMIC PERFORMANCE The DIRECTION (DIR) output indicates the direction of the input rotation. Any change in the state of DIR precedes the corresponding BUSY, DATA and RIPPLE CLOCK updates. DIR can be considered as an asynchronous output and can make multiple changes in state between two consecutive LSB update cycles. This occurs when the direction of rotation of the input changes but the magnitude of the rotation is less than 1 LSB. COMPLEMENT The COMPLEMENT input is an active low input and is internally pulled to +VS via 100 kΩ. Strobing DATA LOAD and COMPLEMENT pins to logic LO will set the logic HI bits of the AD2S83 counter to a LO state. Those bits of the applied data which are logic LO will not change the corresponding bits in the AD2S83 counter. For Example: Initial Counter State Applied Data Word Counter State after DATA LOAD Initial Counter State Applied Data Word Counter State after DATA LOAD and Complement 10101 11000 11000 10101 11000 00101 The AD2S83 allows the user great flexibility in choosing the dynamic characteristics of the resolver-to-digital conversion to ensure the optimum system performance. The characteristics are set by the external components shown in Figure 1. The Component Selection section explains how to select desired maximum tracking rate and bandwidth values. The following paragraphs explain in greater detail the circuit of the AD2S83 and the variations in the dynamic performance available to the user. Loop Compensation The AD2S83 (connected as shown in Figure 1) operates as a Type 2 tracking servo loop where the VCO/counter combination and Integrator perform the two integration functions inherent in a Type 2 loop. Additional compensation in the form of a pole/zero pair is required to stabilize the loop. This compensation is implemented by the integrator components (R4, C4, R5, C5). The overall response the converter is that of a unity gain second order low-pass filter, with the angle of the resolver as the input and the digital position data as the output. The AD2S83 does not have to be connected as tracking converter, parts of the circuit can be used independently. This is particularly true of the Ratio Multiplier which can be used as a control transformer. (For more information contact Motion Control Applications.) A block diagram of the AD2S83 is given in Figure 4. In order to read the counter following a DATA LOAD, the procedure below should be followed: 1. Place outputs in high impedance state (ENABLE = HI). 2. Present data to pins. 3. Pull DATA LOAD and COMPLEMENT pins to ground. 4. Wait 100 ns. 5. Remove data from pins. 6. Remove outputs from high impedance state (ENABLE = LO). 7. Read outputs. R5 AC ERROR C4 SIN COS SIN SIN t t RATIO MULTIPLIER A, SIN ( – ) SIN t C5 PHASE SENSITIVE DEMODULATOR R4 INTEGRATOR DIGITAL CLOCK R6 DIRECTION VCO VELOCITY Figure 4. Functional Diagram REV. D –11– AD2S83 Ratio Multiplier Phase Sensitive Demodulator The ratio multiplier is the input section of the AD2S83. This compares the signal from the resolver (angle θ) to the digital (angle φ) held in the counter. Any difference between these two angles results in an analog voltage at the AC ERROR OUTPUT. This circuit function has historically been called a “Control Transformer” as it was originally performed by an electromechanical device known by that name. The AC ERROR signal is given by A1 sin (θ–φ) sin ωt where ω = 2 π fREF fREF = reference frequency A1 = the gain of the ratio multiplier stage = 14.5. So for 2 V rms inputs signals AC ERROR output in volts/(bit of error) The phase sensitive demodulator is effectively ideal and develops a mean dc output at the DEMODULATOR OUTPUT pin of ±2 2 π × ( DEMODULATOR INPUT rms voltage ) for sinusoidal signals in phase or antiphase with the reference (for a square wave the DEMODULATOR OUTPUT voltage will equal the DEMODULATOR INPUT). This provides a signal at the DEMODULATOR OUTPUT which is a dc level proportional to the positional error of the converter. DC Error Scaling = 160 mV/bit (10-bit resolution) = 40 mV/bit (12-bit resolution) = 10 mV/bit (14-bit resolution) = 2.5 mV/bit (16-bit resolution) When the tracking loop is closed, this error is nulled to zero unless the converter input angle is accelerating. Integrator  360  = 2 × sin  n  × A1   where n = bits per rev = 1,024 for 10-bit resolution = 4,096 for 12-bit resolution = 16,384 for 14-bit resolution = 65,536 for 16-bit resolution giving an AC ERROR output = 178 mV/bit @ 10-bit resolution = 44.5 mV/bit @ 12-bit resolution = 11.125 mV/bit @ 14-bit resolution = 2.78 mV/bit @ 16-bit resolution The ratio multiplier will work in exactly the same way whether the AD2S83 is connected as a tracking converter or as a control transformer, where data is preset into the counters using the DATA LOAD pin. HF Filter The integrator components (R4, C4, R5, C5) are external to the AD2S83 to allow the user to determine the optimum dynamic characteristics for any given application. The Component Selection section explains how to select components for a chosen bandwidth. Since the output from the integrator is fed to the VCO INPUT, it is proportional to velocity (rate of change of output angle) and can be scaled by selection of R6, the VCO input resistor. This is explained in the Voltage Controlled Oscillator (VCO) section below. To prevent the converter from “flickering” (i.e., continually toggling by ± 1 bit when the quantized digital angle, φ, is not an exact representation of the input angle, θ) feedback is internally applied from the VCO to the integrator input to ensure that the VCO will only update the counter when the error is greater than or equal to 1 LSB. In order to ensure that this feedback “hysteresis” is set to 1 LSB the input current to the integrator must be scaled to be 100 nA/bit. Therefore, The AC ERROR OUTPUT may be fed to the PSD via a simple ac coupling network (R2, C1) to remove any dc offset at this point. Note, however, that the PSD of the AD2S83 is a wideband demodulator and is capable of aliasing HF noise down to within the loop bandwidth. This is most likely to happen where the resolver is situated in particularly noisy environments, and the user is advised to fit a simple HF filter R1, C2 prior to the phase sensitive demodulator. The attenuation and frequency response of a filter will affect the loop gain and must be taken into account in deriving the loop transfer function. The suggested filter (R1, C1, R2, C2) is shown in Figure 1 and gives an attenuation at the reference frequency (fREF) of three times at the input to the phase sensitive demodulator. Values of components used in the filter must be chosen to ensure that the phase shift at fREF is within the allowable signal to reference phase shift of the converter. R4 = DC Error Scaling ( mV / bit ) 100 ( nA / bit ) Any offset at the input of the integrator will affect the accuracy of the conversion as it will be treated as an error signal and offset the digital output. One LSB of extra error will be added for each 100 nA of input bias current. The method of adjusting out this offset is given in the Component Selection section. Voltage Controlled Oscillator (VCO) The VCO is essentially a simple integrator feeding a pair of dc level comparators. Whenever the integrator output reaches one of the comparator threshold voltages, a fixed charge is injected into the integrator input to balance the input current. At the same time the counter is clocking either up or down, dependent on the polarity of the input current. In this way the counter is clocked at a rate proportional to the magnitude of the input current of the VCO. –12– REV. D AD2S83 During the VCO reset period the input continues to be integrated. The reset period is constant at 40 ns. The VCO rate is fixed for a given input current by the VCO scaling factor: The tracking rate in rps per µA of VCO input current can be found by dividing the VCO scaling factor by the number of LSB changes per rev (i.e., 4096 for 12-bit resolution). The input resistor R6 determines the scaling between the converter velocity signal voltage at the INTEGRATOR OUTPUT pin and the VCO input current. Thus to achieve a 5 V output at 100 rps (6000 rpm) and 12-bit resolution the VCO input current must be: (100 × 4096)/(8500) = 48.2 µA Thus, R6 would be set to: 5/(48.2 × 10–6) = 103.7 kΩ The velocity offset voltage depends on the VCO input resistor, R6, and the VCO bias current and is given by Velocity Offset Voltage = R6 × (VCO bias current) The temperature coefficient of this offset is given by where the VCO bias current tempco is typically +0.22 nA/°C. The maximum recommended rate for the VCO is 1.1 MHz which sets the maximum possible tracking rate. Since the minimum voltage swing available at the integrator output is ± 8 V, this implies that the minimum value for R6 is 62 kΩ. As Max Current = MinValue R 6 Transfer Function PHASE PLOT 180 135 90 45 0 –45 –90 –135 –180 0.0 GAIN PLOT 12 9 6 3 0 –3 –6 –9 –12 0.0 = 8.5 kHz/µA 0.04 0.1 0.2 0.4 FREQUENCY – fBW 1 2 Figure 5. Gain Plot Velocity Offset Tempco = R6 × (VCO bias current tempco) 0.04 1.1 × 10 6 3 0.1 0.2 0.4 FREQUENCY – fBW 1 2 8.5 × 10 8 = 129 µA = 62 k Ω Figure 6. Phase Plot 129 × 10 –6 By selecting components using the method outlined in the section “Component Selection,” the converter will have a critically damped time response and maximum phase margin. The Closed-Loop Transfer Function is given by: 14 (1 + s N ) θOUT = 2 θ IN ( s N + 2.4)( s N + 3.4 s N + 5.8) where, sN, the normalized frequency variable is given by: s 2 sN = π f BW and fBW is the closed-loop 3 dB bandwidth (selected by the choice of external components). The acceleration constant KA, is given approximately by K A = 6 × ( f BW ) sec 2 –2 The normalized gain and phase diagrams are given in Figures 5 and 6. REV. D –13– AD2S83 The small signal step response is shown in Figure 7. The time from the step to the first peak is t1, and the t2 is the time from the step until the converter is settled to 1 LSB. The times t1 and t2 are given approximately by t1 = t2 = 1 f BW 5 f BW × R 12 POSITION DEMAND + – The only effective way to compensate for dynamic loading effects is to introduce a 2nd order term which will provide the motor with an acceleration or deceleration demand signal (see Figure 9). CONTROL TERMS MOTOR where R = resolution, i.e., 10, 12, 14 or 16. t2 ACTUAL POSITION VELOCITY ELECTRONICS POSITION ELECTRONICS FEEDBACK SOURCE Figure 9. Position Control and Velocity Control t1 TIME Traditionally this would need to be implemented by using separate position and speed feedback transducers, e.g., an encoder or resolver and a dc tachogenerator. The AD2S83 can decode the resolver to provide both velocity and position information. DC Tachogenerator Figure 7. Small Step Response The large signal step response (for steps greater than 5 degrees) applies when the error voltage exceeds the linear range of the converter. Typically the converter will take three times longer to reach the first peak for a 179 degrees step. In response to a velocity step, the velocity output will exhibit the same time response characteristics as outlined above for the position output. THE AD2S83 AS A SILICON TACHOGENERATOR Position Control Using the AD2S83 The DC tachogenerator is a small permanent magnet dc generator. The output is a dc voltage which is proportional to the speed of the rotor and whose polarity is determined by the direction of rotation. Physically they are similar to a resolver. Velocity Error Derivation The AD2S83 has been optimized for use as a feedback device for velocity as well as position. A traditional position control loop shown below compares a demand position with an actual to derive a position error and hence a velocity demand. POSITION DEMAND MOTOR + – CONTROL TERMS The velocity error is the difference between the synthesized dc velocity demand derived from the actual and demand positions and the feedback from the tachogenerator or the AD2S83. The velocity demand is usually derived via a DAC so apart from any quantization noise it is clean. The velocity feedback, therefore, needs to be as close to a pure dc level as possible. The errors which determine the quality of the resultant acceleration demand to the motor are explained below. Linearity Linearity is the maximum deviation from the ideal straight line velocity characteristic. The line used is given by: v = mx + c where v = velocity m = gain scaling x = dc voltage c = zero velocity dc offset ACTUAL POSITION POSITION ELECTRONICS FEEDBACK SOURCE Linearity is generally a function of the input velocity to the tachogenerator or resolver. Reversion Error Figure 8. Position Control Quality of control may be reduced if the load on a motor varies dynamically. System reaction and compensation for a sudden change in the loading depends on how rapidly the system can update the velocity demand to the motor. This can cause rapid acceleration of the motor until the loop updates with a new velocity demand. Reversion or reversal error is an offset which is dependent on the direction of rotation of the transducer; e.g., if 10 rps = 1.000 V dc, then –10 rps = 1.003 V dc with +0.3% reversion error and FSO = ± 8 V dc. Zero Velocity DC Offset This is a residual dc offset present at zero input velocity. This can be externally nulled. –14– REV. D AD2S83 Ripple Content ACCELERATION ERROR Ripple content is due to several factors. Tachogenerators suffer from ripple due to the speed of rotation, commutator segments and the number of poles. The resolver/RDC combination has a predominant ripple at twice the resolver reference as a result of the synchronous demodulator and at a frequency twice per revolution due to the resolver windings mismatch. Motor torque pulsations which are a consequence of excessive velocity ripple have a detrimental effect upon the quality of speed control in servo systems. The resultant “cogging” effect will be particularly noticeable at low speed and when the motor is in the low torque region. Other undesirable side effects such as the increase in acoustic noise from a motor and a temperature rise in the motor stator windings are possible results of the presence of torque ripple. For more detailed information of the causes and sources of errors see the Velocity Errors section. AD2S83 COMPARISON WITH DC TACHOGENERATOR A tracking converter employing a Type 2 servo loop does not suffer any velocity lag, however, there is an additional error due to acceleration. This additional error can be defined using the acceleration constant KA of the converter. KA = Input Acceleration Error in Output Angle The numerator and denominator must have consistent angular units. For example if KA is in sec–2, then the input acceleration may be specified in degrees/sec2 and the error output in degrees. KA does not define maximum input acceleration, only the error due to acceleration. The maximum acceleration allowable before the converter loses track is dependent on the angular accuracy requirements of the system. Angular Accuracy × KA = Degrees/sec2 KA can be used to predict the output position error for a given input acceleration. For example for an acceleration of 100 revs/sec2, KA = 2.7 × 106 sec–2 and 12-bit resolution. Error in LSBs = 100 [rev /sec ] × 2 2.7 × 10 6 2 12 Comparative tests of the AD2S83 and a dc tachogenerator were carried out. The tachogenerator was connected at the nondrive end of the motor shaft with the resolver located behind the drive shaft of the motor. The AD2S83 was located remotely. The AD2S83 was set up with a 200 Hz bandwidth, reference frequency of 2.6 kHz and resolution of 14 bits. The comparative analysis can be summarized: AD2S83 Linearity % 0.1 Reversion Error % FSO 0.3 DC Tacho Conditions 0.1 0.25 0-3600 rpm Input acceleration [ LSB / sec ] K A [sec –2 2 ] = = 0.15 LSBs or 47.5 seconds of arc To determine the value of KA based on the passive components used to define the dynamics of the converter the following should be used. Note the typical operating range of dc tachogenerator is 0 rpm-3600 rpm. The resolver/AD2S83 combination will operate up to speeds in excess of 10000 rpm. Ripple Effects 2 × R 6 × R 4 × ( C 4 + C 5) Where n = resolution of the converter. R4, R6 in ohms C5, C4 in farads. KA = 4.04 × 10 n 11 The comparative analysis of the output ripple from the tachogenerator and the AD2S83 is illustrated below. Minimization of the AD2S83 output ripple is discussed in detail in the Velocity Errors section. Other Factors Other factors concerning choice of feedback source have to be addressed. On average the MTBF of a tachogenerator is 347 days as opposed to typically 8 years for a resolver. Resolvers are relatively insensitive to temperature whereas a tachogenerator will be specified up to a maximum of 100°C with a ± 0.1%/°C (above 25°C) degradation in output voltage. The brushless resolver requires no preventative maintenance; the brushes on a tachogenerator, however, will require periodic checking. REV. D –15– AD2S83 SOURCES OF ERRORS Integrator Offset VELOCITY ERRORS Additional inaccuracies in the conversion of the resolver signals will result from an offset at the input to the integrator. This offset will be treated as an error signal. The resulting angular error will typically be 1 arc minute over the operating temperature range. A description of how to adjust the zero offset is given in the Component Selection section; the circuit required is shown in Figure 1. Differential Phase Shift Some “ripple” or noise will always be present in the velocity signal. Velocity signal ripple is caused by, or related to, the following parameters. The resulting effects are generally additive. This means diagnosis needs to be an iterative process in order to define the source of the error. 1.0 Reference Frequency A ripple content at the reference frequency is superimposed on the velocity signal output. The amplitude depends on the loop bandwidth. This error is a function of a dc offset at the input to Phase Sensitive Demodulator (PSD). 2.0 Resolver Inaccuracies Impedance mismatch occur in the sine and cosine windings of the resolver. These give rise to differential phase shift between the sine and cosine inputs to the RDC and variations in the resolver output amplitudes. 2.1 Sine and Cosine Amplitude Mismatch This is normally identified by the presence of asymmetrical ripple voltages. 2.2 Differential Phase Shift between the Sine and Cosine Inputs The frequency of this ripple is usually twice the input velocity, and the amplitude is proportional to the magnitude of the velocity signal. The phase shift is normally induced through the connections from the resolver to the converter. Maintaining equal lengths of screened twisted pair cable from the resolver to the AD2S83 will reduce the effects of resistive imbalance, and therefore, reduce differential phase shift. 3.0 LSB Update Ripple LSB update noise occurs as the resolver rotates and the digital outputs of the RDC are updated. For a correctly scaled loop, this ripple component has a magnitude of approximately 2 mV peak at 16-bit resolution. 3.1 Ripple due to the LSB rate given by: LSB rate = N × Reference Frequency The PSD generates sums and differences of all its component input frequencies, so when the LSB update rate is an multiple of the reference frequency, a beat frequency is generated. The magnitude of this ripple is a function of the LSB weighting, i.e., ripple is less at 16 bits. 4.0 Torque Ripple Torque ripple is a phenomenon associated with motors. An ac motor naturally exhibits a sinusoidal back emf. In an ideal system the current fed to the motor should, in order to cancel, also be sinusoidal. In practice the current is often trapezoidal. Consequently, the output torque from the motor will not be smooth and torque ripple is created. If the loading on a motor is constant, the velocity of the motor shaft will vary as a result of the cyclic variation of motor torque. The variation in velocity then appears on the velocity output as ripple. This is not an error but a true velocity variation in the system. Phase shift between the sine and cosine signals from the resolver is known as differential phase shift and can cause static error. Some differential phase shift will be present on all resolvers as a result of coupling. A small resolver residual voltage (quadrature voltage) indicates a small differential phase shift. Additional phase shift can be introduced if the sine channel wires and the cosine channel wires are treated differently. For instance, different cable lengths or different loads could cause differential phase shift. The additional error caused by differential phase shift on the input signals approximates to Error = 0.53 a × b arc minutes where a = differential phase shift (degrees). b = signal to reference phase shift (degrees). This error can be minimized by choosing a resolver with a small residual voltage, ensuring that the sine and cosine signals are handled identically and removing the reference phase shift (see the Connecting the Resolver section). By taking these precautions the extra error can be made insignificant. Most resolvers exhibit a phase shift between the signal and the reference. This phase shift will, however, give rise under dynamic conditions to an additional error defined by: Shaft Speed ( rps ) × Phase Shift ( Degrees ) Reference Frequency = Error Degrees Under static operating conditions phase shift between the reference and the signal lines alone will not theoretically affect the converter’s static accuracy. For example, for a phase shift of 20 degrees, a shaft rotation of 22 rps and a reference frequency of 5 kHz, the converter will exhibit an additional error of: 22 × 20 5000 This effect can be eliminated by placing a phase shift in the reference to the converter equivalent to the phase shift in the resolver (see the Connecting the Resolver section). Note: Capacitive and inductive crosstalk in the signal and reference leads and wiring can cause similar problems. = 0.088 Degrees –16– REV. D AD2S83 Offset Errors The limiting factor in the measuring of low or “creep” speeds is the level of dc offset present at zero velocity. The zero velocity dc offset at the output of the AD2S83 is a function of the input bias current to the VCO and the value for the input resistor R6. See “Circuit Functions and Dynamic Performance VCO.” The offset can be minimized by reducing the maximum tracking rate so reducing the value for R6. Offset is a function of tracking rate and therefore resolution; the dc offset is lowest at 16 bits. To increase the dynamic range of the velocity dynamic resolution switching can be employed. (Contact MCG Applications for more information.) CONNECTING THE RESOLVER PHASE LEAD = ARC TAN C 1 2 fRC PHASE LAG = ARC TAN 2 fRC R R PHASE SHIFT CIRCUITS C Figure 10. Phase Shift Circuits TYPICAL CIRCUIT CONFIGURATION The recommended connection circuit is shown in Figure 11. In cases where the reference phase relative to the input signals from the resolver requires adjustment, this can be easily achieved by varying the value of the resistor R2 of the HF filter (see Figure 1). Assume that R1 = R2 = R and C1 = C2 = C 1 Figure 11 shows a typical circuit configuration for the AD2S83 with 12-bit resolution. Values of the external components have been chosen for a reference frequency of 5 kHz and a maximum tracking rate of 260 rps with a bandwidth of 520 Hz. Placing the values for R4, R6, C4 and C5 in the equation for KA gives a value of 2.7 × 106. The resistors are 0.125 W, 5% tolerance preferred values. The capacitors are 100 V ceramic, 10% tolerance components. For signal and reference voltages greater than 2 V rms a simple voltage divider circuit of resistors can be used to generate the correct signal level at the converter. Care should be taken to ensure that the ratios of the resistors between the sine signal line and ground and the cosine signal line and ground are the same. Any difference will result in an additional position error. For more information on resistive scaling of SIN, COS and REFERENCE converter inputs refer to the application note, “Circuit Applications of the 2S81 and 2S80 Resolver-to-Digital Converters.” and Reference Frequency = 2 π RC . By altering the value of R2, the phase of the reference relative to the input signals will change in an approximately linear manner for phase shifts of up to 10 degrees. Increasing R2 by 10% introduces a phase lag of two degrees. Decreasing R2 by 10% introduces a phase lead of two degrees. R9 1M R8 4.7M REFERENCE INPUT 100nF COS HIGH REF LOW COS LOW SIN LOW C3 100nF R3 100k C1 2.2nF R1 15k C2 2.2nF R2 15k R6 62k C7 150pF R4 110k C4 1.5nF R5 180k C5 6.8nF VELOCITY O/P RESOLVER SIGNAL R7 3.3k C6 390pF 100nF 6 SIN HIGH +12V 7 8 9 MSB 10 11 12 DATA OUTPUT 13 14 15 16 17 5 4 3 2 1 44 43 42 41 40 39 38 37 36 RIPPLE CLOCK DIRECTION BUSY COMPLEMENT DATA LOAD –12V AD2S83 TOP VIEW (Not to Scale) 35 34 33 32 31 30 29 SC2 0V INHIBIT 18 19 20 21 22 23 24 25 26 27 28 ENABLE BYTE SELECT LSB +5V DATA OUTPUT NOTE: R7, C6 AND C7 SHOULD BE CONNECTED AS CLOSE AS POSSIBLE TO THE CONVERTER PINS. SIGNAL SCREENS SHOULD BE CONNECTED TO PIN 5. Figure 11. Typical Circuit Configuration REV. D –17– AD2S83 APPLICATIONS Control Transformer OTHER PRODUCT The ratio multiplier of the AD2S83 can be used independently of the loop integrators as a control transformer. In this mode, the resolver inputs θ are multiplied by a digital angle φ, any difference between φ and θ will be represented by the AC ERROR output as Sin ωt sin (θ–φ) or the DEMOD output as sin (θ–φ). To use the AD2S83 in this mode refer to the “Control Transformer” application note. AD2S90. Low-cost resolver-to-digital converter with outputs which emulate optical encoders and a serial output for absolute position information. Unlike the AD2S83, the AD2S90 requires no external components to operate. The AD2S90 is built on LC2MOS and packaged in a 20-lead PLCC. AD2S80A/AD2S81A/AD2S82A. Monolithic resolver-to-digital converter. The AD2S80/AD2S82A offer selectable 10, 12, 14, 16 bits of resolution. The AD2S81A has 12-bit resolution. All devices have user selectable dynamics. The AD2S80A is available in 40-lead DDIP, 44-lead LCC and is qualified to MIL-STD883B REV. D. The AD2S82A is available in a 44-lead PLCC, and the AD2S81A in a 28-lead DDIP. –18– REV. D AD2S83 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Plastic Leaded Chip Carrier (PLCC) (P-44A) C1623b–.5–8/98 PRINTED IN U.S.A. 0.180 (4.57) 0.165 (4.19) 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 6 7 PIN 1 IDENTIFIER 0.056 (1.42) 0.042 (1.07) 40 39 0.025 (0.63) 0.015 (0.38) 0.050 (1.27) BSC 0.63 (16.00) 0.59 (14.99) TOP VIEW (PINS DOWN) 0.021 (0.53) 0.013 (0.33) 0.032 (0.81) 0.026 (0.66) 0.040 (1.01) 0.025 (0.64) 0.110 (2.79) 0.085 (2.16) 17 18 29 28 0.020 (0.50) R 0.656 (16.66) SQ 0.650 (16.51) 0.695 (17.65) SQ 0.685 (17.40) REV. D –19–