AD4003BCPZ-RL7

18-Bit, 2 MSPS Precision SAR Differential ADC AD4003 Data Sheet FEATURES GENERAL DESCRIPTION The AD4003 is a low noise, low power, high speed, 18-bit, 2 MSPS precision successive approximation register (SAR) analog-todigital converter (ADC). It incorporates ease of use features that lower the signal chain power, reduce signal chain complexity, and enable higher channel density. The high-Z mode, coupled with a long acquisition phase, eliminates the need for a dedicated high power, high speed ADC driver, thus broadening the range of low power precision amplifiers that can drive this ADC directly, while still achieving optimum performance. The input span compression feature enables the ADC driver amplifier and the ADC to operate off common supply rails without the need for a negative supply while preserving the full ADC code range. The low serial peripheral interface (SPI) clock rate requirement reduces the digital input/output power consumption, broadens processor options, and simplifies the task of sending data across digital isolation. Throughput: 2 MSPS maximum INL: ±1.0 LSB (±3.8 ppm) maximum Guaranteed 18-bit no missing codes Low power 9.5 mW at 2 MSPS (VDD only) 80 µW at 10 kSPS, 16 mW at 2 MSPS (total) SNR: 100.5 dB typical at 1 kHz, 99 dB typical at 100 kHz THD: −123 dB typical at 1 kHz, −100 dB typical at 100 kHz Ease of use features reduce system power and complexity Input overvoltage clamp circuit Reduced nonlinear input charge kickback High-Z mode Long acquisition phase Input span compression Fast conversion time allows low SPI clock rates SPI-programmable modes, read/write capability, status word Differential analog input range: ±VREF 0 V to VREF with VREF between 2.4 V to 5.1 V Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface SAR architecture: no latency/pipeline delay Guaranteed operation: −40°C to 125°C Serial interface SPI-/QSPI-/MICROWIRE-/DSP-compatible Ability to daisy-chain multiple ADCs and busy indicator 10-lead package: 3 mm × 3 mm LFCSP and 3 mm × 4.90 mm MSOP Operating from a 1.8 V supply, the AD4003 has a ±VREF fully differential input range with VREF ranging from 2.4 V to 5.1 V. The AD4003 consumes only 16 mW at 2 MSPS with a minimum of 75 MHz SCK rate in turbo mode and achieves ±1.0 LSB (±3.8 ppm) INL maximum, guaranteed no missing codes at 18 bits with 100.5 dB typical SNR. The reference voltage is applied externally and can be set independently of the supply voltage. The SPI-compatible versatile serial interface features seven different modes including the ability, using the SDI input, to daisy-chain several ADCs on a single 3-wire bus and provides an optional busy indicator. The AD4003 is compatible with 1.8 V, 2.5 V, 3 V, and 5 V logic, using the separate VIO supply. APPLICATIONS Automatic test equipment Machine automation Medical equipment Battery-powered equipment Precision data acquisition systems The AD4003 is available in a 10-lead MSOP or a 10-lead LFCSP with operation specified from −40°C to +125°C. The device is pin compatible with the 16-bit, 2 MSPS AD4000. FUNCTIONAL BLOCK DIAGRAM 2.5V TO 5V 10µF 1.8V REF VREF VREF /2 0 HIGH-Z MODE VDD VIO 1.8V TO 5V AD4003 TURBO MODE IN+ 18-BIT SAR ADC IN– SERIAL INTERFACE STATUS BITS SPAN CLAMP COMPRESSION GND SDI SCK SDO CNV 3-WIRE OR 4-WIRE SPI INTERFACE (DAISY CHAIN, CS) 14957-001 VREF VREF /2 0 Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD4003 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Driver Amplifier Choice ........................................................... 19 Applications ....................................................................................... 1 Ease of Drive Features ............................................................... 19 General Description ......................................................................... 1 Voltage Reference Input ............................................................ 21 Functional Block Diagram .............................................................. 1 Power Supply............................................................................... 21 Revision History ............................................................................... 2 Digital Interface .......................................................................... 21 Specifications..................................................................................... 3 Register Read/Write Functionality........................................... 22 Timing Specifications .................................................................. 5 Status Word ................................................................................. 24 Absolute Maximum Ratings............................................................ 7 CS Mode, 3-Wire Turbo Mode ................................................. 25 ESD Caution .................................................................................. 7 CS Mode, 3-Wire Without Busy Indicator ............................. 26 Pin Configurations and Function Descriptions ........................... 8 CS Mode, 3-Wire with Busy Indicator .................................... 27 Terminology ...................................................................................... 9 CS Mode, 4-Wire Turbo Mode ................................................. 28 Typical Performance Characteristics ........................................... 10 CS Mode, 4-Wire Without Busy Indicator ............................. 29 Theory of Operation ...................................................................... 14 Circuit Information .................................................................... 14 Converter Operation .................................................................. 14 Transfer Functions...................................................................... 15 Applications Information .............................................................. 16 Typical Connection Diagram ................................................... 16 Analog Inputs .............................................................................. 17 CS Mode, 4-Wire with Busy Indicator .................................... 30 Daisy-Chain Mode ..................................................................... 31 Layout Guidelines....................................................................... 32 Evaluating the AD4003 Performance....................................... 32 Outline Dimensions ....................................................................... 33 Ordering Guide .......................................................................... 33 REVISION HISTORY 10/2016—Revision 0: Initial Version Rev. 0 | Page 2 of 33 Data Sheet AD4003 SPECIFICATIONS VDD = 1.71 V to 1.89 V; VIO = 1.71 V to 5.5 V; VREF = 5 V; all specifications TMIN to TMAX, high-Z mode disabled, span compression disabled, and turbo mode enabled (fS = 2 MSPS), unless otherwise noted. Table 1. Parameter RESOLUTION ANALOG INPUT Voltage Range Operating Input Voltage Common-Mode Input Range Common-Mode Rejection Ratio (CMRR) Analog Input Current Test Conditions/Comments Min 18 VIN+ − VIN− Span compression enabled VIN+, VIN− to GND Span compression enabled −VREF −VREF × 0.8 −0.1 0.1 × VREF VREF/2 − 0.125 fIN = 500 kHz Acquisition phase, T = 25°C High-Z mode enabled, converting dc input at 2 MSPS THROUGHPUT Complete Cycle Conversion Time Acquisition Phase 1 Throughput Rate 2 Transient Response 3 DC ACCURACY No Missing Codes Integral Linearity Error Differential Linearity Error Transition Noise Zero Error Zero Error Drift 4 Gain Error Gain Error Drift4 Power Supply Sensitivity 1/f Noise 5 AC ACCURACY Dynamic Range Total RMS Noise fIN = 1 kHz, −0.5 dBFS, VREF = 5 V Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Total Harmonic Distortion (THD) Signal-to-Noise-and-Distortion Ratio (SINAD) Oversampled Dynamic Range Typ VREF/2 68 0.3 1 Max Unit Bits +VREF +VREF × 0.8 VREF + 0.1 0.9 × VREF VREF/2 + 0.125 V V V V V dB nA µA 500 290 290 0 320 2 250 18 −1.0 −3.8 −0.75 −7 −0.21 −26 −1.23 VDD = 1.8 V ± 5% Bandwidth = 0.1 Hz to 10 Hz 99 98.5 Oversampling ratio (OSR) = 256, VREF = 5 V fIN = 1 kHz, −0.5 dBFS, VREF = 2.5 V SNR SFDR THD SINAD 93.5 93 Rev. 0 | Page 3 of 33 ns ns ns MSPS ns 1.5 6 Bits LSB ppm LSB LSB LSB ppm/°C LSB ppm/°C LSB µV p-p 101 31.5 dB µV rms 100.5 122 −123 100 dB dB dB dB 122 dB 94.5 122 −119 94 dB dB dB dB ±0.4 ±1.52 ±0.3 0.8 ±3 +1.0 +3.8 +0.75 +7 +0.21 +26 +1.23 AD4003 Parameter fIN = 100 kHz, −0.5 dBFS, VREF = 5 V SNR THD SINAD fIN = 400 kHz, −0.5 dBFS, VREF = 5 V SNR THD SINAD −3 dB Input Bandwidth Aperture Delay Aperture Jitter REFERENCE Voltage Range (VREF) Current OVERVOLTAGE CLAMP IIN+/IIN− VIN+/VIN− at Maximum IIN+/IIN− VIN+/VIN− Clamp On/Off Threshold Deactivation Time REF Current at Maximum IIN+/IIN− DIGITAL INPUTS Logic Levels Input Low Voltage, VIL Input High Voltage, VIH Data Sheet Test Conditions/Comments POWER SUPPLIES VDD VIO Standby Current Power Dissipation VDD Only REF Only Typ VREF = 5 V VREF = 2.5 V VREF = 5 V VREF = 2.5 V VREF = 5 V VREF = 2.5 V VIN+/VIN− > VREF 91.5 −94 90 10 1 1 dB dB dB MHz ns ps rms 5.1 V mA 50 50 mA mA V V V V ns µA +0.3 × VIO +0.2 × VIO VIO + 0.3 VIO + 0.3 +1 +1 V V V V µA µA pF 5.4 3.1 5.4 2.8 360 100 −0.3 −0.3 0.7 × VIO 0.8 × VIO −1 −1 6 ISINK = 500 µA ISOURCE = −500 µA Serial 18 bits, twos complement Conversion results available immediately after completed conversion 0.4 VIO − 0.3 1.71 1.71 VDD = 1.8 V, VIO = 1.8 V, T = 25°C VDD = 1.8 V, VIO = 1.8 V, VREF = 5 V 10 kSPS, high-Z mode disabled 1 MSPS, high-Z mode disabled 2 MSPS, high-Z mode disabled 1 MSPS, high-Z mode enabled 2 MSPS, high-Z mode enabled 2 MSPS, high-Z mode disabled 2 MSPS, high-Z mode disabled Rev. 0 | Page 4 of 33 Unit dB dB dB 1.1 5.25 2.68 VIO > 2.7 V VIO ≤ 2.7 V VIO > 2.7 V VIO ≤ 2.7 V Max 99 −100 96.5 2.4 2 MSPS, VREF = 5 V Input Low Current, IIL Input High Current, IIH Input Pin Capacitance DIGITAL OUTPUTS Data Format Pipeline Delay Output Low Voltage, VOL Output High Voltage, VOH Min 1.8 1.89 5.5 V V 1.6 V V µA 80 8 16 10 20 9.5 5.5 µW mW mW mW mW mW mW 18.5 24.5 Data Sheet Parameter VIO Only Energy per Conversion TEMPERATURE RANGE Specified Performance AD4003 Test Conditions/Comments 2 MSPS, high-Z mode disabled Min TMIN to TMAX −40 Typ 1.0 8 Max Unit mW nJ/sample +125 °C The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS. A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 75 MHz. Refer to Table 4 for the maximum achievable throughput for different modes of operation. 3 Transient response is the time required for the ADC to acquire a full-scale input step to ±1 LSB accuracy. 4 The minimum and maximum values are guaranteed by characterization, not production tested. 5 See the 1/f noise plot in Figure 18. 1 2 TIMING SPECIFICATIONS VDD = 1.71 V to 1.89 V; VIO = 1.71 V to 5.5 V; VREF = 5 V; all specifications TMIN to TMAX, high-Z mode disabled, span compression disabled, and turbo mode enabled (fS = 2 MSPS), unless otherwise noted. 1 Table 2. Digital Interface Timing Parameter Conversion Time—CNV Rising Edge to Data Available Acquisition Phase 2 Time Between Conversions CNV Pulse Width (CS Mode) 3 SCK Period (CS Mode) 4 VIO > 2.7 V VIO > 1.7 V SCK Period (Daisy-Chain Mode) 5 VIO >2.7 V VIO > 1.7 V SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid Delay SCK Falling Edge to Data Valid Delay VIO >2.7 V VIO >1.7 V CNV or SDI Low to SDO D17 MSB Valid Delay (CS Mode) VIO >2.7 V VIO >1.7 V CNV Rising Edge to First SCK Rising Edge Delay Last SCK Falling Edge to CNV Rising Edge Delay 6 CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) SDI Valid Setup Time from CNV Rising Edge SDI Valid Hold Time from CNV Rising Edge (CS Mode) SCK Valid Hold Time from CNV Rising Edge (Daisy-Chain Mode) SDI Valid Setup Time from SCK Rising Edge (Daisy-Chain Mode) SDI Valid Hold Time from SCK Rising Edge (Daisy-Chain Mode) Symbol tCONV tACQ tCYC tCNVH tSCK Min Typ 290 Max 320 290 500 10 Unit ns ns ns ns 9.8 12.3 ns ns 20 25 3 3 1.5 ns ns ns ns ns tSCK tSCKL tSCKH tHSDO tDSDO 7.5 10.5 ns ns 10 13 ns ns ns ns ns ns ns ns ns ns tEN tQUIET1 tQUIET2 tDIS tSSDICNV tHSDICNV tHSCKCNV tSSDISCK tHSDISCK 190 60 20 2 2 12 2 2 See Figure 2 for the timing voltage levels. The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS. 3 For turbo mode, tCNVH must match the tQUIET1 minimum. 4 A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 75 MHz. 5 A 50% duty cycle is assumed for SCK. 6 See Figure 22 for SINAD vs. tQUIET2. 1 2 Rev. 0 | Page 5 of 33 AD4003 Data Sheet Table 3. Register Read/Write Timing Parameter READ/WRITE OPERATION CNV Pulse Width 1 SCK Period VIO > 2.7 V VIO > 1.7 V SCK Low Time SCK High Time READ OPERATION CNV Low to SDO D17 MSB Valid Delay VIO > 2.7 V VIO > 1.7 V SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO >2.7 V VIO >1.7 V CNV Rising Edge to SDO High Impedance WRITE OPERATION SDI Valid Setup Time from SCK Rising Edge SDI Valid Hold Time from SCK Rising Edge CNV Rising Edge to SCK Edge Hold Time CNV Falling Edge to SCK Active Edge Setup Time 1 Symbol Min tCNVH tSCK 10 ns 9.8 12.3 3 3 ns ns ns ns tSCKL tSCKH Typ Max Unit tEN tHSDO tDSDO 10 13 ns ns ns 7.5 10.5 20 ns ns ns 1.5 tDIS tSSDISCK tHSDISCK tHCNVSCK tSCNVSCK 2 2 0 6 ns ns ns ns For turbo mode, tCNVH must match the tQUIET1 minimum. Y% VIO1 X% VIO1 tDELAY tDELAY VIH2 VIL2 1FOR VIO ≤ 2.7V, X = 80, AND Y = 20; FOR VIO > 2.7V, X = 70, AND Y = 30. VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS SPECIFICATIONS IN TABLE 1. 2MINIMUM 14957-002 VIH2 VIL2 Figure 2. Voltage Levels for Timing Table 4. Achievable Throughput for Different Modes of Operation Parameter THROUGHPUT, CS MODE 3-Wire and 4-Wire Turbo Mode 3-Wire and 4-Wire Turbo Mode and Six Status Bits 3-Wire and 4-Wire Mode 3-Wire and 4-Wire Mode and Six Status Bits Test Conditions/Comments fSCK = 100 MHz, VIO ≥ 2.7 V fSCK = 80 MHz, VIO < 2.7 V fSCK = 100 MHz, VIO ≥ 2.7 V fSCK = 80 MHz, VIO < 2.7 V fSCK = 100 MHz, VIO ≥ 2.7 V fSCK = 80 MHz, VIO < 2.7 V fSCK = 100 MHz, VIO ≥ 2.7 V fSCK = 80 MHz, VIO < 2.7 V Rev. 0 | Page 6 of 33 Min Typ Max Unit 2 2 2 1.78 1.75 1.62 1.59 1.44 MSPS MSPS MSPS MSPS MSPS MSPS MSPS MSPS Data Sheet AD4003 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 5. Parameter Analog Inputs IN+, IN− to GND1 Supply Voltage REF, VIO to GND VDD to GND VDD to VIO Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature Lead Temperature Soldering ESD Ratings Human Body Model Machine Model Field-Induced Charged Device Model 1 Rating −0.3 V to VREF + 0.4 V or ± 50 mA −0.3 V to +6.0 V −0.3 V to +2.1 V −6 V to +2.4 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.3 V −65°C to +150°C 150°C 260°C reflow as per JEDEC J-STD-020 Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Table 6. Thermal Resistance Package Type RM-101 CP-10-91 1 θJA 147 114 θJC 38 33 Unit °C/W °C/W Test Condition 1: thermal impedance simulated values are based upon use of 2S2P JEDEC PCB. See the Ordering Guide. ESD CAUTION 4 kV 200 V 1.25 kV See the Analog Inputs section for an explanation of IN+ and IN−. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Note that the clamp cannot sustain the overvoltage condition for an indefinite time. Rev. 0 | Page 7 of 33 AD4003 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS REF 1 IN+ 3 REF 1 10 VIO IN– 4 VDD 2 AD4003 9 SDI GND 5 TOP VIEW (Not to Scale) 8 SCK 7 SDO 6 CNV IN– 4 GND 5 AD4003 TOP VIEW (Not to Scale) 9 SDI 8 SCK 7 SDO 6 CNV NOTES 1. CONNECT THE EXPOSED PAD TO GND. THIS CONNECTION IS NOT REQUIRED TO MEET THE SPECIFIED PERFORMANCE. 14957-003 IN+ 3 10 VIO Figure 3. 10-Lead MSOP Pin Configuration 14957-004 VDD 2 Figure 4. 10-Lead LFCSP Pin Configuration Table 7. Pin Function Descriptions Pin No. 1 Mnemonic REF Type1 AI 2 3 4 5 6 VDD IN+ IN− GND CNV P AI AI P DI 7 8 9 SDO SCK SDI DO DI DI 10 VIO P N/A2 EPAD P 1 2 Description Reference Input Voltage. The VREF range is 2.4 V to 5.1 V. This pin is referred to the GND pin and must be decoupled closely to the GND pin with a 10 μF X7R ceramic capacitor. 1.8 V Power Supply. The range of VDD is 1.71 V to 1.89 V. Bypass VDD to GND with a 0.1 μF ceramic capacitor. Differential Positive Analog Input. Differential Negative Analog Input. Power Supply Ground. Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the device: daisy-chain mode or CS mode. In CS mode, the SDO pin is enabled when CNV is low. In daisy-chain mode, the data is read when CNV is high. Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock. Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows. Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 18 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. With CNV low, the device can be programmed by clocking in a 16-bit word on SDI on the rising edge of SCK. Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). Bypass VIO to GND with a 0.1 μF ceramic capacitor. Exposed Pad (LFCSP Only). Connect the exposed pad to GND. This connection is not required to meet the specified performance. AI is analog input, P is power, DI is digital input, and DO is digital output. N/A means not applicable. Rev. 0 | Page 8 of 33 Data Sheet AD4003 TERMINOLOGY Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 30). Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Zero Error Zero error is the difference between the ideal midscale voltage, that is, 0 V, from the actual voltage producing the midscale output code, that is, 0 LSB. Gain Error The first transition (from 100 ... 00 to 100 ... 01) occurs at a level ½ LSB above nominal negative full scale (−4.999981 V for the ±5 V range). The last transition (from 011 … 10 to 011 … 11) occurs for an analog voltage 1½ LSB below the nominal full scale (+4.999943 V for the ±5 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured. The value for dynamic range is expressed in decibels. It is measured with a signal at −60 dBFS so that it includes all noise sources and DNL artifacts. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-Noise-and-Distortion Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components that are less than the Nyquist frequency, including harmonics but excluding dc. The value of SINAD is expressed in decibels. Aperture Delay Aperture delay is the measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Transient Response Transient response is the time required for the ADC to to acquire a full-scale input step to ±1 LSB accuracy. Common-Mode Rejection Ratio (CMRR) CMRR is the ratio of the power in the ADC output at the frequency, f, to the power of a 200 mV p-p sine wave applied to the common-mode voltage of IN+ and IN− of frequency, f. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD as follows: ENOB = (SINADdB − 1.76)/6.02 CMRR (dB) = 10log(PADC_IN/PADC_OUT) ENOB is expressed in bits. Noise Free Code Resolution Noise free code resolution is the number of bits beyond which it is impossible to distinctly resolve individual codes. It is calculated as Noise Free Code Resolution = log2(2N/Peak-to-Peak Noise) Noise free code resolution is expressed in bits. Effective Resolution Effective resolution is calculated as Effective Resolution = log2(2N/RMS Input Noise) Effective resolution is expressed in bits. where: PADC_IN is the common-mode power at the frequency, f, applied to the IN+ and IN− inputs. PADC_OUT is the power at the frequency, f, in the ADC output. Power Supply Rejection Ratio (PSRR) PSRR is the ratio of the power in the ADC output at the frequency, f, to the power of a 200 mV p-p sine wave applied to the ADC VDD supply of frequency, f. PSRR (dB) = 10 log(PVDD_IN/PADC_OUT) where: PVDD_IN is the power at the frequency, f, at the VDD pin. PADC_OUT is the power at the frequency, f, in the ADC output. Rev. 0 | Page 9 of 33 AD4003 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VDD = 1.8 V; VIO = 3.3 V; VREF = 5 V; T = 25°C, high-Z mode disabled, span compression disabled and turbo mode enabled (fS = 2 MSPS), unless otherwise noted. 1.0 0.4 0.8 +125°C +25°C –40°C 0.6 +125°C +25°C –40°C 0.3 0.2 0.2 DNL (LSB) INL (LSB) 0.4 0 –0.2 0.1 0 –0.1 –0.4 –0.2 –0.6 0 32768 65536 98304 131072 163840 196608 229376 262144 CODE –0.4 14957-200 –1.0 0 32768 Figure 5. INL vs. Code and Temperature, VREF = 5 V 65536 98304 131072 163840 196608 229376 262144 CODE 14957-203 –0.3 –0.8 Figure 8. DNL vs. Code and Temperature, VREF = 5 V 1.0 0.4 0.8 +125°C +25°C –40°C 0.6 0.3 0.2 0.2 DNL (LSB) INL (LSB) 0.4 0 –0.2 0.1 0 –0.1 –0.4 –0.2 –0.6 32768 65536 98304 131072 163840 196608 229376 262144 CODE –0.4 0 Figure 6. INL vs. Code and Temperature, VREF = 2.5 V 32768 65536 98304 131072 163840 196608 229376 262144 CODE Figure 9. DNL vs. Code and Temperature, VREF = 2.5 V 1.8 0.8 1.7 0.6 +125°C +25°C –40°C 1.6 TRANSITION NOISE (LSB) 0.4 0.2 INL (LSB) 14957-204 0 14957-201 –1.0 +125°C +25°C –40°C –0.3 –0.8 0 –0.2 –0.4 1.5 1.4 1.3 1.2 1.1 1.0 0 32768 65536 98304 131072 163840 196608 229376 262144 CODE 0.9 14957-202 –0.8 HIGH-Z ENABLED SPAN COMPRESSION ENABLED Figure 7. INL vs. Code, High-Z and Span Compression Modes Enabled, VREF = 5 V Rev. 0 | Page 10 of 33 0.8 2.5 3.0 3.5 4.0 4.5 REFERENCE VOLTAGE (V) Figure 10. Transition Noise vs. Reference Voltage 5.0 14957-206 –0.6 Data Sheet AD4003 4.5M 4.5M 3.0M 3.0M 2.5M 2.0M 1.0M 1.0M 0.5M 0.5M 0 0 14957-205 1.5M Figure 11. Histogram of a DC Input at Code Center, VREF = 2.5 V, 5 V CODE Figure 14. Histogram of a DC Input at Code Transition, VREF = 2.5 V, 5 V 0 0 VREF = 5V SNR = 100.33dB THD = –123.99dB SINAD = 100.31dB –40 –60 –80 –100 –120 –140 –160 1M –80 –100 –120 –140 –180 100 1k 100k 10k 1M FREQUENCY (Hz) Figure 15. 1 kHz, −0.5 dBFS Input Tone FFT, Wide View, VREF = 2.5 V 0 0 VREF = 5V SNR = 98.37dB THD = –98.52dB SINAD = 95.58dB FUNDAMENTAL AMPLITUDE (dB) –20 –60 –80 –100 –120 –140 –160 –40 VREF = 5V SNR = 91.22dB THD = –91.97dB SINAD = 89.15dB –60 –80 –100 –120 –140 10k 100k FREQUENCY (Hz) 1M Figure 13. 100 kHz, −0.5 dBFS Input Tone FFT, Wide View –180 1k 10k 100k FREQUENCY (Hz) Figure 16. 400 kHz, −0.5 dBFS Input Tone FFT, Wide View Rev. 0 | Page 11 of 33 1M 14957-213 –160 14957-210 –180 1k –60 14957-209 100k 10k 14957-207 1k Figure 12. 1 kHz, −0.5 dBFS Input Tone FFT, Wide View, VREF = 5 V –40 –40 –160 FREQUENCY (Hz) –20 VREF = 2.5V SNR = 95.01dB THD = –118.60dB SINAD = 94.99dB –20 FUNDAMENTAL AMPLITUDE (dB) –20 FUNDAMENTAL AMPLITUDE (dB) 2.0M 1.5M CODE FUNDAMENTAL AMPLITUDE (dB) 2.5M 131062 131063 131064 131065 131066 131067 131068 131069 131070 131071 131072 131073 131074 131075 131076 131077 131078 131079 131080 131081 DNL (LSB) 3.5M 131062 131063 131064 131065 131066 131067 131068 131069 131070 131071 131072 131073 131074 131075 131076 131077 131078 131079 131080 131081 DNL (LSB) 3.5M –180 100 VREF = 2.5V VREF = 5V 4.0M 14957-208 VREF = 2.5V VREF = 5V 4.0M AD4003 Data Sheet 16.6 102 101 –114 133 –116 132 16.4 –118 100 131 97 130 –122 129 SFDR (dB) 16.0 98 –120 THD (dB) 99 ENOB (Bits) SNR, SINAD (dB) 16.2 –124 15.8 128 –126 2.7 3.0 3.3 3.6 3.9 4.2 4.5 –128 15.4 5.1 4.8 –130 2.4 14957-219 94 2.4 SFDR THD 15.6 ENOB SINAD SNR 95 REFERENCE VOLTAGE (V) 2.7 3.3 3.6 3.9 4.2 4.5 126 5.1 4.8 REFERENCE VOLTAGE (V) Figure 17. SNR, SINAD, and ENOB vs. Reference Voltage Figure 20. THD and SFDR vs. Reference Voltage 60 1.1 1.0 REFERENCE CURRENT (mA) 59 58 57 56 55 0.9 0.8 0.7 0.6 0.5 0 1 2 3 4 5 6 7 8 9 10 TIME (Seconds) 0.4 2.4 14957-217 54 2.7 3.0 3.3 3.9 3.6 4.2 4.5 4.8 5.1 REFERENCE VOLTAGE (V) Figure 18. 1/f Noise for 0.1 Hz to 10 Hz Bandwidth, 50 kSPS, 2500 Samples Averaged per Reading 14957-218 ADC OUTPUT READING (µV) 3.0 127 14957-216 96 Figure 21. Reference Current vs. Reference Voltage 101 135 DYNAMIC RANGE fIN = 1kHz fIN = 10kHz 130 100 125 99 SINAD (dB) 115 110 98 97 105 95 0 2 4 8 16 32 64 128 256 512 1024 2048 DECIMATION RATE Figure 19. SNR vs. Decimation Rate for Various Input Frequencies 95 0 10 20 30 40 50 tQUIET2 (ns) Figure 22. SINAD vs. tQUIET2 Rev. 0 | Page 12 of 33 60 70 80 14957-215 VIO = 1.89V VIO = 3.6V VIO = 5.5V 96 100 14957-212 SNR (dB) 120 Data Sheet AD4003 16.42 16.40 THD SFDR –114.5 117.9 16.38 100.4 117.8 –115.0 16.32 100.0 16.30 THD (dB) 16.34 ENOB (Bits) 16.36 100.2 16.28 99.8 117.7 117.6 –115.5 117.5 –116.0 117.4 117.3 –116.5 16.26 99.6 117.2 –117.0 16.24 –20 0 20 40 60 80 16.22 120 100 14957-222 99.4 –40 TEMPERATURE (°C) 117.1 –117.5 –40 0 20 40 60 80 100 120 117.0 Figure 26. THD and SFDR vs. Temperature, fIN = 1 kHz 8 25.0 22.5 7 20.0 6 STANDBY CURRENT (µA) 5 VDD HIGH-Z DISABLED VDD HIGH-Z ENABLED REF HIGH-Z DISABLED REF HIGH-Z ENABLED VIO HIGH-Z DISABLED VIO HIGH-Z ENABLED 4 3 2 17.5 15.0 12.5 10.0 7.5 5.0 1 0 20 40 60 80 100 120 TEMPERATURE (°C) 0 –40 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 24. Operating Currents vs. Temperature Figure 27. Standby Current vs. Temperature 10 23 8 21 PFS GAIN ERROR NFS GAIN ERROR ZERO ERROR 6 VIO = 5V VIO = 3.3V VIO = 1.8V 19 4 17 tDSDO (ns) 2 0 –2 15 13 11 –4 9 –6 7 –20 0 20 40 60 TEMPERATURE (°C) 80 100 120 14957-221 –8 –10 –40 –20 14957-226 –20 14957-223 0 –40 2.5 Figure 25. Zero Error and Gain Error vs. Temperature (PFS Is Positive Full Scale and NFS Is Negative Full Scale) Rev. 0 | Page 13 of 33 5 0 20 40 60 80 100 120 140 160 LOAD CAPACITANCE (pF) Figure 28. tDSDO vs. Load Capacitance 180 200 220 14957-224 OPERATING CURRENT (mA) –20 TEMPERATURE (°C) Figure 23. SNR, SINAD, and ENOB vs. Temperature, fIN = 1 kHz ZERO ERROR AND GAIN ERROR (LSB) SNR, SINAD (dB) 118.0 SFDR (dB) ENOB SINAD SNR 100.6 –114.0 14957-225 100.8 AD4003 Data Sheet THEORY OF OPERATION IN+ SWITCHES CONTROL LSB MSB REF GND 131,072C 65,536C 4C 2C C SW+ C BUSY COMP 131,072C 65,536C 4C 2C C CONTROL LOGIC C MSB OUTPUT CODE LSB SW– 14957-007 CNV IN– Figure 29. ADC Simplified Schematic CIRCUIT INFORMATION The AD4003 is a high speed, low power, single-supply, precise, 18-bit ADC based on a SAR architecture. The AD4003 is capable of converting 2,000,000 samples per second (2 MSPS) and powers down between conversions. When operating at 10 kSPS, for example, it typically consumes 80 μW, making it ideal for battery-powered applications because its power scales linearly with throughput. The AD4003 has a valid first conversion after being powered down for long periods. The AD4003 provides the user with an on-chip track-and-hold and does not exhibit any pipeline delay or latency, making it ideal for multiplexed applications. The AD4003 incorporates a multitude of unique ease of use features that result in a lower system power and footprint. The AD4003 can be interfaced to any 1.8 V to 5 V digital logic family. It is available in a 10-lead MSOP or a tiny 10-lead LFCSP that allows space savings and flexible configurations. It is pin for pin compatible with the 14-/16-/18-bit precision SAR ADCs listed in Table 8. Table 8. MSOP, LFCSP 14-/16-/18-Bit Precision SAR ADCs Bits 181 161 163 The AD4003 has an internal voltage clamp that protects the device from overvoltage damage on the analog inputs. The analog input incorporates circuitry that reduces the nonlinear charge kickback seen from a typical switched capacitor SAR input. This reduction in kickback, combined with a longer acquisition phase, means reduced settling requirements on the driving amplifier. This combination allows the use of lower bandwidth and lower power amplifiers as drivers. It has the additional benefit of allowing a larger resistor value in the input RC filter and a corresponding smaller capacitor, which results in a smaller RC load for the amplifier, improving stability and power dissipation. High-Z mode can be enabled via the SPI interface by programming a register bit (see Table 14). When high-Z mode is enabled, the ADC input has low input charging current at low input signal frequencies as well as improved distortion over a wide frequency range up to 100 kHz. For frequencies above 100 kHz and multiplexing, disable high-Z mode. For single-supply applications, a span compression feature creates additional headroom and footroom for the driving amplifier to access the full range of the ADC. The fast conversion time of the AD4003, along with turbo mode, allows low clock rates to read back conversions even when running at the full 2 MSPS throughput rate. Note that a throughput rate of 2 MSPS can be achieved only with turbo mode enabled and a minimum SCK rate of 75 MHz. 143 1 2 3 100 kSPS AD7989-12 AD7684 AD7680, AD7683, AD7988-12 AD7940 250 kSPS AD76912 400 kSPS to 500 kSPS AD7690,2 AD7989-52 AD7687 AD7685,2 AD7694 AD7688,2 AD76932 AD7686,2 AD7988-5 AD79422 AD79462 ≥1000 kSPS AD4003, AD7982,2 AD79842 AD79152 AD4000 AD7980,2 AD79832 True differential. Pin for pin compatible. Pseudo differential. CONVERTER OPERATION The AD4003 is a SAR-based ADC using a charge redistribution sampling digital-to-analog converter (DAC). Figure 29 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 18 binary weighted capacitors, which are connected to the comparator inputs. During the acquisition phase, terminals of the array tied to the input of the comparator are connected to GND via SW+ and SW−. All independent switches connect the other terminal of each capacitor to the analog inputs. Therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN− inputs. Rev. 0 | Page 14 of 33 Data Sheet AD4003 When the acquisition phase is complete and the CNV input goes high, a conversion phase is initiated. When the conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. The differential voltage between the IN+ and IN− inputs captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and VREF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4, …, VREF/262,144). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of this process, the control logic generates the ADC output code and a busy signal indicator. Table 9. Output Codes and Ideal Input Voltages Description FSR − 1 LSB Midscale + 1 LSB Midscale Midscale − 1 LSB −FSR + 1 LSB −FSR 1 2 TRANSFER FUNCTIONS 011...111 011...110 011...101 100...010 100...001 –FSR + 1 LSB +FSR – 1 LSB +FSR – 1.5 LSB ANALOG INPUT 14957-008 ADC CODE (TWOS COMPLEMENT) The ideal transfer characteristics for the AD4003 are shown in Figure 30 and Table 9. –FSR + 0.5 LSB VREF = 5 V with Span Compression Enabled +3.999969 V +30.5 μV 0V −30.5 μV −3.999969 V −4 V Digital Output Code (Hex) 0x1FFFF1 0x00001 0x00000 0x3FFFF 0x20001 0x200002 This output code is also the code for an overranged analog input (VIN+ − VIN− above VREF). This output code is also the code for an underranged analog input (VIN+ − VIN− below −VREF). Because the AD4003 has an on-board conversion clock, the serial clock, SCK, is not required for the conversion process. 100...000 –FSR Analog Input, VREF = 5 V +4.999962 V +38.15 μV 0V −38.15 μV −4.999962 V −5 V Figure 30. ADC Ideal Transfer Function (FSR Is Full-Scale Range) Rev. 0 | Page 15 of 33 AD4003 Data Sheet APPLICATIONS INFORMATION Figure 32 shows a recommended connection diagram when using a single-supply system. This setup is preferable when only a limited number of rails are available in the system and power dissipation is of critical importance. TYPICAL APPLICATION DIAGRAMS Figure 31 shows an example of the recommended connection diagram for the AD4003 when multiple supplies are available. This configuration is used for best performance because the amplifier supplies can be selected to allow the maximum signal range. Figure 33 shows a recommended connection diagram when using a fully differential amplifier. V+ ≥ +6.5V REF1 LDO 1.8V AMP VCM = VREF /2 5V 10kΩ 0.1µF 10kΩ V+ AMP VREF VCM = VREF /2 0.1µF 1.8V TO 5V R REF C 0V VDD VIO SDI IN+ V– SCK AD4003 IN– R AMP CNV GND 3-WIRE/4-WIRE INTERFACE C 0V V– 14957-009 VCM = VREF /2 DIGITAL HOST (MICROPROCESSOR/ FPGA) SDO V+ VREF HOST SUPPLY 10µF V– ≤ –0.5V Figure 31. Typical Application Diagram with Multiple Supplies V+ = +5V REF1 LDO AMP VCM = VREF /2 1.8V 4.096V 10kΩ 10kΩ AMP 0.9 × VREF VCM = VREF /2 0.1 × VREF 0.1µF 0.1µF 100nF 100nF 1.8V TO 5V R REF C VDD VIO SDI IN+ AD40032 SCK SDO IN– AMP 0.9 × VREF VCM = VREF /2 0.1 × VREF HOST SUPPLY 10µF1 R GND DIGITAL HOST (MICROPROCESSOR/ FPGA) CNV 3-WIRE/4-WIRE INTERFACE C 1SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE 2SPAN COMPRESSION MODE ENABLED. 3SEE TABLE 9 FOR RC FILTER AND AMPLIFIER SELECTION. SELECTION. CREF IS USUALLY A 10µF CERAMIC CAPACITOR (X7R). Figure 32. Typical Application Diagram with a Single Supply Rev. 0 | Page 16 of 33 14957-010 3 Data Sheet AD4003 V+ = +5V REF LDO AMP VCM = VREF/2 VCM = VREF /2 R4 1kΩ R3 1kΩ VREF 10kΩ 0 1.8V 4.096V 1.8V TO 5V 0.1µF 0.1µF 10kΩ 10µF HOST SUPPLY V+ +IN VOCM –IN SDO IN– 3-WIRE/4-WIRE INTERFACE 14957-011 0 DIGITAL HOST (MICROPROCESSOR/ FPGA) CNV GND V– R1 1kΩ VREF SCK AD4003 R DIFFERENTIAL AMPLIFIER VIO SDI C +OUT 0.1µF VDD IN+ C VCM = VREF/2 VCM = VREF/2 REF R –OUT R2 1kΩ Figure 33. Typical Application Diagram with a Fully Differential Amplifier V+ = +5V REF LDO AMP 0V R4 1kΩ R3 1kΩ +VREF VCM = VREF /2 10kΩ –VREF 4.096V 10kΩ 10µF 1.8V 0.1µF 0.1µF 1.8V TO 5V HOST SUPPLY V+ +IN –OUT REF R C VREF/2 VOCM –IN DIFFERENTIAL AMPLIFIER R VIO SDI AD4003 C +OUT 0.1µF VDD IN+ IN– GND SCK SDO DIGITAL HOST (MICROPROCESSOR/ FPGA) CNV 3-WIRE/4-WIRE INTERFACE V– 14957-012 R1 1kΩ R2 1kΩ Figure 34. Typical Application Diagram for Single-Ended to Differential Conversion with a Fully Differential Amplifier ANALOG INPUTS Figure 35 shows an equivalent circuit of the analog input structure, including the overvoltage clamp of the AD4003. Input Overvoltage Clamp Circuit Most ADC analog inputs, IN+ and IN−, have no overvoltage protection circuitry apart from ESD protection diodes. During an overvoltage event, an ESD protection diode from an analog input (IN+ or IN−) pin to REF forward biases and shorts the input pin to REF, potentially overloading the reference or causing damage to the device. The AD4003 internal overvoltage clamp circuit with a larger external resistor (REXT = 200 Ω) eliminates the need for external protection diodes and protects the ADC inputs against dc overvoltages. In applications where the amplifier rails are greater than VREF and less than ground, it is possible for the output to exceed the input voltage range of the device. In this case, the AD4003 internal voltage clamp circuit ensures that the voltage on the input pin does not exceed VREF + 0.4 V and prevents damage to the device by clamping the input voltage in a safe operating range and avoiding disturbance of the reference; this is particularly important for systems that share the reference among multiple ADCs. If the analog input exceeds the reference voltage by 0.4 V, the internal clamp circuit turns on and the current flows through the clamp into ground, preventing the input from rising further and potentially causing damage to the device. The clamp turns on before D1 (see Figure 35) and can sink up to 50 mA of current. Rev. 0 | Page 17 of 33 AD4003 Data Sheet When the clamp is active, it sets the OV clamp flag bit in the register that can be read back (see Table 14), which is a sticky bit that must be read to be cleared. The status of the clamp can also be checked in the status bits using an overvoltage clamp flag (see Table 15). The clamp circuit does not dissipate static power in the off state. Note that the clamp cannot sustain the overvoltage condition for an indefinite time. The external RC filter is usually present at the ADC input to band limit the input signal. During an overvoltage event, excessive voltage is dropped across REXT and REXT becomes part of a protection circuit. The REXT value can vary from 200 Ω to 20 kΩ for 15 V protection. The CEXT value can be as low as 100 pF for correct operation of the clamp. See Table 1 for input overvoltage clamp specifications. REF D1 VIN REXT RIN CIN IN+/IN– CEXT CPIN D2 CLAMP 14957-013 0V TO 15V GND Figure 35. Equivalent Analog Input Circuit Differential Input Considerations The analog input structure allows the sampling of the true differential signal between IN+ and IN−. By using these differential inputs, signals common to both inputs are rejected. Figure 36 shows the common-mode rejection capability of the AD4003 over frequency. It is important to note that the differential input signals must be truly antiphase in nature, 180° out of phase, which is required to keep the common-mode voltage of the input signal within the specified range around VREF/2 shown in Table 1. 72 71 CMRR (dB) 70 Switched Capacitor Input During the acquisition phase, the impedance of the analog inputs (IN+ or IN−) can be modeled as a parallel combination of Capacitor CPIN and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 400 Ω and is a lumped component composed of serial resistors and the on resistance of the switches. CIN is typically 40 pF and is mainly the ADC sampling capacitor. During the conversion phase, where the switches are open, the input impedance is limited to CPIN. RIN and CIN make a singlepole, low-pass filter that reduces undesirable aliasing effects and limits noise. RC Filter Values The value of the RC filter and driving amplifier can be selected depending on the input signal bandwidth of interest at the full 2 MSPS throughput. Lower input signal bandwidth means that the RC cutoff can be lower, thereby reducing noise into the converter. For optimum performance at various throughputs, use the recommended RC values (200 Ω, 180 pF) and the ADA4807-1. The RC values in Table 10 are chosen for ease of drive considerations and also greater ADC input protection. The combination of a large R value (200 Ω) and small C value result in a reduced dynamic load for the amplifier to drive. The smaller value of C means less stability/ phase margin concerns with the amplifier. The large value of R limits the current into the ADC input when the amplifier output exceeds the ADC input range. Table 10. RC Filter and Amplifier Selection for Various Input Bandwidths Input Signal Bandwidth (kHz)