AD4004BRMZ-RL7

16-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs AD4000/AD4004/AD4008 Data Sheet FEATURES GENERAL DESCRIPTION Easy Drive Greatly reduced input kickback Input current reduced to 0.4 μA/MSPS Enhanced acquisition phase, ≥79% of cycle time at 1 MSPS First conversion accurate, no latency or pipeline delay Input span compression for single-supply operation Fast conversion time allows low SPI clock rates Input overvoltage clamp protection sinks up to 50 mA SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface High performance Pseudo differential input range 0 V to VREF with VREF from 2.4 V to 5.1 V Throughput: 2 MSPS/1 MSPS/500 kSPS options INL: ±1.0 LSB maximum Guaranteed 16-bit, no missing codes SNR: 93 dB at fIN = 1 kHz, VREF = 5 V THD: −115 dB at fIN = 1 kHz; −95 dB at fIN = 100 kHz SINAD: 82 dB at fIN = 1 MHz (see Figure 17) Oversampled dynamic range 96 dB for OSR = 2 123 dB for OSR = 1024 Low power Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface 2.5 mW at 500 kSPS (VDD only) 70 μW at 10 kSPS, 14 mW typical at 2 MSPS (total power) 10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP Pin compatible with AD4003/AD4007/AD4011 family Guaranteed operation: −40°C to +125°C The AD4000/AD4004/AD4008 are high accuracy, high speed, low power, 16-bit, Easy Drive, precision successive approximation register (SAR) analog-to-digital converters (ADCs) that operate from a single power supply, VDD. The reference voltage, VREF, is applied externally and can be set independent of the supply voltage. The AD4000/AD40004/AD4008 power scales linearly with throughput. Easy Drive features reduce both signal chain complexity and power consumption while enabling higher channel density. The reduced input current, particularly in high-Z mode, coupled with a long signal acquisition phase, eliminates the need for a dedicated ADC driver. Easy Drive broadens the range of companion circuitry that is capable of driving these ADCs (see Figure 2). Input span compression eliminates the need to provide a negative supply to the ADC driver amplifier while preserving access to the full ADC code range. The input overvoltage clamp protects the ADC inputs against overvoltage events, minimizing disturbances on the reference pin and eliminating the need for external protection diodes. Fast device throughput up to 2 MSPS allows users to accurately capture high frequency signals and to implement oversampling techniques to alleviate the challenges associated with antialias filter designs. Decreased serial peripheral interface (SPI) clock rate requirements reduce digital input and output power consumption, broadens digital host options, and simplifies the task of sending data across digital isolation. The SPI-compatible serial user interface is compatible with 1.8 V, 2.5 V, 3 V, and 5 V logic by using the separate VIO logic supply. APPLICATIONS 25 Automated test equipment Machine automation Medical equipment Battery-powered equipment Precision data acquisition systems Instrumentation and control systems INPUT CURRENT (μA) 15 FUNCTIONAL BLOCK DIAGRAM IN+ IN– HIGH-Z MODE REF AD4000/ AD4004/ AD4008 16-BIT SAR ADC SPAN CLAMP COMPRESSION GND VDD TURBO MODE SERIAL INTERFACE STATUS BITS VIO SDI SCK SDO CNV 5 0 –5 –10 –15 1.8V TO 5V –20 3-WIRE OR 4-WIRE SPI INTERFACE (DAISY CHAIN, CS) –25 Figure 1. Rev. E 10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 INPUT DIFFERENTIAL VOLTAGE (V) 5.0 14956-102 10µF VREF VREF /2 0 1.8V 14956-001 2.4V TO 5.1V HIGH-Z DISABLED, 2MSPS HIGH-Z ENABLED, 2MSPS 20 Figure 2. Input Current vs. Input Differential Voltage Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016–2021 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD4000/AD4004/AD4008 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Driver Amplifier Choice ........................................................... 23  Applications ....................................................................................... 1  Ease of Drive Features ............................................................... 24  Functional Block Diagram .......................................................... 1  Voltage Reference Input ............................................................ 25  General Description ......................................................................... 1  Power Supply............................................................................... 25  Revision History ............................................................................... 2  Digital Interface .......................................................................... 25  Specifications..................................................................................... 5  Register Read/Write Functionality........................................... 28  Timing Specifications .................................................................. 8  Status Bits .................................................................................... 30  Absolute Maximum Ratings.......................................................... 10  CS Mode, 3-Wire Turbo Mode ................................................. 31  Thermal Resistance .................................................................... 10  CS Mode, 3-Wire Without Busy Indicator ............................. 32  ESD Caution ................................................................................ 10  CS Mode, 3-Wire with Busy Indicator .................................... 33  Pin Configurations and Function Descriptions ......................... 11  CS Mode, 4-Wire Turbo Mode ................................................. 34  Typical Performance Characteristics ........................................... 12  CS Mode, 4-Wire Without Busy Indicator ............................. 35  Terminology .................................................................................... 18  Theory of Operation ...................................................................... 19  Circuit Information .................................................................... 19  Converter Operation .................................................................. 20  Transfer Functions...................................................................... 20  Applications Information .............................................................. 21  Typical Application Diagrams .................................................. 21  CS Mode, 4-Wire with Busy Indicator .................................... 36  Daisy-Chain Mode ..................................................................... 37  Layout Guidelines....................................................................... 38  Evaluating the AD4000/AD4004/AD4008 Performance ...... 38  Outline Dimensions ....................................................................... 39  Ordering Guide .......................................................................... 40  Analog Inputs .............................................................................. 22  REVISION HISTORY 2/2021—Rev. D to Rev. E Changes to Features Section, Applications Section, General Description Section .......................................................................... 1 Changes to Specifications Section and Table 1 ............................. 5 Changes to Timing Specifications Section .................................... 8 Added Note 1 to Table 2; Renumbered Sequentially ................... 8 Deleted Timing Diagram Section and Figure 3; Renumbered Sequentially ....................................................................................... 8 Added Note 1 to Table 3; Renumbered Sequentially ................... 9 Changes to Thermal Resistance Section...................................... 10 Changes to Table 7 .......................................................................... 11 Changes to Effective Number of Bits (ENOB) Section ............. 18 Changes to Figure 7 Caption and Figure 10 Caption ................ 12 Changes to Figure 11 and Figure 14 ............................................. 12 Changes to Circuit Information Section and Table 8 ................ 19 Changes to Typical Application Diagrams Section .................... 21 Changes to Input Overvoltage Clamp Circuit Section .............. 22 Changes to Table 10, Driver Amplifier Choice Section, and High Frequency Input Signals Section ........................................ 23 Changes to Multiplexed Applications Section, Input Span Compression Section, and High-Z Mode Section ..................... 24 Changes to Figure 44 Caption, Figure 45 Caption, Voltage Reference Input Section, and Digital Interface Section ............ 25 Changes to Register Read/Write Functionality Section and Figure 46 .......................................................................................... 28 Changes to Figure 47...................................................................... 29 Changes to Status Bit Section and Figure 49 .............................. 30 Changes to CS Mode, 3-Wire Turbo Mode Section .................. 31 Changes to CS Mode, 3-Wire Without Busy Indicator Section...... 32 Changes to CS Mode, 3-Wire With Busy Indicator Section, Figure 54, and Figure 55 ................................................................ 33 Changes to CS Mode, 4-Wire Turbo Mode Section .................. 34 Changes to CS Mode, 4-Wire Without Busy Indicator Section...... 35 Changes to CS Mode, 4-Wire with Busy Indicator Section and Figure 61 .......................................................................................... 36 Changes to Daisy-Chain Mode Section and Figure 62 ............. 37 Changes to Layout Guidelines and Evaluating the AD4000/AD4004/AD4008 Performance Section ............................. 38 Updated Outline Dimensions................................................................ 39 Changes to Ordering Guide ................................................................... 40 Rev. E | Page 2 of 40 Data Sheet AD4000/AD4004/AD4008 8/2019—Rev. C to Rev. D Added Figure 2; Renumbered Sequentially ................................... 1 Changes to Features Section and General Description Section ..... 1 Added Figure 18 and Figure 21 .....................................................13 Added Figure 27, Figure 28, and Figure 29 ..................................14 Added Figure 33 and Figure 35 .....................................................15 Changes to Figure 31 and Figure 32 .............................................15 Changes to Figure 38 ......................................................................18 Changes to Input Overvoltage Clamp Circuit Section...............21 Changes to High-Z Mode Section, Figure 45, and Figure 46 ....23 Added Configuration Register Details Section and Serial Clock Frequency Requirements Section .................................................24 Changes to Digital Interface Section ............................................24 Deleted Table 12 and Table 13; Renumbered Sequentially ........25 Added Table 12 and Table 13; Renumbered Sequentially ..........25 Changes to Register Read/Write Functionality Section and Figure 47 ...........................................................................................26 Changes to Figure 48 ......................................................................27 Added Table 58 ................................................................................28 Changes to Status Bits Section .......................................................28 Changes to CS Mode, 3-Wire Turbo Mode Section and Figure 51 ...........................................................................................29 Changes to CS Mode, 3-Wire Without Busy Indicator Section and Figure 53 ...................................................................................30 Changes to CS Mode, 3-Wire with Busy Indicator Section and Figure 55 ...........................................................................................31 Changes to CS Mode, 4-Wire Turbo Mode Section and Figure 57 ...........................................................................................32 Changes to CS Mode, 4-Wire Without Busy Indicator Section and Figure 59 ...................................................................................33 Changes to CS Mode, 4-Wire with Busy Indicator Section and Figure 61 ...........................................................................................34 Changes to Daisy-Chain Mode Section and Figure 64 ..............35 Updated Outline Dimensions ........................................................37 Changes to Ordering Guide ...........................................................38 10/2017—Rev. B to Rev. C Changes to Features Section ............................................................ 1 Added Multiplexed Applications Section ....................................21 Changes to Ordering Guide ...........................................................36 Added Timing Diagram Section ..................................................... 8 Moved Figure 3 .................................................................................. 8 9/2017—Rev. A to Rev. B Added AD4008 ................................................................... Universal Changes to Title, Features Section, General Description Section, and Figure 1........................................................................................ 1 Changes to Table 1 ............................................................................ 4 Changes to Timing Specifications Section and Table 2 ............... 7 Changes to Table 4 ............................................................................ 8 Changes to Table 5 ............................................................................ 9 Changes to Typical Performance Characteristics Section Layout .. 11 Changes to Figure 19 ............................................................................... 13 Added Figure 25; Renumbered Sequentially ............................... 14 Changes to Figure 28 ...................................................................... 14 Change to Zero Error Definition, Terminology Section ........... 16 Changes to Circuit Information Section and Table 8 ................. 17 Changes to Converter Operation Section and Note 1 and Note 2, Table 9 ................................................................................. 18 Changes to High Frequency Input Signals Section, Figure 36 Caption, and Figure 37 Caption .................................................... 21 Added Figure 38 .............................................................................. 21 Changes to Input Span Compression Section, High-Z Mode Section, Figure 40, and Figure 41 Caption................................... 22 Changes to Figure 42 Caption, Figure 43 Caption, Power Supply Section, and Figure 44 Caption ..................................................... 23 Changes to Figure 45, Digital Interface Section, and Table 11 ........ 24 Changes to Register Read/Write Functionality Section and Figure 46 Caption ............................................................................ 25 Changes to CS Mode, 3-Wire Turbo Mode Section ................... 28 Changes to CS Mode, 3-Wire with Busy Indicator Section ...... 30 Changes to CS Mode, 4-Wire Turbo Mode Section ................... 31 Changes to CS Mode, 4-Wire with Busy Indicator Section ...... 33 Changes to Daisy-Chain Mode Section ....................................... 34 Changed Evaluating the AD4000/AD4004 Performance Section to Evaluating the AD4000/AD4004/AD4008 Performance Section .............................................................................................. 35 Changes to Evaluating the AD4000/AD4004/AD4008 Performance Section ....................................................................... 35 Changes to Ordering Guide ........................................................... 36 4/2017—Rev. 0 to Rev. A Added AD4004 ................................................................... Universal Changes to Title, Features Section, General Description Section, and Figure 1 ....................................................................................... 1 Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 6 Changes to Table 4 ............................................................................ 7 Changes to Table 7 ............................................................................ 9 Changes to Figure 19 and Figure 21 ............................................. 12 Changes to Figure 24 ...................................................................... 13 Added Figure 25; Renumbered Sequentially ............................... 13 Moved Terminology Section ......................................................... 15 Changes to Circuit Information Section and Table 8 ................. 16 Changes to Figure 33 ...................................................................... 18 Changes to RC Filters Section ....................................................... 19 Changes to High Frequency Input Signals Section .................... 20 Changes to High-Z Mode Section, Figure 38, and Figure 39 .... 21 Changes to Long Acquisition Phase Section and Figure 43 ...... 22 Changes to Digital Interface Section and Register Read/Write Functionality Section ...................................................................... 23 Changes to Figure 45 ...................................................................... 24 Rev. E | Page 3 of 40 AD4000/AD4004/AD4008 Data Sheet Changes to CS Mode, 3-Wire Turbo Mode Section .................. 26 Added Figure 48.............................................................................. 26 Changes to CS Mode, 4-Wire Turbo Mode................................. 29 Added Figure 54.............................................................................. 29 Changes to Figure 56 and Figure 57 ............................................. 30 Changes to Layout Guidelines Section and Evaluating the AD4000/AD4004 Performance Section ...................................... 33 Updated Outline Dimensions ....................................................... 34 Changes to Ordering Guide Section ............................................ 34 10/2016—Revision 0: Initial Version Rev. E | Page 4 of 40 Data Sheet AD4000/AD4004/AD4008 SPECIFICATIONS VDD = 1.71 V to 1.89 V, VIO = 1.71 V to 5.5 V, REF = VREF = 5 V, all specifications TMIN to TMAX, high-Z mode disabled, span compression disabled, turbo mode enabled, and sampling frequency (fS) = 2 MSPS for the AD4000, fS = 1 MSPS for the AD4004, and fS = 500 kSPS for the AD4008, unless otherwise noted. Table 1. Parameter RESOLUTION ANALOG INPUT Voltage Range Operating Input Voltage Analog Input Current Test Conditions/Comments Min 16 IN+ voltage (VIN+) − IN− voltage (VIN−) VIN+ to GND VIN− to GND Span compression enabled Acquisition phase, T = 25°C High-Z mode enabled, converting dc input at 2 MSPS 0 −0.1 −0.1 0.1 × VREF THROUGHPUT Complete Cycle AD4000 AD4004 AD4008 Conversion Time Acquisition Phase1 AD4000 AD4004 AD4008 Throughput Rate2 AD4000 AD4004 AD4008 Transient Response3 DC ACCURACY No Missing Codes Integral Nonlinearity Error (INL) 500 1000 2000 270 Max Unit Bits VREF VREF + 0.1 +0.1 0.9 × VREF 0.3 1 V V V V nA μA 290 ns ns ns ns 320 290 790 1790 ns ns ns 0 0 0 2 1 500 150 16 −1.0 −0.8 −0.5 MSPS MSPS kSPS ns VDD = 1.8 V ± 5% Bandwidth = 0.1 Hz to 10 Hz 0.5 6 Bits LSB LSB LSB LSB LSB ppm/°C LSB ppm/°C LSB μV p-p Oversampling ratio (OSR) = 2 OSR = 256 OSR = 1024 93.5 96 117 123 37 dB dB dB dB μV rms T = 0°C to 85°C Differential Nonlinearity Error (DNL) Transition Noise Zero Error Zero Error Drift4 Gain Error Gain Error Drift4 Power Supply Sensitivity 1/f Noise5 AC ACCURACY Dynamic Range Oversampled Dynamic Range Typ −4.5 −0.55 −20 −0.92 Total RMS Noise Rev. E | Page 5 of 40 ±0.2 ±0.2 ±0.15 0.5 ±3 +1.0 +0.8 +0.5 +4.5 +0.55 +20 +0.92 AD4000/AD4004/AD4008 Parameter fIN = 1 kHz, −0.5 dBFS, VREF = 5 V Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Total Harmonic Distortion (THD) Signal-to-Noise-and-Distortion Ratio (SINAD) fIN = 1 kHz, −0.5 dBFS, VREF = 2.5 V SNR SFDR THD SINAD fIN = 100 kHz, −0.5 dBFS, VREF = 5 V SNR THD SINAD fIN = 400 kHz, −0.5 dBFS, VREF = 5 V SNR THD SINAD −3 dB Input Bandwidth Aperture Delay Aperture Jitter REFERENCE VREF Voltage Range Current AD4000 AD4004 AD4008 INPUT OVERVOLTAGE CLAMP IN+/IN− Current (IIN+/IIN−) VIN+/VIN− at Maximum IIN+/IIN− VIN+/VIN− Clamp On/Off Threshold Deactivation Time REF Current at Maximum IIN+ DIGITAL INPUTS Logic Levels Input Voltage Low (VIL) Input Voltage High (VIH) Data Sheet Test Conditions/Comments Min Typ 91 93 112 −115 92.5 dB dB dB dB 87.5 115 −113 87 dB dB dB dB 90 −95 89 dB dB dB 85 −91 84 10 1 1 dB dB dB MHz ns ps rms 91 85.5 85.5 REF − GND VREF = 5 V 2 MSPS 1 MSPS 500 kSPS 2.4 Max 5.1 0.75 0.325 0.185 VREF = 5 V VREF = 2.5 V VREF = 5 V VREF = 2.5 V VREF = 5 V VREF = 2.5 V 5.25 2.68 VIN+ > VREF VIO > 2.7 V VIO ≤ 2.7 V VIO > 2.7 V VIO ≤ 2.7 V Input Current Low (IIL) Input Current High (IIH) Input Pin Capacitance 6 Rev. E | Page 6 of 40 V mA mA mA 50 50 mA mA V V V V ns μA +0.3 × VIO +0.2 × VIO VIO + 0.3 VIO + 0.3 +1 +1 V V V V μA μA pF 5.4 3.1 5.4 2.8 360 100 −0.3 −0.3 0.7 × VIO 0.8 × VIO −1 −1 Unit Data Sheet AD4000/AD4004/AD4008 Parameter DIGITAL OUTPUTS Data Format Pipeline Delay Test Conditions/Comments Min Output Voltage, Low (VOL) Output Voltage, High (VOH) POWER SUPPLIES VDD VIO Standby Current Power Dissipation Output current = 500 μA Output current = −500 μA Serial 16 bits, straight binary Conversion results available immediately after completed conversion 0.4 VIO − 0.3 VDD Only REF Only VIO Only Energy per Conversion TEMPERATURE RANGE Specified Performance 1.71 1.71 VDD and VIO = 1.8 V, T = 25°C VDD = 1.8 V, VIO = 1.8 V, VREF = 5 V 10 kSPS, high-Z mode disabled 500 kSPS, high-Z mode disabled 1 MSPS, high-Z mode disabled 2 MSPS, high-Z mode disabled 500 kSPS, high-Z mode enabled 1 MSPS, high-Z mode enabled 2 MSPS, high-Z mode enabled 500 kSPS, high-Z mode disabled 1 MSPS, high-Z mode disabled 2 MSPS, high-Z mode disabled 500 kSPS, high-Z mode disabled 1 MSPS, high-Z mode disabled 2 MSPS, high-Z mode disabled 500 kSPS, high-Z mode disabled 1 MSPS, high-Z mode disabled 2 MSPS, high-Z mode disabled TMIN to TMAX 1.8 Max 1.89 5.5 1.6 70 3.5 7 14 4 8 16 2.5 4.9 9.75 0.9 1.9 3.75 0.1 0.2 0.5 7 −40 1 Typ 4.2 8.2 16 5 9.9 19 +125 Unit V V V V μA μW mW mW mW mW mW mW mW mW mW mW mW mW mW mW mW nJ/sample °C The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS for the AD4000, 1 MSPS for the AD4004, and 500 kSPS for the AD4008. 2 A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 70 MHz. Refer to Table 4 for the maximum achievable throughput for different modes of operation. 3 Transient response is the time required for the ADC to acquire a full-scale input step to ±0.5 LSB accuracy. 4 The minimum and maximum values are guaranteed by characterization, but not production tested. 5 See the 1/f noise plot in Figure 25. Rev. E | Page 7 of 40 AD4000/AD4004/AD4008 Data Sheet TIMING SPECIFICATIONS VDD = 1.71 V to 1.89 V, VIO = 1.71 V to 5.5 V, VREF = 5 V, all specifications TMIN to TMAX, high-Z mode disabled, span compression disabled, turbo mode enabled, and fS = 2 MSPS for the AD4000, fS = 1 MSPS for the AD4004, and fS = 500 kSPS for the AD4008, unless otherwise noted. See Figure 46 to Figure 49, Figure 51, Figure 53, Figure 55, Figure 57, Figure 59, Figure 61, and Figure 63 for timing diagrams. Table 2. Digital Interface Timing Parameter1 CONVERSION TIME—CNV RISING EDGE TO DATA AVAILABLE ACQUISITION PHASE2 AD4000 AD4004 AD4008 TIME BETWEEN CONVERSIONS AD4000 AD4004 AD4008 CNV PULSE WIDTH (CS MODE)3 Symbol tCONV tACQ Min 270 Typ 290 Max 320 Unit ns 290 790 1790 ns ns ns 500 1000 2000 10 ns ns ns ns 9.8 12.3 ns ns 20 25 3 3 1.5 ns ns ns ns ns tCYC tCNVH SCK PERIOD (CS MODE)4 tSCK VIO > 2.7 V VIO > 1.7 V SCK PERIOD (DAISY-CHAIN MODE)5 VIO > 2.7 V VIO > 1.7 V SCK LOW TIME SCK HIGH TIME SCK FALLING EDGE TO DATA REMAINS VALID DELAY SCK FALLING EDGE TO DATA VALID DELAY VIO > 2.7 V VIO > 1.7 V CNV OR SDI LOW TO SDO D15 MOST SIGNIFICANT BIT (MSB) VALID DELAY (CS MODE) tSCK tSCKL tSCKH tHSDO tDSDO 7.5 10.5 ns ns 10 13 ns ns ns ns ns tEN VIO > 2.7 V VIO > 1.7 V CNV RISING EDGE TO FIRST SCK RISING EDGE DELAY LAST SCK FALLING EDGE TO CNV RISING EDGE DELAY6 CNV OR SDI HIGH OR LAST SCK FALLING EDGE TO SDO HIGH IMPEDANCE (CS MODE) tQUIET1 tQUIET2 tDIS 190 60 SDI VALID SETUP TIME FROM CNV RISING EDGE SDI VALID HOLD TIME FROM CNV RISING EDGE (CS MODE) tSSDICNV tHSDICNV 2 2 ns ns SCK VALID HOLD TIME FROM CNV RISING EDGE (DAISY-CHAIN MODE) SDI VALID SETUP TIME FROM SCK RISING EDGE (DAISY-CHAIN MODE) SDI VALID HOLD TIME FROM SCK RISING EDGE (DAISY-CHAIN MODE) tHSCKCNV tSSDISCK tHSDISCK 12 2 2 ns ns ns 1 20 Timing parameters measured with respect to a falling edge are defined as triggered at x% VIO. Timing parameters measured with respect to a rising edge are defined as triggered at y% VIO. For VIO ≤ 2.7 V, x = 80 and y = 20. For VIO > 2.7 V, x = 70 and y = 30. The minimum VIH and maximum VIL are used. See the digital inputs specifications in Table 1. 2 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS for the AD4000, 1 MSPS for the AD4004, and 500 kSPS for the AD4008. 3 For turbo mode, tCNVH must match the tQUIET1 minimum. 4 A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK frequency of 70 MHz. Refer to Table 4 for the maximum achievable throughput for different modes of operation. See the Serial Clock Frequency Requirements section for guidelines on determining the minimum SCK rate required for a given throughput. 5 A 50% duty cycle is assumed for SCK. 6 See Figure 24 for SINAD, SNR, and ENOB vs. tQUIET2. Rev. E | Page 8 of 40 Data Sheet AD4000/AD4004/AD4008 Table 3. Register Read/Write Timing Parameter READ/WRITE OPERATION CNV Pulse Width2 SCK Period VIO > 2.7 V VIO > 1.7 V SCK Low Time SCK High Time READ OPERATION CNV Low to SDO D15 MSB Valid Delay VIO > 2.7 V VIO > 1.7 V SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO > 2.7 V VIO > 1.7 V CNV Rising Edge to SDO High Impedance WRITE OPERATION SDI Valid Setup Time from SCK Rising Edge SDI Valid Hold Time from SCK Rising Edge CNV Rising Edge to SCK Edge Hold Time CNV Falling Edge to SCK Active Edge Setup Time 1 2 Symbol1 Min tCNVH tSCK 10 ns 9.8 12.3 3 3 ns ns ns ns tSCKL tSCKH Typ Max Unit tEN tHSDO tDSDO ns ns ns 7.5 10.5 20 ns ns ns 1.5 tDIS tSSDISCK tHSDISCK tHCNVSCK tSCNVSCK 10 13 2 2 0 6 ns ns ns ns See Figure 46 to Figure 49, Figure 51, Figure 53, Figure 55, Figure 57, Figure 59, Figure 61, and Figure 63. For turbo mode, tCNVH must match the tQUIET1 minimum. Table 4. Achievable Throughput for Different Modes of Operation Parameter THROUGHPUT, CS MODE 3-Wire and 4-Wire Turbo Mode 3-Wire and 4-Wire Turbo Mode and Six Status Bits 3-Wire and 4-Wire Mode 3-Wire and 4-Wire Mode and Six Status Bits Test Conditions/Comments fSCK = 100 MHz, VIO ≥ 2.7 V fSCK = 80 MHz, VIO < 2.7 V fSCK = 100 MHz, VIO ≥ 2.7 V fSCK = 80 MHz, VIO < 2.7 V fSCK = 100 MHz, VIO ≥ 2.7 V fSCK = 80 MHz, VIO < 2.7 V fSCK = 100 MHz, VIO ≥ 2.7 V fSCK = 80 MHz, VIO < 2.7 V Rev. E | Page 9 of 40 Min Typ Max Unit 2 2 2 1.86 1.82 1.69 1.64 1.5 MSPS MSPS MSPS MSPS MSPS MSPS MSPS MSPS AD4000/AD4004/AD4008 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Note that the input overvoltage clamp cannot sustain the overvoltage condition for an indefinite amount of time. Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Table 5. Parameter Analog Inputs IN+, IN− to GND1 Supply Voltage REF, VIO to GND VDD to GND VDD to VIO Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature Lead Temperature Soldering ESD Ratings Human Body Model Machine Model Field Induced Charged Device Model 1 2 Rating −0.3 V to VREF + 0.4 V or ±130 mA2 −0.3 V to +6.0 V −0.3 V to +2.1 V −6 V to +2.4 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.3 V −65°C to +150°C 150°C 260°C reflow as per JEDEC J-STD-020 θJA is the natural convection junction-to-ambient thermal resistance measured in a one cubic foot sealed enclosure. θJC is the junction-to-case thermal resistance. Table 6. Thermal Resistance Package Type1 RM-10 CP-10-9 1 θJA 147 114 θJC 38 33 Unit °C/W °C/W Test Condition 1: thermal impedance simulated values are based upon use of 2S2P JEDEC PCB. See the Ordering Guide. ESD CAUTION 4 kV 200 V 1.25 kV See the Analog Inputs section for an explanation of IN+ and IN−. Current condition tested over a 10 ms time interval. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. E | Page 10 of 40 Data Sheet AD4000/AD4004/AD4008 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS IN+ 3 IN– 4 GND 5 TOP VIEW (Not to Scale) 10 VIO REF 1 9 SDI VDD 2 8 SCK IN+ 3 7 SDO 6 CNV IN– 4 GND 5 AD4000/ AD4004/ AD4008 TOP VIEW (Not to Scale) 10 VIO 9 SDI 8 SCK 7 SDO 6 CNV NOTES 1. CONNECT THE EXPOSED PAD TO GND. THIS CONNECTION IS NOT REQUIRED TO MEET THE SPECIFIED PERFORMANCE. 14956-004 AD4000/ AD4004 14956-003 REF 1 VDD 2 Figure 4. 10-Lead LFCSP Pin Configuration Figure 3. 10-Lead MSOP Pin Configuration Table 7. Pin Function Descriptions Pin No. 1 Mnemonic REF Type1 AI 2 3 VDD IN+ P AI 4 5 6 IN− GND CNV AI P DI 7 SDO DO 8 9 SCK SDI DI DI 10 VIO P N/A2 EPAD P 1 2 Description Reference Input Voltage. The VREF range is 2.4 V to 5.1 V. This pin is referred to the GND pin and must be decoupled closely to the GND pin with a 10 μF, X7R ceramic capacitor. 1.8 V Power Supply. The VDD range is 1.71 V to 1.89 V. Bypass VDD to GND with a 0.1 μF ceramic capacitor. Analog Input. This input is referred to analog ground sense pin (IN−). The device samples the voltage differential between IN+ and IN− on the leading edge on CNV. The operating input range of IN+ − IN− is 0 V to VREF. Analog Input Ground Sense. Connect this pin to the analog ground plane or to a remote sense ground. Power Supply Ground. Connect to the ground plane of the board. Convert Input. This input has multiple functions. On the leading edge, the input initiates the conversions and selects the interface mode of the device, which is either daisy-chain mode or CS mode. In CS mode, the SDO pin is enabled when CNV is low. In daisy-chain mode, the data is read when CNV is high. Serial Data Output. The conversion result is output on this pin. The SDO pin is synchronized to the SCK signal on the SCK pin. Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock. Serial Data Input. This input provides multiple features and selects the interface mode of the ADC as follows: Daisy-chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 16 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. With CNV low, program the device by clocking in a 16-bit word on SDI on the rising edge of SCK. Input/Output Interface Digital Power. Nominally, this pin is at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). Bypass VIO to GND with a 0.1 μF ceramic capacitor. Exposed Pad. Connect the exposed pad to GND. This connection is not required to meet the specified performance. Note that the exposed pad only applies to the LFCSP. AI is analog input, P is power, DI is digital input, and DO is digital output. N/A means not applicable. Rev. E | Page 11 of 40 AD4000/AD4004/AD4008 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VDD = 1.71 V to 1.89 V, VIO = 1.71 V to 5.5 V, VREF = 5 V, all specifications TMIN to TMAX, high-Z mode disabled, span compression disabled, turbo mode enabled, and fS = 2 MSPS for the AD4000, fS = 1 MSPS for the AD4004, and fS = 500 kSPS for the AD4008, unless otherwise noted. 0.5 0.20 +125°C +25°C –40°C 0.4 0.15 0.3 0.10 0.1 DNL (LSB) INL (LSB) 0.2 0 –0.1 0.05 0 –0.05 –0.2 –0.10 –0.3 8192 16384 24576 32768 40960 49152 57344 65536 CODE –0.20 0 8192 16384 24576 32768 40960 49152 57344 65536 CODE Figure 5. INL vs. Code for Various Temperatures, VREF = 5 V 14956-203 0 14956-200 –0.5 +125°C +25°C –40°C –0.15 –0.4 Figure 8. DNL vs. Code for Various Temperatures, VREF = 5 V 0.3 0.20 +125°C +25°C –40°C 0.2 0.15 0.10 DNL (LSB) INL (LSB) 0.1 0 –0.1 0.05 0 –0.05 –0.10 0 8192 16384 24576 32768 40960 49152 57344 65536 CODE –0.20 14956-201 16384 24576 32768 40960 49152 57344 65536 Figure 9. DNL vs. Code for Various Temperatures, VREF = 2.5 V 0.4 0.20 0.3 0.15 0.2 0.10 0.1 0.05 DNL (LSB) INL (LSB) 8192 CODE Figure 6. INL vs. Code for Various Temperatures, VREF = 2.5 V 0 –0.1 0 –0.05 –0.10 –0.2 –0.3 –0.15 SPAN COMPRESSION ENABLED HIGH-Z ENABLED 0 8192 16384 24576 32768 CODE 40960 49152 57344 65536 –0.20 14956-202 –0.4 0 Figure 7. INL vs. Code for High-Z and Span Compression Modes Enabled, VREF = 5 V SPAN COMPRESSION ENABLED HIGH-Z ENABLED 0 8192 16384 24576 32768 CODE 40960 49152 57344 65536 14956-205 –0.3 +125°C +25°C –40°C –0.15 14956-204 –0.2 Figure 10. DNL vs. Code for High-Z and Span Compression Modes Enabled, VREF = 5 V Rev. E | Page 12 of 40 Data Sheet AD4000/AD4004/AD4008 90000 50000 VREF = 2.5V VREF = 5V 80000 40000 70000 35000 CODE COUNT 50000 40000 30000 25000 20000 15000 20000 14956-209 32760 32761 32762 32763 32764 32765 32766 32767 32768 32769 32770 32771 32772 32773 32774 32775 32776 32777 32778 32779 32780 0 32760 32761 32762 32763 32764 32765 32766 32767 32768 32769 32770 32771 32772 32773 32774 32775 32776 32777 32778 32779 32780 5000 0 Figure 11. Histogram of a DC Input at Code Center, VREF = 2.5 V and VREF = 5 V ADC CODE Figure 14. Histogram of a DC Input at Code Transition, VREF = 2.5 V and VREF = 5 V 0 0 VREF = 5V SNR = 92.47dB THD = –115.10dB SINAD = 92.41dB –40 –60 –80 –100 –120 –140 –40 –60 –80 –100 –120 –140 –160 10k 100k 1M FREQUENCY (Hz) –180 100 14956-207 1k 100k 1M Figure 15. 1 kHz, −0.5 dBFS Input Tone FFT, VREF = 2.5 V 0 0 VREF = 5V SNR = 90.16 dB THD = –94.52dB SINAD = 88.33dB FUNDAMENTAL AMPLITUDE (dB) –20 –60 –80 –100 –120 –140 –160 –40 VREF = 5V SNR = 84.65 dB THD = –90.80dB SINAD = 83.89dB –60 –80 –100 –120 –140 –160 10k 100k FREQUENCY (Hz) 1M 14956-211 FUNDAMENTAL AMPLITUDE (dB) 10k FREQUENCY (Hz) Figure 12. 1 kHz, −0.5 dBFS Input Tone Fast Fourier Transform (FFT), VREF = 5 V –180 1k 1k 14956-210 –160 –40 VREF = 2.5V SNR = 87.54dB THD = –112.33dB SINAD = 87.49dB –20 FUNDAMENTAL AMPLITUDE (dB) –20 –180 100 14956-206 10000 10000 ADC CODE FUNDAMENTAL AMPLITUDE (dB) 30000 Figure 13. 100 kHz, −0.5 dBFS Input Tone FFT –180 1k 10k 100k FREQUENCY (Hz) Figure 16. 400 kHz, −0.5 dBFS Input Tone FFT Rev. E | Page 13 of 40 1M 14956-208 CODE COUNT 60000 –20 VREF = 2.5V VREF = 5V 45000 AD4000/AD4004/AD4008 Data Sheet 94 –80 15.2 ENOB SINAD SNR 92 15.0 120 THD SFDR –85 115 14.2 86 14.0 THD (dB) 14.4 88 13.8 84 13.6 82 13.4 10k 13.2 1M 100k 14956-212 80 1k INPUT FREQUENCY (Hz) –90 110 –95 105 –100 100 –105 95 –110 90 –115 85 –120 1k 10k 80 1M 100k 14956-215 14.6 ENOB (Bits) INPUT FREQUENCY (Hz) Figure 17. SNR, SINAD, and Effective Number of Bits (ENOB) vs. Input Frequency Figure 20. THD and SFDR vs. Input Frequency ENOB SINAD SNR 93 –110 15.2 –111 15.1 111 –112 91 14.8 90 14.7 109 –114 108 –115 14.6 107 –116 14.5 88 110 –113 THD (dB) 14.9 89 108 –117 107 14.4 3.3 3.6 3.9 4.2 4.5 4.8 REFERENCE VOLTAGE (V) Figure 18. SNR, SINAD, and ENOB vs. Reference Voltage, fIN = 1 kHz 3.3 3.6 3.9 4.2 REFERENCE VOLTAGE (V) 4.5 106 5.1 4.8 Figure 21. THD and SFDR vs. Reference Voltage, fIN = 1 kHz 93.2 15.15 –100 SNR SINAD ENOB 93.0 3.0 14956-216 3.0 2.7 –102 15.10 92.8 92.2 15.00 THD (dB) 15.05 ENOB (Bits) 92.6 92.4 92.0 91.8 111 THD SFDR 14.95 110 –104 109 –106 108 –108 107 –110 106 –112 105 –114 104 –116 103 SFDR (dB) 2.7 14.3 5.1 –118 2.4 14956-213 87 2.4 91.6 91.4 –40 –20 0 20 40 60 80 100 120 14.90 TEMPERATURE (°C) 14956-220 SNR, SINAD (dB) 112 15.0 ENOB (Bits) SNR, SINAD (dB) 92 113 THD SFDR SFDR (dB) 15.3 94 –118 –40 Figure 19. SNR, SINAD, and ENOB vs. Temperature, fIN = 1 kHz –20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 22. THD and SFDR vs. Temperature, fIN = 1 kHz Rev. E | Page 14 of 40 102 14956-222 SNR, SINAD (dB) 90 SFDR (dB) 14.8 Data Sheet 125 AD4000/AD4004/AD4008 –75 DYNAMIC RANGE fIN = 1kHz fIN = 10kHz 120 –80 –85 115 THD (dB) SNR (dB) –90 110 105 500Ω HIGH-Z OFF 500Ω HIGH-Z ON 1000Ω HIGH-Z OFF 1000Ω HIGH-Z ON –95 –100 100 95 2 4 8 16 32 64 128 256 512 1024 2048 DECIMATION RATE –115 ZERO ERROR AND GAIN ERROR (LSB) 15.15 92.6 ENOB (Bits) 15.05 92.4 0 10 20 30 40 50 60 70 14.95 tQUIET2 (ns) 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 27. Zero Error and Gain Error vs. Temperature Figure 24. SNR, SINAD, and ENOB vs. tQUIET2 25 955 HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z 20 954 15 953 INPUT CURRENT (μA) ADC OUTPUT READING (µV) 50 ZERO ERROR GAIN ERROR 0.8 –1.0 –40 14956-217 92.0 15.00 ENOB SINAD SNR 92.2 20 952 951 950 DISABLED, 2MSPS DISABLED, 1MSPS DISABLED, 500kSPS ENABLED, 2MSPS ENABLED, 1MSPS ENABLED, 500kSPS 10 5 0 –5 –10 –15 949 0 2 4 6 TIME (Seconds) 8 10 14956-218 948 –20 Figure 25. 1/f Noise for 0.1 Hz to 10 Hz Bandwidth, 50 kSPS, 2500 Samples Averaged per Reading Rev. E | Page 15 of 40 –25 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 INPUT DIFFERENTIAL VOLTAGE (V) Figure 28. Analog Input Current vs. Input Differential Voltage 14956-221 SNR, SINAD (dB) 93.0 15.10 10 1.0 15.20 92.8 5 Figure 26. THD vs. Input Frequency for Various Source Impedances 15.25 93.2 2 INPUT FREQUENCY (kHz) Figure 23. SNR vs. Decimation Rate for Various Input Frequencies, 2 MSPS 93.4 1 14956-223 1 14956-225 –110 14956-214 90 200Ω HIGH-Z OFF 200Ω HIGH-Z ON –105 AD4000/AD4004/AD4008 Data Sheet 80 8 7 OPERATING CURRENT (mA) 75 6 PSRR (dB) 5 VDD HIGH-Z ENABLED VDD HIGH-Z DISABLED REF HIGH-Z ENABLED REF HIGH-Z DISABLED VIO HIGH-Z ENABLED VIO HIGH-Z DISABLED 4 3 70 65 2 60 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 55 100 14956-226 1k 3.5 0.8 3.0 0.7 2.5 VDD HIGH-Z ENABLED VDD HIGH-Z DISABLED REF HIGH-Z ENABLED REF HIGH-Z DISABLED VIO HIGH-Z ENABLED VIO HIGH-Z DISABLED 1.5 1.0 0.5 2MSPS 1MSPS 500kSPS 0.6 0.5 0.4 0.3 0.2 0 20 40 60 80 100 120 0 2.4 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 REFERENCE VOLTAGE (V) Figure 33. Reference Current vs. Reference Voltage Figure 30. Operating Current vs. Temperature, AD4004, 1 MSPS 100k 2.0 1.8 10k 1.6 POWER DISSIPATION (µW) OPERATING CURRENT (mA) 2.7 14956-219 –20 TEMPERATURE (°C) 1.4 1.2 VDD HIGH-Z ENABLED VDD HIGH-Z DISABLED REF HIGH-Z ENABLED REF HIGH-Z DISABLED VIO HIGH-Z ENABLED VIO HIGH-Z DISABLED 1.0 0.8 0.6 VDD VIO REF TOTAL POWER 1k 100 10 1 0.4 POWER DISSIPATION MEASUREMENTS APPLY TO EACH PRODUCT OVER ITS SPECIFIED THROUGHPUT RANGE. 0.1 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 14956-325 0.2 0 –40 1M 0.1 14956-232 0 –40 100k Figure 32. PSRR vs. Frequency REFERENCE CURRENT (mA) OPERATING CURRENT (mA) Figure 29. Operating Current vs. Temperature, AD4000, 2 MSPS 2.0 10k FREQUENCY (Hz) 0.01 10 100 1k 10k 100k THROUGHPUT (SPS) Figure 34. Power Dissipation vs. Throughput Figure 31. Operating Current vs. Temperature, AD4008, 500 kSPS Rev. E | Page 16 of 40 1M 2M 14956-227 0 –40 14956-230 1 Data Sheet AD4000/AD4004/AD4008 12 23 11 VIO = 5.0V VIO = 3.3V VIO = 1.8V 21 19 9 8 17 tDSDO (ns) 7 6 5 4 15 13 11 3 9 2 0 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) 120 Figure 35. Standby Current vs. Temperature 5 0 20 40 60 80 100 120 140 160 180 LOAD CAPACITANCE (pF) Figure 36. tDSDO vs. Load Capacitance Rev. E | Page 17 of 40 200 220 14956-228 7 1 14956-224 STANDBY CURRENT (µA) 10 AD4000/AD4004/AD4008 Data Sheet TERMINOLOGY Integral Nonlinearity Error (INL) INL is the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 38). Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Zero Error Zero error is the difference between the ideal voltage that results in the first code transition (½ LSB above analog ground) and the actual voltage producing that code. Gain Error The first transition (from 100 ... 00 to 100 ... 01) occurs at a level ½ LSB above nominal negative full scale (−4.999981 V for the ±5 V range). The last transition (from 011 … 10 to 011 … 11) occurs for an analog voltage 1½ LSB below the nominal full scale (+4.999943 V for the ±5 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD as follows: Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured. The value for dynamic range is expressed in decibels. It is measured with a signal at −60 dBFS so that it includes all noise sources and DNL artifacts. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-Noise-and-Distortion Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components that are less than the Nyquist frequency, including harmonics but excluding dc. The value of SINAD is expressed in decibels. Aperture Delay Aperture delay is the measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Transient Response Transient response is the time required for the ADC to acquire a full-scale input step to ±0.5 LSB accuracy. Power Supply Rejection Ratio (PSRR) PSRR is the ratio of the power in the ADC output at the frequency, f, to the power of a 200 mV p-p sine wave applied to the ADC VDD supply of frequency, f. ENOB = (SINAD − 1.76)/6.02 ENOB is expressed in bits and SINAD is expressed in dB. PSRR (dB) = 10 log(PVDD_IN/PADC_OUT) where: PVDD_IN is the power at the frequency, f, at the VDD pin. PADC_OUT is the power at the frequency, f, in the ADC output. Rev. E | Page 18 of 40 Data Sheet AD4000/AD4004/AD4008 THEORY OF OPERATION IN+ SWITCHES CONTROL MSB REF GND 32,768C LSB 16,384C 4C 2C C SW+ C BUSY COMP 32,768C 16,384C 4C 2C MSB C CONTROL LOGIC C LSB OUTPUT CODE SW– 14956-006 CNV IN– Figure 37. ADC Simplified Schematic CIRCUIT INFORMATION The AD4000/AD4004/AD4008 are high speed, low power, singlesupply, precise, 16-bit pseudo differential ADCs based on a SAR architecture. The AD4000 is capable of converting 2,000,000 samples per second (2 MSPS), the AD4004 is capable of converting 1,000,000 samples per second (1 MSPS), and the AD4008 is capable of converting 500,000 samples per second (500 kSPS). The power consumption of the AD4000/AD4004/AD4008 scales with throughput because they power down in between conversions. For example, when operating at 10 kSPS, the devices typically consume 70 μW, making them ideal for batterypowered applications. The AD4000/AD4004/AD4008 also have a valid first conversion after being powered down for long periods, which can further reduce power consumed in applications in which the ADC does not need to be constantly converting. The AD4000/AD4004/AD4008 provide the user with an on-chip track-and-hold and do not exhibit any pipeline delay or latency, making them ideal for multiplexed applications. The AD4000/AD4004/AD4008 incorporate a multitude of unique easy to use features that result in a lower system power and smaller footprint. The AD4000/AD4004/AD4008 each have an internal voltage clamp that protects the device from overvoltage damage on the analog inputs. The analog input incorporates circuitry that reduces the nonlinear charge kickback seen from a typical switched capacitor SAR input. This reduction in kickback, combined with a longer acquisition phase allows the use of lower bandwidth and lower power amplifiers as drivers. This combination has the additional benefit of allowing a larger resistor value in the input RC filter and a corresponding smaller capacitor, which results in a smaller RC load for the amplifier, improving stability and power dissipation. High-Z mode can be enabled via the SPI interface by programming a register bit (see Table 12). When high-Z mode is enabled, the ADC input has a low input charging current at low input signal frequencies as well as improved distortion over a wide frequency range up to 100 kHz. For frequencies greater than 100 kHz and multiplexing functionality, disable high-Z mode. For single-supply applications, a span compression feature creates additional headroom and footroom for the driving amplifier to access the full range of the ADC. The fast conversion time of the AD4000/AD4004/AD4008, along with turbo mode, allows low clock rates to read back conversions, even when running at their respective maximum throughput rates. Note that, for the AD4000, the full throughput rate of 2 MSPS can be achieved only with turbo mode enabled. The AD4000/AD4004/AD4008 can interface with any 1.8 V to 5 V digital logic family. These devices are available in a 10-lead MSOP or a tiny 10-lead LFCSP that allows space savings and flexible configurations. The AD4000/AD4004/AD4008 are pin for pin compatible with some of the 14-/16-/18-/20-bit precision SAR ADCs listed in Table 8. Table 8. MSOP and LFCSP 14-/16-/18-/20-Bit Precision SAR ADCs Bits 100 kSPS 201 Not applicable 1 18 AD7989-12 250 kSPS Not applicable AD76912 183 161 Rev. E | Page 19 of 40 400 kSPS to 500 kSPS AD40222 AD40112, AD76902, AD7989-52 AD40102 AD7684 AD76872 AD76882, AD76932, AD79162 ≥1000 kSPS AD40202, AD40212 AD40032, AD40072, AD79822, AD79842 AD40022, AD40062 AD40012, AD40052, AD79152 AD4000/AD4004/AD4008 Bits 100 kSPS 163 AD7680, AD7683, AD7988-12 250 kSPS AD76852, AD7694 400 kSPS to 500 kSPS AD40082, AD76862, AD7988-52 143 AD79422 AD79462 AD7940 Data Sheet ≥1000 kSPS AD40002, AD40042, AD79802, AD79832 Not applicable between GND and VREF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4, …, VREF/65,536). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the process completes, the control logic generates the ADC output code and a busy signal indicator. Because the AD4000, the AD4004, and the AD4008 have onboard conversion clocks, the serial clock, SCK, is not required for the conversion process. CONVERTER OPERATION TRANSFER FUNCTIONS The AD4000/AD4004/AD4008 are SAR-based ADCs using a charge redistribution sampling digital-to-analog converter (DAC). Figure 37 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary weighted capacitors, that are connected to the comparator inputs. The ideal transfer characteristics for the AD4000/AD4004/AD4008 are shown in Figure 38 and Table 9. When the acquisition phase is complete and the CNV input goes high, a conversion phase initiates. When the conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. The differential voltage between the IN+ and IN− inputs captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array 111...111 111...110 111...101 000...010 000...001 000...000 –FSR –FSR + 1 LSB –FSR + 0.5 LSB +FSR – 1 LSB +FSR – 1.5 LSB ANALOG INPUT 14956-007 During the acquisition phase, terminals of the array tied to the input of the comparator are connected to ground via the SW+ and SW− switches (see Figure 37). All independent switches connect the other terminal of each capacitor to the analog inputs. The capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN− inputs. ADC CODE (STRAIGHT BINARY) True differential. 2 Pin for pin compatible. 3 Pseudo differential. 1 Figure 38. ADC Ideal Transfer Function (FSR Is Full-Scale Range) Table 9. Output Codes and Ideal Input Voltages Description FSR − 1 LSB Midscale + 1 LSB Midscale Midscale − 1 LSB −FSR + 1 LSB −FSR Analog Input, VREF = 5 V 4.999924 V 2.500076 V 2.5 V 2.499924 V 76.3 μV 0V VREF = 5 V with Span Compression Enabled (V) 4.499939 2.500061 2.5 2.499939 0.50006103 0.5 1 Digital Output Code 0xFFFF1 0x8001 0x8000 0x7FFF 0x0001 0x00002 This output code is also the code for an overranged analog input (VIN+ − VIN− above VREF with span compression disabled and above 0.9 × VREF with span compression enabled). 2 This output code is also the code for an underranged analog input (VIN+ − VIN− below 0 V with span compression disabled and below 0.1 × VREF with span compression enabled). Rev. E | Page 20 of 40 Data Sheet AD4000/AD4004/AD4008 APPLICATIONS INFORMATION Figure 40 shows a recommended connection diagram when using a single-supply system. This setup is preferable when only a limited number of rails are available in the system and power dissipation is of critical importance. TYPICAL APPLICATION DIAGRAMS Figure 39 shows an example of the recommended connection diagram for the AD4000/AD4004/AD4008 when multiple supplies, V+ and V−, are available. This configuration is used for optimal performance because the amplifier supplies can be selected to allow the maximum signal range (see Figure 39 for the range). V+ ≥ +6.5V REF1 LDO 1.8V AMP VCM = VREF /2 5V 10kΩ 100nF 10kΩ VREF VCM = VREF /2 100nF 1.8V TO 5V HOST SUPPLY 10µF V+ R AMP REF C 0V V– VDD VIO SDI IN+ AD4000/ AD4004/ AD4008 SCK DIGITAL HOST (MICROPROCESSOR/ FPGA) SDO IN– CNV GND 14956-008 3-WIRE/4-WIRE INTERFACE V– ≤ –0.5V Figure 39. Typical Application Diagram with Multiple Supplies V+ = 5V REF1 LDO AMP VCM = VREF /2 10kΩ 0.9 × VREF VCM = VREF/2 0.1 × VREF AMP 1.8V 4.096V 10kΩ 100nF 100nF 1.8V TO 5V HOST SUPPLY 10µF1 R REF C VDD VIO SDI IN+ AD4000/ AD4004/ AD40082 3 IN– GND SCK SDO DIGITAL HOST (MICROPROCESSOR/ FPGA) CNV 1SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE 2SPAN COMPRESSION MODE ENABLED. 3SEE TABLE 10 FOR RC FILTER AND AMPLIFIER SELECTION. SELECTION. CREF IS USUALLY A 10µF CERAMIC CAPACITOR (X7R). Figure 40. Typical Application Diagram with a Single Supply Rev. E | Page 21 of 40 14956-009 3-WIRE/4-WIRE INTERFACE AD4000/AD4004/AD4008 Data Sheet ANALOG INPUTS Figure 41 shows an equivalent circuit of the analog input structure, including the overvoltage clamp of the AD4000/AD4004/AD4008. REF D1 VIN REXT RIN CIN IN+ CEXT CPIN D2 CLAMP GND 14956-010 0V TO 15V Figure 41. Equivalent Analog Input Circuit Input Overvoltage Clamp Circuit Most ADC analog inputs, IN+ and IN−, have no overvoltage protection circuitry apart from ESD protection diodes. During an overvoltage event, an ESD protection diode from an analog input pin (IN+ or IN−) to REF forward biases and shorts the input pin to REF, potentially overloading the reference or damaging the device. The AD4000/AD4004/AD4008 internal overvoltage clamp circuit, with a larger external resistor (REXT = 200 Ω), eliminates the need for external protection diodes and protects the ADC inputs against dc overvoltages. In applications where the amplifier rails are greater than VREF and less than ground, it is possible for the output to exceed the input voltage range (specified in Table 1) of the device. In this case, the AD4000/AD4004/AD4008 internal overvoltage clamp circuit ensures that the voltage on the input pin does not exceed VREF + 0.4 V and prevents damage to the device by clamping the input voltage in a safe operating range and avoiding disturbance of the reference, which is particularly important for systems that share the reference among multiple ADCs. If the analog input exceeds the reference voltage by 0.4 V, the internal clamp circuit turns on and the current flows through the clamp into ground, preventing the input from rising further and potentially causing damage to the device. The clamp turns on before D1 (see Figure 41) and can sink up to 50 mA of current. When the clamp is active, it sets the overvoltage (OV) clamp flag bit in the configuration register that is accessed with a 16-bit SPI read command or via the OV in the status bits. The OV clamp flag gives an indication of overvoltage condition when it is set to 0. The OV clamp flag is a read only sticky bit, and is cleared only if the register is read while the overvoltage condition is no longer present. The clamp circuit does not dissipate static power in the off state. Note that the clamp cannot sustain the overvoltage condition for an indefinite amount of time. The external RC filter, formed by the REXT resistor and the CEXT capacitor (see Figure 41), is usually present at the ADC input to band limit the input signal. During an overvoltage event, excessive voltage is dropped across REXT, and REXT becomes part of a protection circuit. The REXT value can vary from 200 Ω to 20 kΩ for 15 V protection. The CEXT value can be as low as 100 pF for correct operation of the clamp. See Table 1 for input overvoltage clamp specifications. The analog input structure allows the sampling of the true differential signal between IN+ and IN−. Signals common to both inputs are rejected when using these differential inputs. Ground potential differences between the sensor and the local ADC ground are eliminated when using IN− to sense a remote signal ground. Switched Capacitor Input During the acquisition phase, the impedance of the analog inputs (IN+ or IN−) can be modeled as a parallel combination of Capacitor CPIN and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 400 Ω and is a lumped component composed of serial resistors and the on resistance of the switches. CIN is typically 40 pF and is mainly the ADC sampling capacitor. During the conversion phase, where the switches are open, the input impedance is limited to CPIN. RIN and CIN make a singlepole, low-pass filter that reduces undesirable aliasing effects and limits noise. RC Filter Values The RC filter value (represented by R and C in Figure 39 and Figure 40) and driving amplifier can be selected depending on the input signal bandwidth of interest at the full throughput. Lower input signal bandwidth means that the RC cutoff can be lower, thereby reducing noise into the converter. For optimum performance at various throughputs, use the recommended RC values (200 Ω, 180 pF) and the ADA4805-1. The RC values shown in Table 10 are chosen for ease of drive considerations and greater ADC input protection. The combination of a large R value (200 Ω) and small C value results in a reduced dynamic load for the amplifier to drive. The smaller value of C means fewer stability and phase margin concerns with the amplifier. The large value of R limits the current into the ADC input when the amplifier output exceeds the ADC input range. Rev. E | Page 22 of 40 Data Sheet AD4000/AD4004/AD4008 Table 10. RC Filter and Amplifier Selection for Various Input Bandwidths Input Signal Bandwidth (kHz)