AD4005BCPZ-RL7

16-Bit, 2 MSPS/1 MSPS, Precision, Differential SAR ADCs AD4001/AD4005 Data Sheet FEATURES GENERAL DESCRIPTION Easy Drive Greatly reduced input kickback Input current reduced to 0.5 μA/MSPS Enhanced acquisition phase, ≥79% of cycle time at 1 MSPS First conversion accurate, no latency or pipeline delay Input span compression for single-supply operation Fast conversion allows low SPI clock rates Input overvoltage clamp protection sinks up to 50 mA SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface High performance Differential analog input range: ±VREF, VREF from 2.4 V to 5.1 V Throughput: 2 MSPS/1 MSPS options INL: ±0.4 LSB maximum Guaranteed 16-bit, no missing codes SNR: 96.2 dB at fIN = 1 kHz, VREF = 5 V THD: −123 dB at fIN = 1 kHz, −99 dB at fIN = 100 kHz SINAD: 88.5 dB at fIN = 1 MHz (see Figure 17) Oversampled dynamic range 99.3 dB for OSR = 2 126 dB for OSR = 1024 Low power Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface 4.9 mW at 1 MSPS (VDD only) 80 μW at 10 kSPS, 16 mW at 2 MSPS (total power) 10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP Pin compatible with AD4003/AD4007/AD4011 family Guaranteed operation: −40°C to +125°C The AD4001/AD4005 are high accuracy, high speed, low power, 16-bit, Easy Drive, precision successive approximation register (SAR) analog-to-digital converters (ADCs) that operate from a single power supply, VDD. The reference voltage, VREF, is applied externally and can be set independent of the supply voltage. The AD4001/AD4005 power scales linearly with throughput. Easy Drive features reduce both signal chain complexity and power consumption while enabling higher channel density. The reduced input current, particularly in high-Z mode, coupled with a long signal acquisition phase, eliminates the need for a dedicated ADC driver. Easy Drive broadens the range of companion circuitry that is capable of driving these ADCs (see Figure 2). Input span compression eliminates the need to provide a negative supply to the ADC driver amplifier while preserving access to the full ADC code range. The input overvoltage clamp protects the ADC inputs against overvoltage events, minimizing disturbances on the reference pin and eliminating the need for external protection diodes. Fast device throughput up to 2 MSPS allows users to accurately capture high frequency signals and to implement oversampling techniques to alleviate the challenges associated with antialias filter designs. Decreased serial peripheral interface (SPI) clock rate requirements reduce digital input and output power consumption, broadens digital host options, and simplifies the task of sending data across digital isolation. The SPI-compatible serial user interface is compatible with 1.8 V, 2.5 V, 3 V, and 5 V logic by using the separate VIO logic supply. APPLICATIONS Automated test equipment Machine automation Medical equipment Battery-powered equipment Precision data acquisition systems Instrumentation and control systems 15 INPUT CURRENT (μA) 9 FUNCTIONAL BLOCK DIAGRAM 1.8V VREF VREF /2 0 VREF VREF /2 0 IN+ IN– HIGH-Z MODE VDD AD4001/ AD4005 16-BIT SAR ADC TURBO MODE SERIAL INTERFACE STATUS BITS SPAN CLAMP COMPRESSION SCK SDO CNV –3 –6 –15 –5 –4 –3 –2 –1 0 1 2 3 4 INPUT DIFFERENTIAL VOLTAGE (V) 5 Figure 2. Input Current vs. Input Differential Voltage Figure 1. Rev. C 0 –12 3-WIRE OR 4-WIRE SPI INTERFACE (DAISY CHAIN, CS) GND 3 –9 VIO 1.8V TO 5V SDI 15368-001 REF 6 15368-328 2.4V TO 5.1V 10µF HIGH-Z DISABLED, 2MSPS HIGH-Z ENABLED, 2MSPS 12 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2017–2021 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD4001/AD4005 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Driver Amplifier Choice ........................................................... 22  Applications ....................................................................................... 1  Ease of Drive Features ............................................................... 24  Functional Block Diagram .............................................................. 1  Voltage Reference Input ............................................................ 25  General Description ......................................................................... 1  Power Supply............................................................................... 25  Revision History ............................................................................... 2  Digital Interface .......................................................................... 25  Specifications..................................................................................... 4  Register Read/Write Functionality........................................... 27  Timing Specifications .................................................................. 7  Status Bits .................................................................................... 29  Absolute Maximum Ratings............................................................ 9  CS Mode, 3-Wire Turbo Mode ................................................. 30  Thermal Resistance ...................................................................... 9  CS Mode, 3-Wire Without Busy Indicator ............................. 31  ESD Caution .................................................................................. 9  CS Mode, 3-Wire with Busy Indicator .................................... 32  Pin Configurations and Function Descriptions ......................... 10  CS Mode, 4-Wire Turbo Mode ................................................. 33  Typical Performance Characteristics ........................................... 11  CS Mode, 4-Wire Without Busy Indicator ............................. 34  Terminology .................................................................................... 17  Theory of Operation ...................................................................... 18  Circuit Information .................................................................... 18  Converter Operation .................................................................. 19  Transfer Functions...................................................................... 19  Applications Information .............................................................. 20  Typical Application Diagrams .................................................. 20  CS Mode, 4-Wire with Busy Indicator .................................... 35  Daisy-Chain Mode ..................................................................... 36  Layout Guidelines....................................................................... 37  Evaluating the AD4001/AD4005 Performance.......................... 37  Outline Dimensions ....................................................................... 38  Ordering Guide .......................................................................... 39  Analog Inputs .............................................................................. 21  REVISION HISTORY 2/2021—Rev. B to Rev. C Changes to Features Section, Applications Section, General Description Section, and Figure 2 .................................................. 1 Changes to Specifications Section and Table 1 ............................. 4 Changes to Timing Specifications Section .................................... 7 Added Note 1 to Table 2; Renumbered Sequentially ................... 7 Changes to Note 3, Table 2 .............................................................. 7 Deleted Figure 3; Renumbered Sequentially................................. 7 Added Note 1 to Table 3 .................................................................. 8 Added Note 2, Table 5 ...................................................................... 9 Changes to Thermal Resistance Section........................................ 9 Changes to Table 7 .......................................................................... 10 Changes to Typical Performance Characteristics Section......... 11 Changes to Terminology Section ................................................. 17 Changes to Circuit Information Section and Table 8 ................ 18 Changes to Typical Application Diagram Section ..................... 20 Changes to Input Overvoltage Clamp Circuit Section .............. 21 Changes to Driver Amplifier and Table 10 ................................. 22 Changes to Single to Differential Driver Section, High Frequency Input Signals Section, and Multiplexed Applications Section .............................................................................................. 23 Changes to Input Span Compression Section, High-Z Mode Section, Figure 46 Caption, and Figure 47 Caption................... 24 Changes Long Acquisition Phase Section, Voltage Reference Input Section, and Digital Interface Section ............................... 25 Deleted Table 12; Renumbered Sequentially .............................. 26 Added Configuration Register Details Section, Serial Clock Frequency Requirements Section, and Table 12; Renumbered Sequentially ..................................................................................... 26 Added Table 13 and Register Read/Write Functionality Section ... 27 Changes to Figure 48 and Figure 49............................................. 28 Changed Status Word Section to Status Bits Section ................. 29 Changes to Status Bits Section, Table 15, and Figure 51 ........... 29 Changes to CS Mode, 3-Wire Turbo Mode Section and Figure 52 .......................................................................................... 30 Changes to CS Mode, 3-Wire Without Busy Indicator Section and Figure 54................................................................................... 31 Changes to CS Mode, 3-Wire With Busy Indicator Section and Figure 56 and Figure 57 ................................................................. 32 Changes to CS Mode, 4-Wire Turbo Mode Section and Figure 58 .......................................................................................... 33 Changes to Figure 56 and Figure 57............................................. 32 Changes to Figure 58...................................................................... 33 Rev. C | Page 2 of 39 Data Sheet AD4001/AD4005 Changes to CS Mode, 4-Wire Without Busy Indicator Section and Figure 60 ...................................................................................34 Changes to CS Mode, 4-Wire With Busy Indicator Section and Figure 63 ...........................................................................................35 Changes to Daisy-Chain Mode and Figure 64 ............................36 Changes to Layout Guidelines Section and Evaluating the AD4001-AD4005 Performance Section .......................................37 Updated Outline Dimensions ........................................................38 Changes to Ordering Guide ...........................................................39 8/2017—Rev. A to Rev. B Changes to General Description Section ....................................... 1 Changes to Table 1 ............................................................................ 6 Changes to Endnote 3, Table 2 ........................................................ 7 Changes to Table 4 ............................................................................ 8 Change to Pin 3 Description and Pin 4 Description, Table 7....10 Reorganized Typical Performance Characteristics Section .......13 Changes to Figure 17, Figure 19, and Figure 21 ..........................13 Added Figure 23; Renumbered Sequentially ...............................14 Changes to Figure 27 ......................................................................15 Changes to Circuit Information Section and Table 8 .................17 Changes to Endnote 1 and Endnote 2, Table 9 ............................18 Changes to Figure 37 Caption and RC Filter Values Section ....21 Changes to High Frequency Input Signals Section, Figure 38 Caption, and Figure 39 Caption ....................................................22 Added Multiplexed Applications Section and Figure 40 ...........22 Changes to Figure 41 and Figure 42 Caption ..............................23 Changes to Figure 43, Figure 44 Caption, Figure 45, and Voltage Reference Input Section..................................................................24 Changes to Power Supply Section, Figure 46, Figure 47, Digital Interface Section, and Table 11 ......................................................25 Changes to CS Mode, 3-Wire Turbo Mode Section ...................29 Changes to CS Mode, 3-Wire with Busy Induction Section and Figure 56 ...........................................................................................31 Changes to CS Mode, 4-Wire Turbo Mode Section and Figure 58 ...........................................................................................32 Changes to CS Mode, 4-Wire with Busy Indicator Section and Figure 62 ...........................................................................................34 4/2017—Rev. 0 to Rev. A Added AD4005 ................................................................... Universal Changes to Title, Features Section, General Description Section, and Figure 1 ....................................................................................... 1 Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 6 Changes to Table 4 ............................................................................ 7 Changes to Figure 19 Caption and Figure 21 .............................. 12 Changes to Figure 24 ...................................................................... 13 Added Figure 25; Renumbered Sequentially ............................... 13 Changes to Circuit Information Section and Table 8 ................. 16 Changes to RC Filter Values Section ............................................ 20 Changes to High Frequency Input Signals Section .................... 21 Changes to High-Z Mode Section and Figure 41 ....................... 22 Changes to Long Acquisition Phase Section ............................... 23 Changes to Digital Interface Section and Register Read/Write Functionality Section ...................................................................... 24 Changes to CS Mode, 3-Wire Turbo Mode Section ................... 27 Changes to CS Mode, 4-Wire Turbo Mode Section ................... 30 Changes to Layout Guidelines Section and Evaluating the AD4001/AD4005 Performance Section ....................................... 34 Updated Outline Dimensions........................................................ 35 Changes to Ordering Guide ........................................................... 35 1/2017—Revision 0: Initial Version Rev. C | Page 3 of 39 AD4001/AD4005 Data Sheet SPECIFICATIONS VDD = 1.71 V to 1.89 V, VIO = 1.71 V to 5.5 V, REF = VREF = 5 V, all specifications TMIN to TMAX, high-Z mode disabled, span compression disabled, turbo mode enabled, and sampling frequency (fS) = 2 MSPS for the AD4001 and fS = 1 MSPS for the AD4005, unless otherwise noted. Table 1. Parameter RESOLUTION ANALOG INPUT Voltage Range Operating Input Voltage Common-Mode Input Range Common-Mode Rejection Ratio (CMRR) Analog Input Current THROUGHPUT Complete Cycle AD4001 AD4005 Conversion Time Acquisition Phase1 AD4001 AD4005 Throughput Rate2 (fS) AD4001 AD4005 Transient Response3 DC ACCURACY No Missing Codes Integral Nonlinearity Error (INL) Differential Nonlinearity Error (DNL) Transition Noise Zero Error Zero Error Drift4 Gain Error Gain Error Drift4 Power Supply Sensitivity 1/f Noise5 AC ACCURACY Dynamic Range Oversampled Dynamic Range Test Conditions/Comments Min 16 IN+ voltage (VIN+) – IN- voltage (VIN−) Span compression enabled VIN+, VIN− to GND Span compression enabled −VREF −VREF × 0.8 −0.1 0.1 × VREF VREF/2 − 0.125 Input frequency (fIN) = 500 kHz Acquisition phase, T = 25°C High-Z mode enabled, converting dc input at 2 MSPS Typ VREF/2 68 0.3 1 Max Unit Bits +VREF +VREF × 0.8 VREF + 0.1 0.9 × VREF VREF/2 + 0.125 V V V V V dB nA μA 500 1000 290 320 290 790 ns ns 0 0 2 1 250 16 −0.4 −0.5 ns ns ns MSPS MSPS ns VDD = 1.8 V ± 5% Bandwidth = 0.1 Hz to 10 Hz 0.25 6 Bits LSB LSB LSB LSB ppm/°C LSB ppm/°C LSB μV p-p Oversampling ratio (OSR) = 2 OSR = 256 OSR = 1024 96.3 99.3 120 126 54 dB dB dB dB μV rms −1.5 −0.28 −16.5 −0.23 Total RMS Noise Rev. C | Page 4 of 39 ±0.2 ±0.2 0.35 ±0.1 ±0.4 +0.4 +0.5 +1.5 +0.28 +16.5 +0.23 Data Sheet Parameter fIN = 1 kHz, −0.5 dBFS, VREF = 5 V Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Total Harmonic Distortion (THD) Signal-to-Noise-and-Distortion Ratio (SINAD) fIN = 1 kHz, −0.5 dBFS, VREF = 2.5 V SNR SFDR THD SINAD fIN = 100 kHz, −0.5 dBFS, VREF = 5 V SNR THD SINAD fIN = 400 kHz, −0.5 dBFS, VREF = 5 V SNR THD SINAD −3 dB Input Bandwidth Aperture Delay Aperture Jitter REFERENCE VREF Voltage Range Current AD4001 AD4005 INPUT OVERVOLTAGE CLAMP IN+/IN− Current (IIN+/IIN−) VIN+/VIN− at Maximum IIN+/IIN− VIN+/VIN− Clamp On/Off Threshold Deactivation Time REF Current at Maximum IIN+/IIN− DIGITAL INPUTS Logic Levels Input Voltage, Low (VIL) Input Voltage, High (VIH) AD4001/AD4005 Test Conditions/Comments Min Typ 95.6 96.2 122 −123 96 dB dB dB dB 93.2 118 −117 93 dB dB dB dB 95.5 −99 93.8 dB dB dB 91 −92 89 10 1 1 dB dB dB MHz ns ps rms 95.5 92.1 92 REF − GND VREF = 5 V 2 MSPS 1 MSPS 2.4 Max 5.1 1.1 0.5 VREF = 5 V VREF = 2.5 V VREF = 5 V VREF = 2.5 V VREF = 5 V VREF = 2.5 V 5.25 2.68 VIN+/VIN− > VREF VIO > 2.7 V VIO ≤ 2.7 V VIO > 2.7 V VIO ≤ 2.7 V Input Current, Low (IIL) Input Current, High (IIH) Input Pin Capacitance 6 Rev. C | Page 5 of 39 V mA mA 50 50 mA mA V V V V ns μA +0.3 × VIO +0.2 × VIO VIO + 0.3 VIO + 0.3 +1 +1 V V V V μA μA pF 5.4 3.1 5.4 2.8 360 100 −0.3 −0.3 0.7 × VIO 0.8 × VIO −1 −1 Unit AD4001/AD4005 Data Sheet Parameter DIGITAL OUTPUTS Data Format Pipeline Delay Test Conditions/Comments Min Output Voltage, Low (VOL) Output Voltage, High (VOH) POWER SUPPLIES VDD VIO Standby Current Power Dissipation Output current = 500 μA Output current = −500 μA Serial 16 bits, twos complement Conversion results available immediately after completed conversion 0.4 VIO − 0.3 VDD Only REF Only VIO Only Energy per Conversion TEMPERATURE RANGE Specified Performance 1.71 1.71 VDD = 1.8 V, VIO = 1.8 V, T = 25°C VDD = 1.8 V, VIO = 1.8 V, VREF = 5 V 10 kSPS, high-Z mode disabled 1 MSPS, high-Z mode disabled 2 MSPS, high-Z mode disabled 1 MSPS, high-Z mode enabled 2 MSPS, high-Z mode enabled 1 MSPS, high-Z mode disabled 2 MSPS, high-Z mode disabled 1 MSPS, high-Z mode disabled 2 MSPS, high-Z mode disabled 1 MSPS, high-Z mode disabled 2 MSPS, high-Z mode disabled TMIN to TMAX 1.8 Max 1.89 5.5 1.6 80 8 16 10 20 4.9 9.5 2.8 5.5 0.4 1.0 8 −40 1 Typ 9.3 18.5 12.3 24.5 +125 Unit V V V V μA μW mW mW mW mW mW mW mW mW mW mW nJ/sample °C The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS for the AD4001 and 1 MSPS for the AD4005. 2 A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 70 MHz. Refer to Table 4 for the maximum achievable throughput for different modes of operation. 3 Transient response is the time required for the ADC to acquire a full-scale input step to ±1 LSB accuracy. 4 The minimum and maximum values are guaranteed by characterization, but not production tested. 5 See the 1/f noise plot in Figure 25. Rev. C | Page 6 of 39 Data Sheet AD4001/AD4005 TIMING SPECIFICATIONS VDD = 1.71 V to 1.89 V, VIO = 1.71 V to 5.5 V, VREF = 5 V, all specifications TMIN to TMAX, high-Z mode disabled, span compression disabled, turbo mode enabled, and sampling frequency (fS) = 2 MSPS for the AD4001 and fS = 1 MSPS for the AD4005, unless otherwise noted. See Figure 48 to Figure 51, Figure 53, Figure 55, Figure 57, Figure 59, Figure 61, Figure 63, and Figure 65. Table 2. Digital Interface Timing Parameter1 CONVERSION TIME—CNV RISING EDGE TO DATA AVAILABLE ACQUISITION PHASE2 AD4001 AD4005 TIME BETWEEN CONVERSIONS AD4001 AD4005 CNV PULSE WIDTH (CS MODE)3 Symbol tCONV tACQ Min 270 Typ 290 Max 320 Unit ns 290 790 ns ns 500 1000 10 ns ns ns 9.8 12.3 ns ns 20 25 3 3 1.5 ns ns ns ns ns tCYC tCNVH tSCK SCK PERIOD (CS MODE) VIO > 2.7 V VIO > 1.7 V SCK PERIOD (DAISY-CHAIN MODE)5 VIO > 2.7 V VIO > 1.7 V SCK LOW TIME SCK HIGH TIME SCK FALLING EDGE TO DATA REMAINS VALID DELAY SCK FALLING EDGE TO DATA VALID DELAY VIO > 2.7 V VIO > 1.7 V 4 tSCK tSCKL tSCKH tHSDO tDSDO CNV OR SDI LOW TO SDO D15 MOST SIGNIFICANT BIT (MSB) VALID DELAY (CS MODE) VIO > 2.7 V VIO > 1.7 V CNV RISING EDGE TO FIRST SCK RISING EDGE DELAY LAST SCK FALLING EDGE TO CNV RISING EDGE DELAY6 CNV OR SDI HIGH OR LAST SCK FALLING EDGE TO SDO HIGH IMPEDANCE (CS MODE) 7.5 10.5 ns ns 10 13 ns ns ns ns ns tEN tQUIET1 tQUIET2 tDIS 190 60 SDI VALID HOLD TIME FROM CNV RISING EDGE (CS MODE) tSSDICNV tHSDICNV 2 2 ns ns SCK VALID HOLD TIME FROM CNV RISING EDGE (DAISY-CHAIN MODE) SDI VALID SETUP TIME FROM SCK RISING EDGE (DAISY-CHAIN MODE) SDI VALID HOLD TIME FROM SCK RISING EDGE (DAISY-CHAIN MODE) tHSCKCNV tSSDISCK tHSDISCK 12 2 2 ns ns ns SDI VALID SETUP TIME FROM CNV RISING EDGE 1 20 Timing parameters measured with respect to a falling edge are defined as triggered at x% VIO. Timing parameters measured with respect to a rising edge are defined as triggered at y% VIO. For VIO ≤ 2.7 V, x = 80 and y = 20. For VIO > 2.7 V, x = 70 and y = 30. The minimum VIH and maximum VIL are used. See digital inputs specifications in Table 1. 2 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS for the AD4001 and 1 MSPS for the AD4005. 3 For turbo mode, tCNVH must match the tQUIET1 minimum. 4 A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK frequency of 70 MHz. Refer to Table 4 for the maximum achievable throughput for different modes of operation. See the Serial Clock Frequency Requirements section for guidelines on determining the minimum SCK rate required for a given throughput. 5 A 50% duty cycle is assumed for SCK. 6 See Figure 24 for SINAD vs. tQUIET2. Rev. C | Page 7 of 39 AD4001/AD4005 Data Sheet Table 3. Register Read/Write Timing Parameter READ/WRITE OPERATION CNV Pulse Width2 SCK Period VIO > 2.7 V VIO > 1.7 V SCK Low Time SCK High Time READ OPERATION CNV Low to SDO D15 MSB Valid Delay VIO > 2.7 V VIO > 1.7 V SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO > 2.7 V VIO > 1.7 V CNV Rising Edge to SDO High Impedance WRITE OPERATION SDI Valid Setup Time from SCK Rising Edge SDI Valid Hold Time from SCK Rising Edge CNV Rising Edge to SCK Edge Hold Time CNV Falling Edge to SCK Active Edge Setup Time 1 2 Symbol1 Min tCNVH tSCK 10 ns 9.8 12.3 3 3 ns ns ns ns tSCKL tSCKH Typ Max Unit tEN tHSDO tDSDO ns ns ns 7.5 10.5 20 ns ns ns 1.5 tDIS tSSDISCK tHSDISCK tHCNVSCK tSCNVSCK 10 13 2 2 0 6 ns ns ns ns See Figure 48 to Figure 51, Figure 53, Figure 55, Figure 57, Figure 59, Figure 61, Figure 63, and Figure 65. For turbo mode, tCNVH must match the tQUIET1 minimum. Table 4. Achievable Throughput for Different Modes of Operation Parameter THROUGHPUT, CS MODE 3-Wire and 4-Wire Turbo Mode 3-Wire and 4-Wire Turbo Mode and Six Status Bits 3-Wire and 4-Wire Mode 3-Wire and 4-Wire Mode and Six Status Bits Test Conditions/Comments fSCK = 100 MHz, VIO ≥ 2.7 V fSCK = 80 MHz, VIO < 2.7 V fSCK = 100 MHz, VIO ≥ 2.7 V fSCK = 80 MHz, VIO < 2.7 V fSCK = 100 MHz, VIO ≥ 2.7 V fSCK = 80 MHz, VIO < 2.7 V fSCK = 100 MHz, VIO ≥ 2.7 V fSCK = 80 MHz, VIO < 2.7 V Rev. C | Page 8 of 39 Min Typ Max Unit 2 2 2 1.86 1.82 1.69 1.64 1.5 MSPS MSPS MSPS MSPS MSPS MSPS MSPS MSPS Data Sheet AD4001/AD4005 ABSOLUTE MAXIMUM RATINGS Note that the input overvoltage clamp cannot sustain the overvoltage condition for an indefinite amount of time. THERMAL RESISTANCE Rating Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. −0.3 V to VREF + 0.4 V or ±50 mA2 θJA is the natural convection junction-to-ambient thermal resistance measured in a one cubic foot sealed enclosure. θJC is the junction-to-case thermal resistance. Table 5. Parameter Analog Inputs IN+, IN− to GND1 Supply Voltage REF, VIO to GND VDD to GND VDD to VIO Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature Lead Temperature Soldering ESD Ratings Human Body Model Machine Model Field Induced Charged Device Model 1 2 −0.3 V to +6.0 V −0.3 V to +2.1 V −6 V to +2.4 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.3 V −65°C to +150°C 150°C 260°C reflow as per JEDEC J-STD-020 Table 6. Thermal Resistance Package Type1 RM-10 CP-10-9 1 θJA 147 114 θJC 38 33 Unit °C/W °C/W Test Condition 1: thermal impedance simulated values are based upon use of 2S2P JEDEC PCB. See the Ordering Guide. ESD CAUTION 4 kV 200 V 1.25 kV See the Analog Inputs section for an explanation of IN+ and IN−. Current condition tested over a 10 ms time interval. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. C | Page 9 of 39 AD4001/AD4005 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS REF 1 IN+ 3 VDD 2 IN+ 3 IN– 4 AD4001/ AD4005 TOP VIEW (Not to Scale) GND 5 10 VIO IN– 4 9 SDI GND 5 8 SCK 7 SDO 6 CNV TOP VIEW (Not to Scale) 9 SDI 8 SCK 7 SDO 6 CNV NOTES 1. CONNECT THE EXPOSED PAD TO GND. THIS CONNECTION IS NOT REQUIRED TO MEET THE SPECIFIED PERFORMANCE. 15368-003 REF 1 10 VIO AD4001/ AD4005 Figure 3. 10-Lead MSOP Pin Configuration 15368-004 VDD 2 Figure 4. 10-Lead LFCSP Pin Configuration Table 7. Pin Function Descriptions Pin No. 1 Mnemonic REF Type1 AI 2 3 4 5 6 VDD IN+ IN− GND CNV P AI AI P DI 7 SDO DO 8 9 SCK SDI DI DI 10 VIO P N/A2 EPAD P 1 2 Description Reference Input Voltage. The VREF range is 2.4 V to 5.1 V. This pin is referred to the GND pin and must be decoupled closely to the GND pin with a 10 μF, X7R ceramic capacitor. 1.8 V Power Supply. The VDD range is 1.71 V to 1.89 V. Bypass VDD to GND with a 0.1 μF ceramic capacitor. Differential Positive Analog Input. See the Differential Input Considerations section. Differential Negative Analog Input. See the Differential Input Considerations section. Power Supply Ground. Connect to the ground plane of the board. Convert Input. This input has multiple functions. On its leading edge, the input initiates the conversions and selects the interface mode of the device, which is either daisy-chain mode or CS mode. In CS mode, the SDO pin is enabled when CNV is low. In daisy-chain mode, the data is read when CNV is high. Serial Data Output. The conversion result is output on this pin. The SDO pin is synchronized to the SCK signal on the SCK pin. Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock. Serial Data Input. This input provides multiple features and selects the interface mode of the ADC as follows: Daisy-chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 16 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. With CNV low, program the device by clocking in a 16-bit word on SDI on the rising edge of SCK. Input/Output Interface Digital Power. Nominally, this pin is at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). Bypass VIO to GND with a 0.1 μF ceramic capacitor. Exposed Pad. Connect the exposed pad to GND. This connection is not required to meet the specified performance. Note that the exposed pad only applies to the LFCSP. AI is analog input, P is power, DI is digital input, and DO is digital output. N/A means not applicable. Rev. C | Page 10 of 39 Data Sheet AD4001/AD4005 TYPICAL PERFORMANCE CHARACTERISTICS VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, T = 25°C, high-Z mode disabled, span compression disabled, turbo mode enabled, and fS = 2 MSPS for the AD4001 and fS = 1 MSPS for the AD4005, unless otherwise noted. 0.4 0.3 0.2 0.2 0.1 0.1 0 –0.1 0 –0.3 –0.3 16384 24576 32768 40960 49152 57344 65536 CODE –0.4 0 0.2 0.1 0.1 0 –0.2 –0.2 –0.3 –0.3 16384 24576 32768 40960 49152 57344 65536 CODE 15368-201 –0.1 8192 –0.4 8192 16384 24576 0.4 0.2 0.1 0.1 0 –0.1 –0.2 –0.2 –0.3 –0.3 16384 24576 32768 CODE 40960 49152 57344 65536 –0.4 15368-407 8192 32768 40960 49152 57344 65536 0 –0.1 0 65536 HIGH-Z ENABLED SPAN COMPRESSION ENABLED 0.3 DNL (LSB) INL (LSB) 0 0.2 –0.4 57344 Figure 9. DNL vs. Code for Various Temperatures, VREF = 2.5 V HIGH-Z ENABLED SPAN COMPRESSION ENABLED 0.3 49152 CODE Figure 6. INL vs. Code for Various Temperatures, VREF = 2.5 V 0.4 40960 0 –0.1 0 32768 –40°C +25°C +125°C 0.3 DNL (LSB) INL (LSB) 0.4 0.2 –0.4 24576 Figure 8. DNL vs. Code for Various Temperatures, VREF = 5 V –40°C +25°C +125°C 0.3 16384 CODE Figure 5. INL vs. Code for Various Temperatures, VREF = 5 V 0.4 8192 15368-204 8192 Figure 7. INL vs. Code for High-Z and Span Compression Modes Enabled, VREF = 5 V 0 8192 16384 24576 32768 CODE 40960 49152 57344 65536 15368-410 0 15368-200 –0.2 15368-203 –0.1 –0.2 –0.4 –40°C +25°C +125°C 0.3 DNL (LSB) INL (LSB) 0.4 –40°C +25°C +125°C Figure 10. DNL vs. Code for High-Z and Span Compression Modes Enabled, VREF = 5 V Rev. C | Page 11 of 39 AD4001/AD4005 600000 500000 800000 400000 CODE COUNT 1000000 600000 200000 200000 100000 32766 32767 32768 32769 32770 CODE 0 0 –80 –100 –120 –140 10k 100k 1M FREQUENCY (Hz) –40 –60 –80 –100 –120 –140 –180 100 10k 100k 1M Figure 15. 1 kHz, −0.5 dBFS Input Tone FFT, VREF = 2.5 V 0 FUNDAMENTAL AMPLITUDE (dB) VREF = 5V SNR = 95.48dB THD = –98.63dB SINAD = 93.84dB –60 –80 –100 –120 –140 VREF = 5V SNR = 91.04dB –20 THD = –91.47dB SINAD = 88.85dB –40 –60 –80 –100 –120 –140 10k 100k FREQUENCY (Hz) 1M Figure 13. 100 kHz, −0.5 dBFS Input Tone FFT –180 1k 10k 100k FREQUENCY (Hz) Figure 16. 400 kHz, −0.5 dBFS Input Tone FFT Rev. C | Page 12 of 39 1M 15368-213 –160 15368-210 –160 –180 1k 1k FREQUENCY (Hz) Figure 12. 1 kHz, −0.5 dBFS Input Tone Fast Fourier Transform (FFT), VREF = 5 V FUNDAMENTAL AMPLITUDE (dB) VREF = 2.5V SNR = 93.12dB THD = –118.26dB SINAD = 93.11dB 15368-209 1k 15368-207 –180 100 –40 32770 –160 –160 –20 32769 0 –60 0 32768 –20 FUNDAMENTAL AMPLITUDE (dB) –40 32767 Figure 14. Histogram of a DC Input at Code Transition, VREF = 2.5 V and VREF = 5 V VREF = 5V SNR = 96.25dB THD = –124.30dB SINAD = 96.23dB –20 32766 CODE Figure 11. Histogram of a DC Input at Code Center, VREF = 2.5 V and VREF = 5 V FUNDAMENTAL AMPLITUDE (dB) 300000 400000 0 VREF = 5V VREF = 2.5V 15368-208 VREF = 5V VREF = 2.5V 15368-205 CODE COUNT 1200000 Data Sheet Data Sheet AD4001/AD4005 94 15.2 93 15.0 92 14.8 91 14.6 90 14.4 –95 120 THD SFDR SNR SINAD ENOB 89 88 THD (dB) 14.2 1k 10k 14.0 1M 100k INPUT FREQUENCY (Hz) 110 –110 105 –115 100 –120 95 1k 15.8 –116 15.7 –118 15.5 94.5 15.4 94.0 92.5 2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 15.1 5.1 REFERENCE VOLTAGE (V) 125 –124 124 –118 15.72 –119 15.71 –120 15.67 96.1 95.9 –40 –20 0 20 40 60 80 100 120 4.2 4.5 120 5.1 4.8 127.1 THD SFDR 127.0 126.9 126.8 –123 126.7 –124 126.6 126.5 –127 15.64 –128 15.63 –129 –40 TEMPERATURE (°C) 3.9 –126 15.65 SNR SINAD ENOB 3.6 –125 15.66 96.0 3.3 –122 THD (dB) 15.68 3.0 –121 ENOB (Bits) 96.2 2.7 REFERENCE VOLTAGE (V) 15.73 15.69 121 –132 2.4 15.70 96.3 122 Figure 21. THD and SFDR vs. Reference Voltage, fIN = 1 kHz 15368-222 SRN, SINAD (dB) 96.4 123 –130 Figure 18. SNR, SINAD, and ENOB vs. Reference Voltage, fIN = 1 kHz 96.5 126 –128 15.2 93.0 127 –126 15.3 93.5 128 –122 THD (dB) 95.0 129 SFDR THD –120 15.6 ENOB (Bits) SNR, SINAD (dB) 95.5 90 1M 100k Figure 20. THD and SFDR vs. Input Frequency 15368-219 96.0 ENOB SNR SINAD 10k INPUT FREQUENCY (Hz) Figure 17. SNR, SINAD, and Effective Number of Bits (ENOB) vs. Input Frequency 96.5 115 –105 –125 15368-211 SRN, SINAD (dB) –100 SFDR (dB) 15.4 15368-214 95 SFDR (dB) 15.6 125 15368-216 96 –90 SFDR (dB) 15.8 Figure 19. SNR, SINAD, and ENOB vs. Temperature, fIN = 1 kHz 126.4 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 22. THD and SFDR vs. Temperature, fIN = 1 kHz Rev. C | Page 13 of 39 126.3 15368-225 97 AD4001/AD4005 130 Data Sheet –80 DYNAMIC RANGE FREQUENCY = 1kHz FREQUENCY = 10kHz 125 –85 –90 –95 115 –100 –105 110 –110 105 –115 100 1 2 4 8 16 32 64 128 256 512 1024 DECIMATION RATE –125 Figure 23. SNR vs. Decimation Rate for Various Input Frequencies, 2 MSPS 0.8 ZERO ERROR, GAIN ERROR (LSB) SINAD (dB) 94 93 92 91 90 0 20 40 60 80 100 tQUIET2 (ns) 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –1.0 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 24. SINAD vs. tQUIET2 Figure 27. Zero Error and Gain Error vs. Temperature (PFS is Positive Full Scale and NFS is Negative Full Scale) 60 15 HIGH-Z HIGH-Z HIGH-Z HIGH-Z 12 59 9 INPUT CURRENT (μA) ADC OUTPUT READING (µV) ZERO ERROR PFS ERROR NFS ERROR –0.8 VIO = 1.89V VIO = 3.6V VIO = 5.5V 15368-215 89 20 Figure 26. THD vs. Input Frequency for Various Source Impedances 1.0 95 10 INPUT FREQUENCY (kHz) 97 96 1 15368-228 –120 15368-212 95 150Ω HIGH-Z DISABLED 150Ω HIGH-Z ENABLED 510Ω HIGH-Z DISABLED 510Ω HIGH-Z ENABLED 1kΩ HIGH-Z DISABLED 1kΩ HIGH-Z ENABLED 15368-221 SNR (dB) 120 58 57 56 DISABLED, 2MSPS DISABLED, 1MSPS ENABLED, 2MSPS ENABLED, 1MSPS 6 3 0 –3 –6 –9 55 1 2 3 4 5 6 TIME (Seconds) 7 8 9 10 Figure 25. 1/f Noise for 0.1 Hz to 10 Hz Bandwidth, 50 kSPS, 2500 Samples Averaged per Reading Rev. C | Page 14 of 39 –15 –5 –4 –3 –2 –1 0 1 2 3 4 5 INPUT DIFFERENTIAL VOLTAGE (V) Figure 28. Analog Input Current vs. Input Differential Voltage 15368-301 0 15368-217 –12 54 Data Sheet AD4001/AD4005 8 72 71 6 70 5 CMRR (dB) VDD HIGH-Z DISABLED VDD HIGH-Z ENABLED REF HIGH-Z DISABLED REF HIGH-Z ENABLED VIO HIGH-Z DISABLED VIO HIGH-Z ENABLED 4 3 69 68 2 67 1 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 66 100 15368-223 0 –40 1k 10k 100k 1M FREQUENCY (Hz) Figure 29. Operating Current vs. Temperature, AD4001, 2 MSPS 15368-303 OPERATING CURRENT (mA) 7 Figure 32. CMRR vs. Frequency 80 4.5 4.0 3.0 70 PSRR (dB) OPERATING CURRENT (mA) 75 3.5 2.5 VDD HIGH-Z ENABLED VDD HIGH-Z DISABLED REF HIGH-Z ENABLED REF HIGH-Z DISABLED VIO HIGH-Z ENABLED VIO HIGH-Z DISABLED 2.0 1.5 65 60 1.0 55 0 20 40 60 80 100 120 TEMPERATURE (°C) 50 100 1k Figure 30. Operating Current vs. Temperature, AD4005, 1 MSPS 1.1 VDD VIO REF TOTAL POWER 1.0 1k 100 10 1 0.1 0.01 10 POWER DISSIPATION MEASUREMENTS APPLY TO EACH PRODUCT OVER ITS SPECIFIED THROUGHPUT RANGE. 100 1k 10k 100k THROUGHPUT (SPS) 1M 2M 1M 2MSPS 1MSPS 0.9 0.8 0.7 0.6 0.5 0.4 0.3 15368-220 POWER DISSIPATION (µW) 10k 100k Figure 33. PSRR vs. Frequency REFERENCE CURRENT (mA) 100k 10k FREQUENCY (Hz) Figure 31. Power Dissipation vs. Throughput 0.2 2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 REFERENCE VOLTAGE (V) Figure 34. Reference Current vs. Reference Voltage Rev. C | Page 15 of 39 5.1 15368-218 –20 15368-325 0 –40 15368-302 0.5 AD4001/AD4005 Data Sheet 25.0 23 22.5 21 17.5 17 tDSDO (ns) 15.0 12.5 10.0 15 13 11 7.5 9 5.0 –20 0 20 40 60 80 100 TEMPERATURE (°C) 120 Figure 35. Standby Current vs. Temperature 5 0 20 40 60 80 100 120 140 160 180 LOAD CAPACITANCE (pF) Figure 36. tDSDO vs. Load Capacitance Rev. C | Page 16 of 39 200 220 15368-224 7 2.5 0 –40 VIO = 5V VIO = 3.3V VIO = 1.8V 19 15368-226 STANDBY CURRENT (µA) 20.0 Data Sheet AD4001/AD4005 TERMINOLOGY Integral Nonlinearity Error (INL) INL is the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 38). Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Zero Error Zero error is the difference between the ideal voltage that results in the first code transition (½ LSB above analog ground) and the actual voltage producing that code. Gain Error The first transition (from 100 ... 00 to 100 ... 01) occurs at a level ½ LSB above nominal negative full scale (−4.999981 V for the ±5 V range). The last transition (from 011 … 10 to 011 … 11) occurs for an analog voltage 1½ LSB below the nominal full scale (+4.999943 V for the ±5 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured. The value for dynamic range is expressed in decibels. It is measured with a signal at −60 dBFS so that it includes all noise sources and DNL artifacts. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-Noise-and-Distortion Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components that are less than the Nyquist frequency, including harmonics but excluding dc. The value of SINAD is expressed in decibels. Aperture Delay Aperture delay is the measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Transient Response Transient response is the time required for the ADC to acquire a full-scale input step to ±1 LSB accuracy. Common-Mode Rejection Ratio (CMRR) CMRR is the ratio of the power in the ADC output at the frequency, f, to the power of a 200 mV p-p sine wave applied to the common-mode voltage of IN+ and IN− of frequency, f. CMRR (dB) = 10log(PADC_IN/PADC_OUT) Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD as follows: where: PADC_IN is the common-mode power at the frequency, f, applied to the IN+ and IN− inputs. PADC_OUT is the power at the frequency, f, in the ADC output. ENOB = (SINAD − 1.76)/6.02 ENOB is expressed in bits, and SINAD is expressed in dB. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Power Supply Rejection Ratio (PSRR) PSRR is the ratio of the power in the ADC output at the frequency, f, to the power of a 200 mV p-p sine wave applied to the ADC VDD supply of frequency, f. PSRR (dB) = 10 log(PVDD_IN/PADC_OUT) where: PVDD_IN is the power at the frequency, f, at the VDD pin. PADC_OUT is the power at the frequency, f, in the ADC output. Rev. C | Page 17 of 39 AD4001/AD4005 Data Sheet THEORY OF OPERATION IN+ SWITCHES CONTROL MSB REF GND 32,768C 16,384C LSB 4C 2C C SW+ C BUSY COMP 32,768C 16,384C 4C 2C C CONTROL LOGIC C MSB OUTPUT CODE LSB SW– 15368-007 CNV IN– Figure 37. ADC Simplified Schematic CIRCUIT INFORMATION The AD4001/AD4005 are high speed, low power, single-supply, precise, 16-bit differential ADCs based on a SAR architecture. The AD4001 is capable of converting 2,000,000 samples per second (2 MSPS), the AD4005 is capable of converting 1,000,000 samples per second (1 MSPS). The power consumption of the AD4001/AD4005 scales with throughput because they power down in between conversions. For example, when operating at 10 kSPS, the devices typically consume 80 μW, making them ideal for battery-powered applications. The AD4001/AD4005 also have a valid first conversion after being powered down for long periods, which can further reduce power consumed in applications in which the ADC does not need to be constantly converting. For single-supply applications, a span compression feature creates additional headroom and footroom for the driving amplifier to access the full range of the ADC. The fast conversion time of the AD4001/AD4005, along with turbo mode, allows low clock rates to read back conversions, even when running at their respective maximum throughput rates of 2 MSPS/1 MSPS. Note that, for the AD4001, the full throughput rate of 2 MSPS can be achieved only with turbo mode enabled. The AD4001/AD4005 can interface with any 1.8 V to 5 V digital logic family. These devices are available in a 10-lead MSOP or a tiny 10-lead LFCSP that allows space savings and flexible configurations. The AD4001/AD4005 are pin for pin compatible with some of the 14-/16-/18-/20-bit precision SAR ADCs listed in Table 8. The AD4001/AD4005 provide the user with an on-chip trackand-hold and do not exhibit any pipeline delay or latency, making them ideal for multiplexed applications. Table 8. MSOP and LFCSP 14-/16-/18-/20-Bit Precision SAR ADCs The AD4001/AD4005 incorporate a multitude of unique, easy to use features that result in a lower system power and smaller footprint. Bits 201 The AD4001/AD4005 each have an internal voltage clamp that protects the device from overvoltage damage on the analog inputs. 181 The analog input incorporates circuitry that reduces the nonlinear charge kickback seen from a typical switched capacitor SAR input. This reduction in kickback, combined with a longer acquisition phase, allows the use of lower bandwidth and lower power amplifiers as drivers. This combination has the additional benefit of allowing a larger resistor value in the input RC filter and a corresponding smaller capacitor, which results in a smaller RC load for the amplifier, improving stability and power dissipation. High-Z mode can be enabled via the SPI interface by programming a register bit (see Table 12). When high-Z mode is enabled, the ADC input has a low input charging current at low input signal frequencies, as well as improved distortion over a wide frequency range up to 100 kHz. For frequencies greater than 100 kHz and multiplexing functionality, disable high-Z mode. 100 kSPS Not applicable AD7989-12 250 kSPS Not applicable AD76912 183 AD7684 AD76872 163 AD7680, AD7683, AD7988-12 AD76852, AD7694 143 AD7940 AD79422 True differential. Pin for pin compatible. 3 Pseudo differential. 2 Rev. C | Page 18 of 39 AD40112, AD76902, AD7989-52 AD40102 161 1 400 kSPS to 500 kSPS AD40222 AD76882, AD76932, AD79162 AD40082, AD76862, AD7988-52 AD79462 ≥1000 kSPS AD40202, AD40212 AD40032, AD40072, AD79822, AD79842 AD40022, AD40062 AD4001, AD4005, AD79152 AD40002, AD40042, AD79802, AD79832 Not applicable Data Sheet AD4001/AD4005 During the acquisition phase, terminals of the array tied to the input of the comparator are connected to ground via the SW+ and SW− switches (see Figure 37). All independent switches connect the other terminal of each capacitor to the analog inputs. The capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN− inputs. Because the AD4001 and the AD4005 have on-board conversion clocks, the serial clock, SCK, is not required for the conversion process. TRANSFER FUNCTIONS The ideal transfer characteristics for the AD4001/AD4005 are shown in Figure 38 and Table 9. When the acquisition phase is complete and the CNV input goes high, a conversion phase initiates. When the conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. The differential voltage between the IN+ and IN− inputs captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and VREF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4, …, VREF/65,536). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After 011...111 011...110 011...101 100...010 100...001 100...000 –FSR –FSR + 1 LSB –FSR + 0.5 LSB +FSR – 1 LSB +FSR – 1.5 LSB ANALOG INPUT 15368-008 The AD4001/AD4005 are SAR-based ADCs using a charge redistribution sampling digital-to-analog converter (DAC). Figure 37 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary weighted capacitors, which are connected to the comparator inputs. the process completes, the control logic generates the ADC output code and a busy signal indicator. ADC CODE (TWOS COMPLEMENT) CONVERTER OPERATION Figure 38. ADC Ideal Transfer Function (FSR Is Full-Scale Range) Table 9. Output Codes and Ideal Input Voltages Description +FSR − 1 LSB Midscale + 1 LSB Midscale Midscale − 1 LSB −FSR + 1 LSB −FSR Analog Input, VREF = 5 V +4.999847 V +152.6 μV 0V −152.6 μV −4.999847 V −5 V VREF = 5 V with Span Compression Enabled +3.999878 V +122.1 μV 0V −122.1 μV −3.999878 V −4 V 1 Digital Output Code (Hex) 0x7FFF1 0x0001 0x0000 0xFFFF 0x8001 0x80002 This output code is also the code for an overranged analog input (VIN+ − VIN− above VREF with span compression disabled and above 0.8 × VREF with span compression enabled). 2 This output code is also the code for an underranged analog input (VIN+ − VIN− below −VREF with span compression disabled and below −0.8 × VREF with span compression enabled). Rev. C | Page 19 of 39 AD4001/AD4005 Data Sheet APPLICATIONS INFORMATION Figure 40 shows a recommended connection diagram when using a single-supply system. This setup is preferable when only a limited number of rails are available in the system and power dissipation is of critical importance. TYPICAL APPLICATION DIAGRAMS Figure 39 shows an example of the recommended connection diagram for the AD4001/AD4005 when multiple supplies, V+ and V−, are available. This configuration is used for optimal performance because the amplifier supplies can be selected to allow the maximum signal range (see Figure 39 for the range). Figure 41 shows a typical application diagram when using a fully differential amplifier (FDA). V+ ≥ +6.5V REF LDO 1.8V AMP VCM = VREF/2 5V 10kΩ 0.1µF 10kΩ V+ AMP VREF VCM = VREF /2 1.8V TO 5V 0.1µF R REF C 0V VDD VIO SDI IN+ V– AD4001/AD4005 IN– R AMP CNV GND 3-WIRE/4-WIRE INTERFACE C 0V DIGITAL HOST (MICROPROCESSOR/ FPGA) V– 15368-009 VCM = VREF /2 SCK SDO V+ VREF HOST SUPPLY 10µF V– ≤ –0.5V Figure 39. Typical Application Diagram with Multiple Supplies V+ = +5V REF1 LDO AMP VCM = VREF/2 4.096V 1.8V 10kΩ 10kΩ AMP 0.9 × VREF VCM = VREF/2 0.1 × VREF 0.1µF 0.1µF 100nF 100nF 1.8V TO 5V R REF C VDD VIO SDI IN+ AD4001/AD40052 SCK SDO IN– AMP 0.9 × VREF VCM = VREF/2 0.1 × VREF HOST SUPPLY 10µF1 R GND DIGITAL HOST (MICROPROCESSOR/ FPGA) CNV 3-WIRE/4-WIRE INTERFACE C 1 SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE 2 SPAN COMPRESSION MODE ENABLED. 3 SEE TABLE 10 FOR RC FILTER AND AMPLIFIER SELECTION. SELECTION. CREF IS USUALLY A 10µF CERAMIC CAPACITOR (X7R). Figure 40. Typical Application Diagram with a Single Supply Rev. C | Page 20 of 39 15368-010 3 Data Sheet AD4001/AD4005 V+ = +5V REF LDO AMP VCM = VREF /2 VREF VCM = VREF/2 R4 1kΩ R3 1kΩ 10kΩ 0 1.8V 4.096V 10kΩ 10µF 1.8V TO 5V 0.1µF 0.1µF HOST SUPPLY V+ +IN VOCM 0.1µF –IN GND SCK SDO CNV 3-WIRE/4-WIRE INTERFACE V– R1 1kΩ 0 DIGITAL HOST (MICROPROCESSOR/ FPGA) 15368-011 VREF SDI IN– R DIFFERENTIAL AMPLIFIER VIO AD4001/AD4005 C +OUT VDD IN+ C VCM = VREF/2 VCM = VREF/2 REF R –OUT R2 1kΩ Figure 41. Typical Application Diagram with a Fully Differential Amplifier reference, which is particularly important for systems that share the reference among multiple ADCs. ANALOG INPUTS Figure 42 shows an equivalent circuit of the analog input structure, including the overvoltage clamp of the AD4001/AD4005. If the analog input exceeds the reference voltage by 0.4 V, the internal clamp circuit turns on and the current flows through the clamp into ground, preventing the input from rising further and potentially causing damage to the device. The clamp turns on before D1 (see Figure 42) and can sink up to 50 mA of current. REF D1 VIN REXT RIN C IN IN+/IN– CEXT CPIN D2 CLAMP GND 15368-013 0V TO 15V Figure 42. Equivalent Analog Input Circuit Input Overvoltage Clamp Circuit Most ADC analog inputs, IN+ and IN−, have no overvoltage protection circuitry apart from ESD protection diodes. During an overvoltage event, an ESD protection diode from an analog input pin (IN+ or IN−) to REF forward biases and shorts the input pin to REF, potentially overloading the reference or damaging the device. The AD4001/AD4005 internal overvoltage clamp circuit with a larger external resistor (REXT = 200 Ω) eliminates the need for external protection diodes and protects the ADC inputs against dc overvoltages. In applications where the amplifier rails are greater than VREF and less than ground, it is possible for the output to exceed the input voltage range (specified in Table 1) of the device. In this case, the AD4001/AD4005 internal overvoltage clamp circuit ensures that the voltage on the input pin does not exceed VREF + 0.4 V and prevents damage to the device by clamping the input voltage in a safe operating range and avoiding disturbance of the When the clamp is active, it sets the overvoltage (OV) clamp flag bit in the configuration register that is accessed with a 16bit SPI read command or via the OV in the status bits. The OV clamp flag gives an indication of overvoltage condition when it is set to 0. The OV clamp flag is a read only sticky bit, and is cleared only if the register is read while the overvoltage condition is no longer present. The clamp circuit does not dissipate static power in the off state. Note that the clamp cannot sustain the overvoltage condition for an indefinite amount of time. The external RC filter, formed by the REXT resistor and the CEXT capacitor (see Figure 42), is usually present at the ADC input to band limit the input signal. During an overvoltage event, excessive voltage is dropped across REXT, and REXT becomes part of a protection circuit. The REXT value can vary from 200 Ω to 20 kΩ for 15 V protection. The CEXT value can be as low as 100 pF for correct operation of the clamp. See Table 1 for input overvoltage clamp specifications. Rev. C | Page 21 of 39 AD4001/AD4005 Data Sheet Differential Input Considerations DRIVER AMPLIFIER CHOICE The analog input structure allows the sampling of the true differential signal between IN+ and IN−. By using these differential inputs, signals common to both inputs are rejected. Figure 32 shows the common-mode rejection capability of the AD4001/AD4005 over frequency. It is important to note that the differential input signals must be truly antiphase in nature, 180° out of phase, which is required to keep the common-mode voltage of the input signal within the specified range around VREF/2 as shown in Table 1. Although the AD4001/AD4005 are easy to drive, the driver amplifier must meet the following requirements:  The noise generated by the driver amplifier must be kept low enough to preserve the SNR and transition noise performance of the AD4001/AD4005. The noise from the driver is filtered by the single-pole, low-pass filter of the AD4001/AD4005 analog input circuit made by RIN and CIN, or by the external filter, if one is used. Because the typical noise of the AD4001/AD4005 is 54 μV rms, the SNR degradation due to the amplifier is the following: Switched Capacitor Input During the acquisition phase, the impedance of the analog inputs (IN+ or IN−) can be modeled as a parallel combination of Capacitor CPIN and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 400 Ω and is a lumped component composed of serial resistors and the on resistance of the switches. CIN is typically 40 pF and is mainly the ADC sampling capacitor. SNRLOSS   54V  20 log   2 π 2  54V  f 3 dB (NeN ) 2        where: f−3 dB is the input bandwidth, in megahertz, of the AD4001/ AD4005 (10 MHz) or the cutoff frequency of the input filter, if one is used. N is the noise gain of the amplifier (for example, 1 in buffer configuration). eN is the equivalent input noise voltage of the operational amplifier in nV/√Hz. During the conversion phase, where the switches are open, the input impedance is limited to CPIN. RIN and CIN make a singlepole, low-pass filter that reduces undesirable aliasing effects and limits noise. RC Filter Values The RC filter value (represented by R and C in Figure 39 to Figure 43) and driving amplifier can be selected depending on the input signal bandwidth of interest at the full throughput. Lower input signal bandwidth means that the RC cutoff can be lower, thereby reducing noise into the converter. For optimum performance at various throughputs, use the recommended RC values (200 Ω, 180 pF) and the ADA4807-1.  For ac applications, the driver must have a THD performance commensurate with the AD4001/AD4005. For multichannel multiplexed applications, the driver amplifier and the analog input circuit of the AD4001/AD4005 must settle for a full-scale step onto the capacitor array at a 16-bit level (0.0001525%, 15.25 ppm). In amplifier data sheets, settling at 0.1% to 0.01% is more commonly specified. Settling at 0.1% to 0.01% may differ significantly from the settling time at a 16-bit level and must be verified prior to driver selection.  The RC values shown in Table 10 are chosen for ease of drive considerations and greater ADC input protection. The combination of a large R value (200 Ω) and small C value results in a reduced dynamic load for the amplifier to drive. The smaller value of C means fewer stability and phase margin concerns with the amplifier. The large value of R limits the current into the ADC input when the amplifier output exceeds the ADC input range. The Precision ADC Driver Tool can be used to model the settling behavior and estimate ac performance of the AD4001/AD4005 with a selected driver amplifier and RC filter. Once the Precision ADC Driver Tool has modelled a specific circuit, the circuit can be exported for simulation in LTspice. Table 10. RC Filter and Amplifier Selection for Various Input Bandwidths Input Signal Bandwidth (kHz)