18-Bit, 2 MSPS/1 MSPS/500 kSPS,
Easy Drive, Differential SAR ADCs
AD4003/AD4007/AD4011
Data Sheet
FEATURES
GENERAL DESCRIPTION
Easy Drive
Greatly reduced input kickback
Input current reduced to 0.5 μA/MSPS
Enhanced acquisition phase, ≥79% of cycle time at 1 MSPS
First conversion accurate, no latency or pipeline delay
Input span compression for single-supply operation
Fast conversion allows low SPI clock rates
Input overvoltage clamp protection sinks up to 50 mA
SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface
High performance
Differential analog input range: ±VREF, VREF from 2.4 V to 5.1 V
Throughput: 2 MSPS/1 MSPS/500 kSPS options
INL: ±1.0 LSB (±3.8 ppm) maximum
Guaranteed 18-bit, no missing codes
SNR: 100.5 dB at fIN = 1 kHz, VREF = 5 V
THD: −123 dB at fIN = 1 kHz, −100 dB at fIN = 100 kHz
SINAD: 89 dB at fIN = 1 MHz (see Figure 17)
Oversampled dynamic range
103.5 dB for OSR = 2
130.5 dB for OSR = 1024
Low power
Single 1.8 V supply operation with 1.71 V to 5.5 V logic
interface
2.4 mW at 500 kSPS (VDD only)
80 μW at 10 kSPS, 16 mW at 2 MSPS (total power)
10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP
Pin compatible with AD4000/AD4004/AD4008 family
Guaranteed operation: −40°C to +125°C
The AD4003/AD4007/AD4011 are high accuracy, high speed,
low power, 18-bit, Easy Drive, precision successive approximation
register (SAR) analog-to-digital converters (ADCs) that operate
from a single power supply, VDD. The reference voltage, VREF, is
applied externally and can be set independent of the supply
voltage. The AD4003/AD4007/AD4011 power scales linearly
with throughput.
APPLICATIONS
Automated test equipment
Machine automation
Medical equipment
Battery-powered equipment
Precision data acquisition systems
Instrumentation and control systems
INPUT CURRENT (μA)
VDD
TURBO
MODE
18-BIT
SAR
ADC
CLAMP
SPAN
COMPRESSION
SERIAL
INTERFACE
STATUS
BITS
GND
3
0
–3
–6
–9
–12
–15
–5
Figure 1.
Rev. D
6
–4
–3
–2
–1
0
1
2
3
4
INPUT DIFFERENTIAL VOLTAGE (V)
5
14957-443
IN–
HIGH-Z
MODE
VIO 1.8V TO 5V
SDI
3-WIRE OR
SCK 4-WIRE
SDO SPI INTERFACE
(DAISY CHAIN, CS)
CNV
14957-001
VREF
VREF /2
0
IN+
HIGH-Z DISABLED, 2MSPS
HIGH-Z ENABLED, 2MSPS
9
AD4003/
AD4007/
AD4011
VREF
VREF/2
0
Fast device throughput up to 2 MSPS allows users to accurately
capture high frequency signals and to implement oversampling
techniques to alleviate the challenges associated with antialias
filter designs. Decreased serial peripheral interface (SPI) clock
rate requirements reduce digital input and output power
consumption, broadens digital host options, and simplifies the
task of sending data across digital isolation. The SPI-compatible
serial user interface is compatible with 1.8 V, 2.5 V, 3 V, and 5 V
logic by using the separate VIO logic supply.
12
1.8V
REF
Input span compression eliminates the need to provide a
negative supply to the ADC driver amplifier while preserving
access to the full ADC code range. The input overvoltage clamp
protects the ADC inputs against overvoltage events, minimizing
disturbances on the reference pin and eliminating the need for
external protection diodes.
15
FUNCTIONAL BLOCK DIAGRAM
2.4V TO 5.1V
10µF
Easy Drive features reduce both signal chain complexity and power
consumption while enabling higher channel density. The reduced
input current, particularly in high-Z mode, coupled with a long
signal acquisition phase, eliminates the need for a dedicated
ADC driver. Easy Drive broadens the range of companion
circuitry that is capable of driving these ADCs (see Figure 2).
Figure 2. Input Current vs. Input Differential Voltage
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2016–2021 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD4003/AD4007/AD4011
Data Sheet
TABLE OF CONTENTS
Features ............................................................................................... 1
Driver Amplifier Choice ........................................................... 23
Applications ........................................................................................ 1
Ease of Drive Features ............................................................... 24
Functional Block Diagram .............................................................. 1
Voltage Reference Input ............................................................ 25
General Description ......................................................................... 1
Power Supply............................................................................... 26
Revision History ............................................................................... 2
Digital Interface .......................................................................... 26
Specifications..................................................................................... 4
Register Read/Write Functionality........................................... 28
Timing Specifications .................................................................. 7
Status Bits .................................................................................... 30
Absolute Maximum Ratings............................................................ 9
CS Mode, 3-Wire Turbo Mode ................................................. 31
Thermal Resistance ...................................................................... 9
CS Mode, 3-Wire Without Busy Indicator ............................. 32
ESD Caution .................................................................................. 9
CS Mode, 3-Wire with Busy Indicator .................................... 33
Pin Configurations and Function Descriptions ......................... 10
CS Mode, 4-Wire Turbo Mode ................................................. 34
Typical Performance Characteristics ........................................... 11
CS Mode, 4-Wire Without Busy Indicator ............................. 35
Terminology .................................................................................... 17
Theory of Operation ...................................................................... 18
Circuit Information .................................................................... 18
Converter Operation .................................................................. 19
Transfer Functions...................................................................... 19
Applications Information .............................................................. 20
Typical Application Diagrams .................................................. 20
CS Mode, 4-Wire with Busy Indicator .................................... 36
Daisy-Chain Mode ..................................................................... 37
Layout Guidelines....................................................................... 38
Evaluating the AD4003/AD4007/AD4011 Performance ...... 38
Outline Dimensions ....................................................................... 39
Ordering Guide .......................................................................... 40
Analog Inputs .............................................................................. 21
REVISION HISTORY
2/2021—Rev. C to Rev. D
Changes to Features Section, Applications Section, and General
Description Section .......................................................................... 1
Changes to Specifications Section and Table 1 ............................. 4
Changes to Timing Specifications Section .................................... 7
Added Note 1 to Table 2; Renumbered Sequentially ................... 7
Added Note 1 to Table 3 .................................................................. 8
Deleted Figure 3; Renumbered Sequentially................................. 8
Changes to Thermal Resistance Section........................................ 9
Changes to Table 7 .......................................................................... 10
Changes to Typical Performance Characteristics Section......... 11
Changes to Terminology Section ................................................. 17
Changes to Circuit Information Section and Table 8 ................ 18
Changes to Typical Application Diagrams Section .................... 20
Changes to Input Overvoltage Clamp Circuit Section .............. 21
Change to Differential Input Considerations Section and
Table 10 ............................................................................................ 22
Changes to Driver Amplifier Choice Section, Single to
Differential Driver Section, and High Frequency Input Signals
Section .............................................................................................. 23
Moved Figure 44 ............................................................................. 23
Changes to Multiplexed Applications Section and High-Z Mode
Section.............................................................................................. 24
Changes to Figure 47, Figure 48, Long Acquisition Phase
Section, and Voltage Reference Input Section ............................ 25
Deleted Table 12 and Table 14; Renumbered Sequentially .............. 26
Changes to Power Supply Section and Digital Interface Section.... 26
Added Configuration Register Details Section and Serial Clock
Frequency Requirements Section ......................................................... 26
Added Table 12 and Table 13; Renumbered Sequentially ................ 27
Changes to Register Read/Write Functionality Section ................... 28
Changes to Figure 49 and Figure 50 ..................................................... 29
Changed Status Word Section to Status Bits Section ........................ 30
Changes to Status Bits Section, Table 15, and Figure 52 ................... 30
Changes to CS Mode, 3-Wire Turbo Mode Section, Figure 53, and
Figure 54 Caption..................................................................................... 31
Changes to CS Mode, 3-Wire Without Busy Indicator Section,
Figure 55, and Figure 56 Caption.......................................................... 32
Changes to CS Mode, 3-Wire with Busy Indicator Section,
Figure 57, and Figure 58 ......................................................................... 33
Changes to CS Mode, 4-Wire Turbo Mode Section, Figure 59, and
Figure 60 Caption..................................................................................... 34
Rev. D | Page 2 of 40
Data Sheet
AD4003/AD4007/AD4011
Changes to CS Mode, 4-Wire Without Busy Indicator Section and
Figure 62 Caption .................................................................................... 35
Changes to CS Mode, 4-Wire with Busy Indicator Section and
Figure 64 .................................................................................................... 36
Changes to Daisy-Chain Mode Section and Figure 66 Caption..... 37
Changes to Layout Guide Section and Evaluating the
AD4003/AD4007/AD4011 Performance Section ............................. 38
Updated Outline Dimensions ............................................................... 39
4/2019—Rev. B to Rev. C
Added Figure 2; Renumbered Sequentially ................................... 1
Changes to Features Section and General Description Section ..... 1
10/2017—Rev. A to Rev. B
Changes to Features and General Description .............................. 1
Moved Figure 1 .................................................................................. 1
Changes to Specifications Section and Table 1 ............................. 4
Changes to Endnote 1 and Endnote 2, Table 1 .............................. 6
Changes to Timing Specifications Section, CNV or SDI Low to
SDO D17 (MSB) Valid Delay (CS Mode) Parameter, Table 2 .... 7
Changes to Endnote 3, Table 2 ........................................................ 7
Changes to Analog Input Parameter, Table 5 ................................ 9
Added Endnote 2, Table 5 ................................................................ 9
Changes to Figure 4 and Table 7 ...................................................10
Changes to Typical Performance Characteristics Section .........11
Reorganized Typical Performance Characteristics Section .......11
Changes to Figure 19 and Figure 19 Caption ..............................13
Changes to Figure 25 Caption through Figure 27 Caption and
Changes to Figure 28 ......................................................................14
Changes to Circuit Information Section and Table 8 .................17
Changes to Converter Operations Section and Table 9 .............18
Changes to Endnote 1 and Endnote 2, Table 9 ............................18
Changes to Applications Information Section ............................19
Moves Figure 38; Renumbered Sequentially ...............................20
Change to Analog Input Section ...................................................20
Changes to Input Overvoltage Clamp Section................................... 21
Changes to High Frequency Input Signals Section, Multiplexed
Applications Section, Driver Amplifier Choice Section, RC Filter
Values Section, Figure 39, and Figure 40 Caption ............................. 22
Changes to High-Z Mode Section, Figure 42, Figure 43, and
Figure 43 Caption ............................................................................23
Changes to Voltage Reference Input Section, Figure 44 Caption,
Figure 45, Figure 46 Caption, and Figure 47 ...............................24
Changes to Digital Interface Section, Power Supply Section, and
Figure 48 Caption ............................................................................25
Changes to Read/Write Functionality Section, Table 12, and
Table 14 .............................................................................................26
Changes to Figure 49 ...................................................................... 27
Changes to Status Word Section and Table 15 ............................ 28
Changes to CS Mode, 4-Wire Turbo Mode Section ....................... 32
Changes to CS Mode, 4-Wire Without Busy Indicator Section......33
Changes to CS Mode, 4-Wire With Busy Indicator Section ..... 34
Change to Daisy-Chain Mode Section ......................................... 35
Changes to Evaluating the AD4003/AD4007/AD4011
Performance Section ....................................................................... 36
Changes to Ordering Guide ........................................................... 38
7/2017—Rev. 0 to Rev. A
Added AD4007 and AD4011............................................ Universal
Changes to Features Section and General Description................ 1
Moved Figure 1 .................................................................................. 3
Changes to Specifications Section .................................................. 4
Changes to Table 1 ............................................................................ 4
Changes to Timing Specifications Section .................................... 7
Changes to Table 2 ............................................................................ 7
Changes to Absolute Maximum Ratings Section ......................... 9
Added Endnote 2 and Endnote 3, Table 6 ..................................... 9
Changes to Typical Performance Characteristics Section ......... 11
Changes to Figure 11 and Figure 14 ............................................. 12
Changes to Figure 19 and Figure 21 ............................................. 13
Added Figure 25 and Figure 26; Renumbered Sequentially ...... 14
Moved Terminology Section ......................................................... 16
Changes to Terminology Section .................................................. 16
Changes to Circuit Information Section and Table 8 ................. 17
Moved Figure 38 .............................................................................. 22
Changes to High Frequency Input Signals Section .................... 22
Added Multiplexed Applications Section .................................... 22
Added Figure 41 .............................................................................. 23
Moved Figure 42 .............................................................................. 23
Changes to High-Z Mode Section and Figure 43 ....................... 23
Changes to Voltage Reference Input Section............................... 24
Changes to Figure 48, Digital Interface Section, and Table 11 ....... 25
Changes to CS Mode, 3-Wire Turbo Mode Section ................... 29
Added Figure 53 .............................................................................. 29
Changes to CS Mode, 4-Wire Turbo Mode Section ................... 32
Added Figure 59 .............................................................................. 32
Change to CS Mode, 4-Wire with Busy Signal Indicator
Section .............................................................................................. 34
Changes to Layout Guidelines Section and Evaluating the
AD4003/AD4007/AD4011 Performance Section ....................... 36
Updated Outline Dimensions........................................................ 37
Changes to Ordering Guide ........................................................... 38
10/2016—Revision 0: Initial Version
Rev. D | Page 3 of 40
AD4003/AD4007/AD4011
Data Sheet
SPECIFICATIONS
VDD = 1.71 V to 1.89 V, VIO = 1.71 V to 5.5 V, REF = VREF = 5 V, all specifications TMIN to TMAX, high-Z mode disabled, span compression
disabled, turbo mode enabled, and sampling frequency (fS) = 2 MSPS for the AD4003, fS = 1 MSPS for the AD4007, and fS = 500 kSPS for
the AD4011, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range
Operating Input Voltage
Common-Mode Input Range
Common-Mode Rejection Ratio (CMRR)
Analog Input Current
Test Conditions/Comments
Min
18
IN+ voltage (VIN+) − IN− voltage (VIN−)
Span compression enabled
VIN+, VIN− to GND
Span compression enabled
−VREF
−VREF × 0.8
−0.1
0.1 × VREF
VREF/2 − 0.125
Input frequency (fIN) = 500 kHz
Acquisition phase, T = 25°C
High-Z mode enabled, converting
dc input at 2 MSPS
THROUGHPUT
Complete Cycle
AD4003
AD4007
AD4011
Conversion Time
Acquisition Phase1
AD4003
AD4007
AD4011
Throughput Rate2
AD4003
AD4007
AD4011
Transient Response3
DC ACCURACY
No Missing Codes
Integral Nonlinearity Error (INL)
Differential Nonlinearity Error (DNL)
Transition Noise
Zero Error
Zero Error Drift4
Gain Error
Gain Error Drift4
Power Supply Sensitivity
1/f Noise5
AC ACCURACY
Dynamic Range
Oversampled Dynamic Range
500
1000
2000
270
Typ
VREF/2
68
0.3
1
290
Max
Unit
Bits
+VREF
+VREF × 0.8
VREF + 0.1
0.9 × VREF
VREF/2 + 0.125
V
V
V
V
V
dB
nA
μA
320
290
790
1790
ns
ns
ns
0
0
0
2
1
500
250
18
−1.0
−3.8
−0.75
ns
ns
ns
ns
MSPS
MSPS
kSPS
ns
VDD = 1.8 V ± 5%
Bandwidth = 0.1 Hz to 10 Hz
1.5
6
Bits
LSB
ppm
LSB
LSB
LSB
ppm/°C
LSB
ppm/°C
LSB
μV p-p
Oversampling ratio (OSR) = 2
OSR = 256
OSR = 1024
101
104
125
131
31.5
dB
dB
dB
dB
μV rms
−7
−0.21
−26
−1.23
Total RMS Noise
Rev. D | Page 4 of 40
±0.4
±1.52
±0.3
0.8
±3
+1.0
+3.8
+0.75
+7
+0.21
+26
+1.23
Data Sheet
Parameter
fIN = 1 kHz, −0.5 dBFS, VREF = 5 V
Signal-to-Noise Ratio (SNR)
Spurious-Free Dynamic Range (SFDR)
Total Harmonic Distortion (THD)
Signal-to-Noise-and-Distortion Ratio
(SINAD)
fIN = 1 kHz, −0.5 dBFS, VREF = 2.5 V
SNR
SFDR
THD
SINAD
fIN = 100 kHz, −0.5 dBFS, VREF = 5 V
SNR
THD
SINAD
fIN = 400 kHz, −0.5 dBFS, VREF = 5 V
SNR
THD
SINAD
−3 dB Input Bandwidth
Aperture Delay
Aperture Jitter
REFERENCE
VREF Voltage Range
Current
AD4003
AD4007
AD4011
INPUT OVERVOLTAGE CLAMP
IN+/IN− Current, IIN+/IIN−
VIN+/VIN− at Maximum IIN+/IIN−
VIN+/VIN− Clamp On/Off Threshold
Deactivation Time
REF Current at Maximum IIN+/IIN−
DIGITAL INPUTS
Logic Levels
Input Voltage, Low (VIL)
Input Voltage, High (VIH)
AD4003/AD4007/AD4011
Test Conditions/Comments
Min
Typ
99
100.5
122
−123
100
dB
dB
dB
dB
94.5
122
−119
94
dB
dB
dB
dB
99
−100
96.5
dB
dB
dB
91.5
−94
90
10
1
1
dB
dB
dB
MHz
ns
ps rms
98.5
93.5
93
REF − GND
2.4
2 MSPS
1 MSPS
500 kSPS
Max
5.1
1.1
0.5
0.26
VREF = 5 V
VREF = 2.5 V
VREF = 5 V
VREF = 2.5 V
VREF = 5 V
VREF = 2.5 V
5.25
2.68
VIN+/VIN− > VREF
VIO > 2.7 V
VIO ≤ 2.7 V
VIO > 2.7 V
VIO ≤ 2.7 V
Input Current, Low (IIL)
Input Current, High (IIH)
Input Pin Capacitance
6
Rev. D | Page 5 of 40
V
mA
mA
mA
50
50
mA
mA
V
V
V
V
ns
μA
+0.3 × VIO
+0.2 × VIO
VIO + 0.3
VIO + 0.3
+1
+1
V
V
V
V
μA
μA
pF
5.4
3.1
5.4
2.8
360
100
−0.3
−0.3
0.7 × VIO
0.8 × VIO
−1
−1
Unit
AD4003/AD4007/AD4011
Data Sheet
Parameter
DIGITAL OUTPUTS
Data Format
Pipeline Delay
Test Conditions/Comments
Min
Output Voltage, Low (VOL)
Output Voltage, High (VOH)
POWER SUPPLIES
VDD
VIO
Standby Current
Power Dissipation
Output current = 500 μA
Output current = −500 μA
Serial 18 bits, twos complement
Conversion results available immediately
after completed conversion
0.4
VIO − 0.3
VDD Only
REF Only
VIO Only
Energy per Conversion
TEMPERATURE RANGE
Specified Performance
1.71
1.71
VDD = 1.8 V, VIO = 1.8 V, T = 25°C
VDD = 1.8 V, VIO = 1.8 V, VREF = 5 V
10 kSPS, high-Z mode disabled
500 kSPS, high-Z mode disabled
1 MSPS, high-Z mode disabled
2 MSPS, high-Z mode disabled
500 kSPS, high-Z mode enabled
1 MSPS, high-Z mode enabled
2 MSPS, high-Z mode enabled
500 kSPS, high-Z mode disabled
1 MSPS, high-Z mode disabled
2 MSPS, high-Z mode disabled
500 kSPS, high-Z mode disabled
1 MSPS, high-Z mode disabled
2 MSPS, high-Z mode disabled
500 kSPS, high-Z mode disabled
1 MSPS, high-Z mode disabled
2 MSPS, high-Z mode disabled
Typ
1.8
Max
1.89
5.5
1.6
80
4
8
16
5
10
20
2.4
4.9
9.5
1.4
2.8
5.5
0.1
0.4
1.0
4.7
9.3
18.5
6.2
12.3
24.5
8
TMIN to TMAX
−40
1
Unit
V
V
V
V
μA
μW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
nJ/sample
+125
°C
The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS for the
AD4003, 1 MSPS for the AD4007, and 500 kSPS for the AD4011.
2
A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK frequency of 75 MHz. Refer to Table 4 for the maximum achievable
throughput for different modes of operation.
3
Transient response is the time required for the ADC to acquire a full-scale input step to ±1 LSB accuracy.
4
The minimum and maximum values are guaranteed by characterization, but not production tested.
5
See the 1/f noise plot in Figure 25.
Rev. D | Page 6 of 40
Data Sheet
AD4003/AD4007/AD4011
TIMING SPECIFICATIONS
VDD = 1.71 V to 1.89 V; VIO = 1.71 V to 5.5 V; VREF = 5 V; all specifications TMIN to TMAX, high-Z mode disabled, span compression
disabled, turbo mode enabled, and fS = 2 MSPS for the AD4003, fS = 1 MSPS for the AD4007, and fS = 500 kSPS for the AD4011, unless
otherwise noted. See Figure 49 to Figure 52, Figure 54, Figure 56, Figure 58, Figure 60, Figure 62, Figure 64, and Figure 66 for timing
diagrams.
Table 2. Digital Interface Timing
Parameter1
CONVERSION TIME—CNV RISING EDGE TO DATA AVAILABLE
ACQUISITION PHASE2
AD4003
AD4007
AD4011
TIME BETWEEN CONVERSIONS
AD4003
AD4007
AD4011
CNV PULSE WIDTH (CS MODE)3
Symbol
tCONV
tACQ
Min
270
Typ
290
Max
320
Unit
ns
290
790
1790
ns
ns
ns
500
1000
2000
10
ns
ns
ns
ns
9.8
12.3
ns
ns
20
25
3
3
1.5
ns
ns
ns
ns
ns
tCYC
tCNVH
SCK PERIOD (CS MODE)4
tSCK
VIO > 2.7 V
VIO > 1.7 V
SCK PERIOD (DAISY-CHAIN MODE)5
VIO > 2.7 V
VIO > 1.7 V
SCK LOW TIME
SCK HIGH TIME
SCK FALLING EDGE TO DATA REMAINS VALID DELAY
SCK FALLING EDGE TO DATA VALID DELAY
VIO > 2.7 V
VIO > 1.7 V
CNV OR SDI LOW TO SDO D17 MOST SIGNIFICANT BIT (MSB) VALID DELAY (CS MODE)
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
7.5
10.5
ns
ns
10
13
ns
ns
ns
ns
ns
tEN
VIO > 2.7 V
VIO > 1.7 V
CNV RISING EDGE TO FIRST SCK RISING EDGE DELAY
LAST SCK FALLING EDGE TO CNV RISING EDGE DELAY6
CNV OR SDI HIGH OR LAST SCK FALLING EDGE TO SDO HIGH IMPEDANCE (CS MODE)
tQUIET1
tQUIET2
tDIS
190
60
SDI VALID SETUP TIME FROM CNV RISING EDGE
SDI VALID HOLD TIME FROM CNV RISING EDGE (CS MODE)
tSSDICNV
tHSDICNV
2
2
ns
ns
SCK VALID HOLD TIME FROM CNV RISING EDGE (DAISY-CHAIN MODE)
SDI VALID SETUP TIME FROM SCK RISING EDGE (DAISY-CHAIN MODE)
SDI VALID HOLD TIME FROM SCK RISING EDGE (DAISY-CHAIN MODE)
tHSCKCNV
tSSDISCK
tHSDISCK
12
2
2
ns
ns
ns
1
20
Timing parameters measured with respect to a falling edge are defined as triggered at x% VIO. Timing parameters measured with respect to a rising edge are defined
as triggered at y% VIO. For VIO ≤ 2.7 V, x = 80 and y = 20. For VIO > 2.7 V, x = 70 and y =30. The minimum VIH and maximum VIL are used. See the digital inputs
specifications in Table 1.
2
The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS for the
AD4003, 1 MSPS for the AD4007, and 500 kSPS for the AD4011.
3
For turbo mode, tCNVH must match the tQUIET1 minimum.
4
A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 75 MHz. Refer to Table 4 for the maximum achievable
throughput for different modes of operation.
5
A 50% duty cycle is assumed for SCK.
6
See Figure 24 for SINAD vs. tQUIET2.
Rev. D | Page 7 of 40
AD4003/AD4007/AD4011
Data Sheet
Table 3. Register Read/Write Timing
Parameter
READ/WRITE OPERATION
CNV Pulse Width2
SCK Period
VIO > 2.7 V
VIO > 1.7 V
SCK Low Time
SCK High Time
READ OPERATION
CNV Low to SDO D17 MSB Valid Delay
VIO > 2.7 V
VIO > 1.7 V
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO > 2.7 V
VIO > 1.7 V
CNV Rising Edge to SDO High Impedance
WRITE OPERATION
SDI Valid Setup Time from SCK Rising Edge
SDI Valid Hold Time from SCK Rising Edge
CNV Rising Edge to SCK Edge Hold Time
CNV Falling Edge to SCK Active Edge Setup Time
1
2
Symbol1
Min
tCNVH
tSCK
10
ns
9.8
12.3
3
3
ns
ns
ns
ns
tSCKL
tSCKH
Typ
Max
Unit
tEN
tHSDO
tDSDO
ns
ns
ns
7.5
10.5
20
ns
ns
ns
1.5
tDIS
tSSDISCK
tHSDISCK
tHCNVSCK
tSCNVSCK
10
13
2
2
0
6
ns
ns
ns
ns
See Figure 49 to Figure 52, Figure 54, Figure 56, Figure 58, Figure 60, Figure 62, Figure 64, and Figure 66.
For turbo mode, tCNVH must match the tQUIET1 minimum.
Table 4. Achievable Throughput for Different Modes of Operation
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
2
2
2
1.78
1.75
1.62
1.59
1.44
MSPS
MSPS
MSPS
MSPS
MSPS
MSPS
MSPS
MSPS
THROUGHPUT, CS MODE
3-Wire and 4-Wire Turbo Mode
3-Wire and 4-Wire Turbo Mode and Six Status Bits
3-Wire and 4-Wire Mode
3-Wire and 4-Wire Mode and Six Status Bits
fSCK = 100 MHz, VIO ≥ 2.7 V
fSCK = 80 MHz, VIO < 2.7 V
fSCK = 100 MHz, VIO ≥ 2.7 V
fSCK = 80 MHz, VIO < 2.7 V
fSCK = 100 MHz, VIO ≥ 2.7 V
fSCK = 80 MHz, VIO < 2.7 V
fSCK = 100 MHz, VIO ≥ 2.7 V
fSCK = 80 MHz, VIO < 2.7 V
Rev. D | Page 8 of 40
Data Sheet
AD4003/AD4007/AD4011
ABSOLUTE MAXIMUM RATINGS
Note that the input overvoltage clamp cannot sustain the
overvoltage condition for an indefinite amount of time.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Table 5.
Parameter
Analog Inputs
IN+, IN− to GND1
Supply Voltage
REF, VIO to GND
VDD to GND
VDD to VIO
Digital Inputs to GND
Digital Outputs to GND
Storage Temperature Range
Junction Temperature
Lead Temperature Soldering
Electrostatic Discharge (ESD) Ratings
Human Body Model (HBM)
Machine Model
Field Induced Charged Device Model
1
2
Rating
−0.3 V to VREF + 0.4 V
or ± 130 mA2
−0.3 V to +6.0 V
−0.3 V to +2.1 V
−6 V to +2.4 V
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
−65°C to +150°C
150°C
260°C reflow as per
JEDEC J-STD-020
θJA is the natural convection, junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure.
θJC is the junction to case thermal resistance.
Table 6. Thermal Resistance
Package Type1
RM-10
CP-10-9
1
θJA
147
114
θJC
38
33
Unit
°C/W
°C/W
Test Condition 1: thermal impedance simulated values are based upon use
of 2S2P JEDEC PCB. See the Ordering Guide.
ESD CAUTION
4 kV
200 V
1.25 kV
See the Analog Inputs section for an explanation of IN+ and IN−.
Current condition tested over a 10 ms time interval.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. D | Page 9 of 40
AD4003/AD4007/AD4011
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
REF 1
IN+ 3
IN– 4
VDD
2
IN+ 3
IN–
4
GND
5
AD4003/
AD4007
TOP VIEW
(Not to Scale)
10
VIO
9
SDI
8
SCK
7
SDO
6
CNV
GND 5
TOP VIEW
(Not to Scale)
9
SDI
8
SCK
7
SDO
6
CNV
NOTES
1. CONNECT THE EXPOSED PAD TO GND.
THIS CONNECTION IS NOT REQUIRED TO
MEET THE SPECIFIED PERFORMANCE.
14957-003
REF 1
10 VIO
AD4003/
AD4007/
AD4011
Figure 3. 10-Lead MSOP Pin Configuration
14957-004
VDD 2
Figure 4. 10-Lead LFCSP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
1
Mnemonic
REF
Type1
AI
2
3
4
5
6
VDD
IN+
IN−
GND
CNV
P
AI
AI
P
DI
7
SDO
DO
8
9
SCK
SDI
DI
DI
10
VIO
P
N/A2
EPAD
P
1
2
Description
Reference Input Voltage. The VREF range is 2.4 V to 5.1 V. This pin is referred to the GND pin and must be
decoupled closely to the GND pin with a 10 μF X7R ceramic capacitor.
1.8 V Power Supply. The VDD range is 1.71 V to 1.89 V. Bypass VDD to GND with a 0.1 μF ceramic capacitor.
Differential Positive Analog Input. See the Differential Input Considerations section.
Differential Negative Analog Input. See the Differential Input Considerations section.
Power Supply Ground. Connect to the ground plane of the board.
Convert Input. This input has multiple functions. On its leading edge, the input initiates the conversions
and selects the interface mode of the device, which is either daisy-chain mode or CS mode. In CS mode,
the SDO pin is enabled when CNV is low. In daisy-chain mode, the data is read when CNV is high.
Serial Data Output. The conversion result is output on the SDO pin. It is synchronized to the SCK signal
on the SCK pin.
Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock.
Serial Data Input. This input provides multiple features and selects the interface mode of the ADC as follows:
Daisy-chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data
input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data
level on SDI is output on SDO with a delay of 18 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable
the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy
indicator feature is enabled. With CNV low, program the device by clocking in a 16-bit word on SDI on
the rising edge of SCK.
Input/Output Interface Digital Power. Nominally, this pin is at the same supply as the host interface (1.8 V,
2.5 V, 3 V, or 5 V). Bypass VIO to GND with a 0.1 μF ceramic capacitor.
Exposed Pad. Connect the exposed pad to GND. This connection is not required to meet the specified
performance. Note that the exposed pad only applies to the LFCSP.
AI is analog input, P is power, DI is digital input, and DO is digital output.
N/A means not applicable.
Rev. D | Page 10 of 40
Data Sheet
AD4003/AD4007/AD4011
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, T = 25°C, high-Z mode disabled, span compression disabled, turbo mode enabled, and fS = 2 MSPS
for the AD4003, fS = 1 MSPS for the AD4007, and fS = 500 kSPS for the AD4011, unless otherwise noted.
1.0
0.4
0.8
+125°C
+25°C
–40°C
0.6
+125°C
+25°C
–40°C
0.3
0.2
0.2
DNL (LSB)
INL (LSB)
0.4
0
–0.2
–0.4
0.1
0
–0.1
–0.2
–0.6
0
32768
65536
98304 131072 163840 196608 229376 262144
CODE
–0.4
14957-200
–1.0
Figure 5. INL vs. Code for Various Temperatures, VREF = 5 V
0
32768
65536
98304 131072 163840 196608 229376 262144
CODE
14957-203
–0.3
–0.8
Figure 8. DNL vs. Code for Various Temperatures, VREF = 5 V
1.0
0.4
0.8
+125°C
+25°C
–40°C
0.6
0.3
0.2
0.2
DNL (LSB)
INL (LSB)
0.4
0
–0.2
0.1
0
–0.1
–0.4
–0.2
–0.6
32768
65536
98304 131072 163840 196608 229376 262144
CODE
–0.4
0
32768
65536
98304 131072 163840 196608 229376 262144
CODE
Figure 9. DNL vs. Code for Various Temperatures, VREF = 2.5 V
Figure 6. INL vs. Code for Various Temperatures, VREF = 2.5 V
1.8
0.8
1.7
0.6
+125°C
+25°C
–40°C
1.6
TRANSITION NOISE (LSB)
0.4
0
–0.2
–0.4
1.5
1.4
1.3
1.2
1.1
1.0
–0.6
0.9
HIGH-Z ENABLED
SPAN COMPRESSION ENABLED
32768
65536
98304 131072 163840 196608 229376 262144
CODE
0.8
2.5
14957-202
0
Figure 7. INL vs. Code for High-Z and Span Compression Modes Enabled, VREF = 5 V
3.0
3.5
4.0
REFERENCE VOLTAGE (V)
4.5
5.0
14957-206
INL (LSB)
0.2
–0.8
14957-204
0
14957-201
–1.0
+125°C
+25°C
–40°C
–0.3
–0.8
Figure 10. Transition Noise vs. Reference Voltage for Various Temperatures
Rev. D | Page 11 of 40
AD4003/AD4007/AD4011
Data Sheet
4.5M
3.0M
3.0M
2.5M
2.0M
2.0M
1.0M
1.0M
0.5M
0.5M
0
0
14957-205
1.5M
131078
131079
131080
131081
1.5M
CODE
Figure 11. Histogram of a DC Input at Code Center, VREF = 2.5 V and VREF = 5 V
CODE
Figure 14. Histogram of a DC Input at Code Transition, VREF = 2.5 V and
VREF = 5 V
0
0
VREF = 5V
SNR = 100.33dB
THD = –123.99dB
SINAD = 100.31dB
–40
–60
–80
–100
–120
–140
–40
–60
–80
–100
–120
–140
–160
10k
100k
1M
FREQUENCY (Hz)
–180
100
14957-207
1k
1M
0
VREF = 5V
SNR = 98.37dB
THD = –98.52dB
SINAD = 95.58dB
FUNDAMENTAL AMPLITUDE (dB)
–20
–60
–80
–100
–120
–140
–40
VREF = 5V
SNR = 91.22dB
THD = –91.97dB
SINAD = 89.15dB
–60
–80
–100
–120
–140
–160
10k
100k
FREQUENCY (Hz)
1M
Figure 13. 100 kHz, −0.5 dBFS Input Tone FFT
–180
1k
10k
100k
FREQUENCY (Hz)
Figure 16. 400 kHz, −0.5 dBFS Input Tone FFT
Rev. D | Page 12 of 40
1M
14957-213
–160
14957-210
FUNDAMENTAL AMPLITUDE (dB)
100k
Figure 15. 1 kHz, −0.5 dBFS Input Tone FFT, VREF = 2.5 V
0
–180
1k
10k
FREQUENCY (Hz)
Figure 12. 1 kHz, −0.5 dBFS Input Tone Fast Fourier Transform (FFT), VREF = 5 V
–40
1k
14957-209
–160
–20
VREF = 2.5V
SNR = 95.01dB
THD = –118.60dB
SINAD = 94.99dB
–20
FUNDAMENTAL AMPLITUDE (dB)
–20
FUNDAMENTAL AMPLITUDE (dB)
2.5M
131062
131063
131064
131065
131066
131067
131068
131069
131070
131071
131072
131073
131074
131075
131076
131077
CODE COUNT
3.5M
–180
100
VREF = 2.5V
VREF = 5V
4.0M
3.5M
131062
131063
131064
131065
131066
131067
131068
131069
131070
131071
131072
131073
131074
131075
131076
131077
CODE COUNT
4.0M
14957-208
VREF = 2.5V
VREF = 5V
131078
131079
131080
131081
4.5M
Data Sheet
AD4003/AD4007/AD4011
102
100
17.0
–90
120
16.5
–95
115
16.0
–100
110
–105
105
15.0
–110
100
14.5
–115
SFDR (dB)
15.5
94
THD (dB)
96
ENOB (Bits)
SNR, SINAD (dB)
98
92
ENOB
SINAD
SNR
–120
1k
INPUT FREQUENCY (Hz)
Figure 20. THD and SFDR vs. Input Frequency
Figure 17. SNR, SINAD, and Effective Number of Bits (ENOB) vs. Input
Frequency
16.6
101
16.4
16.2
–116
132
98
16.0
97
130
–122
129
–124
15.8
128
–126
96
15.6
ENOB
SINAD
SNR
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
15.4
5.1
–130
2.4
REFERENCE VOLTAGE (V)
3.3
3.6
3.9
4.2
4.5
4.8
126
5.1
–114.0
16.40
ENOB
SINAD
SNR
3.0
REFERENCE VOLTAGE (V)
16.42
100.6
2.7
127
Figure 21. THD and SFDR vs. Reference Voltage, fIN = 1 kHz
Figure 18. SNR, SINAD, and ENOB vs. Reference Voltage, fIN = 1 kHz
100.8
SFDR
THD
–128
14957-219
95
118.0
THD
SFDR
–114.5
117.9
117.8
16.38
100.4
–115.0
100.2
16.32
100.0
16.30
THD (dB)
16.34
ENOB (Bits)
16.36
16.28
99.8
117.7
117.6
–115.5
117.5
–116.0
117.4
117.3
–116.5
117.2
16.26
99.6
99.4
–40
–117.0
16.24
–20
0
20
40
60
80
100
120
16.22
TEMPERATURE (°C)
14957-222
SNR, SINAD (dB)
131
–120
THD (dB)
99
ENOB (Bits)
SNR, SINAD (dB)
133
–118
100
94
2.4
–114
–117.5
–40
117.1
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 22. THD and SFDR vs. Temperature, fIN = 1 kHz
Figure 19. SNR, SINAD, and ENOB vs. Temperature, fIN = 1 kHz
Rev. D | Page 13 of 40
117.0
14957-225
102
90
1M
100k
14957-216
INPUT FREQUENCY (Hz)
10k
14957-214
14.0
1M
100k
SFDR (dB)
10k
SFDR (dB)
88
1k
95
THD
SFDR
14957-211
90
AD4003/AD4007/AD4011
130
–90
–95
120
–100
THD (dB)
125
115
–110
105
–115
100
–120
95
–125
1
2
4
8
16
32
64
128
256
512 1024
DECIMATION RATE
1
10
20
10
98
97
0
10
20
30
40
50
60
70
80
tQUIET2 (ns)
4
2
0
–2
–4
–6
–8
–10
–40
14957-215
VIO = 1.89V
VIO = 3.6V
VIO = 5.5V
PFS GAIN ERROR
NFS GAIN ERROR
ZERO ERROR
6
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 27. Zero Error and Gain Error vs. Temperature (PFS Is Positive Full
Scale and NFS Is Negative Full Scale )
Figure 24. SINAD vs. tQUIET2
15
60
12
ANALOG INPUT CURRENT (μA)
59
58
57
56
55
9
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
DISABLED, 2MSPS
DISABLED, 1MSPS
DISABLED, 500kSPS
ENABLED, 2MSPS
ENABLED, 1MSPS
ENABLED, 500kSPS
6
3
0
–3
–6
–9
1
2
3
4
5
6
7
8
9
TIME (Seconds)
10
–15
–5
–4
–3
–2
–1
0
1
2
3
4
5
INPUT DIFFERENTIAL VOLTAGE (V)
Figure 28. Analog Input Current vs. Input Differential Voltage
Figure 25. 1/f Noise for 0.1 Hz to 10 Hz Bandwidth, 50 kSPS,
2500 Samples Averaged per Reading
Rev. D | Page 14 of 40
14957-343
0
14957-217
–12
54
14957-221
99
96
8
ZERO ERROR AND GAIN ERROR (LSB)
100
ADC OUTPUT READING (µV)
150Ω HIGH-Z DISABLED
150Ω HIGH-Z ENABLED
Figure 26. THD vs. Input Frequency for Various Source Impedances
101
95
1kΩ HIGH-Z DISABLED
1kΩ HIGH-Z ENABLED
510Ω HIGH-Z DISABLED
510Ω HIGH-Z ENABLED
INPUT FREQUENCY (KHz)
Figure 23. SNR vs. Decimation Rate for Various Input Frequencies, 2 MSPS
SINAD (dB)
–105
110
14957-212
SNR (dB)
–85
DYNAMIC RANGE
fIN = 1kHz
fIN = 10kHz
14957-228
135
Data Sheet
Data Sheet
AD4003/AD4007/AD4011
8
72
OPERATING CURRENT (mA)
7
71
6
70
CMRR (dB)
5
VDD HIGH-Z DISABLED
VDD HIGH-Z ENABLED
REF HIGH-Z DISABLED
REF HIGH-Z ENABLED
VIO HIGH-Z DISABLED
VIO HIGH-Z ENABLED
4
3
69
68
2
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
66
100
14957-223
0
–40
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 29. Operating Current vs. Temperature, AD4003, 2 MSPS
14957-303
67
1
Figure 32. CMRR vs. Frequency
4.5
80
4.0
3.0
70
PSRR (dB)
2.5
1.5
1.0
VDD HIGH-Z ENABLED
VDD HIGH-Z DISABLED
REF HIGH-Z ENABLED
REF HIGH-Z DISABLED
VIO HIGH-Z ENABLED
VIO HIGH-Z DISABLED
60
55
0.5
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
50
100
14957-326
0
–40
65
1k
Figure 30. Operating Current vs. Temperature, AD4007, 1 MSPS
REFERENCE CURRENT (mA)
1.5
0
–40
1M
2MSPS
1MSPS
500kSPS
1.0
VDD HIGH-Z ENABLED
VDD HIGH-Z DISABLED
REF HIGH-Z ENABLED
REF HIGH-Z DISABLED
VIO HIGH-Z ENABLED
VIO HIGH-Z DISABLED
0.8
0.6
0.4
0.2
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
14957-325
OPERATING CURRENT (mA)
1.2
2.0
0.5
100k
Figure 33. PSRR vs. Frequency
2.5
1.0
10k
FREQUENCY (Hz)
14957-302
2.0
Figure 31. Operating Current vs. Temperature, AD4011, 500 kSPS
0
2.4
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
REFERENCE VOLTAGE (V)
Figure 34. Reference Current vs. Reference Voltages
Rev. D | Page 15 of 40
5.1
14957-218
OPERATING CURRENT (mA)
75
3.5
AD4003/AD4007/AD4011
100k
23
VDD
VIO
REF
TOTAL POWER
21
1k
tDSDO (ns)
17
100
10
15
13
11
1
9
POWER DISSIPATION MEASUREMENTS
APPLY TO EACH PRODUCT OVER ITS
SPECIFIED THROUGHPUT RANGE.
0.01
10
100
1k
10k
100k
1M 2M
THROUGHPUT (SPS)
7
25.0
22.5
20.0
17.5
15.0
12.5
10.0
7.5
5.0
0
20
40
60
80
100
TEMPERATURE (°C)
120
14957-226
2.5
–20
0
20
40
60
80
100
120
140
160
LOAD CAPACITANCE (pF)
Figure 37. tDSDO vs. Load Capacitance
Figure 35. Power Dissipation vs. Throughput, VIO = 1.8 V
0
–40
5
Figure 36. Standby Current vs. Temperature
Rev. D | Page 16 of 40
180
200
220
14957-224
0.1
STANDBY CURRENT (µA)
VIO = 5V
VIO = 3.3V
VIO = 1.8V
19
14957-220
POWER DISSIPATION (µW)
10k
Data Sheet
Data Sheet
AD4003/AD4007/AD4011
TERMINOLOGY
Integral Nonlinearity Error (INL)
INL is the deviation of each individual code from a line drawn
from negative full scale through positive full scale. The point
used as negative full scale occurs ½ LSB before the first code
transition. Positive full scale is defined as a level 1½ LSB beyond
the last code transition. The deviation is measured from the
middle of each code to the true straight line (see Figure 39).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Zero Error
Zero error is the difference between the ideal voltage that
results in the first code transition (1/2 LSB above analog
ground) and the actual voltage producing that code.
Gain Error
The first transition (from 100 ... 00 to 100 ... 01) occurs at a level
½ LSB above nominal negative full scale (−4.999981 V for the
±5 V range). The last transition (from 011 … 10 to 011 … 11)
occurs for an analog voltage 1½ LSB below the nominal full
scale (+4.999943 V for the ±5 V range). The gain error is the
deviation of the difference between the actual level of the last
transition and the actual level of the first transition from the
difference between the ideal levels.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD as follows:
ENOB = (SINADdB − 1.76)/6.02
ENOB is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and
is expressed in decibels.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured. The value for dynamic range is
expressed in decibels. It is measured with a signal at −60 dBFS
so that it includes all noise sources and DNL artifacts.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-Noise-and-Distortion Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components that are less than
the Nyquist frequency, including harmonics but excluding dc.
The value of SINAD is expressed in decibels.
Aperture Delay
Aperture delay is the measure of the acquisition performance
and is the time between the rising edge of the CNV input and
when the input signal is held for a conversion.
Transient Response
Transient response is the time required for the ADC to acquire a
full-scale input step to ±1 LSB accuracy.
Common-Mode Rejection Ratio (CMRR)
CMRR is the ratio of the power in the ADC output at the
frequency, f, to the power of a 200 mV p-p sine wave applied
to the common-mode voltage of IN+ and IN− of frequency, f.
CMRR (dB) = 10log(PADC_IN/PADC_OUT)
where:
PADC_IN is the common-mode power at the frequency, f, applied
to the IN+ and IN− inputs.
PADC_OUT is the power at the frequency, f, in the ADC output.
Power Supply Rejection Ratio (PSRR)
PSRR is the ratio of the power in the ADC output at the
frequency, f, to the power of a 200 mV p-p sine wave applied
to the ADC VDD supply of frequency, f.
PSRR (dB) = 10 log(PVDD_IN/PADC_OUT)
where:
PVDD_IN is the power at the frequency, f, at the VDD pin.
PADC_OUT is the power at the frequency, f, in the ADC output.
Rev. D | Page 17 of 40
AD4003/AD4007/AD4011
Data Sheet
THEORY OF OPERATION
IN+
SWITCHES CONTROL
LSB
MSB
REF
GND
131,072C
65,536C
4C
2C
C
SW+
C
BUSY
COMP
131,072C
65,536C
4C
2C
C
CONTROL
LOGIC
C
MSB
OUTPUT CODE
LSB
SW–
14957-007
CNV
IN–
Figure 38. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD4003/AD4007/AD4011 are high speed, low power,
single-supply, precise, 18-bit ADCs based on a SAR architecture.
The AD4003 is capable of converting 2,000,000 samples per
second (2 MSPS), the AD4007 is capable of converting 1,000,000
samples per second (1 MSPS), and the AD4011 is capable of
converting 500,000 samples per second (500 kSPS). The power
consumption of the AD4003/AD4007/AD4011 scales with
throughput, because they power down in between conversions.
For example, when operating at 10 kSPS, the devices typically
consume 80 μW, making them ideal for battery-powered
applications. The AD4003/AD4007/AD4011 also have a valid
first conversion after being powered down for long periods,
which can further reduce power consumed in applications in
which the ADC does not need to be constantly converting.
The AD4003/AD4007/AD4011 provide the user with an on-chip,
track-and-hold and do not exhibit any pipeline delay or latency,
making them ideal for multiplexed applications.
The AD4003/AD4007/AD4011 incorporate a multitude of
unique easy to use features that result in a lower system power
and smaller footprint.
The AD4003/AD4007/AD4011 each have an internal voltage
clamp that protects the device from overvoltage damage on the
analog inputs.
range up to 100 kHz. For frequencies greater than 100 kHz and
multiplexing functionality, disable high-Z mode.
For single-supply applications, a span compression feature creates
additional headroom and footroom for the driving amplifier to
access the full range of the ADC.
The fast conversion time of the AD4003/AD4007/AD4011, along
with turbo mode, allows low clock rates to read back conversions,
even when running at their respective maximum throughput
rates. Note that for the AD4003, the full throughput rate of
2 MSPS can be achieved only with turbo mode enabled.
The AD4003/AD4007/AD4011 can interface with any 1.8 V to 5 V
digital logic family. They are available in a 10-lead MSOP or a tiny
10-lead LFCSP that allows space savings and flexible configurations.
The AD4003/AD4007/AD4011 are pin for pin compatible with
some of the 14-/16-/18-/20-bit precision SAR ADCs listed in
Table 8.
Table 8. MSOP, LFCSP 14-/16-/18-/20-Bit Precision SAR ADCs
Bits 100 kSPS
201 Not
applicable
181 AD7989-12
The analog input incorporates circuitry that reduces the nonlinear
charge kickback seen from a typical switched capacitor SAR input.
This reduction in kickback, combined with a longer acquisition
phase, allows the use of lower bandwidth and lower power
amplifiers as drivers. This combination has the additional benefit
of allowing a larger resistor value in the input RC filter and a
corresponding smaller capacitor, which results in a smaller RC load
for the amplifier, improving stability and power dissipation.
183
High-Z mode can be enabled via the SPI interface by programming
a register bit (see Table 14). When high-Z mode is enabled, the
ADC input has a low input charging current at low input signal
frequencies as well as improved distortion over a wide frequency
250 kSPS
Not
applicable
AD76912
AD7684
AD76872
163
AD7680,
AD7683,
AD7988-12
AD76852,
AD7694
143
AD7940
AD79422
True differential.
Pin for pin compatible.
3
Pseudo differential.
2
Rev. D | Page 18 of 40
AD40112,
AD76902,
AD7989-52
AD40102
161
1
400 kSPS to
500 kSPS
AD40222
AD76882,
AD76932,
AD79162
AD40082,
AD76862,
AD7988-52
AD79462
≥1000 kSPS
AD40202,
AD40212
AD40032,
AD40072,
AD79822,
AD79842
AD40022,
AD40062
AD4001,
AD4005,
AD79152
AD40002,
AD40042,
AD79802,
AD7983
Not applicable
Data Sheet
AD4003/AD4007/AD4011
During the acquisition phase, terminals of the array tied to the
input of the comparator are connected to ground via the SW+ and
SW− switches (see Figure 38). All independent switches connect
the other terminal of each capacitor to the analog inputs. The
capacitor arrays are used as sampling capacitors and acquire the
analog signal on the IN+ and IN− inputs.
When the acquisition phase is complete and the CNV input goes
high, a conversion phase initiates. When the conversion phase
begins, SW+ and SW− are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the GND input. The differential voltage between the IN+ and
IN− inputs captured at the end of the acquisition phase is applied
to the comparator inputs, causing the comparator to become
unbalanced. By switching each element of the capacitor array
between GND and VREF, the comparator input varies by binary
weighted voltage steps (VREF/2, VREF/4, …, VREF/262,144). The
control logic toggles these switches, starting with the MSB, to
bring the comparator back into a balanced condition. After the
Because the AD4003, AD4007, and AD4011 have on-board
conversion clocks, the serial clock (SCK) is not required for the
conversion process.
TRANSFER FUNCTIONS
The ideal transfer characteristics for the AD4003/AD4007/
AD4011 are shown in Figure 39 and Table 9.
011...111
011...110
011...101
100...010
100...001
100...000
–FSR
–FSR + 1 LSB
–FSR + 0.5 LSB
+FSR – 1 LSB
+FSR – 1.5 LSB
ANALOG INPUT
14957-008
The AD4003/AD4007/AD4011 are SAR-based ADCs using a
charge redistribution sampling digital-to-analog converter (DAC).
Figure 38 shows the simplified schematic of the ADC. The
capacitive DAC consists of two identical arrays of 18 binary
weighted capacitors, which are connected to the comparator inputs.
completion of this process, the control logic generates the ADC
output code and a busy signal indicator.
ADC CODE (TWOS COMPLEMENT)
CONVERTER OPERATION
Figure 39. ADC Ideal Transfer Function (FSR Is Full-Scale Range)
Table 9. Output Codes and Ideal Input Voltages
Description
FSR − 1 LSB
Midscale + 1 LSB
Midscale
Midscale − 1 LSB
−FSR + 1 LSB
−FSR
Analog Input, VREF = 5 V
+4.999962 V
+38.15 μV
0V
−38.15 μV
−4.999962 V
−5 V
VREF = 5 V with Span Compression Enabled
+3.999969 V
+30.5 μV
0V
−30.5 μV
−3.999969 V
−4 V
1
Digital Output Code (Hex)
0x1FFFF1
0x00001
0x00000
0x3FFFF
0x20001
0x200002
This output code is also the code for an overranged analog input (VIN+ − VIN− above VREF with the span compression disabled and above 0.8 ×VREF with the span
compression enabled).
2
This output code is also the code for an underranged analog input (VIN+ − VIN− below −VREF with the span compression disabled and above 0.8 ×VREF with the span
compression enabled).
Rev. D | Page 19 of 40
AD4003/AD4007/AD4011
Data Sheet
APPLICATIONS INFORMATION
Figure 41 shows a recommended connection diagram when
using a single-supply system. This setup is preferable when only
a limited number of rails are available in the system and power
dissipation is of critical importance.
TYPICAL APPLICATION DIAGRAMS
Figure 40 shows an example of the recommended connection
diagram for the AD4003/AD4007/AD4011 when multiple supplies,
V+ and V−, are available. This configuration is used for optimal
performance because the amplifier supplies can be selected to
allow the maximum signal range (see Figure 40 for the range).
Figure 42 shows a typical application diagram when using a
fully differential amplifier (FDA).
V+ ≥ +6.5V
REF
LDO
1.8V
AMP
VCM = VREF/2
5V
10kΩ
0.1µF
10kΩ
AMP
VREF
R
REF
C
0V
V+
VCM = VREF /2
VDD
VIO
SDI
IN+
V–
AD4003/
AD4007/
AD4011
IN–
R
AMP
VREF
SCK
DIGITAL HOST
(MICROPROCESSOR/
FPGA)
SDO
CNV
GND
3-WIRE/4-WIRE
INTERFACE
C
0V
HOST
SUPPLY
V–
14957-009
VCM = VREF /2
1.8V TO 5V
0.1µF
10µF
V+
V– ≤ –0.5V
Figure 40. Typical Application Diagram with Multiple Supplies
V+ = 5V
REF1
LDO
AMP
VCM = VREF /2
1.8V
4.096V
10kΩ
10kΩ
AMP
0.9 × VREF
VCM = VREF /2
0.1 × VREF
0.1µF
0.1µF
100nF
100nF
R
REF
C
VDD
SDI
AD4003/AD4007/
AD40112
IN–
AMP
0.9 × VREF
VCM = VREF /2
0.1 × VREF
HOST
SUPPLY
VIO
IN+
R
1.8V TO 5V
10µF1
GND
SCK
SDO
DIGITAL HOST
(MICROPROCESSOR/
FPGA)
CNV
3-WIRE/4-WIRE
INTERFACE
C
1 SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION. C
REF IS USUALLY A 10µF CERAMIC CAPACITOR (X7R).
2 SPAN COMPRESSION MODE ENABLED.
3 SEE TABLE 10 FOR RC FILTER AND AMPLIFIER SELECTION.
Figure 41. Typical Application Diagram with a Single Supply
Rev. D | Page 20 of 40
14957-010
3
Data Sheet
AD4003/AD4007/AD4011
V+ = 5V
REF
LDO
AMP
VCM = VREF/2
VCM = VREF/2
R4
1kΩ
R3
1kΩ
VREF
10kΩ
0
4.096V
10kΩ
10µF
1.8V
1.8V TO 5V
0.1µF 0.1µF
HOST
SUPPLY
V+
+IN
VOCM
0.1µF
–IN
GND
SCK
SDO
CNV
3-WIRE/4-WIRE
INTERFACE
V–
R1
1kΩ
0
DIGITAL HOST
(MICROPROCESSOR/
FPGA)
14957-011
VREF
SDI
IN–
R
DIFFERENTIAL
AMPLIFIER
VIO
AD4003/AD4007/
AD4011
C
+OUT
VDD
IN+
C
VCM = VREF /2
VCM = VREF/2
REF
R
–OUT
R2
1kΩ
Figure 42. Typical Application Diagram with a Fully Differential Amplifier
If the analog input exceeds the reference voltage by 0.4 V, the
internal clamp circuit turns on and the current flows through
the clamp into ground, preventing the input from rising further
and potentially causing damage to the device. The clamp turns
on before D1 (see Figure 43) and can sink up to 50 mA of current.
ANALOG INPUTS
Figure 43 shows an equivalent circuit of the analog input
structure, including the overvoltage clamp of the AD4003/
AD4007/AD4011.
REF
D1
VIN
REXT
RIN
IN+/IN–
CEXT
CPIN
D2
CLAMP
GND
14957-013
0V TO 15V
CIN
Figure 43. Equivalent Analog Input Circuit
Input Overvoltage Clamp Circuit
Most ADC analog inputs, IN+ and IN−, have no overvoltage
protection circuitry apart from ESD protection diodes. During
an overvoltage event, an ESD protection diode from an analog
input pin (IN+ or IN−) pin to REF forward biases and shorts
the input pin to REF, potentially overloading the reference or
causing damage to the device. The AD4003/AD4007/AD4011
internal overvoltage clamp circuit with a larger external resistor
(REXT = 200 Ω) eliminates the need for external protection
diodes and protects the ADC inputs against dc overvoltages.
When the clamp is active, it sets the overvoltage (OV) clamp flag
bit in the configuration register that is accessed with a 16-bit
SPI read command or via the OV in the status bits. The OV
clamp flag gives an indication of overvoltage condition when
it is set to 0. The OV clamp flag is a read only sticky bit and is
cleared only if the register is a read while the overvoltage
condition is no longer present.
The clamp circuit does not dissipate static power in the off state.
Note that the clamp cannot sustain the overvoltage condition for
an indefinite amount of time.
The external RC filter, formed by the REXT resistor and The CEXT
capacitor (see Figure 43) is usually present at the ADC input to
band limit the input signal. During an overvoltage event, excessive
voltage is dropped across REXT and REXT becomes part of a
protection circuit. The REXT value can vary from 200 Ω to 20 kΩ
for 15 V protection. The CEXT value can be as low as 100 pF for
correct operation of the clamp. See Table 1 for input overvoltage
clamp specifications.
In applications where the amplifier rails are greater than VREF
and less than ground, it is possible for the output to exceed the
input voltage range (specified in Table 1) of the device. In this case,
the AD4003/AD4007/AD4011 internal overvoltage clamp circuit
ensures that the voltage on the input pin does not exceed VREF +
0.4 V and prevents damage to the device by clamping the input
voltage in a safe operating range and avoiding disturbance of the
reference, which is particularly important for systems that share
the reference among multiple ADCs.
Rev. D | Page 21 of 40
AD4003/AD4007/AD4011
Data Sheet
During the conversion phase, where the switches are open, the
input impedance is limited to CPIN. RIN and CIN make a singlepole, low-pass filter that reduces undesirable aliasing effects
and limits noise.
Differential Input Considerations
The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these differential
inputs, signals common to both inputs are rejected. Figure 32
shows the common-mode rejection capability of the AD4003/
AD4007/AD4011 over frequency. It is important to note that
the differential input signals must be truly antiphase in nature, 180°
out of phase, which is required to keep the common-mode voltage
of the input signal within the specified range around VREF/2 as
shown in Table 1.
RC Filter Values
The RC filter value (represented by R and C in Figure 40 to
Figure 42 and Figure 44) and driving amplifier can be selected
depending on the input signal bandwidth of interest at the full
throughput. Lower input signal bandwidth means that the RC
cutoff can be lower, thereby reducing noise into the converter.
For optimum performance at various throughputs, use the
recommended RC values (200 Ω, 180 pF) and the ADA4807-1.
Switched Capacitor Input
During the acquisition phase, the impedance of the analog
inputs (IN+ or IN−) can be modeled as a parallel combination
of Capacitor CPIN and the network formed by the series connection
of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically
400 Ω and is a lumped component composed of serial resistors
and the on resistance of the switches. CIN is typically 40 pF and
is mainly the ADC sampling capacitor.
The RC values shown in Table 10 are chosen for ease of drive considerations and greater ADC input protection. The combination
of a large R value (200 Ω) and small C value results in a reduced
dynamic load for the amplifier to drive. The smaller value of
C means fewer stability and phase margin concerns with the
amplifier. The large value of R limits the current into the ADC
input when the amplifier output exceeds the ADC input range.
Table 10. RC Filter and Amplifier Selection for Various Input Bandwidths
Input Signal Bandwidth (kHz)
