AD4022BRMZ-RL7

20-Bit, 1.8 MSPS/1 MSPS/500 kSPS, Easy Drive, Differential SAR ADCs AD4020/AD4021/AD4022 Data Sheet FEATURES GENERAL DESCRIPTION Easy Drive Greatly reduced input kickback Input current reduced to 0.5 μA/MSPS Enhanced acquisition phase, ≥77% of cycle time at 1 MSPS First conversion accurate, no latency or pipeline delay Input span compression for single-supply operation Fast conversion allows low SPI clock rates Input overvoltage clamp protection sinks up to 50 mA SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface High performance Differential analog input range: ±VREF, VREF from 2.4 V to 5.1 V Throughput: 1.8 MSPS/1 MSPS/500 kSPS options INL: ±3.1 ppm maximum Guaranteed 20-bit, no missing codes SNR: 100.5 dB at fIN = 1 kHz, VREF = 5 V THD: −123 dB at fIN = 1 kHz, −100 dB at fIN = 100 kHz SINAD: 89 dB at fIN = 900 kHz (see Figure 17) Oversampled dynamic range 104 dB for OSR = 2 131 dB for OSR = 1024 Low power Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface 2.7 mW at 500 kSPS (VDD only) 83 µW at 10 kSPS, 15 mW at 1.8 MSPS (total power) 10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP Pin compatible with AD4003/AD4007/AD4011 family Guaranteed operation: −40°C to +125°C The AD4020/AD4021/AD4022 are high accuracy, high speed, low power, 20-bit, Easy Drive, precision successive approximation register (SAR) analog-to-digital converters (ADCs) that operate from a single power supply, VDD. The reference voltage, VREF, is applied externally and can be set independent of the supply voltage. The AD4020/AD4021/AD4022 power scales linearly with throughput. APPLICATIONS Automated test equipment Machine automation Medical equipment Battery-powered equipment Precision data acquisition systems Instrumentation and control systems 12 1.8V VDD VIO 1.8V TO 5V IN+ VREF IN– 20-BIT SAR ADC VREF/2 SERIAL INTERFACE STATUS BITS SPAN CLAMP COMPRESSION 0 GND SDO CNV 6 3 0 –3 –6 –9 SDI SCK 3-WIRE OR 4-WIRE SPI INTERFACE (DAISY CHAIN, CS) 15369-001 0 TURBO MODE 9 –12 –15 –5 –3 –1 1 3 INPUT DIFFERENTIAL VOLTAGE (V) 5 15369-147 REF HIGH-Z MODE VREF/2 25°C HIGH-Z DISABLED, 1.8MSPS 25°C HIGH-Z ENABLED, 1.8MSPS 15 AD4020/AD4021/AD4022 VREF Fast device throughput up to 1.8 MSPS allows users to accurately capture high frequency signals and to implement oversampling techniques to alleviate the challenges associated with antialias filter designs. Decreased serial peripheral interface (SPI) clock rate requirements reduce digital input/output power consumption, broadens digital host options, and simplifies the task of sending data across digital isolation. The SPI-compatible serial user interface is compatible with 1.8 V, 2.5 V, 3 V, and 5 V logic by using the separate VIO logic supply. INPUT CURRENT (µA) 10µF Input span compression eliminates the need to provide a negative supply to the ADC driver amplifier while preserving access to the full ADC code range. The input overvoltage clamp protects the ADC inputs against overvoltage events, minimizing disturbances on the reference pin, and eliminating the need for external protection diodes. 18 FUNCTIONAL BLOCK DIAGRAM 2.5V TO 5V Easy Drive features reduce both signal chain complexity and power consumption while enabling higher channel density. The reduced input current, particularly in high-Z mode, coupled with a long signal acquisition phase, eliminates the need for a dedicated ADC driver. Easy Drive broadens the range of companion circuitry that is capable of driving these ADCs (see Figure 2). Figure 2. Input Current vs. Input Differential Voltage Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2017–2021 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD4020/AD4021/AD4022 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Driver Amplifier Choice ........................................................... 22 Applications ....................................................................................... 1 Ease of Drive Features ............................................................... 24 Functional Block Diagram .............................................................. 1 Voltage Reference Input ............................................................ 25 General Description ......................................................................... 1 Power Supply............................................................................... 25 Revision History ............................................................................... 2 Digital Interface .......................................................................... 26 Specifications..................................................................................... 4 Register Read/Write Functionality........................................... 28 Timing Specifications .................................................................. 7 Status Bits .................................................................................... 30 Absolute Maximum Ratings............................................................ 9 CS Mode, 3-Wire Turbo Mode ................................................. 31 Thermal Resistance ...................................................................... 9 CS Mode, 3-Wire Without Busy Indicator ................................. 32 ESD Caution .................................................................................. 9 CS Mode, 3-Wire with Busy Indicator .................................... 33 Pin Configurations and Function Descriptions ......................... 10 CS Mode, 4-Wire Turbo Mode ................................................. 34 Typical Performance Characteristics ........................................... 11 CS Mode, 4-Wire Without Busy Indicator ................................. 35 Terminology .................................................................................... 17 Theory of Operation ...................................................................... 18 Circuit Information .................................................................... 18 Converter Operation .................................................................. 19 Transfer Functions...................................................................... 19 Applications Information .............................................................. 20 Typical Application Diagrams .................................................. 20 CS Mode, 4-Wire with Busy Indicator .................................... 36 Daisy-Chain Mode ..................................................................... 37 Layout Guidelines....................................................................... 38 Evaluating the AD4020/AD4021/AD4022 Performance ...... 38 Outline Dimensions ....................................................................... 39 Ordering Guide .......................................................................... 40 Analog Inputs .............................................................................. 21 REVISION HISTORY 2/2021—Rev. B to Rev. C Changes to Features Section and Applications Section ............... 1 Changes to Specifications Section .................................................. 4 Changed Voltage Range (VREF) Parameter, Table 1 to VREF Voltage Range Parameter, Table 1................................................... 5 Changes to VREF Voltage Range Parameter, Table 1 ..................... 5 Changed CNV or SDI Low to SDO D17 MSB Valid Delay (CS Mode) Parameter, Table 2 to CNV or SDI Low to SDO D19 MSB Valid Delay (CS Mode) Parameter, Table 2 ......................... 7 Changes to CS Mode, 3-Wire Turbo Mode Section .................. 31 Changes to Figure 58...................................................................... 33 Changes to CS Mode, 4-Wire Without Busy Indicator Mode Section.............................................................................................. 35 Changes to CS Mode, 4-Wire With Busy Indicator Mode Section and Figure 64..................................................................... 36 Changes to Daisy-Chain Mode Section ...................................... 37 Updated Outline Dimensions ....................................................... 42 Changes to Ordering Guide .......................................................... 43 Changes CNV Low to SDO D17 MSB Valid Delay Parameter, Table 3 to CNV Low to SDO D19 MSB Valid Delay Parameter, Table 3 ................................................................................................ 8 Changes to Figure 35 Caption....................................................... 16 Changes to Table 8 .......................................................................... 18 Changes to Input Overvoltage Clamp Circuit Section .............. 21 Changes to Driver Amplifier Choice Section and Table 10 ...... 22 Changes to High-Z Mode Section ................................................ 24 Changes to Figure 47, Figure 38, and Power Supply Section .... 25 Changes to Serial Clock Frequency Requirements Section ...... 26 Added Note 1 to Table 13 .............................................................. 27 Changes to Register Read/Write Functionality Section ............ 28 Changes to Status Bits Section ...................................................... 30 11/2019—Rev. A to Rev. B Added AD4021 and AD4022 ............................................ Universal Added Figure 2; Renumbered Sequentially ...................................1 Changes to Features Section and General Description Section .......1 Changes to Specifications Section and Table 1 ..............................4 Changes to Timing Specifications Section and Table 2 ................7 Deleted Figure 3; Renumbered Sequentially .................................8 Changes to Table 3.............................................................................8 Added Endnote 2, Table 5 ................................................................9 Changes to Absolute Maximum Ratings Section and Thermal Resistance Section .............................................................................9 Changes to Figure 4 and Table 7................................................... 10 Rev. C | Page 2 of 40 Data Sheet AD4020/AD4021/AD4022 Changes to Typical Performance Characteristics Section .........11 Added Figure 30 and Figure 31 .....................................................15 Changes to Terminology Section ..................................................17 Changes to Circuit Information Section and Table 8 .................18 Changes to Converter Operation Section and Endnote 1 and Endnote 2, Table 9 ...........................................................................19 Changes to Typical Application Diagrams Section ....................20 Changes to Input Overvoltage Clamp Circuit Section...............21 Changes to Figure 44, Single to Differential Driver Section, and High Frequency Input Signals Section .........................................23 Changes to High-Z Mode Section, Figure 47 Caption, and Figure 48 Caption ............................................................................24 Deleted Table 12, Table 13, and Table 14; Renumbered Sequentially ......................................................................................25 Changes to Voltage Reference Input Section, Power Supply Section, and Digital Interface Section ..........................................25 Added Configuration Register Details Section ...........................25 Added Serial Clock Frequency Requirements Section, Table 12, and Table 13; Renumbered Sequentially ......................................26 Changes to Register Read/Write Functionality Section, Table 14, and Figure 49 ...................................................................................27 Changes to Figure 50 ......................................................................28 Changed Status Word Section to Status Bits Section..................29 Changes to Status Bits Section and Table 15 ............................... 29 Changes to CS Mode, 3-Wire Turbo Mode Section, Figure 54 Caption, and Figure 54 Caption .................................................... 30 Changes to CS Mode, 3-Wire Without the Busy Indicator Section, Figure 55 Caption, and Figure 56 Caption ................... 31 Changes to CS Mode, 3-Wire with the Busy Indicator Section, Figure 57 Caption, and Figure 58 Caption .................................. 32 Changes to CS Mode, 4-Wire Turbo Mode Section and Figure 60 Caption ............................................................................ 33 Changes to CS Mode, 4-Wire Without the Busy Indicator Section and Figure 62 Caption ...................................................... 34 Changes to CS Mode, 4-Wire with the Busy Indicator Section and Figure 64 Caption .................................................................... 35 Changes to Daisy-Chain Mode Section and Figure 66 Caption .... 36 Changes to Layout Guidelines Section and Evaluating the AD4020/AD4021/AD4022 Performance Section ....................... 37 Changes to Ordering Guide ........................................................... 39 7/2017—Rev. 0 to Rev. A Change to Integral Nonlinearity Error (INL) Parameter, Table 1 .... 3 7/2017—Revision 0: Initial Version Rev. C | Page 3 of 40 AD4020/AD4021/AD4022 Data Sheet SPECIFICATIONS VDD = 1.71 V to 1.89 V, VIO = 1.71 V to 5.5 V, REF = VREF = 5 V, all specifications TMIN to TMAX, high-Z mode disabled, span compression disabled, turbo mode enabled, and sampling frequency (fS) = 1.8 MSPS for the AD4020, fS = 1 MSPS for the AD4021, and fS = 500 kSPS for the AD4022, unless otherwise noted. Table 1. Parameter RESOLUTION ANALOG INPUT Voltage Range Operating Input Voltage Common-Mode Input Range Common-Mode Rejection Ratio (CMRR) Analog Input Current Test Conditions/Comments Min 20 IN+ voltage (VIN+) − IN− voltage (VIN−) Span compression enabled VIN+, VIN− to GND Span compression enabled THROUGHPUT Complete Cycle AD4020 AD4021 AD4022 Conversion Time Acquisition Phase 1 AD4020 AD4021 AD4022 Throughput Rate 2 (fS) AD4020 AD4021 AD4022 Transient Response 3 DC ACCURACY No Missing Codes Integral Nonlinearity Error (INL) Unit Bits −VREF +VREF V −VREF × 0.8 −0.1 0.1 × VREF VREF/2 − 0.125 +VREF × 0.8 +VREF + 0.1 0.9 × VREF VREF/2 + 0.125 V V V V dB nA 555 1000 2000 300 VREF/2 68 0.3 1 µA 320 ns ns ns ns 350 325 770 1770 ns ns ns 0 0 0 1.8 1 500 325 20 −3.1 −2 −0.5 MSPS MSPS kSPS ns VDD = 1.8 V ± 5% Bandwidth = 0.1 Hz to 10 Hz ±6 6 Bits ppm ppm LSB LSB LSB ppm/°C LSB ppm/°C LSB µV p-p Oversampling ratio (OSR) = 2 OSR = 256 OSR = 1024 101 104 125 131 dB dB dB dB T = 0°C to 70°C Differential Nonlinearity Error (DNL) Transition Noise Zero Error Zero Error Drift 4 Gain Error Gain Error Drift4 Power Supply Sensitivity 1/f Noise 5 AC ACCURACY Dynamic Range Oversampled Dynamic Range Max Input frequency (fIN) = 500 kHz Acquisition phase, TA = 25°C High-Z mode enabled, converting dc input at 1.8 MSPS Typ −35 −0.3 −88 −1.2 Rev. C | Page 4 of 40 ±1 ±1 ±0.3 3.3 ±12 +3.1 +2 +0.5 +35 +0.3 +88 +1.2 Data Sheet Parameter Total RMS Noise fIN = 1 kHz, −0.5 dBFS, VREF = 5 V Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Total Harmonic Distortion (THD) Signal-to-Noise-and-Distortion Ratio (SINAD) fIN = 1 kHz, −0.5 dBFS, VREF = 2.5 V SNR SFDR THD SINAD fIN = 100 kHz, −0.5 dBFS, VREF = 5 V SNR THD SINAD fIN = 400 kHz, −0.5 dBFS, VREF = 5 V SNR THD SINAD −3 dB Input Bandwidth Aperture Delay Aperture Jitter REFERENCE VREF Voltage Range Current AD4020 AD4021 AD4022 INPUT OVERVOLTAGE CLAMP IN+/IN− Current (IIN+/IIN−) VIN+/VIN− at Maximum IIN+/IIN− VIN+/VIN− Clamp On/Off Threshold Deactivation Time REF Current at Maximum IIN+/IIN− DIGITAL INPUTS Logic Levels Input Voltage Low (VIL) Input Voltage High (VIH) AD4020/AD4021/AD4022 Test Conditions/Comments Min Typ 31.5 99 100.5 122 −123 100 dB dB dB dB 94.7 122 −119 94.5 dB dB dB dB 99 −100 96.5 dB dB dB 92.5 −94 90 10 1 1 dB dB dB MHz ns ps rms 98.5 93.3 93 REF − GND VREF = 5 V 1.8 MSPS 1 MSPS 500 kSPS 2.4 Max 5.1 1.1 0.58 0.32 VREF = 5 V VREF = 2.5 V VREF = 5 V VREF = 2.5 V VREF = 5 V VREF = 2.5 V 5.25 2.68 VIN+/VIN− > VREF VIO > 2.7 V VIO ≤ 2.7 V VIO > 2.7 V VIO ≤ 2.7 V Input Current Low (IIL) Input Current High (IIH) Input Pin Capacitance 6 Rev. C | Page 5 of 40 V mA mA mA 50 50 mA mA V V V V ns µA +0.3 × VIO +0.2 × VIO VIO + 0.3 VIO + 0.3 +1 +1 V V V V µA µA pF 5.4 3.1 5.4 2.8 360 100 −0.3 −0.3 0.7 × VIO 0.8 × VIO −1 −1 Unit µV rms AD4020/AD4021/AD4022 Data Sheet Parameter DIGITAL OUTPUTS Data Format Pipeline Delay Test Conditions/Comments Min Output Voltage Low (VOL) Output Voltage High (VOH) POWER SUPPLIES VDD VIO Standby Current Power Dissipation Output current = 500 µA Output current = −500 µA Serial, 20 bits, twos complement Conversion results available immediately after completed conversion 0.4 VIO − 0.3 VDD Only REF Only VIO Only Energy per Conversion TEMPERATURE RANGE Specified Performance 1.71 1.71 VDD = 1.8 V, VIO = 1.8 V, TA = 25°C VDD = 1.8 V, VIO = 1.8 V, VREF = 5 V 10 kSPS, high-Z mode disabled 500 kSPS, high-Z mode disabled 1 MSPS, high-Z mode disabled 1.8 MSPS, high-Z mode disabled 500 kSPS, high-Z mode enabled 1 MSPS, high-Z mode enabled 1.8 MSPS, high-Z mode enabled 500 kSPS, high-Z mode disabled 1 MSPS, high-Z mode disabled 1.8 MSPS, high-Z mode disabled 500 kSPS, high-Z mode disabled 1 MSPS, high-Z mode disabled 1.8 MSPS, high-Z mode disabled 500 kSPS, high-Z mode disabled 1 MSPS, high-Z mode disabled 1.8 MSPS, high-Z mode disabled TMIN to TMAX Typ 1.8 Max 1.89 5.5 1.6 83 4.5 8.3 15 5.7 10.8 19 2.7 5.1 9.0 1.6 2.9 5.0 0.13 0.4 1.0 8.3 −40 5.1 10 19 6.9 13 25 +125 Unit V V V V µA µW mW mW mW mW mW mW mW mW mW mW mW mW mW mW mW nJ/sample °C The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 1.8 MSPS for the AD4020, 1 MSPS for the AD4021, and 500 kSPS for the AD4022. 2 A throughput rate of 1.8 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 71 MHz. Refer to Table 4 for the maximum achievable throughput for different modes of operation. 3 Transient response is the time required for the ADC to acquire a full-scale input step to ±2 LSB accuracy. 4 The minimum and maximum values are guaranteed by characterization, but not production tested. 5 See the 1/f noise plot in Figure 25. 1 Rev. C | Page 6 of 40 Data Sheet AD4020/AD4021/AD4022 TIMING SPECIFICATIONS VDD = 1.71 V to 1.89 V, VIO = 1.71 V to 5.5 V, VREF = 5 V, all specifications TMIN to TMAX, high-Z mode disabled, span compression disabled, turbo mode enabled, and fS = 1.8 MSPS for the AD4020, fS = 1 MSPS for the AD4021, and fS = 500 kSPS for the AD4022, unless otherwise noted. See Figure 49 to Figure 52, Figure 54, Figure 56, Figure 58, Figure 60, Figure 62, Figure 64, and Figure 66 for timing diagrams. Table 2. Digital Interface Timing Parameter 1 CONVERSION TIME—CNV RISING EDGE TO DATA AVAILABLE ACQUISITION PHASE 2 AD4020 AD4021 AD4022 TIME BETWEEN CONVERSIONS AD4020 AD4021 AD4022 CNV PULSE WIDTH (CS MODE) 3 Symbol tCONV tACQ SCK PERIOD CS Mode 4 tSCK Min 300 Typ 320 Max 350 Unit ns 325 770 1770 ns ns ns 555 1000 2000 10 ns ns ns ns 9.8 12.3 ns ns 20 25 ns ns 3 3 1.5 ns ns ns tCYC tCNVH VIO > 2.7 V VIO > 1.7 V Daisy-Chain Mode 5 VIO > 2.7 V VIO > 1.7 V SCK Low Time High Time Falling Edge to Data Remains Valid Delay Falling Edge to Data Valid Delay VIO > 2.7 V VIO > 1.7 V CNV OR SDI LOW TO SDO D19 MSB VALID DELAY (CS MODE) tSCKL tSCKH tHSDO tDSDO 7.5 10.5 ns ns 10 13 ns ns ns ns ns tEN VIO > 2.7 V VIO > 1.7 V CNV RISING EDGE TO FIRST SCK RISING EDGE DELAY LAST SCK FALLING EDGE TO CNV RISING EDGE DELAY 6 CNV OR SDI HIGH OR LAST SCK FALLING EDGE TO SDO HIGH IMPEDANCE (CS MODE) tQUIET1 tQUIET2 tDIS 200 60 SDI Valid Setup Time from CNV Rising Edge Valid Hold Time from CNV Rising Edge (CS Mode) tSSDICNV tHSDICNV 2 2 ns ns Valid Setup Time from SCK Rising Edge (Daisy-Chain Mode) Valid Hold Time from SCK Rising Edge (Daisy-Chain Mode) SCK VALID HOLD TIME FROM CNV RISING EDGE (DAISY-CHAIN MODE) tSSDISCK tHSDISCK tHSCKCNV 2 2 12 ns ns ns 20 Timing parameters measured with respect to a falling edge are defined as triggered at x% VIO. Timing parameters measured with respect to a rising edge are defined as triggered at y% VIO. For VIO ≤ 2.7 V, x = 80 and y = 20. For VIO > 2.7 V, x = 70 and y = 30. The minimum VIH and maximum VIL are used. See the digital inputs specifications in Table 1. 2 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 1.8 MSPS for the AD4020, 1 MSPS for the AD4021, and 500 kSPS for the AD4022. 3 For turbo mode, tCNVH must match the tQUIET1 minimum. 4 A throughput rate of 1.8 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 71 MHz. Refer to Table 4 for the maximum achievable throughput for different modes of operation. See the Serial Clock Frequency Requirements section for guidelines on determining the minimum SCK rate required for a given throughput. 5 A 50% duty cycle is assumed for SCK. 6 See Figure 24 for SINAD vs. tQUIET2. 1 Rev. C | Page 7 of 40 AD4020/AD4021/AD4022 Data Sheet Table 3. Register Read/Write Timing Parameter READ/WRITE OPERATION CNV Pulse Width 2 SCK Period VIO > 2.7 V VIO > 1.7 V SCK Low Time SCK High Time READ OPERATION CNV Low to SDO D19 MSB Valid Delay VIO > 2.7 V VIO > 1.7 V SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO > 2.7 V VIO > 1.7 V CNV Rising Edge to SDO High Impedance WRITE OPERATION SDI Valid Setup Time from SCK Rising Edge SDI Valid Hold Time from SCK Rising Edge CNV Rising Edge to SCK Edge Hold Time CNV Falling Edge to SCK Active Edge Setup Time 1 2 Symbol 1 Min tCNVH tSCK 10 ns 9.8 12.3 3 3 ns ns ns ns tSCKL tSCKH Typ Max Unit tEN tHSDO tDSDO ns ns ns 7.5 10.5 20 ns ns ns 1.5 tDIS tSSDISCK tHSDISCK tHCNVSCK tSCNVSCK 10 13 2 2 0 6 ns ns ns ns See Figure 49 to Figure 52, Figure 54, Figure 56, Figure 58, Figure 60, Figure 62, Figure 64, and Figure 66. For turbo mode, tCNVH must match the tQUIET1 minimum. Table 4. Achievable Throughput for Different Modes of Operation Parameter THROUGHPUT, CS MODE 3-Wire and 4-Wire Turbo Mode 3-Wire and 4-Wire Turbo Mode and Six Status Bits 3-Wire and 4-Wire Mode 3-Wire and 4-Wire Mode and Six Status Bits Test Conditions/Comments fSCK = 100 MHz, VIO ≥ 2.7 V fSCK = 80 MHz, VIO < 2.7 V fSCK = 100 MHz, VIO ≥ 2.7 V fSCK = 80 MHz, VIO < 2.7 V fSCK = 100 MHz, VIO ≥ 2.7 V fSCK = 80 MHz, VIO < 2.7 V fSCK = 100 MHz, VIO ≥ 2.7 V fSCK = 80 MHz, VIO < 2.7 V Rev. C | Page 8 of 40 Min Typ Max Unit 1.80 1.80 1.80 1.67 1.61 1.49 1.47 1.34 MSPS MSPS MSPS MSPS MSPS MSPS MSPS MSPS Data Sheet AD4020/AD4021/AD4022 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Note that the input overvoltage clamp cannot sustain the overvoltage condition for an indefinite amount of time. Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Table 5. Parameter Analog Inputs IN+, IN− to GND1 Supply Voltage REF, VIO to GND VDD to GND VDD to VIO Digital Inputs to GND Digital Output to GND Storage Temperature Range Junction Temperature Lead Temperature Soldering Reflow ESD Ratings Human Body Model Machine Model Field Induced Charged Device Model 1 2 Rating −0.3 V to VREF + 0.4 V, or ±50 mA2 −0.3 V to +6.0 V −0.3 V to +2.1 V −6 V to +2.4 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.3 V −65°C to +150°C 150°C 260°C as per (JEDEC JSTD-020) θJA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. θJC is the junction to case thermal resistance. Table 6. Thermal Resistance Package Type1 RM-10 CP-10-9 1 θJA 147 114 θJC 38 33 Unit °C/W °C/W Test Condition 1: thermal impedance simulated values are based upon use of 2S2P JEDEC PCB. See the Ordering Guide section. ESD CAUTION 4 kV 200 V 1.25 kV See the Analog Inputs section for an explanation of IN+ and IN−. Current condition tested over a 10 ms interval. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. C | Page 9 of 40 AD4020/AD4021/AD4022 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS REF 1 IN+ 3 IN– 4 REF 1 10 VIO IN+ 3 IN– 4 GND 5 TOP VIEW (Not to Scale) 9 SDI 8 SCK 7 SDO 6 CNV TOP VIEW (Not to Scale) 9 SDI 8 SCK 7 SDO 6 CNV NOTES 1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO GND. THIS CONNECTION IS NOT REQUIRED TO MEET THE SPECIFIED PERFORMANCE. 15369-003 AD4020/ AD4021/ AD4022 VDD 2 GND 5 10 VIO AD4020/ AD4021/ AD4022 Figure 3. 10-Lead MSOP Pin Configuration 15369-004 VDD 2 Figure 4. 10-Lead LFCSP Pin Configuration Table 7. Pin Function Descriptions Pin No. 1 Mnemonic REF Type 1 AI 2 3 4 5 6 VDD IN+ IN− GND CNV P AI AI P DI 7 SDO DO 8 9 SCK SDI DI DI 10 VIO P N/A 2 EPAD P 1 2 Description Reference Input Voltage. The VREF range is 2.4 V to 5.1 V. This pin is referred to the GND pin and must be decoupled closely to the GND pin with a 10 µF X7R ceramic capacitor. 1.8 V Power Supply. The VDD range is 1.71 V to 1.89 V. Bypass VDD to GND with a 0.1 μF ceramic capacitor. Differential Positive Analog Input. See the Differential Input Considerations section. Differential Negative Analog Input. See the Differential Input Considerations section. Power Supply Ground. Connect to the ground plane of the board. Convert Input. This input has multiple functions. On the leading edge, the input initiates the conversions and selects the interface mode of the device, which is either daisy-chain mode or CS mode. In CS mode, the SDO pin is enabled when CNV is low. In daisy-chain mode, the data is read when CNV is high. Serial Data Output. The conversion result is output on this pin. The pin is synchronized to the SCK signal on the SCK pin. Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock. Serial Data Input. This input provides multiple features and selects the interface mode of the ADC as follows: Daisy-chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 20 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. With CNV low, program the device by clocking in a 16-bit word on SDI on the rising edge of SCK. Input/Output Interface Digital Power. Nominally, this pin is at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). Bypass VIO to ground with a 0.1 μF ceramic capacitor. Exposed Pad. Connect the exposed pad to GND. This connection is not required to meet the specified performance. Note that the exposed pad only applies to the LFCSP. AI is analog input, P is power, DI is digital input, and DO is digital output. N/A means not applicable. Rev. C | Page 10 of 40 Data Sheet AD4020/AD4021/AD4022 TYPICAL PERFORMANCE CHARACTERISTICS VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, T = 25°C, high-Z mode disabled, span compression disabled, turbo mode enabled, and fS = 1.8 MSPS for the AD4020, fS = 1 MSPS for the AD4021, and fS = 500 kSPS for the AD4022, unless otherwise noted. 2.0 1.0 +125°C +25°C –40°C 1.5 +125°C +25°C –40°C 0.8 0.6 1.0 0.4 DNL (ppm) INL (ppm) 0.5 0 –0.5 0.2 0 –0.2 –0.4 –1.0 –0.6 –1.5 0 131072 262144 393216 524288 655360 786432 917504 1048576 CODE –1.0 15369-005 –2.0 0 393216 524288 655360 786432 917504 1048576 Figure 8. DNL vs. Code for Various Temperatures, VREF = 5 V 1.0 +125°C +25°C –40°C 1.5 262144 CODE Figure 5. INL vs. Code for Various Temperatures, VREF = 5 V 2.0 131072 15369-008 –0.8 +125°C +25°C –40°C 0.8 0.6 1.0 DNL (ppm) INL (ppm) 0.4 0.5 0 –0.5 0.2 0 –0.2 –0.4 –1.0 –0.6 –1.5 131072 262144 393216 524288 655360 786432 917504 1048576 CODE –1.0 15369-006 0 0 262144 393216 524288 655360 786432 917504 1048576 CODE Figure 6. INL vs. Code for Various Temperatures, VREF = 2.5 V Figure 9. DNL vs. Code for Various Temperatures, VREF = 2.5 V 1.0 3 HIGH-Z ENABLED SPAN COMPRESSION ENABLED HIGH-Z ENABLED SPAN COMPRESSION ENABLED 0.8 2 0.6 0.4 DNL (ppm) 1 0 –1 0.2 0 –0.2 –0.4 –0.6 –2 –3 0 131072 262144 393216 524288 655360 786432 917504 1048576 CODE –1.0 0 131072 262144 393216 524288 655360 786432 917504 1048576 CODE Figure 10. DNL vs. Code for High-Z and Span Compression Modes Enabled, VREF = 5 V Figure 7. INL vs. Code for High-Z and Span Compression Modes Enabled, VREF = 5 V Rev. C | Page 11 of 40 15369-010 –0.8 15369-007 INL (ppm) 131072 15369-009 –0.8 –2.0 AD4020/AD4021/AD4022 Data Sheet 250000 250000 2.5V CODE CENTER 5V CODE CENTER 2.5V CODE TRANSITION 5V CODE TRANSITION 200000 CODE COUNT 150000 100000 50000 524230 524240 524250 524260 524270 ADC CODE 0 Figure 11. Histogram of a DC Input at Code Center, VREF = 2.5 V and VREF = 5 V 524205 VREF = 5V SNR = 100.33dB THD = –123.99dB SINAD = 100.31dB 524255 524265 VREF = 2.5V SNR = 95.01dB THD = –118.60dB SINAD = 94.99dB –20 –60 –80 –100 –120 –140 –40 –60 –80 –100 –120 –140 –160 10k 100k 900k FREQUENCY (Hz) –180 100 15369-012 1k 1k 10k 100k 900k FREQUENCY (Hz) Figure 12. 1 kHz, −0.5 dBFS Input Tone Fast Fourier Transform (FFT), VREF = 5 V 15369-015 –160 Figure 15. 1 kHz, −0.5 dBFS Input Tone FFT, VREF = 2.5 V 0 0 VREF = 5V SNR = 98.37dB THD = –98.52dB SINAD = 95.58dB FUNDAMENTAL AMPLITUDE (dB) –20 –60 –80 –100 –120 –140 –160 –40 VREF = 5V SNR = 91.22dB THD = –91.97dB SINAD = 89.15dB –60 –80 –100 –120 –140 –160 10k 100k FREQUENCY (Hz) 900k 15369-013 FUNDAMENTAL AMPLITUDE (dB) 524245 Figure 14. Histogram of a DC Input at Code Transition, VREF = 2.5 V and VREF = 5 V FUNDAMENTAL AMPLITUDE (dB) –40 –180 1k 524235 0 –20 –40 524225 ADC CODE 0 –20 524215 15369-014 524220 15369-011 0 FUNDAMENTAL AMPLITUDE (dB) 100000 50000 524210 –180 100 150000 Figure 13. 100 kHz, −0.5 dBFS Input Tone FFT –180 1k 10k 100k FREQUENCY (Hz) Figure 16. 400 kHz, −0.5 dBFS Input Tone FFT Rev. C | Page 12 of 40 900k 15369-016 CODE COUNT 200000 Data Sheet AD4020/AD4021/AD4022 102 100 17.0 –90 120 16.5 –95 115 16.0 –100 110 –105 105 15.0 –110 100 14.5 –115 SFDR (dB) 15.5 94 THD (dB) 96 ENOB (Bits) SNR, SINAD (dB) 98 92 ENOB SINAD SNR 95 THD SFDR 10k 14.0 900k 100k –120 1k INPUT FREQUENCY (Hz) Figure 20. THD and SFDR vs. Input Frequency 16.6 101 16.4 –114 133 –116 132 –118 131 15.8 96 128 –126 15.6 ENOB SINAD SNR 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 15.4 5.1 –130 2.4 REFERENCE VOLTAGE (V) 100.8 2.7 3.0 3.3 3.6 3.9 4.2 4.5 126 5.1 4.8 Figure 21. THD and SFDR vs. Reference Voltage, fIN = 1 kHz 16.42 –114.0 118.0 16.40 ENOB SINAD SNR 127 REFERENCE VOLTAGE (V) Figure 18. SNR, SINAD, and ENOB vs. Reference Voltage, fIN = 1 kHz 100.6 SFDR THD –128 15369-017 95 94 2.4 129 –124 THD SFDR –114.5 117.9 16.38 100.4 117.8 16.36 16.32 100.0 16.30 THD (dB) 100.2 –115.0 ENOB (Bits) 16.34 117.7 117.6 –115.5 117.5 –116.0 117.4 16.28 99.8 117.3 –116.5 16.26 117.2 99.6 –117.0 16.24 16.22 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 117.1 15369-023 99.4 –40 15369-020 97 130 –122 SFDR (dB) 16.0 –117.5 –40 117.0 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 19. SNR, SINAD, and ENOB vs. Temperature, fIN = 1 kHz Figure 22. THD and SFDR vs. Temperature, fIN = 1 kHz Rev. C | Page 13 of 40 15369-026 98 –120 THD (dB) 99 SFDR (dB) 16.2 ENOB (Bits) SNR, SINAD (dB) 100 SNR, SINAD (dB) 90 900k 100k INPUT FREQUENCY (Hz) Figure 17. SNR, SINAD, and Effective Number of Bits (ENOB) vs. Input Frequency 102 10k 15369-038 88 1k 15369-037 90 AD4020/AD4021/AD4022 Data Sheet –85 140 DYNAMIC RANGE fIN = 1kHz fIN = 10kHz 135 –90 130 –95 –100 120 115 –105 –110 110 –115 105 –120 100 0 2 4 8 16 32 64 128 256 512 1024 DECIMATION RATE 10 20 Figure 26. THD vs. Input Frequency for Various Source Impedances 10 100 99 98 97 96 95 94 VIO = 5.5V VIO = 3.6V VIO = 1.89V 10 20 30 40 50 60 70 80 tQUIET2 (ns) 6 4 2 0 –2 –4 –6 –40 15369-022 0 ZERO ERROR PFS GAIN ERROR NFS GAIN ERROR 8 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 15369-025 ZERO ERROR AND GAIN ERROR (LSB) 101 SINAD (dB) 1 INPUT FREQUENCY (KHz) Figure 23. SNR vs. Decimation Rate for Various Input Frequencies, 1.8 MSPS Figure 27. Zero Error and Gain Error vs. Temperature (PFS Is Positive Full Scale and NFS Is Negative Full Scale) Figure 24. SINAD vs. tQUIET2 18 60 15 ANALOG INPUT CURRENT (µA) 59 ADC OUTPUT READING (µV) 150Ω HIGH-Z DISABLED 150Ω HIGH-Z ENABLED –125 15369-019 95 93 1kΩ HIGH-Z DISABLED 1kΩ HIGH-Z ENABLED 510Ω HIGH-Z DISABLED 510Ω HIGH-Z ENABLED 15369-041 THD (dB) SNR (dB) 125 58 57 56 55 12 9 25°C HIGH-Z 25°C HIGH-Z 25°C HIGH-Z 25°C HIGH-Z 25°C HIGH-Z 25°C HIGH-Z DISABLED, 1.8MSPS DISABLED, 1MSPS DISABLED, 500MSPS ENABLED, 1.8MSPS ENABLED, 1MSPS ENABLED, 500MSPS 6 3 0 –3 –6 –9 0 1 2 3 4 5 6 TIME (Seconds) 7 8 9 10 Figure 25. 1/f Noise for 0.1 Hz to 10 Hz Bandwidth, 50 kSPS, 2500 Samples Averaged per Reading Rev. C | Page 14 of 40 –15 –5 –3 –1 1 3 5 INPUT DIFFERENTIAL VOLTAGE (V) Figure 28. Analog Input Current vs. Input Differential Voltage 15369-040 54 15369-018 –12 Data Sheet AD4020/AD4021/AD4022 72 10 71 8 7 70 6 CMRR (dB) OPEARTING CURRENT (mA) 9 5 VDD HIGH-Z DISABLED VDD HIGH-Z ENABLED REF HIGH-Z DISABLED REF HIGH-Z ENABLED VIO HIGH-Z DISABLED VIO HIGH-Z ENABLED 4 3 2 69 68 67 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 66 100 15369-024 0 –40 1k 100k 10k 1M FREQUENCY (Hz) Figure 29. Operating Current vs. Temperature, AD4020, 1.8 MSPS 15369-035 1 Figure 32. CMRR vs. Frequency 5.0 80 75 4.0 3.5 70 3.0 PSRR (dB) OPERATING CURRENT (mA) 4.5 VDD HIGH-Z DISABLED VDD HIGH-Z ENABLED REF HIGH-Z DISABLED REF HIGH-Z ENABLED VIO HIGH-Z DISABLED VIO HIGH-Z ENABLED 2.5 2.0 1.5 65 60 1.0 55 10 60 110 TEMPERATURE (°C) 50 100 15369-148 0 –40 1k Figure 30. Operating Current vs. Temperature, AD4021, 1 MSPS 1M 100k Figure 33. PSRR vs. Frequency 2.5 1.0 0.9 REFERENCE CURRENT (mA) 2.0 1.5 VDD HIGH-Z DISABLED VDD HIGH-Z ENABLED REF HIGH-Z DISABLED REF HIGH-Z ENABLED VIO HIGH-Z DISABLED VIO HIGH-Z EVABLED 1.0 0.5 1.8MSPS 1MSPS 500kSPS 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 –40 10 60 110 TEMPERATURE (°C) Figure 31. Operating Current vs. Temperature, AD4022, 500 kSPS 0 2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 REFERENCE VOLTAGE (V) Figure 34. Reference Current vs. Reference Voltage Rev. C | Page 15 of 40 5.1 15369-021 0.1 15369-149 OPERATING CURRENT (mA) 10k FREQUENCY (Hz) 15369-044 0.5 AD4020/AD4021/AD4022 100k 23 VDD VIO VREF TOTAL POWER 10k 21 VIO = 5V VIO = 3.3V VIO = 1.8V 19 1k 17 tDSDO (ns) 100 10 13 11 1 9 0.10 100 1k 10k 100k 1M 1.8M THROUGHPUT (SPS) 15369-146 7 0.01 10 25.0 22.5 20.0 17.5 15.0 12.5 10.0 7.5 5.0 –20 0 20 40 60 80 100 TEMPERATURE (°C) 120 15369-027 2.5 0 –40 5 0 20 40 60 80 100 120 140 160 LOAD CAPACITANCE (pF) Figure 37 . tDSDO vs. Load Capacitance Figure 35. Power Dissipation vs. Throughput STANDBY CURRENT (µA) 15 Figure 36. Standby Current vs. Temperature Rev. C | Page 16 of 40 180 200 220 15369-028 POWER DISSIPATION (µW) Data Sheet Data Sheet AD4020/AD4021/AD4022 TERMINOLOGY Integral Nonlinearity Error (INL) INL is the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 39). Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Zero Error Zero error is the difference between the ideal voltage that results in the first code transition (½ LSB above analog ground) and the actual voltage producing that code. Gain Error The first transition (from 100 … 00 to 100 … 01) occurs at a level ½ LSB above nominal negative full scale (−4.999995 V for the ±5 V range). The last transition (from 011 … 10 to 011 … 11) occurs for an analog voltage 1½ LSB below the nominal full scale (+4.999986 V for the ±5 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured. The value for dynamic range is expressed in decibels. It is measured with a signal at −60 dBFS so that it includes all noise sources and DNL artifacts. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-Noise-and-Distortion Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components that are less than the Nyquist frequency, including harmonics but excluding dc. The value of SINAD is expressed in decibels. Aperture Delay Aperture delay is the measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Transient Response Transient response is the time required for the ADC to acquire a full-scale input step to ±1 LSB accuracy. Common-Mode Rejection Ratio (CMRR) CMRR is the ratio of the power in the ADC output at the frequency, f, to the power of a 200 mV p-p sine wave applied to the common-mode voltage of IN+ and IN− of frequency, f. CMRR (dB) = 10log(PADC_IN/PADC_OUT) Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD as follows: where: PADC_IN is the common-mode power at the frequency, f, applied to the IN+ and IN− inputs. PADC_OUT is the power at the frequency, f, in the ADC output. ENOB = (SINAD − 1.76)/6.02 ENOB is expressed in bits and SINAD is expressed in dB. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Power Supply Rejection Ratio (PSRR) PSRR is the ratio of the power in the ADC output at the frequency, f, to the power of a 200 mV p-p sine wave applied to the ADC VDD supply of frequency, f. PSRR (dB) = 10 log(PVDD_IN/PADC_OUT) where: PVDD_IN is the power at the frequency, f, at the VDD pin. PADC_OUT is the power at the frequency, f, in the ADC output. Rev. C | Page 17 of 40 AD4020/AD4021/AD4022 Data Sheet THEORY OF OPERATION IN+ SWITCHES CONTROL LSB MSB REF 524,288C 262,144C 4C 2C C SW+ C BUSY CONTROL LOGIC COMP GND 524,288C 262,144C 4C 2C C C OUTPUT CODE LSB MSB SW– 15369-029 CNV IN– Figure 38. ADC Simplified Schematic CIRCUIT INFORMATION The AD4020/AD4021/AD4022 are high speed, low power, singlesupply, precise, 20-bit differential ADCs based on a SAR architecture. The AD4020 is capable of converting 1,800,000 samples per second (1.8 MSPS), the AD4021 is capable of converting 1,000,000 samples per second (1 MSPS), and the AD4022 is capable of converting 500,000 samples per second (500 kSPS). The power consumption of the AD4020/AD4021/AD4022 scales with throughput because they power down in between conversions. For example, when operating at 10 kSPS, they typically consume 83 µW, making them ideal for battery-powered applications. The AD4020/AD4021/AD4022 also have a valid first conversion after being powered down for long periods, which can further reduce power consumed in applications in which the ADC does not need to be constantly converting. The AD4020/AD4021/AD4022 provide the user with an on-chip track-and-hold and do not exhibit any pipeline delay or latency, making them ideal for multiplexed applications. range up to 100 kHz. For frequencies greater than 100 kHz and multiplexing functionality, disable high-Z mode. For single-supply applications, a span compression feature creates additional headroom and footroom for the driving amplifier to access the full range of the ADC. The fast conversion time of the AD4020/AD4021/AD4022, along with turbo mode, allows low clock rates to read back conversions, even when running at their respective maximum throughput rates. Note that, for the AD4020, the full throughput rate of 1.8 MSPS can be achieved only with turbo mode enabled. The AD4020/AD4021/AD4022 can interface with any 1.8 V to 5 V digital logic family. These devices are available in a 10-lead MSOP or a tiny 10-lead LFCSP that allows space savings and flexible configurations. The AD4020/AD4021/AD4022 are pin for pin compatible with some of the 14-/16-/18-/20-bit precision SAR ADCs listed in Table 8. Table 8. MSOP and LFCSP 14-/16-/18-/20-Bit Precision SAR ADCs The AD4020/AD4021/AD4022 incorporate a multitude of unique, easy to use features that result in a lower system power and smaller footprint. Bits 201 The AD4020/AD4021/AD4022 each have an internal voltage clamp that protects the device from overvoltage damage on the analog inputs. 181 The analog input incorporates circuitry that reduces the nonlinear charge kickback seen from a typical switched capacitor SAR input. This reduction in kickback, combined with a longer acquisition phase, allows the use of lower bandwidth and lower power amplifiers as drivers. This combination has the additional benefit of allowing a larger resistor value in the input RC filter and a corresponding smaller capacitor, which results in a smaller RC load for the amplifier, improving stability and power dissipation. 183 High-Z mode can be enabled via the SPI interface by programming a register bit (see Table 12). When high-Z mode is enabled, the ADC input has a low input charging current at low input signal frequencies as well as improved distortion over a wide frequency 100 kSPS Not applicable AD7989-12 400 kSPS to 250 kSPS 500 kSPS Not AD40222 applicable AD40112, AD76912 AD76902, AD7989-52 AD40102 161 AD7684 AD76872 163 AD7680, AD7683, AD7988-12 AD76852, AD7694 143 AD7940 AD79422 1 2 3 True differential. Pin for pin compatible. Pseudo differential. Rev. C | Page 18 of 40 AD76882, AD76932, AD79162 AD40082, AD76862, AD7988-52 AD79462 ≥1000 kSPS AD40202, AD40212 AD40032, AD40072, AD79822, AD79842 AD40022, AD40062 AD40012, AD40052, AD79152 AD40002, AD40042, AD79802, AD79832 Not applicable Data Sheet AD4020/AD4021/AD4022 TRANSFER FUNCTIONS The AD4020/AD4021/AD4022 are SAR-based ADCs using a charge redistribution sampling digital-to-analog converter (DAC). Figure 38 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 20 binary weighted capacitors that are connected to the comparator inputs. The ideal transfer characteristics for the AD4020/AD4021/ AD4022 are shown in Figure 39 and Table 9. When the acquisition phase is complete and the CNV input goes high, a conversion phase initiates. When the conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. The differential voltage between the IN+ and IN− inputs captured at the end of the acquisition phase is applied to the comparator inputs, unbalancing the comparator. By switching each element of the capacitor array between GND and VREF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4, …, VREF/1,048,576). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the process completes, the control logic generates the ADC output code and a busy signal indicator. 011...111 011...110 011...101 100...010 100...001 100...000 –FSR –FSR + 1 LSB –FSR + 0.5 LSB +FSR – 1 LSB +FSR – 1.5 LSB ANALOG INPUT 15369-030 During the acquisition phase, terminals of the array tied to the input of the comparator are connected to ground via the SW+ and SW− switches (see Figure 38). All independent switches connect the other terminal of each capacitor to the analog inputs. The capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN− inputs. ADC CODE (TWOS COMPLEMENT) CONVERTER OPERATION Figure 39. ADC Ideal Transfer Function (FSR Is Full-Scale Range) Because the AD4020/AD4021/AD4022 have on-board conversion clocks, the serial clock, SCK, is not required for the conversion process. Table 9. Output Codes and Ideal Input Voltages Description FSR − 1 LSB Midscale + 1 LSB Midscale Midscale − 1 LSB −FSR + 1 LSB −FSR Analog Input, VREF = 5 V +4.99999046 V +9.54 µV 0V −9.54 µV −4.99999046 V −5 V VREF = 5 V with Span Compression Enabled +3.99999237 V +7.63 µV 0V −7.63 µV −3.99999237 V −4 V Digital Output Code (Hex) 0x7FFFF1 0x00001 0x00000 0xFFFFF 0x80001 0x800002 This output code is also the code for an overranged analog input (VIN+ − VIN− above VREF with span compression disabled and above 0.8 × VREF with span compression enabled). 2 This output code is also the code for an underranged analog input (VIN+ − VIN− below −VREF with span compression disabled and below -0.8 × VREF with span compression enabled). 1 Rev. C | Page 19 of 40 AD4020/AD4021/AD4022 Data Sheet APPLICATIONS INFORMATION TYPICAL APPLICATION DIAGRAMS Figure 41 shows a recommended connection diagram when using a single-supply system. This setup is preferable when only a limited number of rails are available in the system and power dissipation is of critical importance. Figure 40 shows an example of the recommended connection diagram for the AD4020/AD4021/AD4022 when multiple supplies, V+ and V−, are available. This configuration is used for optimal performance because the amplifier supplies can be selected to allow the maximum signal range (see Figure 40 for the range). Figure 42 shows a typical application diagram when using a fully differential amplifier (FDA). V+ ≥ +6.5V REF LDO 1.8V AMP VREF /2 5V 10kΩ 0.1µF 10kΩ 0.1µF 1.8V TO 5V HOST SUPPLY 10µF V+ R AMP VREF VREF /2 VIO SDI IN+ V– AD4020/ AD4021/ AD4022 V+ SCK VREF /2 CNV GND 3-WIRE/4-WIRE INTERFACE C 0V DIGITAL HOST (MICROPROCESSOR/ FPGA) SDO IN– R AMP VREF VDD REF C 0V 15369-031 V– V– ≤ –0.5V Figure 40. Typical Application Diagram with Multiple Supplies V+ = +5V REF1 LDO AMP VREF /2 1.8V 4.096V 10kΩ 10kΩ 0.1µF 100nF 100nF 1.8V TO 5V HOST SUPPLY 10µF2 R AMP VREF VREF /2 0.1µF REF C 0 VDD SDI IN+ AD4020/ AD4021/ AD40222 IN– AMP VREF VREF /2 R VIO SCK SDO CNV GND 3-WIRE/4-WIRE INTERFACE C 0 DIGITAL HOST (MICROPROCESSOR/ FPGA) 3, 4 SELECTION. Figure 41. Typical Application Diagram with a Single Supply Rev. C | Page 20 of 40 15369-032 1SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE 2C REF IS USUALLY A 10µF CERAMIC CAPACITOR (X7R). 3SEE THE DRIVER AMPLIFIER CHOICE SECTION. 4SEE THE ANALOG INPUTS SECTION. Data Sheet AD4020/AD4021/AD4022 V+ = +5V REF LDO AMP VREF /2 VREF /2 R4 1kΩ R3 1kΩ VREF 10kΩ 0 4.096V 10kΩ 10µF 1.8V 0.1µF 0.1µF 1.8V TO 5V HOST SUPPLY V+ +IN REF R –OUT IN+ C VREF /2 VOCM C +OUT 0.1µF –IN R DIFFERENTIAL AMPLIFIER IN– VDD VIO SDI AD4020/ AD4021/ AD4022 SCK SDO CNV GND 3-WIRE/4-WIRE INTERFACE V– R1 1kΩ VREF 0 15369-033 VREF /2 DIGITAL HOST (MICROPROCESSOR/ FPGA) R2 1kΩ Figure 42. Typical Application Diagram with a Fully Differential Amplifier ANALOG INPUTS If the analog input exceeds the reference voltage by 0.4 V, the internal clamp circuit turns on and the current flows through the clamp into ground, preventing the input from rising further and potentially causing damage to the device. The clamp turns on before D1 (see Figure 43) and can sink up to 50 mA of current. Figure 43 shows an equivalent circuit of the analog input structure, including the overvoltage clamp of the AD4020/AD4021/AD4022. REF D1 VIN RIN CIN IN+/IN– CEXT CPIN D2 CLAMP GND 15369-034 0V TO 15V REXT Figure 43. Equivalent Analog Input Circuit Input Overvoltage Clamp Circuit Most ADC analog inputs, IN+ and IN−, have no overvoltage protection circuitry apart from ESD protection diodes. During an overvoltage event, an ESD protection diode from an analog input pin (IN+ or IN−) to REF forward biases and shorts the input pin to REF, potentially overloading the reference or damaging the device. The AD4020/AD4021/AD4022 internal overvoltage clamp circuit with a larger external resistor (REXT = 200 Ω) eliminates the need for external protection diodes and protects the ADC inputs against dc overvoltages. In applications where the amplifier rails are greater than VREF and less than ground, it is possible for the output to exceed the input voltage range (specified in Table 1) of the device. In this case, the AD4020/AD4021/AD4022 internal overvoltage clamp circuit ensures that the voltage on the input pin does not exceed VREF + 0.4 V and prevents damage to the device by clamping the input voltage in a safe operating range and avoiding disturbance of the reference, which is particularly important for systems that share the reference among multiple ADCs. When the clamp is active, it sets the overvoltage (OV) clamp flag bit in the configuration register that is accessed with a 16-bit SPI read command or via the OV in the status bits. The OV clamp flag gives an indication of overvoltage condition when it is set to 0. The OV clamp flag is a read only sticky bit, and is cleared only if the register is read while the overvoltage condition is no longer present. The clamp circuit does not dissipate static power in the off state. Note that the clamp cannot sustain the overvoltage condition for an indefinite amount of time. The external RC filter, formed by the REXT resistor and the CEXT capacitor (see Figure 43), is usually present at the ADC input to band limit the input signal. During an overvoltage event, excessive voltage is dropped across REXT, and REXT becomes part of a protection circuit. The REXT value can vary from 200 Ω to 20 kΩ for 15 V protection. The CEXT value can be as low as 100 pF for correct operation of the clamp. See Table 1 for input overvoltage clamp specifications. Rev. C | Page 21 of 40 AD4020/AD4021/AD4022 Data Sheet Differential Input Considerations DRIVER AMPLIFIER CHOICE The analog input structure allows the sampling of the true differential signal between IN+ and IN−. By using these differential inputs, signals common to both inputs are rejected. Figure 32 shows the common-mode rejection capability of the AD4020/ AD4021/AD4022 over frequency. It is important to note that the differential input signals must be truly antiphase in nature, 180° out of phase, which is required to keep the common-mode voltage of the input signal within the specified range around VREF/2, as shown in Table 1. Although the AD4020/AD4021/AD4022 are easy to drive, the driver amplifier must meet the following requirements: • The noise generated by the driver amplifier must be kept low enough to preserve the SNR and transition noise performance of the AD4020/AD4021/AD4022. The noise from the driver is filtered by the single-pole, low-pass filter of the analog input circuit made by RIN and CIN, or by the external filter, if one is used. Because the typical noise of the AD4020/AD4021/AD4022 is 31.5 µV rms, the SNR degradation due to the amplifier is the following: Switched Capacitor Input During the acquisition phase, the impedance of the analog inputs (IN+ or IN−) can be modeled as a parallel combination of Capacitor CPIN and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 400 Ω and is a lumped component composed of serial resistors and the on resistance of the switches. CIN is typically 40 pF and is mainly the ADC sampling capacitor. SNRLOSS RC Filter Values The RC values in Table 10 are chosen for ease of drive considerations and greater ADC input protection. The combination of a large R value (200 Ω) and small C value results in a reduced dynamic load for the amplifier to drive. The smaller value of C means fewer stability and phase margin concerns with the amplifier. The large value of R limits the current into the ADC input when the amplifier output exceeds the ADC input range.       where: f−3 dB is the input bandwidth, in megahertz, of the AD4020/ AD4021/AD4022 (10 MHz) or the cutoff frequency of the input filter, if one is used. N is the noise gain of the amplifier (for example, 1 in buffer configuration). eN is the equivalent input noise voltage of the operational amplifier in nV/√Hz. During the conversion phase, where the switches are open, the input impedance is limited to CPIN. RIN and CIN make a singlepole, low-pass filter that reduces undesirable aliasing effects and limits noise. The RC filter value (represented by R and C in Figure 40 to Figure 42 and Figure 44) and driving amplifier can be selected depending on the input signal bandwidth of interest at the full throughput. Lower input signal bandwidth means that the RC cutoff can be lower, thereby reducing noise into the converter. For optimum performance at various throughputs, use the recommended RC values (200 Ω, 180 pF) and the ADA4807-1.   31.5  = 20 log  π 2  31.5 + f −3 dB (Ne N )2 2  • For ac applications, the driver must have a THD performance commensurate with the AD4020/AD4021/AD4022. For multichannel multiplexed applications, the driver amplifier and the analog input circuit of the AD4020/ AD4021/AD4022 must settle for a full-scale step onto the capacitor array at a 20-bit level (0.00001%, 1 ppm). In amplifier data sheets, settling at 0.1% to 0.01% is more commonly specified. Settling at 0.1% to 0.01% can differ significantly from the settling time at a 20-bit level and must be verified prior to driver selection. • The Precision ADC Driver Tool can be used to model the settling behavior and estimate ac performance of the AD4020/ AD4021/AD4022 with a selected driver amplifier and RC filter. Once the Precision ADC Driver Tool has modeled a specific circuit, the circuit can be exported for simulation in LTspice. Table 10. RC Filter and Amplifier Selection for Various Input Bandwidths Input Signal Bandwidth (kHz) ND + NS tCYC − tCONV − t EN − tQUIET2 where tCONV corresponds to the conversion time, and is described in Table 2. Rev. C | Page 26 of 40 Data Sheet AD4020/AD4021/AD4022 Table 12. Configuration Register Bits [7:5] 4 Bit Name Reserved Status bits enable 3 Span compression enable 2 High-Z mode enable 1 Turbo mode enable 0 OV clamp flag 1 Description Reserved memory. Enables status bits (see the Status Bits section). 0: disables status bits. 1: enables status bits. Enables span compression (see the Input Span Compression section). 0: disables span compression. 1: enables span compression. Enables high-Z mode (see the High-Z Mode section). 0: disables high-Z mode. 1: enables high-Z mode. Enables turbo mode. 0: disables turbo mode. 1: enables turbo mode. Indicates an overvoltage event triggered the input overvoltage clamp circuit (see the Input Overvoltage Clamp Circuit section). This bit is sticky, and clears only when read after the overvoltage event has ended. 0: indicates an overvoltage event has occurred. 1: indicates no overvoltage event has occurred. Reset 0x0 0x0 Access 1 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x1 R R is read-only and R/W stands for read/write. Read only bits cannot be updated with a register write operation. R/W bits can be updated with a register write operation. Table 13. SCK Frequency Requirements for Various Throughputs CS Mode 3-Wire and 4-Wire Turbo Modes 3-Wire and 4-Wire Turbo Modes with Six Status Bits 1 3-Wire and 4-Wire Modes 3-Wire and 4-Wire Modes with Status Word 1 Throughput 1.8 MSPS (AD4020) 1 MSPS (AD4020, AD4021) 500 kSPS (AD4020, AD4021, AD4022) 100 kSPS (AD4020, AD4021, AD4022) 1.8 MSPS (AD4020) 1 MSPS (AD4020, AD4021) 500 kSPS (AD4020, AD4021, AD4020) 100 kSPS (AD4020, AD4021, AD4022) 1.6 MSPS (AD4020) 1 MSPS (AD4020, AD4021) 500 kSPS (AD4020, AD4021, AD4022) 100 kSPS (AD4020, AD4021, AD4022) 1.4 MSPS (AD4020) 1 MSPS (AD4020, AD4021) 500 kSPS (AD4020, AD4021, AD4022) 100 kSPS (AD4020, AD4021, AD4022) Minimum SCK Frequency (MHz) 71 28 12 2.5 92 36 16 3 98 35 13 2.5 90 45 17 3 It is not necessary to clock out all six status bits. The minimum required SCK frequency is reduced when clocking out fewer than six status bits. See the Serial Clock Frequency Requirements and the Status Bits sections. Rev. C | Page 27 of 40 AD4020/AD4021/AD4022 Data Sheet REGISTER READ/WRITE FUNCTIONALITY full byte. When performing a read operation, the current register contents are shifted out on SDO, MSB first. Figure 49 and Figure 50 show timing diagrams for register read and write operations when using any of the CS modes. Figure 51 shows the timing diagram for performing a register write operation to multiple devices connected in daisy-chain mode. The AD4020/AD4021/AD4022 configuration register is read from and written to with a 16-bit SPI instruction. The state of the fields in the configuration register determine which of the device features are enabled or disabled (see the Configuration Register Details section). Register reads are not supported when daisy-chaining multiple devices (see the Daisy-Chain Mode section). To verify the contents of the configuration register, enable and read the status bits (see the Status Bits section). The 16-bit SPI instructions consist of the 8-bit register access command (see Table 14) followed by the register data. When performing register read and write operations, CNV is analogous to a chip select signal, and CNV must be brought low to access the configuration register contents. Data on SDI is latched in on each SCK rising edge. Data is shifted out on SDO on each SCK falling edge. SDO returns to a high impedance state when CNV is brought high. The LSB of the configuration register (Bit 0) is a read only bit that allows digital hosts to ensure the desired digital interface mode is selected in the frame immediately following a register write operation. For digital hosts that are limited to 16-bit SPI frames (such as some microcontrollers), set this bit accordingly to ensure SDI is at the desired level on the rising edge of CNV. For example, set this bit to 1 and/or set the idle state of SDI to 1 when using any of the CS modes. The first bit read on SDI after a CNV falling edge (represented by WEN in Table 14) must be a 0 to initiate the register access command. The next bit (R/W) determines whether the instruction is a write or a read. The following six bits must match the values for Bit 5 through Bit 0, shown in Table 14, to perform the SPI read/write. SPI write instructions can be performed in the same frame as reading a conversion result. To ensure the conversion is executed correctly, the CNV signal must obey the timing requirements for the selected interface mode. When performing a write operation, the new register contents are written over SDI MSB first, and the writeable bits in the configuration register are updated after the device receives the Table 14. Register Access Command Bit 7 WEN Bit 6 R/W Bit 5 0 Bit 4 1 Bit 3 0 Bit 2 1 Bit 1 0 Bit 0 0 tCYC tSCK tCNVH 1 CNV tSCNVSCK 1 2 3 4 5 WEN (0) SDO R/W (1) 0 1 0 1 8-BIT REGISTER ACCESS COMMAND tEN D19 7 8 9 10 D18 D17 D16 D15 0 12 13 14 15 16 1 0 tDIS tHSDO tDSDO D14 11 tSCKH tHSDISCK tSSDISCK 1 6 D13 D12 B7 B6 B5 B4 B3 B2 B1 REGISTER DATA ON B7 TO B0 1THE CNV HIGH TIME MUST FOLLOW THE t CONV SPECIFICATION TO GENERATE A VALID CONVERSION RESULT. 2THE SCK FALLING EDGE TO CNV RISING EDGE DELAY MUST FOLLOW THE t QUIET2 SPECIFICATION TO ENSURE 3X MEANS DON’T CARE. Figure 49. Register Read Timing Diagram Rev. C | Page 28 of 40 SPECIFIED PERFORMANCE. B0 X3 15369-046 SCK SDI tQUIET22 tSCKL Data Sheet AD4020/AD4021/AD4022 tCYC tCNVH 1 tHCNVSCK tSCK CNV tSCKL tSCNVSCK SCK 1 2 3 4 5 6 7 9 8 10 11 12 13 14 tQUIET22 15 16 17 18 19 20 tSCKH tHSDISCK tSSDISCK SDI R/W (0) WEN (0) 1 0 0 1 1 0 B7 0 B6 B5 B4 SDO D18 D17 D16 D15 D14 B1 1 B0 D13 tDIS tHSDO tDSDO D19 B2 REGISTER DATA ON B7 TO B0 8-BIT REGISTER ACCESS COMMAND tEN B3 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 15369-047 CONVERSION RESULT ON D19 TO D0 1THE CNV HIGH TIME MUST FOLLOW THE t CONV SPECIFICATION TO GENERATE A VALID CONVERSION RESULT. 2THE SCK FALLING EDGE TO CNV RISING EDGE DELAY MUST FOLLOW THE t QUIET2 SPECIFICATION TO ENSURE SPECIFIED PERFORMANCE. Figure 50. Register Write Timing Diagram tCYC tCNVH tSCK CNV tSCNVSCK SCK tSCKL 1 24 tSCKH SDIA SDOA/SDIB 0 COMMAND (0x14) 0 DATA (0xAB) COMMAND (0x14) 0 DATA (0xAB) 0 0 COMMAND (0x14) Figure 51. Register Write Timing Diagram, Daisy-Chain Mode Rev. C | Page 29 of 40 0 15369-048 tDIS SDOB AD4020/AD4021/AD4022 Data Sheet STATUS BITS daisy-chain mode, however, all six status bits must be clocked out for each connected device. A set of six optional status bits can be appended to the end of each conversion result. The status bits allow the digital host to check the state of the input overvoltage protection circuit and verify that the ADC features are configured correctly without interrupting conversions. The status bits are enabled when the status bits enable bit in the configuration register is set to 1 (see Configuration Register Details section). Table 15 shows a description of each status bit. Figure 52 shows the serial interface timing for CS mode, 3-wire without busy indicator with all six status bits clocked out. Table 15. Status Bits Descriptions When enabled, the status bits are clocked out MSB first starting on the SCK falling edge immediately following the LSB of the conversion result. The SDO line returns to high impedance after the sixth status bit is clocked out (except in daisy-chain mode). The user is not required to clock out all status bits to start the next conversion. For example, if the digital host needs to monitor the OV clamp flag but also needs to minimize the SCK frequency, the remaining status bits can be ignored to limit the number of SCK pulses required per conversion period. When using multiple AD4020/AD4021/AD4022 devices in Bit 5 Bit Name OV clamp flag 4 Span compression 3 High-Z mode 2 Turbo mode [1:0] Reserved Description Indicates the state of the OV clamp flag in the configuration register. Indicates the state of the span compression enable bit in the configuration register. Indicates the state of the High-Z mode enable bit in the configuration register. Indicates the state of the turbo mode enable bit in the configuration register. Reserved. SDI = 1 tCYC tCNVH CNV tACQ ACQUISITION ACQUISITION CONVERSION tSCK tCONV tQUIET2 tSCKL 1 2 3 18 25 26 tSCKH tHSDO tEN SDO 24 20 19 tDSDO D19 D18 D17 tDIS D1 B1 D0 STATUS BITS B[5:0] Figure 52. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing Diagram Including Status Bits Rev. C | Page 30 of 40 B0 15369-049 SCK Data Sheet AD4020/AD4021/AD4022 When performing conversions in this mode, SDI must be held high. A CNV rising edge initiates a conversion and forces SDO to high impedance. The user must wait tQUIET1 time after the CNV rising edge before bringing CNV low to clock out the previous conversion result. When the conversion is complete (after tCONV), the AD4020/AD4021/AD4022 enter the acquisition phase and power down. CS MODE, 3-WIRE TURBO MODE This mode is typically used when a single AD4020/AD4021/ AD4022 device is connected to an SPI-compatible digital host. Turbo mode allows lower SCK frequencies by increasing the time that the ADC conversion result can be clocked out. The AD4020 can achieve a throughput rate of 1.8 MSPS only when turbo mode is enabled and using a minimum SCK rate of 71 MHz (see the Serial Clock Frequency Requirements section). The connection diagram is shown in Figure 53, and the corresponding timing diagram is shown in Figure 54. When CNV goes low, the MSB is output to SDO. The remaining data bits are clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time, as dictated by tHSDO (see Table 2). If the status bits are not enabled, SDO returns to high impedance after the 20th SCK falling edge. If the status bits are enabled, they are shifted out on SDO on the 21st through the 26th SCK falling edges (see the Status Bits section). SDO returns to high impedance after the final SCK falling edge, or when CNV goes high (whichever occurs first). The user must also provide a delay of tQUIET2 between the final SCK falling edge and the next CNV rising edge to ensure specified performance. To enable turbo mode, set the turbo mode enable bit in the configuration register to 1 (see Table 12). This mode replaces the 3-wire with busy indicator mode when turbo mode is enabled. Writing to the user configuration register requires SDI to be connected to the digital host (see the Register Read/Write Functionality section). When turbo mode is enabled, the conversion result read on SDO corresponds to the result of the previous conversion. DATA OUT CONVERT DIGITAL HOST CNV AD4020/ AD4021/ AD4022 SDI SDO DATA IN 15369-050 SCK CLK Figure 53. CS Mode, 3-Wire Turbo Mode Connection Diagram SDI = 1 tCYC CNV tACQ CONVERSION ACQUISITION tCONV tSCK tSCKL tQUIET1 SCK 1 2 3 19 20 tSCKH HSDO tDSDO tEN SDO 18 tQUIET2 D19 D18 D17 tDIS D1 D0 Figure 54. CS Mode, 3-Wire Turbo Mode Serial Interface Timing Diagram (Status Bits Not Shown) Rev. C | Page 31 of 40 15369-051 ACQUISITION AD4020/AD4021/AD4022 Data Sheet CS MODE, 3-WIRE WITHOUT BUSY INDICATOR time to avoid the generation of the busy signal indicator. When the conversion is complete, the AD4020/AD4021/AD4022 enter the acquisition phase and power down. There must not be any digital activity on SCK during the conversion. This mode is typically used when a single AD4020/AD4021/ AD4022 device is connected to an SPI-compatible digital host. The connection diagram is shown in Figure 55, and the corresponding timing diagram is shown in Figure 56. When CNV goes low, the MSB is output onto SDO. The remaining data bits are clocked out on SDO by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time, as dictated by tHSDO (see Table 2). If the status bits are not enabled, SDO returns to high impedance after the 20th SCK falling edge. If the status bits are enabled, they are shifted out on SDO on the 21st through the 26th SCK falling edges (see the Status Bits section). SDO returns to high impedance after the final SCK falling edge, or when CNV goes high (whichever occurs first). Turbo mode must be disabled to use this mode. To disable turbo mode, set the turbo mode enable bit in the configuration register to 0 (see Table 12). Turbo mode is disabled by default. When performing conversions in this mode, SDI must be held high. SDI can be connected to VIO if register reading and writing is not required. A rising edge on CNV initiates a conversion and forces SDO to high impedance. After a conversion is initiated, it continues until completion, irrespective of the state of CNV. This feature can be useful when bringing CNV low to select other SPI devices, such as analog multiplexers. However, CNV must be returned high before the minimum conversion time (tCONV) elapses and then held high for the maximum possible conversion CONVERT DIGITAL HOST CNV VIO SDI1 AD4020/ AD4021/ AD4022 DATA IN SDO SCK 1SDI MUST BE CONNECTED TO THE DIGITAL HOST DATA OUT TO WRITE TO THE CONFIGURATION REGISTER. 15369-052 CLK Figure 55. CS Mode, 3-Wire Without Busy Indicator Connection Diagram SDI = 1 tCYC tCNVH CNV tACQ CONVERSION ACQUISITION tSCK tCONV tSCKL SCK 1 2 3 18 19 20 tSCKH HSDO tEN SDO tQUIET2 tDSDO D19 D18 D17 tDIS D1 D0 Figure 56. CS Mode, 3-Wire Without the Busy Indicator Serial Interface Timing Diagram (Status Bits Not Shown) Rev. C | Page 32 of 40 15369-053 ACQUISITION Data Sheet AD4020/AD4021/AD4022 CS MODE, 3-WIRE WITH BUSY INDICATOR AD4022 then enter the acquisition phase and power down. There must not be any digital activity on the SCK during the conversion. This mode is typically used when a single AD4020/AD4021/ AD4022 device is connected to an SPI-compatible digital host with an interrupt input (IRQ). The connection diagram is shown in Figure 57, and the corresponding timing diagram is shown in Figure 58. When the conversion is complete, SDO is driven low. With a pull-up resistor (for example, 1 kΩ) on the SDO line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. The data bits are then clocked out MSB first on SDO by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time, as dictated by tHSDO (see Table 2). The conversion result is clocked out on SDO on the first 20 SCK falling edges. If the status bits are enabled, they are clocked out on SDO on the 21st through the 26th SCK falling edges (see the Status Bits section). SDO returns to high impedance after an optional additional SCK falling edge or the next CNV rising edge (whichever occurs first). Turbo mode must be disabled to use this mode. To disable turbo mode, set the turbo mode enable bit in the configuration register to 0 (see Table 12). Turbo mode is disabled by default. When performing conversions in this mode, SDI must be held high. SDI can be connected to VIO if register reading and writing is not required. A rising edge on CNV initiates a conversion and forces SDO to high impedance. SDO remains high impedance until the completion of the conversion, irrespective of the state of CNV. Prior to the minimum conversion time, CNV can select other SPI devices, such as analog multiplexers. However, CNV must be returned low before the minimum conversion time (tCONV) elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. When the conversion is complete, the AD4020/AD4021/ If multiple AD4020/AD4021/AD4022 devices are selected at the same time, the SDO output pin handles this contention without damage or induced latch-up. It is recommended to keep this contention as short as possible to limit extra power dissipation. CONVERT VIO DIGITAL HOST CNV 1kΩ VIO SDI1 AD4020/ AD4021/ AD4022 SDO DATA IN IRQ SCK 15369-054 CLK 1SDI MUST BE CONNECTED TO THE DIGITAL HOST DATA OUT TO WRITE TO THE CONFIGURATION REGISTER. Figure 57. CS Mode, 3-Wire with Busy Indicator Connection Diagram SDI = 1 tCYC tCNVH CNV tACQ CONVERSION ACQUISITION tSCK tCONV tSCKL SCK 1 2 3 tHSDO tQUIET2 19 20 21 tSCKH tDSDO SDO D19 D18 tDIS D1 D0 Figure 58. CS Mode, 3-Wire with the Busy Indicator Serial Interface Timing Diagram (Status Bits Not Shown) Rev. C | Page 33 of 40 15369-055 ACQUISITION AD4020/AD4021/AD4022 Data Sheet conversion and data readback phase. When performing conversions in this mode, SDI must be high during the CNV rising edge. The user must wait tQUIET1 time after the CNV rising edge before bringing SDI low to clock out the previous conversion result. When the conversion is complete (after tCONV), the AD4020/ AD4021/AD4022 enter the acquisition phase and power down. CS MODE, 4-WIRE TURBO MODE This mode is typically used when a single AD4020/4021/4022 device is connected to an SPI-compatible digital host. Turbo mode allows lower SCK frequencies by increasing the time that the ADC conversion result can be clocked out. The AD4020 can achieve a throughput rate of 1.8 MSPS only when turbo mode is enabled and using a minimum SCK frequency of 71 MHz (see the Serial Clock Frequency Requirements section). The connection diagram is shown in Figure 59, and the corresponding timing diagram is shown in Figure 60. SDI is analogous to a chip select input, and bringing SDI low outputs the MSB of the conversion result on SDO. The remaining data bits are clocked out on SDO by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time, as dictated by tHSDO (see Table 2). The conversion result is clocked out on SDO on the first 20 SCK falling edges. If the status bits are enabled, they are shifted out on SDO on the 21st through the 26th SCK falling edges (see the Status Bits section). SDO returns to high impedance after the final SCK falling edge, or when CNV goes high (whichever occurs first). The user must also provide a delay of tQUIET2 between the final SCK falling edge and the next CNV rising edge to ensure specified performance. To enable turbo mode, set the turbo mode enable bit in the configuration register to 1 (see Table 12). This mode replaces the 4-wire with busy indicator mode when turbo mode is enabled. The digital host must be able to write data over SDI to perform register reads and writes (see the Register Read/Write Functionality section). When turbo mode is enabled, the conversion result read on SDO corresponds to the result of the previous conversion. A rising edge on CNV initiates a conversion and forces SDO to high impedance. CNV must be held high throughout the DATA OUT CONVERT DIGITAL HOST CNV AD4020/ AD4021/ AD4022 SDI SDO DATA IN 15369-056 SCK CLK Figure 59. CS Mode, 4-Wire Turbo Mode Connection Diagram CNV tCYC tSSDICNV SDI tHSDICNV ACQUISITION tACQ CONVERSION ACQUISITION tSCK tCONV tSCKL tQUIET2 tQUIET1 1 2 3 18 tHSDO 20 tSCKH tEN SDO 19 tDIS tDSDO D19 D18 D17 D1 D0 Figure 60. CS Mode, 4-Wire Turbo Mode Timing Diagram (Status Bits Not Shown) Rev. C | Page 34 of 40 15369-057 SCK Data Sheet AD4020/AD4021/AD4022 CS MODE, 4-WIRE WITHOUT BUSY INDICATOR the busy signal indicator. When the conversion is complete, the AD4020/AD4021/AD4022 enter the acquisition phase and power down. There must not be any digital activity on SCK during the conversion. This mode is typically used when multiple AD4020/AD4021/ AD4022 devices are connected to an SPI-compatible digital host. A connection diagram example using two AD4020/AD4021/AD4022 devices is shown in Figure 61, and the corresponding timing diagram is shown in Figure 62. SDI is analogous to a chip select input and each ADC result can be read by bringing the corresponding SDI input low. Bringing SDI low on each device outputs the MSB of the conversion result on the corresponding SDO pin. The remaining data bits are clocked out on SDO by subsequent SCK falling edges. The data is valid on both SCK edges. The conversion result is clocked out on SDO on the first 20 SCK falling edges. If the status bits are enabled, they are shifted out on SDO on the 21st through the 26th SCK falling edges (see the Status Bits section). SDO returns to high impedance after the final SCK falling edge, or when SDI goes high (whichever occurs first). If the SDO of each device is tied together, ensure SDI is only low for one device at a time. The user must also provide a delay of tQUIET2 between the final SCK falling edge and the next CNV rising edge to ensure specified performance. Turbo mode must be disabled to use this mode. To disable turbo mode, set the turbo mode enable bit in the configuration register to 0 (see Table 12). Turbo mode is disabled by default. A rising edge on CNV initiates a conversion and forces SDO to high impedance. When performing conversions in this mode, SDI must be high during the CNV rising edge. CNV must be held high throughout the conversion and data readback phase. When performing conversions in this mode, SDI must be high during the CNV rising edge. Prior to the minimum conversion time (tCONV), SDI can select other SPI devices, such as analog multiplexers. However, SDI must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of CS2 CS1 CONVERT CNV SDI CNV AD4020/ AD4021/ AD4022 SDO AD4020/ AD4021/ AD4022 SDI DEVICE A DEVICE B SCK SCK DIGITAL HOST SDO 15369-058 DATA IN CLK Figure 61. CS Mode, 4-Wire Without Busy Indicator Connection Diagram CYC CNV tACQ ACQUISITION CONVERSION ACQUISITION tCONV tQUIET2 tSSDICNV SDI(CS1) tHSDICNV SDI(CS2) tSCK tSCKL 1 2 3 18 tHSDO 20 21 22 38 39 40 tDIS tDSDO tEN SDO 19 tSCKH D19 D18 D17 D1 D0 D19 D18 D1 Figure 62. CS Mode, 4-Wire Without the Busy Indicator Serial Interface Timing Diagram (Status Bits Not Shown) Rev. C | Page 35 of 40 D0 15369-059 SCK AD4020/AD4021/AD4022 Data Sheet CS MODE, 4-WIRE WITH BUSY INDICATOR minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. When the conversion is complete, the AD4020/AD4021/AD4022 enter the acquisition phase and power down. There must not be any digital activity on SCK during the conversion. This mode is typically used when a single AD4020/AD4021/ AD4022 device is connected to an SPI-compatible digital host with an interrupt input (IRQ), and when CNV, which samples the analog input, is required to be independent of the signal used to select the data reading. This independence is particularly important in applications where low jitter on CNV is desired. The connection diagram is shown in Figure 63, and the corresponding timing diagram is shown in Figure 64. When the conversion is complete, SDO is driven low. With a pull-up resistor (for example, 1 kΩ) on the SDO line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. The data bits are then clocked out MSB first on SDO by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time, as dictated by tHSDO (see Table 2). The conversion result is clocked out on SDO on the first 20 SCK falling edges. If the status bits are enabled, they are clocked out on SDO on the 21st through the 26th SCK falling edges (see the Status Bits section). SDO returns to high impedance after an optional additional SCK falling edge or the next CNV rising edge (whichever occurs first). Turbo mode must be disabled to use this mode. To disable turbo mode, set the turbo mode enable bit in the configuration register to 0 (see Table 12). Turbo mode is disabled by default. A rising edge on CNV initiates a conversion and forces SDO to high impedance. When performing conversions in this mode, SDI must be high during the CNV rising edge. CNV must be held high throughout the conversion and data readback phase. When performing conversions in this mode, SDI must be high during the CNV rising edge. Prior to the minimum conversion time (tCONV), SDI can select other SPI devices, such as analog multiplexers. However, SDI must be returned low before the CS1 CONVERT VIO CNV SDI DIGITAL HOST 1kΩ AD4020/ AD4021/ AD4022 DATA IN SDO IRQ 15369-060 SCK CLK Figure 63. CS Mode, 4-Wire with Busy Indicator Connection Diagram tCYC CNV tACQ ACQUISITION ACQUISITION CONVERSION tCONV tSSDICNV SDI tSCK tHSDICNV tSCKL 1 2 3 tHSDO 19 20 21 tSCKH tDIS tDSDO tEN SDO D19 D18 D1 D0 Figure 64. CS Mode, 4-Wire with the Busy Indicator Serial Interface Timing Diagram (Status Bits Not Shown) Rev. C | Page 36 of 40 15369-061 SCK tQUIET2 Data Sheet AD4020/AD4021/AD4022 each ADC, SDI feeds the input of the internal shift register and is clocked in on each SCK rising edge. Results are therefore passed through each device until they are all received by the digital host. When the status bits are disabled, 20 × N clocks are required to read back N ADCs. When the status bits are enabled, 26 × N clocks are required to read back the conversion data and status bits for N ADCs. The data is valid on both SCK edges. DAISY-CHAIN MODE Use this mode to daisy-chain multiple AD4020/AD4021/AD4022 devices on a 3-wire or 4-wire serial interface. This feature is useful for reducing component count and wiring connections such as cases with isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. A connection diagram example using two AD4020/AD4021/AD4022 devices is shown in Figure 65, and the corresponding timing diagram is shown in Figure 66. The maximum achievable conversion rate when using daisy-chain mode is typically less than when reading a single device because the number of bits to clock out is larger (see the Serial Clock Frequency Requirements section). Turbo mode must be disabled to use this mode. To disable turbo mode, set the turbo mode enable bit in the configuration register to 0 (see Table 12). Writing to the user configuration register requires SDI to be connected to the digital host (see the Register Read/Write Functionality section). Turbo mode is disabled by default. It is possible to write to each ADC register in daisy-chain mode. The timing diagram is shown in Figure 51. This mode requires 4-wire operation because data is clocked in on the SDI line with CNV held low. The same command byte and register data can be shifted through the entire chain to program all ADCs in the chain with the same register contents, which requires 8 × (N + 1) clocks for N ADCs. It is possible to write different register contents to each ADC in the chain by writing to the furthest ADC in the chain first, using 8 × (N + 1) clocks, and then the second furthest ADC with 8 × N clocks, and so forth until reaching the nearest ADC in the chain, which requires 16 clocks for the command and register data. It is not possible to read register contents in daisy-chain mode. When SDI and CNV are low, SDO is driven low. A rising edge on CNV initiates a conversion and SDO remains low. When performing conversions in this mode, SDI and SCK must be low during the CNV rising edge. CNV must be held high throughout the conversion and data readback phase. When the conversion is complete, the MSB is output onto SDO of each device, and the AD4020/AD4021/AD4022 enter the acquisition phase and power down. The remaining data bits are clocked out on SDO by subsequent SCK falling edges. For CONVERT CNV AD4020/ AD4021/ AD4022 SDO SDI DEVICE A DEVICE B SCK SCK DIGITAL HOST SDO DATA IN CLK 1SDI MUST BE CONNECTED TO THE DIGITAL HOST DATA OUT TO WRITE TO THE CONFIGURATION REGISTER. 15369-062 SDI1 CNV AD4020/ AD4021/ AD4022 Figure 65. Daisy-Chain Mode Connection Diagram SDIA = 0 tCYC CNV tACQ ACQUISITION CONVERSION tCONV tSCK SCK 1 tHSCKCNV 2 3 18 19 tSSDISCK 20 21 22 38 39 40 tSCKH tHSDISCK tEN SDOA = SDIB tQUIET2 tSCKL tQUIET2 DA19 DA18 DA17 DA1 DA0 tHSDO tDSDO SDOB DB19 tDIS DB18 DB17 DB1 DB0 DA19 DA18 Figure 66. Daisy-Chain Mode Serial Interface Timing Diagram (Status Bits Not Shown) Rev. C | Page 37 of 40 DA1 DA0 15369-063 ACQUISITION AD4020/AD4021/AD4022 Data Sheet LAYOUT GUIDELINES The PCB that houses the AD4020/AD4021/AD4022 must be designed so that the analog and digital sections are physically separated, such as on opposite sides of the device as shown in Figure 67. The pinout of the AD4020/AD4021/AD4022, with the analog signals on the left side and the digital signals on the right side, helps to separate the analog and digital signals. Avoid running digital lines under the device because they couple noise onto the die, unless a ground plane under the AD4020/ AD4021/AD4022 is used as a shield. Fast switching signals, such as CNV or clocks, must not run near analog signal paths. Avoid crossover of digital and analog signals. EVALUATING THE AD4020/AD4021/AD4022 PERFORMANCE Other recommended layouts for the AD4020/AD4021/AD4022 are outlined in the user guide of the evaluation board for the AD4020 (EVAL-AD4020FMCZ). The evaluation board package includes a fully assembled and tested evaluation board with the AD4020, the UG-1042 user guide, and software for controlling the board from a PC via the EVAL-SDP-CH1Z. The EVALAD4020FMCZ can also be used to evaluate the AD4021 and AD4022 by limiting the throughput to 1 MSPS and 500 kSPS, respectively, in the software (see UG-1042 for more information). At least one ground plane must be used. The ground plane can be common or split between the digital and analog sections. In the latter case, join the planes underneath the AD4020/AD4021/AD4022 devices. Finally, decouple the VDD and VIO power supplies of the AD4020/AD4021/AD4022 with ceramic capacitors, typically 0.1 µF, placed close to the AD4020/AD4021/AD4022 and connected using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. 15369-064 The AD4020/AD4021/AD4022 voltage reference input (REF) has a dynamic input impedance. Decouple the REF pin with minimal parasitic inductances by placing the reference decoupling ceramic capacitor close to (ideally right up against) the REF and GND pins, and connect them with wide, low impedance traces. Figure 67. Example Layout of the AD4020 (Top Layer) 15369-065 An example of the AD4020 layout following these rules is shown in Figure 67 and Figure 68. Note that the AD4021/AD4022 layout is equivalent to the AD4020 layout. Figure 68. Example Layout of the AD4020 (Bottom Layer) Rev. C | Page 38 of 40 Data Sheet AD4020/AD4021/AD4022 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 0.70 0.55 0.40 0.23 0.13 6° 0° 091709-A 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 69. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters DETAIL A (JEDEC 95) 2.48 2.38 2.23 3.10 3.00 SQ 2.90 0.50 BSC 10 6 1.74 1.64 1.49 EXPOSED PAD 0.50 0.40 0.30 1 5 BOTTOM VIE W TOP VIEW 0.80 0.75 0.70 SEATING PLANE SIDE VIEW 0.30 0.25 0.20 0.05 MAX 0.02 NOM COPLANARITY 0.08 P IN 1 I N D IC ATO R AR EA OP TI O N S (SEE DETAIL A) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.20 REF Figure 70. 10-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-10-9) Dimensions shown in millimeters Rev. C | Page 39 of 40 0.20 MIN 05-26-2020-D PIN 1 INDICATOR AREA AD4020/AD4021/AD4022 Data Sheet ORDERING GUIDE Model 1, 2 AD4020BRMZ AD4020BRMZ-RL7 AD4020BCPZ-RL7 AD4021BRMZ AD4021BRMZ-RL7 AD4021BCPZ-RL7 AD4022BRMZ AD4022BRMZ-RL7 AD4022BCPZ-RL7 EVAL-AD4020FMCZ 1 2 Integral Nonlinearity (INL) ±3.1 ppm ±3.1 ppm ±3.1 ppm ±3.1 ppm ±3.1 ppm ±3.1 ppm ±3.1 ppm ±3.1 ppm ±3.1 ppm Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 10-Lead MSOP, Tube 10-Lead MSOP, Reel 10-Lead LFCSP, Reel 10-Lead MSOP, Tube 10-Lead MSOP, Reel 10-Lead LFCSP, Reel 10-Lead MSOP, Tube 10-Lead MSOP, Reel 10-Lead LFCSP, Reel AD4020 Evaluation Board Compatible with EVAL-SDP-CH1Z Ordering Quantity 50 1000 1500 50 1000 1500 50 1000 1500 Package Option RM-10 RM-10 CP-10-9 RM-10 RM-10 CP-10-9 RM-10 RM-10 CP-10-9 Marking Code C8L C8L C8L CAD CAD CAC CAF CAF CAE Z = RoHS Compliant Part. The EVAL-AD4020FMCZ can evaluate the AD4021 and AD4022 by setting the throughput to 1 MSPS and 500 kSPS in its software, respectively (see the UG-1042). ©2017–2021 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D15369-2/21(C) Rev. C | Page 40 of 40