AD4030-24BBCZ

Data Sheet AD4030-24/AD4032-24 24-Bit, 2 MSPS/500 kSPS, SAR ADCs FEATURES ► FUNCTIONAL BLOCK DIAGRAM High performance Throughput: 2 MSPS (AD4030-24) or 500 kSPS (AD4032-24) options ► INL: ±0.9 ppm maximum from −40°C to +125°C ► SNR: 108.4 dB typical ► THD: −127 dB typical ► NSD: −169 dBFS/Hz typical Low power ► 30 mW at 2 MSPS ► 10 mW at 500 kSPS ► 3 mW at 10 kSPS Easy Drive™ features reduce system complexity ► Low 1.2 μA input current for dc inputs at 2 MSPS ► Wide common-mode input range: −(1/128) × VREF to +(129/128) × VREF Flexible external reference voltage range: 4.096 V to 5 V ► Accurate integrated reference buffer with 2 μF bypass capacitor Programmable block averaging filter with up to 216 decimation ► Extended sample resolution to 30 bits ► Overrange and synchronization bits Flexi-SPI digital interface ► 1, 2, or 4 SDO lanes allows slower SCK ► Echo clock mode simplifies use of digital isolator ► Compatible with 1.2 V to 1.8 V logic 7 mm × 7 mm, 64-Ball CSP_BGA package with internal supply and reference capacitors to help reduce system footprint ► ► ► ► ► ► ► APPLICATIONS ► ► ► ► ► ► Automatic test equipment Digital control loops Medical instrumentation Seismology Semiconductor manufacturing Scientific instrumentation Figure 1. Functional Block Diagram GENERAL DESCRIPTION The AD4030-24/AD4032-24 are 2 MSPS or 500 kSPS successive approximation register (SAR), analog-to-digital converters (ADC) with Easy Drive™. With a guaranteed maximum ±0.9 ppm integral nonlinearity (INL) and no missing codes at 24-bits, the AD4030-24/ AD4032-24 achieve unparalleled precision from −40°C to +125°C. Figure 1 shows the functional architecture of the AD4030-24/ AD4032-24. A low drift, internal precision reference buffer eases voltage reference sharing with other system circuitry. The AD4030-24/ AD4032-24 offer a typical dynamic range of 109 dB when using a 5 V reference. The low noise floor enables signal chains requiring less gain and lower power. A block averaging filter with programmable decimation ratio can increase dynamic range up to 155.5 dB. The wide differential input and common mode ranges allow inputs to use the full ±VREF range without saturating, simplifying signal conditioning requirements and system calibration. The improved settling of the Easy Drive analog inputs broadens the selection of analog front-end components compatible with the AD4030-24/ AD4032-24. Both single-ended and differential signals are supported. The versatile Flexi-SPI serial peripheral interface (SPI) eases host processor and ADC integration. A wide data clocking window, multiple SDO lanes, and optional dual data rate (DDR) data clocking can reduce the serial clock to 10 MHz while operating at a sample rate of 2 MSPS or 500 kSPS. Echo clock mode and ADC host clock mode relax the timing requirements and simplify the use of digital isolators. The 7 mm × 7 mm, 64-Ball CSP_BGA package of the AD4030-24/ AD4032-24 integrates all critical power supply and reference bypass capacitors, reducing the footprint and system component count, and lessening sensitivity to board layout. Rev. A DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Data Sheet AD4030-24/AD4032-24 TABLE OF CONTENTS Features................................................................ 1 Applications........................................................... 1 Functional Block Diagram......................................1 General Description...............................................1 Specifications........................................................ 4 Timing Specifications......................................... 6 Absolute Maximum Ratings.................................12 Thermal Resistance......................................... 12 Electrostatic Discharge (ESD) Ratings.............12 ESD Caution.....................................................12 Pin Configuration and Function Descriptions...... 13 Typical Performance Characteristics................... 15 Terminology......................................................... 20 Integral Nonlinearity Error (INL)....................... 20 Differential Nonlinearity Error (DNL).................20 Zero Error (ZE)................................................. 20 Gain Error (GE)................................................ 20 Spurious-Free Dynamic Range (SFDR)...........20 Effective Number of Bits (ENOB)..................... 20 Total Harmonic Distortion (THD)...................... 20 Dynamic Range (DR)....................................... 20 Signal-to-Noise Ratio (SNR)............................ 20 Signal-to-Noise-and-Distortion (SINAD) Ratio............................................................... 20 Aperture Delay................................................. 20 Transient Response......................................... 20 Common-Mode Rejection Ratio (CMRR)......... 20 Power Supply Rejection Ratio (PSRR)............ 20 Theory of Operation.............................................21 Overview.......................................................... 21 Converter Operation.........................................21 Transfer Function............................................. 22 Analog Features............................................... 22 Digital Sample Processing Features................ 22 Applications Information...................................... 25 Typical Application Diagrams........................... 25 Analog Front-End Design................................. 25 Reference Circuitry Design ............................. 25 Device Reset.................................................... 27 Power Supplies................................................ 27 Serial Interface.................................................... 29 SPI Signals.......................................................29 Sample Conversion Timing and Data Transfer.......................................................... 31 Clocking Modes ...............................................32 Data Clocking Requirements and Timing.........35 Layout Guidelines................................................39 Registers............................................................. 40 Register Details................................................... 41 Interface Configuration A Register................... 41 Interface Configuration B Register................... 41 Device Configuration Register..........................42 Chip Type Register...........................................42 Product ID Low Register.................................. 42 Product ID High Register..................................42 Chip Grade Register.........................................43 Scratch Pad Register....................................... 43 SPI Revision Register...................................... 43 Vendor ID Low Register................................... 44 Vendor ID High Register...................................44 Stream Mode Register..................................... 44 Interface Status A Register.............................. 44 Exit Configuration Mode Register.....................45 Averaging Mode Register.................................45 Offset Registers................................................46 Gain Registers..................................................46 Modes Register................................................ 47 Internal Oscillator Register............................... 47 Output Driver Register......................................48 Test Pattern Registers...................................... 48 Digital Diagnostics Register............................. 49 Digital Errors Register...................................... 49 Outline Dimensions............................................. 50 Ordering Guide.................................................50 Evaluation Boards............................................ 50 REVISION HISTORY 8/2022—Rev. 0 to Rev. A Added AD4032-24........................................................................................................................................... 1 Changes to Features Section, Figure 1, and General Description Section..................................................... 1 Changes to Table 1.......................................................................................................................................... 4 Changes to Table 2.......................................................................................................................................... 6 Change to Table 9..........................................................................................................................................12 Changes to Figure 11.....................................................................................................................................13 Changes to Figure 25 Caption....................................................................................................................... 17 analog.com Rev. A | 2 of 50 Data Sheet AD4030-24/AD4032-24 TABLE OF CONTENTS Added Figure 26; Renumbered Sequentially................................................................................................. 17 Changes to Figure 30 Caption and Figure 35................................................................................................18 Added Figure 31............................................................................................................................................ 18 Added Figure 36............................................................................................................................................ 19 Changes to Overview Section........................................................................................................................21 Changes to Figure 44 and Figure 45............................................................................................................. 25 Changes to Figure 46 and Reference Circuitry Design Section.................................................................... 26 Changes to Figure 50.................................................................................................................................... 29 Changes to Figure 54 and Figure 55............................................................................................................. 33 Changes to Table 23...................................................................................................................................... 43 Changes to Table 28...................................................................................................................................... 44 Changes to Table 29...................................................................................................................................... 45 Changes to Table 38...................................................................................................................................... 48 Updated Outline Dimensions......................................................................................................................... 50 Changes to Ordering Guide........................................................................................................................... 50 4/2022—Revision 0: Initial Version analog.com Rev. A | 3 of 50 Data Sheet AD4030-24/AD4032-24 SPECIFICATIONS VDD_5V = 5.4 V, VDD_1.8V = 1.8 V, VIO = 1.8 V, REFIN = 5 V, input common mode = 2.5 V, fS = 2 MSPS for the AD4030-24 or 500 kSPS for the AD4032-24, and all specifications TMIN to TMAX, unless otherwise noted. Typical values are at TA = 25°C. Table 1. Parameter RESOLUTION ANALOG INPUT Voltage Range Absolute Input Voltage Common-Mode Input Range Common-Mode Rejection Ratio (CMRR) Analog Input Current Analog Input Capacitance THROUGHPUT Complete Cycle AD4030-24 AD4032-24 Conversion Time Acquisition Phase1 AD4030-24 AD4032-24 Throughput Rate AD4030-24 AD4032-24 DC ACCURACY No Missing Codes Integral Nonlinearity Error (INL) Differential Nonlinearity Error (DNL) Transition Noise Zero Error Zero Error Drift Gain Error Gain Error Temperature Drift Power Supply Sensitivity Low Frequency Noise2 AC ACCURACY Dynamic Range Noise Spectral Density (NSD) Total RMS Noise Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Total Harmonic Distortion (THD) Signal-to-Noise-and-Distortion (SINAD) Ratio Oversampled Dynamic Range analog.com Test Conditions/Comments Min Typ Max 24 VIN+ − VIN− VIN+, VIN− to GND (VIN+ + VIN−)/2 fIN = 10 kHz Acquisition phase, T = 25°C Converting any dc input at 2 MSPS Acquisition phase Outside acquisition phase (CPIN) Bits −(65/64) × VREF −(1/128) × VREF −(1/128) × VREF 132 0.8 1.2 120 4 +(65/64) × VREF V +(129/128) × VREF V +(129/128) × VREF V dB nA µA pF pF 500 2000 264 282 300 ns ns ns 244 1744 260 1760 275 1775 ns ns 2 500 MSPS kSPS 0 0 24 −0.9 −90 Buffer disabled, REF = 5 V Buffer enabled, REFIN = 5 V Buffer disabled, REF = 5 V Buffer enabled, REFIN = 5 V VDD_5V = 5.4 V ± 0.1 V VDD_1.8V = 1.8 V ± 5% Bandwidth = 0.1 Hz to 10 Hz fIN = 1 kHz, −0.5 dBFS fIN = 1 kHz, −0.5 dBFS fIN = 1 kHz, −0.5 dBFS fIN = 1 kHz, −0.5 dBFS Averaging = 2 Averaging = 256 Averaging = 65536 Unit −0.004 −0.008 105.6 105.6 ±0.1 ±0.5 21 0 ±0.007 ±0.0002 ±0.0006 ±0.025 ±0.07 ±0.1 ±0.2 1.3 109 −169 12.5 108.4 127 −127 108.3 112 133 155.5 +0.9 +90 +0.004 +0.008 −115 Bits ppm LSB LSB rms μV ppm/°C %FS %FS ppm/°C ppm/°C ppm ppm µV p-p dB dBFS/Hz µV rms dB dB dB dB dB dB dB Rev. A | 4 of 50 Data Sheet AD4030-24/AD4032-24 SPECIFICATIONS Table 1. Parameter SNR SFDR THD SINAD SNR THD SINAD −3 dB Input Bandwidth Aperture Delay Aperture Jitter INTERNAL REFERENCE BUFFER REFIN Voltage Range REFIN Bias Current REFIN Input Capacitance Reference Buffer Offset Error Reference Buffer Offset Drift Power-On Settling Time EXTERNALLY OVERDRIVEN REFERENCE REF Voltage Range REF Current AD4030-24 AD4032-24 REF Input Capacitance DIGITAL INPUTS Logic Levels Input Voltage Low (VIL) Input Voltage High (VIH) Input Current Low (IIL) Input Current High (IIH) Input Pin Capacitance DIGITAL OUTPUTS Pipeline Delay Output Voltage Low (VOL) Output Voltage High (VOH) analog.com Test Conditions/Comments Min VDD_5V = 5.0 V, fIN = 1 kHz, −0.5 dBFS, REFIN = 4.096 V VDD_5V = 5.0 V, fIN = 1 kHz, −0.5 dBFS, REFIN = 4.096 V VDD_5V = 5.0 V, fIN = 1 kHz, −0.5 dBFS, REFIN = 4.096 V VDD_5V = 5.0 V, fIN = 1 kHz, −0.5 dBFS, REFIN = 4.096 V fIN = 100 kHz, −0.5 dBFS fIN = 100 kHz, −0.5 dBFS fIN = 100 kHz, −0.5 dBFS External reference drives REFIN 5.3 V ≤ VDD_5V ≤ 5.5 V 4.8 V ≤ VDD_5V ≤ 5.25 V 4.75 V ≤ VDD_5V ≤ 5.25 V REFIN = 5 V, TA = 25°C REFIN = 4.5 V, TA = 25°C REFIN = 4.096 V, TA = 25°C External reference drives REF (REFIN = 0 V) 5.3 V ≤ VDD_5V ≤ 5.5 V 4.8 V ≤ VDD_5V ≤ 5.25 V 4.75 V ≤ VDD_5V ≤ 5.25 V 4.95 4.046 −50 −100 −100 4.95 4.046 fS = 2 MSPS fS = 500 kSPS Typ Max Unit 106.7 dB 130 dB −130 dB 106.7 dB 108.1 −113 106.9 74 0.7 1.4 dB dB dB MHz ns ps rms 5 4.5 4.096 5 40 ±25 ±25 ±25 ±0.3 3 5 4.5 4.096 5.05 4.146 +50 +100 +100 5.05 4.146 1.8 0.5 2 V V V nA pF µV μV µV µV/°C ms V V V µA µA µF 1.14 V ≤ VIO ≤ 1.89 V −0.3 0.65 × VIO −10 −10 +0.35 × VIO VIO + 0.3 +10 +10 V V µA µA pF 0.25 × VIO V V 2 1.14 V ≤ VIO ≤ 1.89 V ISINK = 2 mA ISOURCE = 2 mA Conversion results available immediately after completed conversion 0.75 × VIO Rev. A | 5 of 50 Data Sheet AD4030-24/AD4032-24 SPECIFICATIONS Table 1. Parameter POWER SUPPLIES VDD_5V VDD_1.8V VIO3 Standby Current VDD_5V VDD_1.8V VIO Shutdown Current VDD_5V VDD_1.8V VIO Operating Current, AD4030-24 VDD_5V VDD_1.8V VIO Operating Current, AD4032-24 VDD_5V VDD_1.8V VIO Power Dissipation tRESET_DELAY tRESET_PW TEMPERATURE RANGE Specified Performance Test Conditions/Comments Min Typ Max Unit REF = 5 V REF = 4.5 V REF = 4.096 V 5.3 4.8 4.75 1.71 1.14 5.4 5 5 1.8 5.5 5.25 5.25 1.89 1.89 V V V V V 2 MSPS VDD_5V = 5.4 V VDD_1.8V = 1.8 V VIO = 1.8 V, 1-lane SDO 500 kSPS VDD_5V = 5.4 V VDD_1.8V = 1.8 V VIO = 1.8 V, 1-lane SDO 2 MSPS 500 kSPS After power-on, delay from VDD_5V and VDD_1.8V valid to RST assertion RST pulse width TMIN to TMAX −40 500 90 1.14 V SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO > 1.71 V VIO > 1.14 V CS Rising Edge to SDO High Impedance SDI Valid Setup Time to SCK Rising Edge SDI Valid Hold Time from SCK Rising Edge CS Falling Edge to First SCK Rising Edge VIO > 1.71 V VIO > 1.14 V Last SCK Edge to CS Rising Edge tCSPW tSCK 10 ns 11.6 12.3 5.2 5.2 2.1 ns ns ns ns ns analog.com tSCKL tSCKH tHSDO tDSDO tCSDIS tSSDI tHSDI tCSSCK tSCKCS Typ Max 9.4 11.8 9 Unit 1.5 1.5 ns ns ns ns ns 11.6 12.3 5.2 ns ns ns Rev. A | 7 of 50 Data Sheet AD4030-24/AD4032-24 SPECIFICATIONS Figure 3. Register Configuration Mode Write Timing Figure 4. Register Configuration Mode Read Timing Figure 5. Register Configuration Mode Command Timing Table 4. SPI-Compatible Mode Timing Parameter Symbol SCK Period VIO > 1.71 V VIO > 1.14 V SCK Low Time VIO > 1.71 V VIO > 1.14 V SCK High Time VIO > 1.71 V VIO > 1.14 V SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO > 1.71 V VIO > 1.14 V tSCK analog.com Min Typ Max Unit 9.8 12.3 ns ns 4.2 5.2 ns ns 4.2 5.2 1.4 ns ns ns tSCKL tSCKH tHSDO tDSDO 5.6 8.1 ns ns Rev. A | 8 of 50 Data Sheet AD4030-24/AD4032-24 SPECIFICATIONS Table 4. SPI-Compatible Mode Timing Parameter Symbol CS Falling Edge to SDO Valid VIO > 1.71 V VIO > 1.14 V CS Falling Edge to First SCK Rising Edge VIO > 1.71 V VIO > 1.14 V Last SCK Edge to CS Rising Edge CS Rising Edge to SDO High Impedance CS Falling Edge to BUSY Rising Edge tCSEN Min Typ Max Unit 6.8 9.3 ns ns ns tCSSCK tSCKCS tCSDIS tCSBUSY 9.8 12.3 4.2 9 6 ns ns ns ns ns Figure 6. SPI Clocking Mode 1-Lane SDR Timing Table 5. Echo Clock Mode Timing, SDR, 1-Lane Parameter Symbol SCK Period VIO > 1.71 V VIO > 1.14 V SCK Low Time, SCK High Time VIO > 1.71 V VIO > 1.14 V SCK Rising Edge to Data/SCKOUT Remains Valid SCK Rising Edge to Data/SCKOUT Valid Delay VIO > 1.71 V VIO > 1.14 V CS Falling Edge to First SCK Rising Edge VIO > 1.71 V VIO > 1.14 V Skew Between Data and SCKOUT Last SCK Edge to CS Rising Edge CS Rising Edge to SDO High Impedance tSCK analog.com Min Typ Max Unit 9.8 12.3 ns ns 4.2 5.2 1.1 ns ns ns tSCKL, tSCKH tHSDO tDSDO 5.6 8.1 ns ns +0.4 ns ns ns ns ns tCSSCK tSKEW tSCKCS tCSDIS 9.8 12.3 −0.4 4.2 0 9 Rev. A | 9 of 50 Data Sheet AD4030-24/AD4032-24 SPECIFICATIONS Figure 7. Echo Clock Mode Timing, SDR, 1-Lane Table 6. Echo Clock Mode Timing, DDR, 1-Lane Parameter Symbol Min SCK Period SCK Low Time, SCK High Time SCK Edge to Data/SCKOUT Remains Valid SCK Edge to Data/SCKOUT Valid Delay VIO > 1.71 V VIO > 1.14 V CS Falling Edge to First SCK Rising Edge Skew Between Data and SCKOUT Last SCK Edge to CS Rising Edge CS Rising Edge to SDO High Impedance tSCK tSCKL, tSCKH tHSDO tDSDO 12.3 5.2 1.1 Typ Max ns ns ns 6.2 8.7 tCSSCK tSKEW tSCKCS tCSDIS 12.3 −0.4 9 Unit 0 +0.4 9 ns ns ns ns ns ns Figure 8. Echo Clock Mode Timing, DDR, 1-Lane analog.com Rev. A | 10 of 50 Data Sheet AD4030-24/AD4032-24 SPECIFICATIONS Table 7. Host Clock Mode Timing Parameter Symbol SCK Period OSC_DIV = No Divide OSC_DIV = Divide by 2 OSC_DIV = Divide by 4 SCK Low Time SCK High Time CS Falling Edge to First SCKOUT Rising Edge VIO > 1.71 V VIO > 1.14 V Skew Between Data and SCKOUT Last SCKOUT Edge to CS Rising Edge CS Rising Edge to SDO High Impedance tSCKOUT tSCKOUTL tSCKOUTH tDSCKOUT tSKEW tSCKOUTCS tCSDIS Min Typ Max Unit 11.8 23.6 47.4 0.45 × tSCKOUT 0.45 × tSCKOUT 12.5 25 50 13.3 26.6 53.2 0.55 × tSCKOUT 0.55 × tSCKOUT ns ns ns ns ns 10 10 −0.4 5.2 13.6 15 0 19 21 +0.4 ns ns ns ns ns 9 Figure 9. Host Clock Mode Timing, SDR, 1-Lane Figure 10. Host Clock Mode Timing, DDR, 1-Lane analog.com Rev. A | 11 of 50 Data Sheet AD4030-24/AD4032-24 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 8. Parameter Analog Inputs IN+, IN−, REFIN to GND Supply Voltage VDD_5V, REF to GND VDD_1.8V, VIO to GND Digital Inputs to GND CNV to GND Digital Outputs to GND Storage Temperature Range Operating Junction Temperature Range Maximum Reflow (Package Body) Temperature Rating −0.3 V to VDD_5V + 0.3 V −0.3 V to +6.0 V −0.3 V to +2.1 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.3 V −55°C to +150°C −40°C to +125°C 260°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Table 9. Thermal Resistance Package Type θJA θJC Unit 05-08-1797 35 16 °C/W ELECTROSTATIC DISCHARGE (ESD) RATINGS The following ESD information is provided for handling of ESD-sensitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Field induced charged device model (FICDM) per ANSI/ESDA/JEDEC JS-002. ESD Ratings for AD4030-24/AD4032-24 Table 10. AD4030-24/AD4032-24, 64-Ball CSP_BGA ESD Model Withstand Threshold (kV) Class HBM FICDM 4 1.25 3A C3 ESD CAUTION ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. analog.com Rev. A | 12 of 50 Data Sheet AD4030-24/AD4032-24 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 11. Pin Configuration Table 11. Pin Function Descriptions Type1 Description A1, A4, A5, B2, B4, B5, C2 to GND C5, D1, D4, D5, E1, E4, E5, F2 to F5, G2, G4, G5, H1, H2, H4 A2 REFIN P Power Supply Ground. AI A3, B3 VDD_5V P A6 CNV DI A7 A8, B8 RST VIO DI P B1 B6, B7, C6, D6, E6, E7, F6, G6, H8 C1 C7 C8 D2, D3, E2, E3 IN+ IOGND AI P Buffered Reference Input. When using the internal reference buffer, drive REFIN with 4.096 V to 5 V (referred to ground). To disable the reference buffer, tie REFIN to ground and drive REF with 4.096 V to 5 V. 5 V Power Supply. The range of VDD_5V depends on the reference value, 5.3 V to 5.5 V for a 5 V reference, and 4.75 V to 5.25 V for a 4.096 V reference. This pin has a 1 μF bypass capacitor inside the package. Convert Input. A rising edge on this input powers up the device and initiates a new conversion. This signal must have low jitter to achieve the specified performance of the ADC. Logic levels are determined by the VIO pin. Reset Input (Active Low). Asynchronous device reset. Input/Output Interface Digital Power. Nominally, this pin is at the same supply as the host interface (1.8 V, 1.5 V, or 1.2 V). This pin has a 0.2 μF bypass capacitor inside the package. For VIO < 1.4 V, Bit IO2X of the output driver register must be set to 1. Positive Analog Input. VIO Ground. Connect to the same ground plane as all GND pins. IN− SDO3 SDO1 REF AI DO DO AI D7 D8 E8 SDO2 SDO0 BUSY_SCKOUT DO DO DO Pin No. analog.com Mnemonic Negative Analog Input. Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. Optional Unbuffered Reference Input. Drive REF with 4.096 V to 5 V (referred to ground). This pin has a 2 μF bypass capacitor inside the package. When using the internal reference buffer, do not connect REF. Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. BUSY Indicator in SPI Clocking Mode. This pin goes high at the start of a new conversion and returns low when the conversion has finished. Logic levels are determined by the VIO pin. When SCKOUT is enabled, this pin function is either an echo of the incoming SCK from the host controller or a clock sourced by the internal oscillator. Rev. A | 13 of 50 Data Sheet AD4030-24/AD4032-24 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 11. Pin Function Descriptions Type1 Pin No. Mnemonic F1 F7, F8, G7, G8 G1 G3, H3 NIC DNC NIC VDD_1.8V P H5 H6 H7 CS SDI SCK DI DI DI 1 Description Not Internally Connected. These pins are not connected internally. Do Not Connect to These Pins. They are internally connected to digital output drivers in high-Z mode. Not Internally Connected. These pins are not connected internally. 1.8 V Power Supply. The range of VDD_1.8V is 1.71 V to 1.89 V. This pin has a 1 μF bypass capacitor inside the package. Chip Select Input (Active Low). Serial Data Input. Serial Data Clock Input. When the device is selected (CS = low), the conversion result is shifted out by this clock. AI is analog input, P is power, DI is digital input, and DO is digital output. analog.com Rev. A | 14 of 50 Data Sheet AD4030-24/AD4032-24 TYPICAL PERFORMANCE CHARACTERISTICS VDD_5V = 5.4 V, VDD_1.8V = 1.8 V, VIO = 1.8V, REFIN = 5 V, input common mode = 2.5 V, fS = 2 MSPS for the AD4030-24 or 500 kSPS for the AD4032-24, and all specifications TMIN to TMAX, unless otherwise noted. Typical values are at TA = 25°C. Figure 12. INL Error vs. Output Code, Differential Input Figure 13. INL Error vs. Output Code, Single-Ended Input Figure 14. Code Histogram for Shorted Inputs analog.com Figure 15. FFT, 2 MSPS, fIN = 1 kHz, VREF = 5 V Figure 16. SNR, SINAD vs. Input Frequency Figure 17. THD vs. Input Frequency, Various Amplitudes Rev. A | 15 of 50 Data Sheet AD4030-24/AD4032-24 TYPICAL PERFORMANCE CHARACTERISTICS Figure 18. SNR, SINAD vs. Input Amplitude, fIN = 1 kHz Figure 21. INL vs. Temperature Figure 19. SNR, SINAD vs. Temperature, fIN = 1 kHz Figure 22. Zero Error and Gain Error vs. Temperature Figure 20. THD vs. Temperature, fIN = 1 kHz Figure 23. Dynamic Range vs. Number of Averages analog.com Rev. A | 16 of 50 Data Sheet AD4030-24/AD4032-24 TYPICAL PERFORMANCE CHARACTERISTICS Figure 24. Low Frequency Noise (Output Data Rate = 19.5 SPS After Averaging Blocks of 2048 Samples) Figure 27. Reference Buffer Offset vs. Temperature Figure 28. Error During Conversion Burst After Long Idle Time Figure 25. Analog Input Current vs. Differential Input Voltage, AD4030-24, 2 MSPS Figure 29. REFIN Current Normal Operation and REFIN Current Shutdown Mode vs. Temperature Figure 26. Analog Input Current vs. Differential Input, AD4032-24, 500 kSPS analog.com Rev. A | 17 of 50 Data Sheet AD4030-24/AD4032-24 TYPICAL PERFORMANCE CHARACTERISTICS Figure 30. REF Current vs. Analog Input, AD4030-24, 2 MSPS Figure 33. REF Current vs. Temperature Figure 31. REF Current vs. Analog Input, AD4032-24, 500 kSPS Figure 34. Supply Current vs. Sample Rate Figure 32. Common-Mode Rejection Ratio (CMRR) vs. Input Frequency Figure 35. Supply Current vs. Temperature, AD4030-24, 2 MSPS analog.com Rev. A | 18 of 50 Data Sheet AD4030-24/AD4032-24 TYPICAL PERFORMANCE CHARACTERISTICS Figure 36. Supply Current vs. Temperature, AD4032-24, 500 kSPS Figure 37. Standby Current vs. Temperature Figure 38. Shutdown Current vs. Temperature analog.com Rev. A | 19 of 50 Data Sheet AD4030-24/AD4032-24 TERMINOLOGY INTEGRAL NONLINEARITY ERROR (INL) INL is the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 40). DIFFERENTIAL NONLINEARITY ERROR (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. ZERO ERROR (ZE) Zero error is the difference between the ideal midscale voltage, 0 V, and the actual voltage producing the midscale output code, 0 LSB. GAIN ERROR (GE) The first transition (from 100 ... 00 to 100 ... 01) occurs at a level ½ LSB above nominal negative full scale. The last transition (from 011 … 10 to 011 … 11) occurs for an analog voltage 1½ LSB below the nominal full scale. The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. SPURIOUS-FREE DYNAMIC RANGE (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of a full-scale input signal and the peak spurious signal. EFFECTIVE NUMBER OF BITS (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD as follows: ENOB = (SINADdB − 1.76)/6.02. ENOB is expressed in bits. TOTAL HARMONIC DISTORTION (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) RATIO SINAD is the ratio of the rms voltage of a full-scale sine wave to the rms sum of all other spectral components that are less than the Nyquist frequency, including harmonics but excluding dc. The value of SINAD is expressed in decibels. APERTURE DELAY Aperture delay is the measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion. TRANSIENT RESPONSE Transient response is the time required for the ADC to acquire a full-scale input step to ±1 LSB accuracy. COMMON-MODE REJECTION RATIO (CMRR) CMRR is the ratio of the power in the ADC output at the frequency, f, to the power of a 4.5 V p-p sine wave applied to the input common-mode voltage of frequency, f. CMRR (dB) = 10× log(PADC_IN/PADC_OUT) where: PADC_IN is the common-mode power at the frequency, f, applied to the inputs. PADC_OUT is the power at the frequency, f, in the ADC output. POWER SUPPLY REJECTION RATIO (PSRR) PSRR is the ratio of the power in the ADC output at the frequency, f, to the power of a 200 mV p-p sine wave applied to the ADC VDD supply of frequency, f. PSRR (dB) = 10 × log(PVDD_IN/PADC_OUT) where: PVDD_IN is the power at the frequency, f, at the VDD pin. PADC_OUT is the power at the frequency, f, in the ADC output. DYNAMIC RANGE (DR) Dynamic range is the rms voltage of a full-scale sine wave to the total rms voltage of the noise measured. The value for dynamic range is expressed in decibels. It is measured with a signal at −60 dBFS so that it includes all noise sources and DNL artifacts. SIGNAL-TO-NOISE RATIO (SNR) SNR is the ratio of the rms voltage of a full-scale sine wave to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. analog.com Rev. A | 20 of 50 Data Sheet AD4030-24/AD4032-24 THEORY OF OPERATION Figure 39 shows the basic functions of the AD4030-24/AD4032-24 . Figure 39. AD4030-24/AD4032-24 Functional Block Diagram and Signal Processing Architecture OVERVIEW The AD4030-24/AD4032-24 are low noise, low power, high speed, 24-bit successive approximation register (SAR) ADCs. The AD4030-24 is capable of converting 2,000,000 samples per second (2 MSPS), and the AD4032-24 is capable of converting 500,000 samples per second (500 kSPS). It offers several analog and digital features to ease system design. The analog features include a wide common-mode range that eases level shifting requirements as well as an extended fully differential input range of ±(65/64) × VREF, easing the margin requirements on signal conditioning. The AD4030-24/AD4032-24 have an integrated reference buffer with an integrated decoupling capacitor to minimize the external components on board. The on-chip track-and-hold circuitry does not exhibit any pipeline delay or latency, making this circuitry ideal for control loops and high speed applications. The digital features include offset correction, gain adjustment, and averaging, which offload the host processor. The user can configure the device for analog.com one of several output code formats (see the Summary of Selectable Output Data Formats section). The AD4030-24/AD4032-24 use a Flexi-SPI, allowing the data to be accessed via multiple SPI lanes, which relaxes clocking requirements for the host SPI controller. An echo clock mode is also available to assist in data clocking, simplifying the use of isolated data interfaces. The AD4030-24/AD4032-24 has a valid first conversion after exiting power-down mode. The architecture achieves ±0.9 ppm INL maximum, with no missing codes at 24 bits and 108.4 dB SNR. The AD4030-24 dissipates only 30 mW at 2 MSPS. CONVERTER OPERATION The AD4030-24/AD4032-24 operate in two phases, acquisition phase and conversion phase. In the acquisition phase, the internal track-and-hold circuitry is connected to each input pin (IN+, IN−) and samples the voltage on each pin independently. Issuing a Rev. A | 21 of 50 Data Sheet AD4030-24/AD4032-24 THEORY OF OPERATION rising edge pulse on the CNV pin initiates a conversion. The rising edge pulse on the CNV pin also asserts the BUSY signal to indicate a conversion in progress. At the end of the conversion, the BUSY signal is deasserted. The conversion result is a 24-bit code representing the input voltage difference and an 8-bit code representing the input common-mode voltage. Depending on the device configuration, this conversion result can be processed digitally and latched into the internal output register. The acquisition circuit on each input pin is also precharged to the previous sample voltage, which minimizes the kick-back charge to the input driver. The host processor retrieves the output code via the SDO pins that are internally connected to the internal output register. TRANSFER FUNCTION In the default configuration, the AD4030-24/AD4032-24 digitizes the full-scale difference voltage of 2 × VREF into 224 levels, resulting in an LSB size of 0.596 µV with VREF = 5 V. Note that 1 LSB at 24 bits is approximately 0.06 ppm. The ideal transfer function is shown in Figure 40. The differential output data is in twos complement format. Table 12 summarizes the mapping of input voltages to differential output codes. analog input of the AD4030-24/AD4032-24 easier to drive than other conventional SAR ADCs. The reduced kickback, combined with a longer acquisition phase, means reduced settling requirements on the driving amplifier. This combination also allows the use of larger resistor values, which are beneficial for improving amplifier stability. Furthermore, the bandwidth of the RC filter is reduced, resulting in lower noise and/or power consumption of the signal chain. The common-mode voltage is not restricted except by the absolute voltage range for each input (from −1/128 × VREF to 129/128 × VREF). The analog inputs can be modeled by the equivalent circuit shown in Figure 41. In the acquisition phase, each input pin has approximately 116 pF input capacitance (CIN) from the sampling capacitor in series with 19 Ω on resistance (RON) of the sampling switch. During conversion phase, each input has the capacitance of the input pin (CPIN), which is about 4 pF. Any signal that is common to both inputs is reduced by the common-mode rejection of the ADC. During conversion, the analog inputs draw only a small leakage current. Figure 41. Equivalent Circuit for the AD4030-24/AD4032-24 Differential Analog Input Figure 40. ADC Ideal Transfer Function for the Differential Output Codes (FSR Is Full-Scale Range) Table 12. Input Voltage to Output Code Mapping Description Analog Input Voltage Difference Digital Output Code (Twos Complement, Hex) FSR − 1LSB Midscale + 1LSB Midscale Midscale − 1LSB −FSR + 1LSB −FSR (8388607 × VREF)/(8388608) VREF/(8388608) 0V −VREF/(8388608) −(8388607 × VREF)/(8388608) − VREF 0x7FFFFF 0x000001 0x000000 0xFFFFFF 0x800001 0x800000 ANALOG FEATURES The AD4030-24/AD4032-24 has a precharging circuit as part of the internal track-and-hold circuitry, which charges the internal sampling capacitors to the previously sampled input voltage. This reduces the charge kickback, making the precharge circuit on the analog.com Each input is sampled independently. The conversion results do not saturate assuming each of the inputs are within the specified full-scale input range. Note that digital domain saturation occurs if the digital offset and digital gain parameters are configured to map the conversion result to numeral values that exceed the full-scale digital range (−223 to +223− 1 for the 24-bit word). An input voltage difference up to ±(65/64) × VREF can be captured and converted without saturation by setting the digital gain parameter to a value < 1. The slew rate at the analog input pins must be less than 400 V/µs during the acquisition phase and less than 30 V/µs at the sampling moment to ensure good performance. This can be ensured by choosing values for the external RC circuit that allow the RC time-constant to be more than 12.5 ns (R × C > 12.5e-9). DIGITAL SAMPLE PROCESSING FEATURES The AD4030-24/AD4032-24 supports several digital and data processing features that can be applied to the signal samples. These features are enabled and disabled via the control registers of the AD4030-24/AD4032-24. Figure 39 contains a signal processing architecture block diagram showing the available digital and data processing features. Rev. A | 22 of 50 Data Sheet AD4030-24/AD4032-24 THEORY OF OPERATION Full-Scale Saturation The conversion results saturate digitally (before any post-processing) when either or both inputs exceed the analog limits specified herein. After applying offset and gain scaling, the results are truncated to 24-bit representation (saturating at maximum 0x7FFFFF and minimum 0x800000). Care must be taken to avoid unintentional saturation, especially when applying digital offset and/or gain scaling. See the Digital Offset Adjust and Digital Gain sections for more details on the use of these features. Common-Mode Output When the host controller writes 0x1 or 0x2 to the OUT_DATA_MD bit field of the modes register (see the Modes Register section), an 8-bit code representing the input common-mode voltage is appended to the 16-bit or 24-bit code representing the input voltage difference. The LSB size of the 8-bit code is VREF/256. The 8-bit code saturates at 0 and 255 when the common mode input voltage is 0 V and VREF, respectively. The 8-bit code is not affected by digital offset and gain scaling, which is applied only to the code representing the input voltage difference. Block Averaging The AD4030-24/AD4032-24 provide a block averaging filter (SINC1) with programmable block length 2N, N = 1, 2, 3, …, 16. The filter is reset after processing each block of 2N samples. The filter is enabled by writing 0x3 to the OUT_DATA_MD bit field of the modes register (see the Modes Register section) as well as a value (1 ≤ N ≤ 16) to the AVG_VAL bit field in the averaging mode register (see the Averaging Mode Register section). In this configuration, the output sample word is 32 bits. The 30 most significant bits (MSBs) represent the numerical value of the 24-bit codes averaged in blocks of 2N samples. The automatic scaling allows the 24 MSBs of the 30-bit code are equal to the 24-bit codes when averaging blocks of constant values. The 31st bit (OR) is an overrange warning bit that is high when one or more samples in the block are subject to saturation. The 32nd bit (SYNC) is high once every 2N conversion cycles to indicate when the average values are updated at the end of each block of samples. See the Digital Sample Processing Features section for more information. The effective data rate in averaging mode is fCNV/2N. The reset value of N in the AVG_VAL bit field is 0x00 (no averaging). Figure 57 shows an example timing diagram in averaging mode. Figure 42 shows the frequency response of the filter for an N = 1, 2, 3, 4, 5. analog.com Figure 42. Frequency Response Examples for the Block Averaging Filter Digital Offset Adjust The ADC can be programmed to add a 24-bit signed offset value to the sample data (see the Register Details section). When adding an offset to the samples, it is possible to cause the sample data to saturate numerically. The user must take this into account when using the offset feature. The default value is 0x000000. See the Offset Registers section for more details. Digital Gain The ADC can be programmed to apply a 16-bit unsigned digital gain (Register 0x1C and Register 0x1D) to the digital samples (see the Register Details section). The gain is applied to each sample based on the following equation: CodeOUT = CodeIN × (USER_GAIN/0x8000) where: 0x0000 ≤ USER_GAIN ≤ 0xFFFF. The effective gain range is 0 to 1.99997. Note that applying gain to the samples may cause numerical saturation. The default value is 0x8000 (gain = 1). To measure input voltage differences exceeding ±VREF, set the gain less than the unity to avoid the numerical saturation of the 24-bit, 16-bit, or 30-bit output differential codes. See the Gain Registers section for more details. Test Pattern To facilitate functional testing and debugging of the SPI, the host controller can write a 32-bit test pattern to the AD4030-24/ AD4032-24 (see the Test Pattern Registers section). The value written to the test pattern registers is output using the normal sample cycle timing. The 32-bit test pattern output mode is enabled by writing 0x4 to the OUT_DATA_MD bit field of the modes register (see the Modes Register section). The default value stored in the test pattern registers is 0x5A5A0F0F. Rev. A | 23 of 50 Data Sheet AD4030-24/AD4032-24 THEORY OF OPERATION Summary of Selectable Output Data Formats Figure 43 summarizes the output data formats that are available on the AD4030-24/AD4032-24, which are selected in the modes register (see the Modes Register section). Note that the OR and SYNC flags are each 1-bit. Figure 43. Summary of Selectable Output Sample Formats analog.com Rev. A | 24 of 50 Data Sheet AD4030-24/AD4032-24 APPLICATIONS INFORMATION TYPICAL APPLICATION DIAGRAMS Figure 44. Differential Driver Analog Front End Figure 45. Unity Gain Dual Buffer Configuration ANALOG FRONT-END DESIGN Driver Amplifier Choice Figure 44 shows two examples for driving the AD4030-24/ AD4032-24. Either can be combined with an upstream stage that provides additional signal conditioning. Both can accommodate single-ended or differential inputs. To take advantage of the SNR and THD performance of the AD4030-24/AD4032-24, it is important to choose a driver amplifier that has low enough noise and THD sufficient to meet the application requirements. In addition to the amplifiers shown in Figure 44, the LTC6227 is another driver option. Analog Devices offers several companion driver amplifiers that can be found on the ADC drivers web page. analog.com REFERENCE CIRCUITRY DESIGN The AD4030-24/AD4032-24 require an external reference to define its input range. This reference must be 4.096 V to 5 V. An optimal choice for the reference is the ADR4550 or ADR4540. These ADCs have several features that reduce the charge pulled from the reference, making the AD4030-24/AD4032-24 much easier to use than other ADCs. For most applications, the reference can drive the REFIN pin, which has an internal precision buffer that isolates the reference from the ADC circuitry. The buffer has a high input impedance and small input current (5 nA typical) that allows multiple ADCs to share a common reference. An RC circuit between the reference and the REFIN pin can be used to filter Rev. A | 25 of 50 Data Sheet AD4030-24/AD4032-24 APPLICATIONS INFORMATION reference noise (see Figure 46). Suggested values are 100 Ω < R < 1 kΩ, and C ≥ 10 μF. Figure 46. Reference with Noise Filter For the best possible gain error, the internal buffer can be disabled (REFIN = 0 V) and an external reference can be used to drive the REF pins. The current drawn by the REF pins is small ( 1.71 V, and 81 MHz for 1.14 V ≤ the VIO pins < 1.71 V. ► SDO0 through SDO3 (outputs). Data lanes to the host controller. The number of active data lanes can be either 1, 2, or 4 lanes (see Table 14). The number of data lanes is configured in the Modes Register section. ► BUSY_SCKOUT (output). The behavior of the BUSY_SCKOUT pin is dependent on the selected clocking mode. Table 13 defines the behavior of the BUSY_SCKOUT pin for each clocking mode. ► Table 13. BUSY_SCKOUT Pin Behavior vs. Clocking Mode Clocking Mode Behavior SPI Clocking Mode Valid BUSY_SCKOUT pin signal for the ADC conversion status. The busy signal on the BUSY_SCKOUT pin goes high when a conversion is triggered by the CNV signal. The busy signal on the BUSY_SCKOUT pin goes low when the conversion is complete. Bit clock. The BUSY_SCKOUT pin is a delayed version of SCK input. Bit clock. The BUSY_SCKOUT pin sources the clock signal from the internal oscillator. Echo Clock Mode Host Clock Mode Register Access Mode Figure 50. AD4030-24/AD4032-24 Multilane SPI SPI SIGNALS The SPI is a multilane interface that is used to both configure the ADC as well as retrieve sampled data. It consists of the following signals: CS (input) (chip select). CS must be set to low to initiate and enable a data transfer to or from the SDI pins or SDOx pins of the ADC. CS timing for reading sample data can be moderated by observing the state of the BUSY pin. For echo clock mode and host clock mode, CS timing must be controlled by the host processor because the BUSY_SCKOUT pin is used as the bit clock output for these clocking modes. ► SDI (input). Serial data input stream from the host controller to the ADC. The SDI signal is only used when writing data into one of the user registers of the AD4030-24/AD4032-24. ► CNV (input). The CNV signal is sourced by the host controller and initiates a sample conversion. The frequency of the CNV signal determines the sampling rate of the AD4030-24/AD4032-24. The maximum frequency of the CNV clock is 2 MSPS. ► analog.com The AD4030-24/AD4032-24 offer programmable user registers that are used to configure the device as outlined in the Registers section. By default, at power-up, the device is in conversion mode. Therefore, to access the user registers, a special access command must be sent by the host controller over the SPI, as shown in Figure 5. When this register access command is sent over the SPI, the device enters the register configuration mode. To read back the values from one of the user registers listed in the Registers section, the host controller must send the pattern shown in Figure 4. To write to one of the user registers, the host controller must send the pattern shown in Figure 3. In either case (read/write), the host controller must always issue 24 clock pulses on SCK line and pull CS low for the entire transaction. After writing to/reading from the appropriate user registers, the host controller must exit the register configuration mode by writing 0x01 to register address 0x0014 as detailed in the EXIT configuration mode register. An algorithm for register read/write access is as follows: 1. Perform a read back from a dummy register address 0x3FFF, to enter the register configuration mode. 2. Read back from or write to the desired user register addresses. 3. Exit the register configuration mode by writing 0x01 to register address 0x0014. Exiting register configuration mode causes the register updates to take effect. Rev. A | 29 of 50 Data Sheet AD4030-24/AD4032-24 SERIAL INTERFACE Stream Mode The AD4030-24/AD4032-24 also offer a way to perform bulk register read/write transactions, while the AD4030-24/AD4032-24 is in register configuration mode. To perform bulk read/write registers transactions, CS must be kept low and SCK pulses must be issued in multiples of 8 as each register is only one byte (8 bits) wide. In stream mode, only address decrementing is allowed, meaning that the user can read back from/write to the initial register address and register addresses that are directly below the initial register address. It is recommended that register accesses in stream mode be applied to register blocks with contiguous addresses. However, it is possible to address registers that are not present in the register map. To do so, simply write all zeros to these registers, or, when reading back, simply discard the contents read from these registers, since it is random data. See the Registers section to see which register address is valid and continuous. For example, to read back a 24-bit offset value in one shot, the user must issue 24 SCK pulses starting from Register Address 0x0018. Figure 51 shows timing diagram for bulk read starting at a given address. Figure 51. Stream Mode Bulk Register Read Back Operation analog.com Rev. A | 30 of 50 Data Sheet AD4030-24/AD4032-24 SERIAL INTERFACE SAMPLE CONVERSION TIMING AND DATA TRANSFER A conversion is started on the rising edge of the CNV signal, as shown in Figure 52. Once the conversion is complete, CS can be asserted, which causes the current conversion result to be loaded into the output shift register. Referring to Figure 52, there are two optional data transfer zones for sample N. Zone 1 represents the use case where CS is asserted immediately following the de-assertion of BUSY signal for the sample N conversion (in SPI conversion mode), or after 300 ns for echo and host clock modes. For Zone 1, the available time to read out sample N is given by the following: Zone 1 Data Read Window = tCYC – tCONV – tQUIET_CNV_ADV For example, if fCNV is 2 MSPS (tCYC = 500 ns) and using the typical value of tCONV (282 ns), the available window width is 198.4 ns (= 500 ns – 282 ns – 19.6 ns). Zone 2 represents the case where assertion of CS to read Sample N is delayed until after the conversion for Sample N + 1 is initiated. To prevent data corruption, a quiet zone must be observed before and after each rising edge of the CNV signal, as shown in Figure 52. The quiet zone immediately before the rising edge of CNV is tQUIET_CNV_ADV and is equal to 19.6 ns. The quiet zone immediately after the rising edge of CNV is tQUIET_CNV_DELAY and is equal to 9.8 ns. Assuming that the CS is asserted immediately after the quiet zone around the rising edge of CNV, the amount of time available to clock out the data is the following: Zone 2 Data Read Window = tCYC – tQUIET_CNV_DELAY – tQUIET_CNV_ADV For example, if fCNV is 2 MSPS (tCYC = 500 ns) and using the typical value of tCONV (282 ns), the available window width is 470.6 ns (= 500 ns – 9.8 ns – 19.6 ns). The Zone 2 transfer window is longer than the Zone 1 window, which can enable the use of a slower SCK on the SPI and ease the timing requirements for the interface. When using Zone 2 for the data transfer, it is recommended to assert CS immediately after the quiet zone. However, Zone 2 must be asserted at least 25 ns before the falling edge of BUSY for Sample N + 1. If not, Sample N is overwritten with Sample N + 1. Figure 52. Example Timing for Data Transfer Zones analog.com Rev. A | 31 of 50 Data Sheet AD4030-24/AD4032-24 SERIAL INTERFACE CLOCKING MODES This section covers the various clocking modes supported by the AD4030-24/AD4032-24 SPI. These modes are available for 1-lane, 2-lanes, and 4-lanes. The clocking mode is configured in the modes register (see Table 16 for register descriptions). SPI Clocking Mode SPI clocking mode is the default clocking mode of the AD4030-24/ AD4032-24 and is equivalent to a host-sourced bit clock (SCK), in which the host controller uses its own clock to latch the output data. The SPI-compatible clocking mode is enabled by writing 0x0 to the CLK_MD bit field of the modes register (see the Modes Register section). The interface connection is as shown in Figure 50. In this mode, the BUSY_SCKOUT pin signal is valid and indicates the completion of a conversion (high to low transition of the BUSY_SCKOUT pin). A simplified sample cycle is shown in Figure 53. When not in averaging mode, if the host controller does not use the BUSY_SCKOUT pin signal to detect the completion of a conversion and instead uses an internal timer to retrieve the data, the host controller must wait at least 300 ns after the rising edge of the CNV pulse before asserting CS low. When operating in block averaging mode, the host controller must assert CS low no sooner than 300 ns after the rising edge of the CNV pulse for the last sample in the block. Figure 53. Typical Sample Cycle for SPI Clocking Mode analog.com Rev. A | 32 of 50 Data Sheet AD4030-24/AD4032-24 SERIAL INTERFACE Echo Clock Mode Figure 54 shows the signal connections for the echo clock mode. The echo clock mode is enabled by writing 0x1 to the CLK_MD bit field of the modes register (see the Modes Register section). In this mode, the BUSY_SCKOUT pin cannot be used to detect a conversion completion. The BUSY_SCKOUT pin becomes a bit clock output and is sourced by looping through the SCK of the host controller to the BUSY_SCKOUT pin (with some fixed delay, 5.4 ns to 7.9 ns, depending on the voltage of the VIO pins). To begin retrieving the conversion data in nonaveraging mode, the host controller must assert CS low no sooner than 300 ns after the rising edge of the CNV pulse. When the ADC is configured for block averaging mode, the host controller must assert CS low no sooner than 300 ns after the rising edge of the CNV pulse for the last sample in the block. Example timing diagrams are shown in the Data Clocking Requirements and Timing section. When echo clock mode is enabled, the BUSY_SCKOUT pin is aligned with the SDOx pins transitions, making the data and clock timing insensitive to asymmetric propagation delays in the paths of the SDOx pins and SCK pins. the rising edge of the CNV pulse. When the ADC is configured in averaging mode for 2N averages, the host must not assert CS low sooner than 300 ns after the rising edge of the CNV pulse for the last sample in the block. Figure 55. Host Clock Mode Signal Path Example Single Data Rate Single data rate clocking (SDR), in which one bit (per active lane) is clocked out during a single clock cycle, is supported for all output configurations and sample formats (see Table 14). The SDR clocking mode is enabled by default at power-up or can be enabled by writing 0 to the DDR_MD bit of the modes register (see the Modes Register section). Dual Data Rate Dual data rate (DDR) mode (two data bit transitions per clock cycle per active lane) is available only for host clock mode and echo clock mode. Figure 54. Echo Clock Mode Signal Path Diagram The DDR clocking mode is enabled by writing 1 to the DDR_MD bit of the modes register (see the Modes Register section). The DDR mode uses half the number of SCK pulses to clock out conversion data in comparison to SDR mode. Host Clock Mode 1-Lane Output Data Clocking Mode When enabled, host clock mode uses the internal oscillator as the bit clock source. The host clock mode is enabled by writing 0x2 to the CLK_MD bit field of the modes register. The bit clock frequency can be programmed in the OSC_DIV bit field in the internal oscillator register, with available divisor values of 1, 2, or 4 (see the Internal Oscillator Register section). Figure 55 shows the signal connections for the host clock mode. In this mode, the BUSY_SCKOUT pin provides the bit clock output and cannot be used to detect a conversion completion. The AD4030-24/AD4032-24 automatically calculate the number of clock pulses required to clock out the conversion data based on word size, number of active lanes, and choice of single data rate mode or dual data rate mode. The number of clock pulses can be read from the OSC_LIMIT bit field of the internal oscillator register. The SCK_IN from the host must not be active. When retrieving the conversion data in nonaveraging mode, the host must not assert CS low sooner than 300 ns after 1-lane is the default output data clocking mode at power-up. The 1-lane output data clocking mode is enabled by writing 0x0 to the LANE_MD bit of the modes register (see the Modes Register section). The active lane is SDO0. Example timing diagrams for 1-lane mode using SPI clocking mode, echo clock mode, and host clock mode are in the Data Clocking Requirements and Timing section. analog.com 2-Lane Output Data Clocking Mode When 2-lane output data clocking mode is enabled, the sample word bits are split between two SDO lanes. Figure 58 shows how the bits are allocated between the lanes for 2-lane mode. The bit arrangement is the same for SPI clock mode, echo clock mode, and host clock mode. 2-lane output data clocking mode is enabled by writing 0x1 to the LANE_MD bit of the modes register (see Rev. A | 33 of 50 Data Sheet AD4030-24/AD4032-24 SERIAL INTERFACE the Modes Register section). The host controller must recombine the data coming from the SDO lanes to reconstruct the original sample word. The number of SCK pulses required to clock out the conversion data is reduced by one-half with respect to the 1-lane mode. Table 14 lists the active SDO lanes for 2-lane mode. Example timing diagrams for 2-lane mode using SPI clock mode, echo clock mode, and host clock mode are in the Data Clocking Requirements and Timing section. 4-Lane Output Data Clocking Mode When 4-lane output data clocking mode is enabled, the sample word bits are split between four SDO lanes. Figure 59 shows how the bits are allocated between the lanes for 4-lane mode. The bit arrangement is the same for SPI clock mode, echo clock mode, and host clock mode. 4-lane output data clocking mode is enabled by writing 0x2 to the LANE_MD bit of the modes register (see the Modes Register section). The host controller must recombine the data coming from the SDO lanes to reconstruct the original sample word. The number of SCK pulses required to clock out the conversion data is reduced by one-fourth with respect to the 1-lane output data clocking. The active SDO lanes for 4-lane mode are shown in Table 14. Example timing diagrams for 4-lane mode using SPI clock mode, echo clock mode, and host clock mode are in the Data Clocking Requirements and Timing section. Data Output Modes Summary Table 14 is a summary of the supported data output modes of the AD4030-24/AD4032-24. Table 14. AD4030-24/AD4032-24 Supported Data Output Modes Number of Lanes Active SDO Lanes Clock Mode Supported Data Clocking Mode Output Sample Data-Word Length 1 SDO0 2 SDO0, SDO1 4 SDO0, SDO1, SDO2, SDO3 SPI Echo Host SPI Echo Host SPI Echo Host SDR only SDR and DDR SDR and DDR SDR only SDR and DDR SDR and DDR SDR only SDR and DDR SDR and DDR 24 or 32 24 or 32 24 or 32 24 or 32 24 or 32 24 or 32 24 or 32 24 or 32 24 or 32 analog.com Rev. A | 34 of 50 Data Sheet AD4030-24/AD4032-24 SERIAL INTERFACE DATA CLOCKING REQUIREMENTS AND TIMING Basic and Averaging Conversion Cycles Figure 56 shows the basic conversion cycle for a single sample. This cycle applies to SPI clocking mode. When using echo clock mode and host clock mode, the BUSY_SCKOUT pin function is disabled and the bit clock is sourced on the BUSY_SCKOUT pin. The data transfer must meet the requirements described in the Sample Conversion Timing and Data Transfer section. Table 15 contains the minimum and maximum values for the conversion timing parameters, which apply to all clocking modes. Table 15. Conversion Cycle Timing Parameters Parameter Min Max tCNVH tCNVL tCONV 10 ns 20 ns 264 ns No specific maximum No specific maximum 300 ns The duration of the data transfer period is dependent on the sample resolution, number of active lanes, SCK frequency, and data clocking mode (SDR or DDR). The nominal value of the transfer duration is given by Data   Transfer   Duration = tTRANS = × 1 fSCK × 1 K   seconds NBITS MLANES where: NBITS = number of bits to clock out MLANES = number of lanes used to clock out the data (1, 2, or 4) fSCK = SCK clock frequency, in Hz K = 1 (SDR only, DDR not available for SPI mode clocking) For a given fSCK, number of data lanes, sample word size, and SDR/DDR mode, the minimum sample period when using Zone 1 for the data transfer is as follows: Minimum Zone 1 Sample Period: tCYC ≥ NBITS MLANES × fSCK × K + tCONV + tQUIET_CNV_ADV The minimum sample period when using Zone 2 for data transfer is as follows:   tCYC ≥ NBITS MLANES × fSCK × K + tQUIET_CNV_ADV + tQUIET_CNV_DELAY Figure 57 shows a typical conversion cycle when the averaging mode is active and SPI clocking mode is being used. The BUSY signal is asserted for a number of CNV clock periods that are equal to the configured number of samples to be averaged. The averaged sample is available when the BUSY signal is deasserted. Like nonaveraged mode, if the configured clocking mode is either echo clock or host clock, the BUSY signal is replaced by the output bit clock (SCKOUT). The host controller must manage the timing for asserting CS. Figure 56. Basic Single Sample Conversion Cycle Figure 57. Example Conversion Cycle for Averaging Mode analog.com Rev. A | 35 of 50 Data Sheet AD4030-24/AD4032-24 SERIAL INTERFACE SPI Clocking Mode Timing Diagrams 1-Lane, SDR Mode Figure 6 shows a conversion cycle for single lane data output, SDR mode (1-bit per clock cycle). 2-Lane, SDR Mode Figure 58 shows a conversion cycle for 2-lane data output using SDR clocking mode. See the 2-Lane Output Data Clocking Mode section for more information. Figure 58. 2-Lane Mode, SDR Timing Diagram analog.com Rev. A | 36 of 50 Data Sheet AD4030-24/AD4032-24 SERIAL INTERFACE 4-Lane, SDR Mode Figure 59 shows a conversion cycle for 4-lane data output using SDR clocking mode. See the 4-Lane Output Data Clocking Mode section for more information. Figure 59. 4-Lane, SDR Timing Diagram analog.com Rev. A | 37 of 50 Data Sheet AD4030-24/AD4032-24 SERIAL INTERFACE Echo Clock Timing Diagrams Host Clock Mode Timing 1-Lane, SDR Mode, Echo Clock Mode 1-Lane, Host Clock Mode, SDR Figure 7 shows the timing relationships for SDR mode (1-bit per SCK period) in 1-lane echo clock mode. The timing relationships between the signals apply to both 24-bit and 32-bit sample word formats. Figure 9 shows the timing relationships for host clock mode when using SDR mode and 1-lane mode. Similar to echo clock mode, the clock rising edges are aligned to the data bit transitions. The frequency of SCKOUT signal is controlled by the OSC_DIV value programmed in the internal oscillator register (see the Internal Oscillator Register section). SCKOUT is a delayed version of the incoming SCK. The delay (tDSDO) has a maximum value of 5.6 ns (at VIO > 1.71 V). Changes in SDOx logic states are aligned to the rising edges of SCKOUT. The clock and data edge alignments are the same for 1-lane, 2-lane, and 4-lane output data modes. 1-Lane, DDR Mode, Echo Clock Mode Figure 8 shows the timing relationships for DDR mode (2-bit transitions per SCKOUT period) in 1-lane mode echo clock mode. The timing relationships between the signals apply to both 24-bit and 32-bit sample word formats. 1-Lane, Host Clock Mode, DDR Figure 10 shows the timing relationships for host clock mode when using DDR. Similar to echo clock mode, the rising and falling clock edges are aligned to the data bit transitions. The frequency of SCKOUT signal is controlled by the OSC_DIV value programmed in the internal oscillator register (see the Internal Oscillator Register section). Similar to SDR mode, SCKOUT is a delayed version of the incoming SCK. Changes in SDOx logic states are aligned to both rising and falling edges of SCKOUT. analog.com Rev. A | 38 of 50 Data Sheet AD4030-24/AD4032-24 LAYOUT GUIDELINES The following layout guidelines are recommended to achieve maximum performance of the AD4030-24/AD4032-24: The AD4030-24/AD4032-24 contain internal 1 μF bypass capacitors for VDD_5V and VDD_1.8V, and VIO contains an internal 0.2 μF capacitor. Therefore, no external bypass capacitors are required, which saves on board space, bill of materials count, and reduces layout sensitivity. ► It is recommended to have all the analog signals flow in from the left side of the AD4030-24/AD4032-24 and all the digital signals to flow in and out from the right side of the AD4030-24/ AD4032-24 because this helps isolate analog signals from digital signals. ► Use a solid ground plane under the AD4030-24/AD4032-24 and connect all the analog ground (GND) pins and digital ground (IOGND) pins to the shared ground plane to avoid formation of ground loops. ► Traces routed to either the REFIN pin or REF pins must be isolated and shielded from other signals. Avoid routing signals beneath the reference trace (REFIN or REF). The REF pins are connected to an internal 2 µF capacitor, eliminating the need to place a decoupling capacitor on the output of the external reference buffer. If a noise reduction filter is placed between the output of the reference (or buffer) and the chosen reference input, it must be placed as close as possible to the AD4030-24/ AD4032-24. ► analog.com Rev. A | 39 of 50 Data Sheet AD4030-24/AD4032-24 REGISTERS The AD4030-24/AD4032-24 have programmable user registers that are used to configure the device. These registers can be accessed while the AD4030-24/AD4032-24 is in register configuration mode. Table 16 contains the complete list of the AD4030-24/AD4032-24 user registers and bit fields in the registers. The Register Details section contains details about the functions of each of the bit fields. The access mode specifies whether the register is comprised only of read-only bits (R) or a mix of read-only and read/write bits (R/W). Read-only bits cannot be overwritten by an SPI write transaction, but read/write bits can. Table 16. AD4030-24/AD4032-24 Register Summary Reg Name Bits Bit 7 Bit 6 Bit 5 0x00 INTERFACE_CONFIG _A INTERFACE_CONFIG _B DEVICE_CONFIG [7:0] SW_RESET RESERVED [7:0] SINGLE_INST STALLING ADDR_ASC SDO_EN ENSION ABLE RESERVED 0x03 0x04 0x05 0x06 0x0A 0x0B 0x0C 0x0D 0x0E 0x11 CHIP_TYPE PRODUCT_ID_L PRODUCT_ID_H CHIP_GRADE SCRATCH_PAD SPI_REVISION VENDOR_L VENDOR_H STREAM_MODE INTERFACE_STATUS _A [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] 0x14 EXIT_CFG_MD [7:0] 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x34 AVG OFFSET_LB OFFSET_MB OFFSET_HB UNUSED1_LB UNUSED1_MB UNUSED1_HB GAIN_LB GAIN_HB UNUSED2_LB UNUSED2_HB MODES OSCILLATOR IO TEST_PAT_BYTE0 TEST_PAT_BYTE1 TEST_PAT_BYTE2 TEST_PAT_BYTE3 DIG_DIAG [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] 0x35 DIG_ERR [7:0] 0x01 0x02 analog.com [7:0] Reset R/W 0x10 R/W 0x00 R/W OPERATING_MO 0x00 DES RESERVED CHIP_TYPE 0x07 PRODUCT_ID[7:0] 0x00 PRODUCT_ID[15:8] 0x20 GRADE DEVICE_REVISION 0x00 SCRATCH_VALUE 0x00 SPI_TYPE VERSION 0x81 VID[7:0] 0x56 VID[15:8] 0x04 LOOP_COUNT 0x00 RESERVED CLOCK_C RESERVED 0x00 OUNT_ER R RESERVED EXIT_CO 0x00 NFIG_MD AVG_SYNC RESERVED AVG_VAL 0x00 USER_OFFSET[7:0] 0x00 USER_OFFSET[15:8] 0x00 USER_OFFSET[23:16] 0x00 UNUSED1[7:0] 0x00 UNUSED1[15:8] 0x00 UNUSED1[23:16] 0x00 USER_GAIN[7:0] 0x00 USER_GAIN[15:8] 0x80 UNUSED2[7:0] 0x00 UNUSED2[15:8] 0x80 LANE_MD CLK_MD DDR_MD OUT_DATA_MD 0x00 OSC_LIMIT OSC_DIV 0x00 RESERVED IO2X 0x00 TEST_DATA_PAT[7:0] 0x0F TEST_DATA_PAT[15:8] 0x0F TEST_DATA_PAT[23:16] 0x5A TEST_DATA_PAT[31:24] 0x5A POWERUP_CO RESET_OC RESERVED FUSE_CR 0x40 MPLETED CURRED C_EN RESERVED FUSE_CR 0x00 C_ERR R/W RESERVED Bit 4 Bit 3 Bit 2 RESERVED SHORT_INST RUCTION Bit 1 Bit 0 SW_RES ETX RESERVED R R R R R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. A | 40 of 50 Data Sheet AD4030-24/AD4032-24 REGISTER DETAILS INTERFACE CONFIGURATION A REGISTER Address: 0x00, Reset: 0x10, Name: INTERFACE_CONFIG_A Interface configuration settings. Table 17. Bit Descriptions for INTERFACE_CONFIG_A Bits Bit Name Description Reset Access 7 SW_RESET 0x0 R/W 6 5 RESERVED ADDR_ASCENSION 0x0 0x0 R R 4 [3:1] 0 SDO_ENABLE RESERVED SW_RESETX First of Two SW_RESET Bits. This bit appears in two locations in this register. Both locations must be written at the same time to trigger a software reset of the device. All registers except for this register are reset to their default values. Reserved. Determines Sequential Addressing Behavior. 0: address accessed is decremented by one for each data byte when streaming. 1: not a valid option. SDOx Pin Enable. Reserved. Second of Two SW_RESET Bits. This bit appears in two locations in this register. Both locations must be written at the same time to trigger a software reset of the device. All registers except for this register are reset to their default values. 0x1 0x0 0x0 R R R/W INTERFACE CONFIGURATION B REGISTER Address: 0x01, Reset: 0x00, Name: INTERFACE_CONFIG_B Additional interface configuration settings. Table 18. Bit Descriptions for INTERFACE_CONFIG_B Bits Bit Name Description Reset Access 7 SINGLE_INST 0x0 R/W 6 [5:4] 3 STALLING RESERVED SHORT_INSTRUCTION Select Streaming or Single Instruction Mode. 0: streaming mode is enabled. The address decrements as successive data bytes are received. 1: single instruction mode is enabled. Reserved for Stalling Feature. Reserved. Set the Instruction Phase Address to 7 Bits or 15 Bits. 0: 15-bit addressing. 1: 7-bit addressing. 0x0 0x0 0x0 R/W R R analog.com Rev. A | 41 of 50 Data Sheet AD4030-24/AD4032-24 REGISTER DETAILS Table 18. Bit Descriptions for INTERFACE_CONFIG_B Bits Bit Name Description Reset Access [2:0] RESERVED Reserved. 0x0 R DEVICE CONFIGURATION REGISTER Address: 0x02, Reset: 0x00, Name: DEVICE_CONFIG Table 19. Bit Descriptions for DEVICE_CONFIG Bits Bit Name Description Reset Access [7:2] [1:0] RESERVED OPERATING_MODES Reserved. Power Modes 00: normal operating mode. 11: shutdown mode. 0x0 0x0 R R/W CHIP TYPE REGISTER Address: 0x03, Reset: 0x07, Name: CHIP_TYPE The chip type is used to identify the family of Analog Devices products a given device belongs to. Use the chip type with the product ID to uniquely identify a given product. Table 20. Bit Descriptions for CHIP_TYPE Bits Bit Name Description Reset Access [7:4] [3:0] RESERVED CHIP_TYPE Reserved. Precision ADC. 0x0 0x7 R R PRODUCT ID LOW REGISTER Address: 0x04, Reset: 0x00, Name: PRODUCT_ID_L Low byte of the product ID. Table 21. Bit Descriptions for PRODUCT_ID_L Bits Bit Name Description Reset Access [7:0] PRODUCT_ID[7:0] Device Chip Type/Family. Use the product ID with the chip type to identify a product. 0x0 R PRODUCT ID HIGH REGISTER Address: 0x05, Reset: 0x20, Name: PRODUCT_ID_H High byte of the product ID. analog.com Rev. A | 42 of 50 Data Sheet AD4030-24/AD4032-24 REGISTER DETAILS Table 22. Bit Descriptions for PRODUCT_ID_H Bits Bit Name Description Reset Access [7:0] PRODUCT_ID[15:8] Device Chip Type/Family. Use the product ID with the chip type to identify a product. 0x20 R CHIP GRADE REGISTER Address: 0x06, Reset: 0x81, Name: CHIP_GRADE Identifies product variations and device revisions. Table 23. Bit Descriptions for CHIP_GRADE Bits Bit Name Description Reset Access [7:3] GRADE This is the Device Performance Grade. AD4030-24: 0b10000. AD4032-24: 0b10010. This is the Device Hardware Revision. 0x10 0x12 0x1 R R R [2:0] DEVICE_REVISION SCRATCH PAD REGISTER Address: 0x0A, Reset: 0x00, Name: SCRATCH_PAD This register can be used to test writes and reads. Table 24. Bit Descriptions for SCRATCH_PAD Bits Bit Name Description Reset Access [7:0] SCRATCH_VALUE Software Scratchpad. Software can write to and read from this location without any device side effects. 0x0 R/W SPI REVISION REGISTER Address: 0x0B, Reset: 0x81, Name: SPI_REVISION Indicates the SPI revision. Table 25. Bit Descriptions for SPI_REVISION Bits Bit Name Description Reset Access [7:6] SPI_TYPE Always Reads as 0x2. 0x2 R analog.com Rev. A | 43 of 50 Data Sheet AD4030-24/AD4032-24 REGISTER DETAILS Table 25. Bit Descriptions for SPI_REVISION Bits Bit Name Description Reset Access [5:0] VERSION SPI Version. 0x1 R VENDOR ID LOW REGISTER Address: 0x0C, Reset: 0x56, Name: VENDOR_L Low byte of the vendor ID. Table 26. Bit Descriptions for VENDOR_L Bits Bit Name Description Reset Access [7:0] VID[7:0] Analog Devices Vendor ID. 0x56 R VENDOR ID HIGH REGISTER Address: 0x0D, Reset: 0x04, Name: VENDOR_H High byte of the vendor ID. Table 27. Bit Descriptions for VENDOR_H Bits Bit Name Description Reset Access [7:0] VID[15:8] Analog Devices Vendor ID. 0x4 R STREAM MODE REGISTER Address: 0x0E, Reset: 0x00, Name: STREAM_MODE Defines the length of the loop when streaming data. Table 28. Bit Descriptions for STREAM_MODE Bits Bit Name Description Reset Access [7:0] LOOP_COUNT Sets the Data Byte Count Before Looping to Start Address. Not enabled in the AD4030-24. 0x0 R/W INTERFACE STATUS A REGISTER Address: 0x11, Reset: 0x00, Name: INTERFACE_STATUS_A Status bits are set to 1 to indicate an active condition. The status bits can be cleared by writing a 1 to the corresponding bit location. analog.com Rev. A | 44 of 50 Data Sheet AD4030-24/AD4032-24 REGISTER DETAILS Table 29. Bit Descriptions for INTERFACE_STATUS_A Bits Bit Name Description Reset Access [7:5] 4 RESERVED CLOCK_COUNT_ERR 0x0 0x0 R R/W1C [3:0] RESERVED Reserved. Incorrect Number of Clocks Detected in a Transaction. 0 = no error. 1 = incorrect number of clocks detected in a transaction. Write 1 to clear. Reserved. 0x0 R EXIT CONFIGURATION MODE REGISTER Address: 0x14, Reset: 0x00, Name: EXIT_CFG_MD Table 30. Bit Descriptions for EXIT_CFG_MD Bits Bit Name Description Reset Access [7:1] 0 RESERVED EXIT_CONFIG_MD Reserved. Exit Register Config Mode. Write 1 to exit register configuration mode. Self clearing upon CS = 1. 0x0 0x0 R R/W AVERAGING MODE REGISTER Address: 0x15, Reset: 0x00, Name: AVG Table 31. Bit Descriptions for AVG Bits Bit Name Description Reset Access 7 [6:5] [4:0] AVG_SYNC RESERVED AVG_VAL Averaging Filter Reset. 1 = reset, self clearing. Reserved. Averaging Filter Block Length, 2N. 0x00 = no averaging. 0x01 = 21 samples. 0x02 = 22 samples. 0x03 = 23 samples. 0x04 = 24 samples. 0x05 = 25 samples. … 0x0F = 215 samples. 0x10 = 216 samples. 0x11 through 0x1F = invalid. 0x0 0x0 0x0 R/W R R/W analog.com Rev. A | 45 of 50 Data Sheet AD4030-24/AD4032-24 REGISTER DETAILS OFFSET REGISTERS Address: 0x16, Reset: 0x00, Name: OFFSET_LB Table 32. Bit Descriptions for OFFSET_LB Bits Bit Name Description Reset Access [7:0] USER_OFFSET[7:0] 24-Bit Offset. Twos complement (signed). 0x0 R/W V   1   LSB   =   REF /GAIN. 223 Address: 0x17, Reset: 0x00, Name: OFFSET_MB Table 33. Bit Descriptions for OFFSET_MB Bits Bit Name Description Reset Access [7:0] USER_OFFSET[15:8] 24-Bit Offset. Twos complement (signed). 0x0 R/W V   1   LSB   =   REF /GAIN. 223 Address: 0x18, Reset: 0x00, Name: OFFSET_HB Table 34. Bit Descriptions for OFFSET_HB Bits Bit Name Description Reset Access [7:0] USER_OFFSET[23:16] 24-Bit Offset. Twos complement (signed). 0x0 R/W Reset Access V   1   LSB   =   REF /GAIN. 223 GAIN REGISTERS Address: 0x1C, Reset: 0x00, Name: GAIN_LB Table 35. Bit Descriptions for GAIN_LB Bits Bit Name Description [7:0] USER_GAIN[7:0] Gain Word (Unsigned). Multiplier Output = Input × Gain Word/0x8000. Maximum Effective Gain = 0xFFFF/ 0x0 0x8000 = 1.99997. R/W Address: 0x1D, Reset: 0x80, Name: GAIN_HB analog.com Rev. A | 46 of 50 Data Sheet AD4030-24/AD4032-24 REGISTER DETAILS Table 36. Bit Descriptions for GAIN_HB Bits Bit Name Description Reset Access [7:0] USER_GAIN[15:8] Gain Word (Unsigned). Multiplier Output = Input × Gain Word/0x8000. Maximum Effective Gain = 0xFFFF/0x8000 = 1.99997. 0x80 R/W MODES REGISTER Address: 0x20, Reset: 0x00, Name: MODES Table 37. Bit Descriptions for MODES Bits Bit Name Description Reset Access [7:6] LANE_MD 0x0 R/W [5:4] CLK_MD 0x0 R/W 3 DDR_MD 0x0 R/W [2:0] OUT_DATA_MD Lane Mode Select. 00 = one lane. 01 = two lanes. 10 = four lanes. 11 = invalid setting. Clock Mode Select. 00 = SPI clocking mode. 01 = echo clock mode. 10 = host clock mode. 11 = invalid setting. DDR Mode Enable/Disable. 0 = SDR. 1 = DDR (only valid for echo clock mode and host clock mode). Output Data Mode Select. 000 = 24-bit differential data. 001 = 16-bit differential data + 8-bit common-mode data. 010 = 24-bit differential data + 8-bit common-mode data. 011 = 30-bit averaged differential data + OR bit + SYNC bit. 100 = 32-bit test data pattern (TEST_DATA_PAT). 0x0 R/W INTERNAL OSCILLATOR REGISTER Address: 0x21, Reset: 0x00, Name: OSCILLATOR analog.com Rev. A | 47 of 50 Data Sheet AD4030-24/AD4032-24 REGISTER DETAILS Table 38. Bit Descriptions for OSCILLATOR Bits Bit Name Description Reset Access [7:2] OSC_LIMIT 0x0 R [1:0] OSC_DIV Oscillator Limit Setting. Oscillator is limited to this number of clock pulses plus one. Automatically calculated by the AD4030-24 based on the data-word size, number of active SDO lanes, and data rate mode (SDR or DDR). Oscillator Divider Setting. 00 = no divide (divide by 1). 01 = divide by 2. 10 = divide by 4. 11 = invalid setting. 0x0 R/W OUTPUT DRIVER REGISTER Address: 0x22, Reset: 0x00, Name: IO Table 39. Bit Descriptions for IO Bits Bit Name Description Reset Access [7:1] 0 RESERVED IO2X Reserved. Double Output Driver Strength. 1 = double output driver strength. 0 = normal output driver strength. 0x0 0x0 R R/W TEST PATTERN REGISTERS Address: 0x23, Reset: 0x0F, Name: TEST_PAT_BYTE0 Table 40. Bit Descriptions for TEST_PAT_BYTE0 Bits Bit Name Description Reset Access [7:0] TEST_DATA_PAT[7:0] 32-Bit Test Pattern. Applied when OUT_DATA_MD = 4. 0xF R/W Address: 0x24, Reset: 0x0F, Name: TEST_PAT_BYTE1 Table 41. Bit Descriptions for TEST_PAT_BYTE1 Bits Bit Name Description Reset Access [7:0] TEST_DATA_PAT[15:8] 32-Bit Test Pattern. Applied when OUT_DATA_MD = 4. 0xF R/W Address: 0x25, Reset: 0x5A, Name: TEST_PAT_BYTE2 analog.com Rev. A | 48 of 50 Data Sheet AD4030-24/AD4032-24 REGISTER DETAILS Table 42. Bit Descriptions for TEST_PAT_BYTE2 Bits Bit Name Description Reset Access [7:0] TEST_DATA_PAT[23:16] 32-Bit Test Pattern. Applied when OUT_DATA_MD = 4. 0x5A R/W Address: 0x26, Reset: 0x5A, Name: TEST_PAT_BYTE3 Table 43. Bit Descriptions for TEST_PAT_BYTE3 Bits Bit Name Description Reset Access [7:0] TEST_DATA_PAT[31:24] 32-Bit Test Pattern. Applied when OUT_DATA_MD = 4. 0x5A R/W DIGITAL DIAGNOSTICS REGISTER Address: 0x34, Reset: 0x40, Name: DIG_DIAG Table 44. Bit Descriptions for DIG_DIAG Bits Bit Name Description Reset Access 7 POWERUP_COMPLETED 0x0 R 6 RESET_OCCURRED 0x1 R/W1C [5:1] 0 RESERVED FUSE_CRC_EN Power-Up Completed. 1 = power-up completed. Self clearing. Reset Occurred. This bit is set to 1 upon a reset event. Write 1 to clear (useful for detecting brownouts). Reserved. Fuse CRC Enable. Write a 1 to force recheck of CRC. 0x0 0x0 R R/W DIGITAL ERRORS REGISTER Address: 0x35, Reset: 0x00, Name: DIG_ERR Table 45. Bit Descriptions for DIG_ERR Bits Bit Name Description Reset Access [7:1] 0 RESERVED FUSE_CRC_ERR Reserved. Fuse CRC Error. This bit is set to 1 upon a fuse CRC error. Write 1 to clear. 0x0 0x0 R R/W1C analog.com Rev. A | 49 of 50 Data Sheet AD4030-24/AD4032-24 OUTLINE DIMENSIONS Figure 60. 64-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (05-08-1797) Dimensions shown in millimeters Updated: May 10, 2022 ORDERING GUIDE Model1 Temperature Range Package Description Packing Quantity Package Option AD4030-24BBCZ AD4030-24BBCZ-RL AD4032-24BBCZ AD4032-24BBCZ-RL -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C 64-Ball CSP-BGA (7 mm x 7 mm x 1.72 mm) 64-Ball CSP-BGA (7 mm x 7 mm x 1.72 mm) 64-Ball CSP-BGA (7 mm x 7 mm x 1.72 mm) 64-Ball CSP-BGA (7 mm x 7 mm x 1.72 mm) Tray, 260 Reel, 2000 Tray, 260 Reel, 2000 05-08-1797 05-08-1797 05-08-1797 05-08-1797 1 Z = RoHS Compliant Part. EVALUATION BOARDS Evaluation Board1, 2 Description EVAL-AD4030-24-KTZ EVAL-AD4030-24FMCZ Evaluation Kit Evaluation Board 1 Z = RoHS Compliant Part. 2 The EVAL-AD4030-24-KTZ and EVAL-AD4030-24FMCZ can be used to evaluate the AD4032-24. ©2022 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Rev. A | 50 of 50