Data Sheet
Single-Supply, Multichannel, 125 kSPS,
24-Bit, Sigma-Delta ADC with ±10 V Inputs
AD4115
FEATURES
GENERAL DESCRIPTION
24-bit ADC with integrated AFE
Fast and flexible output rate: 2.5 SPS to 125 kSPS
Channel scan data rate of 24,845 SPS per channel
(40.25 µs settling)
85 dB common mode rejection of 50 Hz and 60 Hz at
20 SPS per channel
±10 V inputs, either 8 differential or 16 single-ended
VIN pin absolute maximum rating ±65 V
Absolute input pin voltage up to ±20 V
Minimum 1 MΩ impedance
On-chip 2.5 V reference
±0.12% initial accuracy at 25°C, ±5 ppm/°C (typical) drift
Internal or external clock
Power supplies
AVDD = 4.5 V to 5.5 V
IOVDD = 2 V to 5.5 V
Total current consumption AVDD + IOVDD (IDD) = 10.4 mA
Temperature range: −40°C to +105°C
3-wire or 4-wire serial digital interface (Schmitt trigger on SCLK)
SPI, QSPI, MICROWIRE, and DSP compatible
The AD4115 is a low power, low noise, 24-bit, sigma-delta (Σ-Δ)
analog-to-digital converter (ADC) that integrates an analog
front end (AFE) for eight fully differential or 16 single-ended,
high impedance (≥1 MΩ), bipolar, ±10 V voltage inputs.
APPLICATIONS
Process control
Programmable logic controller (PLC) and distributed control
system (DCS) modules
Instrumentation and measurement
Rev. A
The AD4115 integrates key analog and digital signal
conditioning blocks to configure eight individual setups for
each analog input channel in use. The AD4115 features a
maximum channel scan rate of 24,845 kSPS (40.25 µs) for fully
settled data.
The embedded 2.5 V, low drift (±5 ppm/°C), band gap internal
reference (with output reference buffer) reduces the external
component count.
The digital filter allows flexible settings, including simultaneous
50 Hz and 60 Hz rejection at a 27.27 SPS output data rate. The
user can select different filter settings depending on the
requirements of each channel in the application. The automatic
channel sequencer enables the ADC to switch through each
enabled channel.
The precision performance of the AD4115 is achieved by
integrating the proprietary iPassives® technology from Analog
Devices, Inc. The AD4115 is factory calibrated to achieve a high
degree of specified accuracy.
The AD4115 operates with a single power supply that allows
simplified use in galvanically isolated applications. The specified
operating temperature range is −40°C to +105°C. The AD4115
is housed in a 40-lead, 6 mm × 6 mm LFCSP.
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Technical Support
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AD4115
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Calibration Modes ..................................................................... 32
Applications ...................................................................................... 1
Digital Interface .............................................................................. 33
General Description ......................................................................... 1
Checksum Protection ................................................................ 33
Revision History ............................................................................... 3
CRC Calculation......................................................................... 34
Functional Block Diagram .............................................................. 4
Integrated Functions ...................................................................... 36
Specifications .................................................................................... 5
General-Purpose Input/Output ............................................... 36
Timing Characteristics ................................................................ 7
External Multiplexer Control ................................................... 36
Absolute Maximum Ratings ........................................................... 9
Delay ............................................................................................ 36
Thermal Resistance ...................................................................... 9
16-Bit and 24-Bit Conversions ................................................. 36
Electrostatic Discharge (ESD) Ratings ...................................... 9
DOUT_RESET ........................................................................... 36
ESD Caution.................................................................................. 9
Synchronization ......................................................................... 36
Pin Configuration and Function Descriptions .......................... 10
Error Flags ................................................................................... 37
Typical Performance Characteristics ........................................... 12
DATA_STAT Function............................................................. 37
Theory of Operation ...................................................................... 15
IOSTRENGTH Function .......................................................... 37
Power Supplies ............................................................................ 16
Internal Temperature Sensor ................................................... 38
Digital Communication ............................................................ 16
Applications Information ............................................................. 39
AD4115 Reset.............................................................................. 16
Grounding and Layout .............................................................. 39
Configuration Overview............................................................ 18
Register Summary .......................................................................... 40
Noise Performance and Resolution ............................................. 21
Register Details ............................................................................... 42
Circuit Description......................................................................... 23
Communications Register ........................................................ 42
Muliplexer ................................................................................... 23
Status Register............................................................................. 43
Voltage Inputs............................................................................. 23
ADC Mode Register ................................................................... 44
Absolute Input Pin Voltages ..................................................... 24
Interface Mode Register ............................................................ 45
Data Output Coding .................................................................. 24
Register Check ............................................................................ 46
AD4115 Reference Options ...................................................... 24
Data Register ............................................................................... 46
Buffered Reference Input .......................................................... 25
GPIO Configuration Register ................................................... 47
Clock Source ............................................................................... 25
ID Register .................................................................................. 48
Digital Filter .................................................................................... 27
Channel Register 0 to Channel Register 15 ............................ 48
Sinc5 + Sinc1 Filter .................................................................... 27
Setup Configuration Register 0 to Setup Configuration
Register 7 ..................................................................................... 49
Sinc3 Filter................................................................................... 27
Single-Cycle Settling Mode ....................................................... 27
Enhanced 50 Hz and 60 Hz Rejection Filters ......................... 28
Operating Modes ............................................................................ 30
Continuous Conversion Mode ................................................. 30
Continuous Read Mode ............................................................ 30
Single Conversion Mode ........................................................... 30
Filter Configuration Register 0 to Filter Configuration
Register 7 ..................................................................................... 50
Offset Register 0 to OFFSET Register 7 .................................. 51
Gain Register 0 to Gain Register 7 ........................................... 51
Outline Dimensions ....................................................................... 52
Ordering Guide .......................................................................... 52
Standby Mode and Power-Down Mode ................................. 32
Rev. A | Page 2 of 52
Data Sheet
AD4115
REVISION HISTORY
11/2020—Rev. 0 to Rev. A
Changes to General Description Section ....................................... 1
Change to Total Unadjusted Error (TUE) Parameter,
Table 1................................................................................................. 5
Changes to Table 16 and Table 17 ................................................21
Changes to Table 30 ........................................................................50
7/2020—Revision 0: Initial Version
Rev. A | Page 3 of 52
AD4115
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
AVDD
REGCAPA
REF–
REF+
IOVDD
BUFFERED
PRECISION
REFERENCE
1.8V
LDO
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
VIN8
VIN9
VIN10
VIN11
VIN12
VIN13
VIN14
VIN15
VINCOM
REFOUT
REGCAPD
1.8V
LDO
INTERNAL
REFERENCE
RAIL-TO-RAIL
REFERENCE
INPUT BUFFERS
PRECISION
VOLTAGE
DIVIDER
CS
SCLK
DIGITAL
FILTER
Σ-Δ ADC
MUX
SERIAL
INTERFACE
DIN
DOUT/RDY
SYNC
ERROR
AD4115
VBIAS–
GPO CONTROL
XTAL AND INTERNAL
CLOCK OSCILLATOR
CIRCUITRY
AVSS
GPIO0 GPIO1 GPO2 GPO3
Figure 1.
Rev. A | Page 4 of 52
XTAL1
XTAL2/CLKIO
23874-001
TEMPERATURE
SENSOR
Data Sheet
AD4115
SPECIFICATIONS
AVDD = 4.5 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = 0 V, DGND = 0 V, VBIAS− = 0 V, REF+ = 2.5 V, REF− = AVSS, internal master
clock (MCLK) = 8 MHz, TA = TMIN to TMAX (−40°C to +105°C), unless otherwise noted. VREF is the reference voltage, FS is full scale, and
FSR is full-scale range.
Table 1.
Parameter
VOLTAGE INPUTS
Differential Input Voltage Range1
Absolute Input Pin Voltage
Input Impedance
Offset Error 2
Offset Drift
Gain Error
Gain Drift
Integral Nonlinearity (INL)
Total Unadjusted Error (TUE) 3
Power Supply Rejection Ratio (PSRR)
Common-Mode Rejection Ratio
(CMRR)
At DC
At 50 Hz and 60 Hz
Normal Mode Rejection3
Resolution
Noise
ADC SPEED AND PERFORMANCE
ADC Output Data Rate (ODR)
No Missing Codes3
INTERNAL REFERENCE
Output Voltage
Initial Accuracy3, 4
Temperature Coefficient
Reference Load Current (ILOAD)
PSRR
Load Regulation (∆VOUT/∆ILOAD 5)
Voltage Noise (eN)
Voltage Noise Density
Turn On Settling Time
Short-Circuit Current (ISC)
EXTERNAL REFERENCE INPUTS
Differential Input Range
Absolute Voltage Limits
Buffers Disabled
Buffers Enabled
External Reference Input Current
Test Conditions/Comments
Min
Specified performance
Functional
−10
−VREF × 10
−20
1
Max
Unit
+10
+VREF × 10
+20
V
V
V
MΩ
mV
µV/°C
% FS
ppm/°C
% FSR
0.07
0.09
0.12
0.07
0.08
70
% FSR
% FSR
% FSR
% FSR
% FSR
dB
85
120
dB
dB
71
90
85
90
dB
dB
TA = 25°C
Typ
±1.5
±8
±0.05
±1
±0.01
TA = 25°C
TA = 25°C, internal VREF
0°C to 105°C, internal VREF
−40°C to +105°C, internal VREF
25°C, external VREF
−40°C to +105°C, external VREF
AVDD for input voltage (VIN) = 1 V
VIN = 1 V
20 Hz output data rate (postfilter), 50 Hz ±
1 Hz and 60 Hz ± 1 Hz
50 Hz ± 1 Hz and 60 Hz ± 1 Hz
Internal clock, 20 SPS ODR (postfilter)
External clock, 20 SPS ODR (postfilter)
See Table 16 and Table 17
See Table 16 and Table 17
One channel, see Table 16
Excluding sinc3 filter ≥ 62.5 kHz notch
100 nF external capacitor to AVSS
REFOUT with respect to AVSS
REFOUT, TA = 25°C
2.5
24
125,000
2.5
−0.12
±5
−10
AVDD (line regulation)
95
32
4.5
215
200
25
0.1 Hz to 10 Hz, 2.5 V reference
1 kHz, 2.5 V reference
100 nF REFOUT capacitor
VREF = (REF+) − (REF−)
1
AVSS − 0.05
AVSS
Rev. A | Page 5 of 52
+0.12
+12
+10
2.5
SPS
Bits
V
%
ppm/°C
mA
dB
ppm/mA
µV rms
nV/√Hz
µs
mA
AVDD
V
AVDD + 0.05
AVDD
V
V
AD4115
Parameter
Buffers Disabled
Input Current
Input Current Drift
Buffers Enabled
Input Current
Input Current Drift
Normal Mode Rejection
CMRR
TEMPERATURE SENSOR
Accuracy
Sensitivity
GENERAL-PURPOSE OUTPUTS
(GPIO0, GPIO1, GPO2, GPO3)
Floating State Output Capacitance
Output Voltage3
High (VOH)
Low (VOL)
CLOCK
Internal Clock
Frequency
Accuracy
Duty Cycle
Output Voltage
VOH
VOL
Crystal
Frequency
Start-Up Time
External Clock (CLKIO)
Duty Cycle
LOGIC INPUTS
Input Voltage3
High (VINH)
Low (VINL)
Hysteresis
Leakage Current
LOGIC OUTPUT (DOUT/RDY)
Output Voltage3
VOH
VOL
Leakage Current3
Output Capacitance
POWER REQUIREMENTS
Power Supply Voltage
Data Sheet
Test Conditions/Comments
Min
External clock
Internal clock
After user calibration at 25°C
Typ
Max
Unit
±36
±1.2
±3
µA/V
nA/V/°C
nA/V/°C
±400
0.6
nA
nA/°C
95
dB
±2
477
°C
µV/K
5
pF
With respect to AVSS
Source current (ISOURCE) = 200 µA
Sink current (ISINK) = 800 µA
AVDD − 1
AVSS + 0.4
8
−2.5%
+2.5%
50
0.8 × IOVDD
0.4
14
30
2 V ≤ IOVDD < 2.3 V
2.3 V ≤ IOVDD ≤ 5.5 V
2 V ≤ IOVDD < 2.3 V
2.3 V ≤ IOVDD ≤ 5.5 V
IOVDD ≥ 2.7 V
IOVDD < 2.7 V
IOVDD ≥ 4.5 V, ISOURCE = 1 mA
2.7 V ≤ IOVDD < 4.5 V, ISOURCE = 500 µA
IOVDD < 2.7 V, ISOURCE = 200 µA
IOVDD ≥ 4.5 V, ISINK = 2 mA
2.7 V ≤ IOVDD < 4.5 V, ISINK = 1 mA
IOVDD < 2.7 V, ISINK = 400 µA
Floating state
Floating state
Rev. A | Page 6 of 52
16
10
8
50
16.384
8.192
70
0.65 × IOVDD
0.7 × IOVDD
0.35 ×
IOVDD
0.7
0.25
0.2
+10
0.08
0.04
−10
0.8 × IOVDD
0.8 × IOVDD
0.8 × IOVDD
0.4
0.4
0.4
+10
−10
10
V
V
MHz
%
%
V
V
MHz
µs
MHz
%
V
V
V
V
V
V
µA
V
V
V
V
V
V
µA
pF
Data Sheet
AD4115
Parameter
AVDD to AVSS
AVSS to DGND
IOVDD to DGND
IOVDD to AVSS
POWER SUPPLY CURRENTS 6
Full Operating Mode
AVDD Current
IOVDD Current
Standby Mode
Power-Down Mode
POWER DISSIPATION
Full Operating Mode
Standby Mode
Power-Down Mode
Test Conditions/Comments
Min
4.5
−2.75
2
Typ
Max
5.5
0
5.5
6.35
Unit
V
V
V
V
9.4
1.4
210
185
11.5
1.8
mA
mA
µA
µA
For AVSS < DGND
All outputs unloaded, digital inputs
connected to IOVDD or DGND
Including internal reference
Internal clock
All VIN = 0 V
All VIN = 0 V
52
1
925
mW
mW
µW
The full specification is guaranteed for a differential input signal of ±10 V. The device is functional up to a differential input signal of ±VREF × 10. However, the specified
absolute pin voltage must not be exceeded for the proper function.
Following a system zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected.
3
Specification is not production tested but is supported by characterization data at the initial product release.
4
This specification includes moisture sensitivity level (MSL) preconditioning effects.
5
VOUT is the output voltage.
6
This specification is with no load on the REFOUT pin and the digital output pins.
1
2
TIMING CHARACTERISTICS
IOVDD = 2 V to 5.5 V, DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = IOVDD, capacitive load (CLOAD) = 20 pF, unless otherwise noted.
Table 2.
Parameter 1, 2
SCLK
t3
t4
READ OPERATION
t1
t2 3
t5 5
t6
t7
WRITE OPERATION
t8
t9
t10
t11
Limit at TMIN or TMAX
Unit
Test Conditions/Comments
25
25
ns min
ns min
SCLK high pulse width
SCLK low pulse width
0
15
40
0
12.5
25
2.5
20
0
10
ns min
ns max
ns max
ns min
ns max
ns max
ns min
ns max
ns min
ns min
CS falling edge to DOUT/RDY active time
IOVDD = 4.75 V to 5.5 V
IOVDD = 2 V to 3.6 V
SCLK active edge to data valid delay 4
IOVDD = 4.75 V to 5.5 V
IOVDD = 2 V to 3.6 V
Bus relinquish time after CS inactive edge
0
8
8
5
ns min
ns min
ns min
ns min
CS falling edge to SCLK active edge setup time4
Data valid to SCLK edge setup time
Data valid to SCLK edge hold time
CS rising edge to SCLK edge hold time
SCLK inactive edge to CS inactive edge
SCLK inactive edge to DOUT/RDY high/low
Sample tested during initial release to ensure compliance.
See Figure 2 and Figure 3.
3
This parameter is defined as the time required for the output to cross the VOL or VOH limit.
4
The SCLK active edge is the falling edge of SCLK.
5
DOUT/RDY returns high after a data register read. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while
DOUT/RDY is high. Ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the digital word can be read
only once.
1
2
Rev. A | Page 7 of 52
AD4115
Data Sheet
Timing Diagrams
CS (I)
t6
t1
t5
MSB
DOUT/RDY (O)
LSB
t7
t2
t3
23874-002
SCLK (I)
t4
I = INPUT, O = OUTPUT
Figure 2. Read Cycle Timing Diagram
CS (I)
t11
t8
SCLK (I)
t9
t10
MSB
LSB
I = INPUT, O = OUTPUT
Figure 3. Write Cycle Timing Diagram
Rev. A | Page 8 of 52
23874-003
DIN (I)
Data Sheet
AD4115
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 3.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
AVDD to AVSS
AVDD to DGND
IOVDD to DGND
IOVDD to AVSS
AVSS to DGND
VINx to AVSS
Reference Input Voltage to AVSS
Digital Input Voltage to DGND
Digital Output Voltage to DGND
Digital Input Current
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Lead Soldering, Reflow Temperature
Rating
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +7.5 V
−3.25 V to +0.3 V
−65 V to +65 V
−0.3 V to AVDD + 0.3 V
−0.3 V to IOVDD + 0.3 V
−0.3 V to IOVDD + 0.3 V
10 mA
−40°C to +105°C
−65°C to +150°C
150°C
260°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
θJC is the thermal resistance from the junction to the package case.
Table 4. Thermal Resistance
Package Type
CP-40-151
θJA
342
θJC
2.633
Unit
°C/W
4-Layer JEDEC PCB.
Thermal impedance simulated values are based on JEDEC 2S2P thermal test
PCB with 16 thermal vias. θJA is specified for a device soldered on a JEDEC
test PCB for surface-mount packages. See JEDEC JESD51.
3
A cold plate is attached to the PCB bottom and measured at the exposed paddle.
1
2
ELECTROSTATIC DISCHARGE (ESD) RATINGS
The following ESD information is provided for handling of
ESD-sensitive devices in an ESD protected area only.
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
Charged device model (CDM) per ANSI/ESDA/JEDEC JS-002.
ESD Ratings for AD4115
Table 5. AD4115, 40-Lead LFCSP
ESD Model
HBM
CDM
ESD CAUTION
Rev. A | Page 9 of 52
Withstand Threshold (v)
±1000
±1250
Class
1C
C3
AD4115
Data Sheet
40
39
38
37
36
35
34
33
32
31
REF+
REF–
GPO3
VIN15
VIN14
VIN13
VIN12
VIN11
VIN10
VIN9
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
AD4115
TOP VIEW
(Not to Scale)
30
29
28
27
26
25
24
23
22
21
VIN8
VIN7
VIN6
VIN5
VIN4
GPO2
GPIO1
GPIO0
REGCAPD
DGND
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT ANYTHING TO DNC.
DNC IS INTERNALLY CONNECTED TO AVSS.
2. EXPOSED PAD. SOLDER THE EXPOSED PAD TO A SIMILAR PAD ON
THE PCB THAT IS UNDER THE EXPOSED PAD TO CONFER MECHANICAL
STRENGTH TO THE PACKAGE AND FOR HEAT DISSIPATION. THE EXPOSED
PAD MUST BE CONNECTED TO AVSS THROUGH THIS PAD ON THE PCB.
Table 6. Pin Function Descriptions
Pin No.
1
Mnemonic 1
VINCOM
Type 2
AI
2
VIN0
AI
3
VIN1
AI
4
VIN2
AI
5
VIN3
AI
6
REFOUT
AO
7
REGCAPA
AO
8
9
10
11
12
13
AVSS
AVDD
DNC
VBIAS−
XTAL1
XTAL2/CLKIO
P
P
N/A
AI
AI
AI/DI
14
DOUT/RDY
DO
15
DIN
DI
16
SCLK
DI
17
CS
DI
23874-004
VBIAS–
XTAL1
XTAL2/CLKIO
DOUT/RDY
DIN
SCLK
CS
ERROR
SYNC
IOVDD
11
12
13
14
15
16
17
18
19
20
VINCOM
VIN0
VIN1
VIN2
VIN3
REFOUT
REGCAPA
AVSS
AVDD
DNC
Figure 4. Pin Configuration
Description
Voltage Input Common. Voltage inputs are referenced to VINCOM when the inputs are configured as
single-ended. Connect VINCOM to analog ground.
Voltage Input 0. VIN0 is either referenced to VINCOM in single-ended configuration or referenced to a
positive input of an input pair with VIN1 in differential configuration.
Voltage Input 1. VIN1 is either referenced to VINCOM in single-ended configuration or referenced to a
negative input of an input pair with VIN0 in differential configuration.
Voltage Input 2. VIN2 is either referenced to VINCOM in single-ended configuration or referenced to a
positive input of an input pair with VIN3 in differential configuration.
Voltage Input 3. VIN3 is either referenced to VINCOM in single-ended configuration or referenced to a
negative input of an input pair with VIN2 in differential configuration.
Internal Reference Buffered Output. The output is 2.5 V with respect to AVSS. Decouple REFOUT to AVSS
using a 0.1 µF capacitor.
Analog Low Dropout (LDO) Regulator Output. Decouple REGCAPA to AVSS using a 1 µF capacitor and a
0.1 µF capacitor.
Negative Analog Supply. AVSS ranges from −2.75 V to 0 V and is nominally set to 0 V.
Analog Supply Voltage. AVDD ranges from 3.0 V to 5.5 V with respect to AVSS.
Do Not Connect. Do not connect anything to DNC. DNC is internally connected to AVSS.
Voltage Bias Negative. VBIAS− sets the bias voltage for the voltage input AFE. Connect VBIAS− to AVSS.
Input 1 for Crystal.
Input 2 for Crystal/Clock Input or Output. See the CLOCKSEL bit settings in the ADC Mode Register
section for more information.
Serial Data Output/Data Ready Output. The DOUT/RDY dual-purpose pin functions as a serial data
output pin to access the output shift register on the ADC. The output shift register can contain data from
any on-chip data or control registers. The data-word or control word information is placed on the
DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. When CS is high, the
DOUT/RDY output is tristated. When CS is low, and a register is not being read, DOUT/RDY operates as a
data ready pin and goes low to indicate the completion of a conversion. If the data is not read after the
conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can be used as
an interrupt to a processor that indicates that valid data is available.
Serial Data Input to the Input Shift Register on the ADC. Data in the input shift register is transferred to
the control registers on the ADC, and the register address (RA) bits of the communications register
identify the appropriate register. Data is clocked in on the rising edge of SCLK.
Serial Clock Input. The SCLK serial clock input is used for data transfers to and from the ADC. SCLK has a
Schmitt triggered input.
Chip Select Input. CS is an active low logic input used to select the ADC. Use CS to select the ADC in
systems with more than one device on the serial bus. CS can be hardwired low to allow the ADC to
Rev. A | Page 10 of 52
Data Sheet
AD4115
Pin No.
Mnemonic 1
Type 2
18
ERROR
DI/O
19
SYNC
DI
20
IOVDD
P
21
22
DGND
REGCAPD
P
AO
23
24
25
26
GPIO0
GPIO1
GPO2
VIN4
DI/O
DI/O
DO
AI
27
VIN5
AI
28
VIN6
AI
29
VIN7
AI
30
VIN8
AI
31
VIN9
AI
32
VIN10
AI
33
VIN11
AI
34
VIN12
AI
35
VIN13
AI
36
VIN14
AI
37
VIN15
AI
38
39
GPO3
REF−
DO
AI
40
REF+
AI
EP
P
1
2
Description
operate in 3-wire mode with SCLK, DIN, and DOUT/RDY used to interface with the device. When CS is
high, the DOUT/RDY output is tristated.
Error Input/Output or General-Purpose Output. ERROR can be used in one of the following three modes:
Active low error input mode. This mode sets the ADC_ERROR bit in the status register.
Active low, open-drain error output mode. The status register error bits are mapped to the ERROR pin.
The ERROR pins of multiple devices can be wired together to a common pull-up resistor so that an error
on any device can be observed.
General-purpose output mode. The status of the pin is controlled by the ERR_DAT bit in the GPIOCON
register. ERROR is referenced between IOVDD and DGND.
Synchronization Input. SYNC allows digital filter and analog modulator synchronization when using
multiple devices.
Digital Input/Output Supply Voltage. The IOVDD voltage ranges from 2 V to 5.5 V (nominal). IOVDD is
independent of AVDD. For example, IOVDD operates at 3.3 V when AVDD equals 5 V, or vice versa. If
AVSS is set to −2.5 V, the voltage on IOVDD must not exceed 3.6 V.
Digital Ground.
Digital LDO Regulator Output. REGCAPD is for decoupling purposes only. Decouple REGCAPD to DGND
using a 1 µF capacitor.
General-Purpose Input/Output 0. Logic input/output on GPIO0 is referred to the AVDD and AVSS supplies.
General-Purpose Input/Output 1. Logic input/output on GPIO1 is referred to the AVDD and AVSS supplies.
General-Purpose Output 2. Logic output on GPO2 is referred to the AVDD and AVSS supplies.
Voltage Input 4. VIN4 is either referenced to VINCOM in single-ended configuration or referenced to a
positive input of an input pair with VIN5 in differential configuration.
Voltage Input 5. VIN5 is either referenced to VINCOM in single-ended configuration or referenced to a
negative input of an input pair with VIN4 in differential configuration.
Voltage Input 6. VIN6 is either referenced to VINCOM in single-ended configuration or referenced to a
positive input of an input pair with VIN7 in differential configuration.
Voltage Input 7. VIN7 is either referenced to VINCOM in single-ended configuration or referenced to a
negative input of an input pair with VIN6 in differential configuration.
Voltage Input 8. VIN8 is either referenced to VINCOM in single-ended configuration or referenced to a
positive input of an input pair with VIN9 in differential configuration.
Voltage Input 9. VIN9 is either referenced to VINCOM in single-ended configuration or referenced to a
negative input of an input pair with VIN8 in differential configuration.
Voltage Input 10. VIN10 is either referenced to VINCOM in single-ended configuration or referenced to a
positive input of an input pair with VIN11 in differential configuration.
Voltage Input 11. VIN11 is either referenced to VINCOM in single-ended configuration or referenced to a
negative input of an input pair with VIN10 in differential configuration.
Voltage Input 12. VIN12 is either referenced to VINCOM in single-ended configuration or referenced to a
positive input of an input pair with VIN13 in differential configuration.
Voltage Input 13. VIN13 is either referenced to VINCOM in single-ended configuration or referenced to a
negative input of an input pair with VIN12 in differential configuration.
Voltage Input 14. VIN14 is either referenced to VINCOM in single-ended configuration or referenced to a
positive input of an input pair with VIN15 in differential configuration.
Voltage Input 15. VIN15 is either referenced to VINCOM in single-ended configuration or referenced to a
negative input of an input pair with VIN14 in differential configuration.
General-Purpose Output 3. Logic output on GPO3 is referred to the AVDD and AVSS supplies.
Reference Input Negative Terminal. The REF− voltage can span from AVSS to AVDD − 1 V. The reference
can be selected through the REF_SELx bits in the setup configuration registers.
Reference Input Positive Terminal. An external reference can be applied between REF+ and REF−. The
REF+ voltage can span from AVDD to AVSS + 1 V. The reference can be selected through the REF_SELx
bits in the setup configuration registers.
Exposed Pad. Solder the exposed pad to a similar pad on the PCB that is under the exposed pad to
confer mechanical strength to the package and for heat dissipation. The exposed pad must be
connected to AVSS through this pad on the PCB.
The dual function pin mnemonics are referenced by the relevant function only throughout this data sheet.
AI is analog input, AO is analog output, P is power supply, N/A is not applicable, DI is digital input, DO is digital output, and DI/O is bidirectional digital input/output.
Rev. A | Page 11 of 52
AD4115
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
350
8387974
8387973
300
8387972
250
OCCURRENCE
ADC CODE
8387971
8387970
8387969
200
150
8387968
100
8387967
8387973
8387972
SAMPLE NUMBER
0
8387971
1000
8387970
800
8387969
600
8387968
400
8387967
200
8387966
0
23874-205
8387965
23874-208
50
8387966
ADC CODE
Figure 8. Histogram (Output Data Rate = 2.5 SPS)
Figure 5. Noise (Output Data Rate = 2.5 SPS)
8388000
60
8387990
50
40
OCCURRENCE
ADC CODE
8387980
8387970
8387960
30
20
8387950
200
400
600
800
1000
SAMPLE NUMBER
0
8387937
8387949
8387941
8387943
8387945
8387947
8387949
8387951
8387953
8387955
8387957
8387959
8387961
8387963
8387965
8387967
8387969
8387971
8387973
8387975
8387977
8387979
8387981
8387983
8387985
8387987
0
23874-206
8387930
23874-209
10
8387940
ADC CODE
Figure 6. Noise (Output Data Rate = 2.5 kSPS)
Figure 9. Histogram (Output Data Rate = 2.5 kSPS)
8388050
25
8388000
20
OCCURRENCE
8387900
8387850
15
10
0
200
400
600
800
SAMPLE NUMBER
1000
0
8387793
8387801
8387809
8387817
8387825
8387833
8387841
8387849
8387857
8387865
8387873
8387881
8387889
8387897
8387905
8387913
8387921
8387929
8387937
8387945
8387953
8387961
8387969
8387977
8387985
8387993
8388001
8388009
8388017
8387750
ADC CODE
Figure 10. Histogram (Output Data Rate = 125 kSPS
Figure 7. Noise (Output Data Rate = 125 kSPS)
Rev. A | Page 12 of 52
23874-210
5
8387800
23874-207
ADC CODE
8387950
Data Sheet
AD4115
–60
30
–70
25
–80
OCCURRENCE
CMRR (dB)
–90
–100
–110
–120
20
15
10
–130
–140
–160
10
20
30
40
50
23874-121
5
23874-117
–150
0
60
7.996
7.999
8.002
VIN FREQUENCY (Hz)
8.005
8.008
8.011
8.014
8.017
FREQUENCY (MHz)
Figure 11. CMRR vs. VIN Frequency (VIN = 0.1 V, Output Data Rate = 20 SPS,
Enhanced Filter)
Figure 14. Internal Oscillator Frequency and
Accuracy Distribution Histogram
–40
35
–50
30
–60
25
OCCURRENCE
PSRR (dB)
–70
–80
–90
–100
20
15
10
–110
–130
1
10
100
1k
10k
100k
1M
10M
23874-123
5
23874-118
–120
0
100M
–4.8
–4.0
VIN FREQUENCY (Hz)
Figure 12. PSRR vs. VIN Frequency
–3.2
–2.4
–1.6 –0.8
OFFSET ERROR (mV)
0
0.8
1.6
Figure 15. Offset Error Distribution Histogram
10
30
8
25
OCCURRENCE
4
2
20
15
10
0
–4
–10
–8
–6
–4
–2
0
2
4
6
8
23874-124
5
–2
23874-120
INL (ppm OF FSR)
6
0
3.2
10
3.9
4.6
5.3
6.0
6.7
7.4
OFFSET ERROR DRIFT (µV/°C)
VIN (V)
Figure 16. Offset Error Drift Distribution Histogram
Figure 13. INL vs. VIN
Rev. A | Page 13 of 52
8.1
AD4115
Data Sheet
35
30
30
25
OCCURRENCE
20
15
20
15
10
10
23874-125
0
0.032
0.023
0.014
0.005
–0.004
–0.013
–0.022
–0.031
–0.040
0
23874-126
5
5
–0.049
OCCURRENCE
25
0.68
0.81
0.94
1.07
1.20
1.33
1.46
GAIN ERROR DRIFT (ppm/°C)
GAIN ERROR (% of Full Scale)
Figure 17. Gain Error Distribution Histogram
Figure 18. Gain Error Drift Distribution Histogram
Rev. A | Page 14 of 52
1.59
Data Sheet
AD4115
THEORY OF OPERATION
The AD4115 offers a fast settling, high resolution, multiplexed
ADC with high levels of configurability, including the following
features:
The AD4115 includes two separate linear regulator blocks for
the analog and digital circuitry. The analog LDO regulator
regulates the AVDD supply to 1.8 V.
•
The linear regulator for the digital IOVDD supply performs a
function similar to the LDO regulator and regulates the input
voltage applied at the IOVDD pin to 1.8 V. The serial interface
signals always operate from the IOVDD supply seen at the pin.
For example, if 3.3 V is applied to the IOVDD pin, the interface
logic inputs and outputs operate at this level.
•
•
•
The AD4115 includes a precision, 2.5 V, low drift (±5 ppm/°C),
band gap internal reference. Use this reference in ADC
conversions to reduce the external component count. When
enabled, the internal reference is output to the REFOUT pin.
The internal reference can be used as a low noise biasing
voltage for the external circuitry and must be connected to a
0.1 μF decoupling capacitor.
The AD4115 is designed for a multitude of factory automation
and process control applications, including PLC and DCS
modules. The AD4115 reduces overall system cost and design
burden and maintains a high level of accuracy. The AD4115
offers the following system benefits:
•
•
•
•
•
A single 5 V power supply.
Guaranteed minimum 1 MΩ input impedance.
Overrange voltage greater than ±10 V.
Reduced calibration costs.
High channel count.
16MHz
CX2
CX1
OPTIONAL EXTERNAL
CRYSTAL CIRCUITRY
CAPACITORS
XTAL1 12
XTAL2/CLKIO 13
DOUT/RDY 14
2
VIN0
3
VIN1
DOUT/RDY
DIN
DIN 15
CLKIN
OPTIONAL
EXTERNAL
CLOCK
INPUT
SCLK
SCLK 16
CS
CS 17
IOVDD
IOVDD 20
AD4115
0.1µF
DGND 21
37 VIN15
REGCAPD 22
0.1µF
1µF
AVDD
AVDD 9
1
VINCOM
0.1µF
REFOUT 6
0.1µF
11 VBIAS–
REGCAPA 7
AVSS
0.1µF
8
Figure 19. Typical Connection Diagram
Rev. A | Page 15 of 52
1µF
23874-010
•
Eight fully differential voltage inputs or 16 single-ended
voltage inputs.
High impedance voltage divider with integrated precision
matched resistors
Embedded proprietary iPassives® technology within a
small device footprint.
Per channel configurability where up to eight different
setups can be defined. A separate setup can be mapped to
each channel. Each setup allows the user to configure
whether the buffers are enabled or disabled, gain and offset
correction, filter type, ODR, and reference source selection.
Highly configurable digital filter enabling conversion rates
up to 125 kSPS on a single channel and 24.845 kSPS
switching.
AD4115
Data Sheet
The AD4115 has two independent power supply pins, AVDD
and IOVDD. The AD4115 has no specific requirements for a
power supply sequence. However, when all power supplies are
stable, a device reset is required. See the AD4115 Reset section
for information on how to reset the device.
AVDD powers the internal 1.8 V analog LDO regulator that
powers the ADC core. AVDD also powers the crosspoint
multiplexer and integrated input buffers. AVDD is referenced to
AVSS, and AVDD − AVSS = 5 V. AVDD and AVSS can be a
single 5 V supply or ±2.5 V split supplies. Consider the absolute
maximum ratings when using split supplies (see the Absolute
Maximum Ratings section).
IOVDD powers the internal 1.8 V digital LDO regulator that
powers the ADC digital logic. IOVDD sets the voltage levels for
the serial peripheral interface (SPI) of the ADC. IOVDD is
referenced to DGND, and the voltage from IOVDD to DGND can
vary from 2 V (minimum) to 5.5 V (maximum).
determine the specific register to which the read or write
operation applies (see Table 20).
When the read or write operation to the selected register is
complete, the interface returns to the default state to expect a
write operation to the communications register.
Figure 21 and Figure 22 show a write to and a read from a
register by writing the 8-bit command to the communications
register followed by the data for the addressed register.
Figure 21 shows an 8-bit command with the register address
followed by 8 bits, 16 bits, or 24 bits of data where the data
length on DIN depends on the selected register. Figure 22
shows an 8-bit command with the register address followed by
8 bits, 16 bits, 24 bits, or 32 bits of data where the data length
on DOUT depends on the selected register.
To verify correct communication with the device, read the ID
register. The ID register is a read only register and contains the
value of 0x38DX for the AD4115. The communication register
and ID register details are described in Table 7 and Table 8.
Single-Supply Operation (AVSS = DGND)
When the AD4115 is powered from a single supply connected
to AVDD, the supply must be 5 V. In this configuration, AVSS
and DGND can be shorted together on a single ground plane.
IOVDD can range from 2 V to 5.5 V in this unipolar input
configuration.
8-BIT COMMAND
UP TO 24-BIT INPUT
8-BIT CRC
CMD
DATA
CRC
CS
DIN
23874-157
POWER SUPPLIES
SCLK
DIGITAL COMMUNICATION
The AD4115 has either a 3-wire or 4-wire SPI interface that is
compatible with QSPI™, MICROWIRE®, and digital signal
processors (DSPs). The interface operates in SPI Mode 3 and can
be operated with CS tied low. In SPI Mode 3, SCLK idles high, the
falling edge of SCLK is the drive edge, and the rising edge of
SCLK is the sample edge. Data is clocked out on the falling
(drive) edge and data is clocked in on the rising (sample) edge.
SAMPLE EDGE
UP TO 32-BIT OUTPUT
DIN
CMD
DOUT/
RDY
DATA
CRC
23874-158
SCLK
Figure 20. SPI Mode 3 SCLK Edges
8-BIT CRC
CS
23874-011
DRIVE EDGE
Figure 21. Writing to a Register
8-BIT COMMAND
Figure 22. Reading from a Register
AD4115 RESET
Accessing the ADC Register Map
The communications register controls access to the full ADC
register map. This register is an 8-bit, write only register. On
power-up or after a reset, the digital interface defaults to a state
where the interface expects a write to the communications
register. Therefore, all communication begins by writing to the
communications register.
The data written to the communications register determines
which register is accessed and if the next operation is a read or
write. The RA bits (Bits[5:0] in Register Address 0x00)
When a power-up cycle completes and the power supplies are
stable, a device reset is required. If interface synchronization is
lost, a device reset is required. A write operation of at least 64 serial
clock cycles with DIN high returns the ADC to the default state
by resetting the entire device, including the register contents.
Alternatively, if CS is used with the digital interface, returning CS
high sets the digital interface to the default state and halts any
serial interface operation.
Rev. A | Page 16 of 52
Data Sheet
AD4115
Table 7. Communications Register Bit Map
Register
0x00
Name
COMMS
Bits
[7:0]
Bit 7
WEN
Bit 6
R/W
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RA
Reset
0x00
R/W
W
Reset
0x38DX 1
R/W
R
Table 8. ID Register Bit Map
Register
0x07
1
Name
ID
Bits
[15:0]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
ID
X means don’t care.
Rev. A | Page 17 of 52
Bit 2
Bit 1
Bit 0
AD4115
Data Sheet
CONFIGURATION OVERVIEW
Channel Configuration
After a power-on or reset, the AD4115 default configuration is
as follows:
The AD4115 has 16 independent channels and eight independent
setups. The user can select any input pair on any channel, as
well as any of the eight setups for any channel, which allows full
flexibility in the channel configuration. This flexibility allows per
channel configuration when using differential inputs and singleended inputs because each channel can have an individual
dedicated setup.
•
•
•
•
•
Channel configuration: Channel 0 is enabled, the VIN0
and VIN1 pair is selected as the input. Setup 0 is selected
(see the Setup Configuration section for more information).
Setup configuration: the analog input buffers and the
reference input buffers are disabled. The REF+ and REF− pins
are selected as the reference source. Note that for this setup,
the default channel does not operate correctly because the
input buffers must be enabled for a VINx input.
Filter configuration: the sinc5 + sinc1 filter is selected and
the maximum output data rate of 125 kSPS is selected.
ADC mode: continuous conversion mode and the internal
oscillator are enabled. The internal reference is disabled.
Interface mode: cyclic redundancy check (CRC) and the
data and status output are disabled.
Note that only a few of the register setting options are shown in
this example list. For full register information, see the Register
Details section.
Channel Registers
The channel registers select which voltage input is used for the
corresponding channel. Each channel register contains a channel
enable/disable bit and the setup selection bits that select from
eight available setups to use for the channel.
When the AD4115 operates with more than one channel enabled,
the channel sequencer cycles through the enabled channels in
sequential order from Channel 0 to Channel 15. If a channel is
disabled, that channel is skipped by the sequencer. Details on
the channel register for Channel 0 are shown in Table 9.
Figure 23 shows an overview of the suggested flow for changing
the ADC configuration, divided into the following three blocks:
Channel configuration.
Setup configuration.
ADC mode and interface mode configuration.
A
CHANNEL CONFIGURATION
SELECT INPUT AND SETUP FOR EACH ADC CHANNEL
B
SETUP CONFIGURATION
8 POSSIBLE ADC SETUPS
SELECT FILTER ORDER, OUTPUT DATA RATE, AND MORE
C
ADC MODE AND INTERFACE MODE CONFIGURATION
SELECT ADC OPERATING MODE, CLOCK SOURCE,
ENABLE CRC, DATA AND STATUS, AND MORE
23874-137
•
•
•
Figure 23. Suggested ADC Configuration Flow
Table 9. Channel Register 0 Bit Map
Register
0x10
Name
CH0
Bits
[15:8]
[7:0]
Bit 7
CH_EN0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
SETUP_SEL0
Reserved
INPUT0[7:0]
Rev. A | Page 18 of 52
Bit 1
Bit 0
INPUT0[9:8]
Reset
0x8001
R/W
R/W
Data Sheet
AD4115
Setup Configuration
Setup Configuration Registers
The AD4115 has eight independent setups. Each setup consists
of the following four types of registers:
The setup configuration registers allow the user to select
between bipolar mode and unipolar mode to determine the ADC
output coding. The user can also select the reference source using
these registers. Three reference source options are available: a
reference connected between the REF+ and REF− pins, the
internal reference, or using AVDD – AVSS as the reference.
The input and reference buffers can also be enabled or disabled
using these registers.
Setup configuration register
Filter configuration register
Gain register
Offset register
For example, Setup 0 consists of Setup Configuration
Register 0, Filter Configuration Register 0, Gain Register 0, and
Offset Register 0. Figure 24 shows the grouping of these
registers. The setup is selectable from the channel registers (see
the Channel Configuration section), which allows each channel
to be assigned to one of the eight separate setups. Table 10 through
Table 13 show the four registers that are associated with Setup 0.
This structure is repeated for Setup 1 to Setup 7.
SETUP CONFIGURATION
REGISTERS
FILTER CONFIGURATION
REGISTERS
Filter Configuration Registers
The filter configuration registers select which digital filter is
used at the output of the ADC modulator. Set the bits in these
registers to select the order of the filter and the output data rate.
For more information, see the Digital Filter section.
GAIN REGISTERS
OFFSET REGISTERS
SETUPCON0 0x20
FILTCON0 0x28
GAIN0
0x38
OFFSET0 0x30
SETUPCON1 0x21
FILTCON1 0x29
GAIN1
0x39
OFFSET1
SETUPCON2 0x22
FILTCON2 0x2A
GAIN2
0x3A
OFFSET2 0x32
0x31
SETUPCON3 0x23
FILTCON3 0x2B
GAIN3
0x3B
OFFSET3 0x33
SETUPCON4 0x24
FILTCON4 0x2C
GAIN4
0x3C
OFFSET4 0x34
SETUPCON5 0x25
FILTCON5 0x2D
GAIN5
0x3D
OFFSET5 0x35
SETUPCON6 0x26
FILTCON6 0x2E
GAIN6
0x3E
OFFSET6 0x36
GAIN7
0x3F
SETUPCON7 0x27
SELECT PERIPHERAL
FUNCTIONS FOR
ADC CHANNEL
FILTCON7 0x2F
SELECT DIGITAL
FILTER TYPE
AND OUTPUT DATA RATE
INPUT BUFFERS
REFERENCE INPUT BUFFERS
REFERENCE SOURCE
GAIN CORRECTION
OPTIONALLY
PROGRAMMED
PER SETUP AS REQUIRED
OFFSET7 0x37
OFFSET CORRECTION
OPTIONALLY PROGRAMMED
PER SETUP AS REQUIRED
125kSPS TO 2.5SPS
SINC5 + SINC1
SINC3
SINC3 MAP
ENHANCED 50Hz/60Hz
23874-138
•
•
•
•
Figure 24. ADC Setup Register Grouping
Table 10. Setup Configuration Register 0
Register Name
0x20
SETUPCON0
Bits
Bit 7
[15:8]
[7:0]
Bit 6
Reserved
Reserved
Bit 5
Bit 4
BI_UNIPOLAR0
REF_SEL0
Bit 3
Bit 2
REFBUF0+ REFBUF0−
Reserved
Bit 1 Bit 0
INBUF0
Reset
0x1000
R/W
R/W
Table 11. Filter Configuration Register 0
Register Name
0x28
FILTCON0
Bits
[15:8]
[7:0]
Bit 7
SINC3_MAP0
Reserved
Bit 6
Bit 5 Bit 4
Reserved
ORDER0
Bit 3
ENHFILTEN0
Bit 2
Bit 1 Bit 0
ENHFILT0
Reset
0x0500
ODR0
Table 12. Gain Register 0
Register
0x38
Name
GAIN0
Bits
[23:0]
Bits[23:0]
GAIN0
Reset
0x5XXXX0
R/W
R/W
Table 13. Offset Register 0
Register
0x30
Name
OFFSET0
Bits
[23:0]
Bits[23:0]
OFFSET0
Rev. A | Page 19 of 52
Reset
0x800000
R/W
R/W
R/W
R/W
AD4115
Data Sheet
Gain Registers
also select the standby and power-down modes, as well as any
of the calibration modes. The ADC mode register also contains
the clock source select bits and internal reference enable bit. The
reference select bits are contained in the setup configuration
registers (see the Setup Configuration section for more
information). The details of the ADC mode register are shown in
Table 14.
The gain registers are 24-bit, read and write registers that hold
the gain calibration coefficient for the ADC. The power-on reset
value of the gain registers is 0x5XXXX0.
Offset Registers
The offset registers are 24-bit, read and write registers that hold
the offset calibration coefficient for the ADC. The power-on
reset value of the offset registers is 0x800000.
Interface Mode Register
The interface mode register configures the digital interface
operation. This register allows the user to control data-word
length, CRC enable, data plus status read, and continuous read
mode. The details of this register are shown in Table 15. For
more information, see the Digital Interface section.
ADC Mode and Interface Mode Configuration
The ADC mode register and the interface mode register configure
the core peripherals for the AD4115 to use, as well as the mode
for the digital interface.
ADC Mode Register
The ADC mode register primarily sets the ADC conversion
mode to either continuous or single conversion. The user can
Table 14. ADC Mode Register
Register
0x01
Name
ADCMODE
Bits
[15:8]
[7:0]
Bit 7
REF_EN
Reserved
Bit 6
Reserved
Bit 5
SING_CYC
Mode
Bit 4
Bit 3
Bit 2
Reserved
CLOCKSEL
Bit 1
Bit 0
Delay
Reserved
Reset
0x2000
R/W
R/W
Table 15. Interface Mode Register
Register
0x02
Name
IFMODE
Bits
[15:8]
Bit 7
Bit 6
Reserved
[7:0]
CONTREAD
DATA_
STAT
Bit 5
REG_
CHECK
Bit 4
ALT_
SYNC
Reserved
Bit 3
IOSTRENGTH
Rev. A | Page 20 of 52
CRC_EN
Bit
Bit 1
2
Reserved
Reserved
Bit 0
DOUT_RESET
WL16
Reset
0x0000
R/W
R/W
Data Sheet
AD4115
NOISE PERFORMANCE AND RESOLUTION
Table 16 to Table 17 show the rms noise, peak-to-peak noise,
effective resolution, and noise free (peak-to-peak) resolution of the
device for various ODRs. These values are typical and are
measured with an external 2.5 V reference and with the ADC
continuously converting on multiple channels. The values in
Table 16 and Table 17 are generated for the ±10 V voltage input
range, with a differential input voltage of 0 V. Note that the
peak-to-peak resolution is calculated based on the peak-to-peak
noise. The peak-to-peak resolution represents the resolution for
which there is no code flicker.
Table 16. ±10 V Voltage Input RMS Noise Resolution vs. ODR Using a Sinc5 + Sinc1 Filter
Default Output Data Rate
(SPS), SING_CYC = 0 and
Single Channel Enabled
125,000
62,500
31,250
25,000
15,625
10,390
4994
2498
1000
500
395.5
200
100
59.87
49.92
20
16.7
10
5
2.5
1
2
Output Data Rate (SPS per
Channel), SING_CYC = 1 or
Multiple Channels Enabled
24,845
20,725
15,564
13,841
10,390
10,390
4,994
2,499
1,000
500
395.5
200
100
59.89
49.92
20.
16.66
10
5
2.5
Settling
Time 1
40.25 µs
48.25 µs
64.25 µs
72.25 µs
96.25 µs
96.25 µs
200.25 µs
400.25 µs
1 ms
2 ms
2.53 ms
5 ms
10 ms
16.7 ms
20.03 ms
50 ms
60.03 ms
100 ms
200 ms
400 ms
Notch
Frequency
(Hz)
125,000
62,500
31,250
25,000
15,625
15,625
5952.4
2717.4
1033.1
508.1
400.6
201.3
100.3
59.98
50
20.01
16.67
10
5
2.5
Noise
(µV rms) 2
140.36
124.42
99.14
89.57
72.94
71.01
45.67
32.42
20.24
13.88
12.61
9.702
7.36
5.38
5.52
4.52
4.07
3.15
2.92
2.49
Effective
Resolution
(Bits)
17.12
17.29
17.62
17.77
18.06
18.10
18.74
19.23
19.91
20.46
20.60
20.98
21.37
21.83
21.79
22.08
22.23
22.6
22.7
22.7
Noise
(µV p-p)
926.38
821.17
654.32
591.16
481.40
468.67
301.42
213.97
133.58
91.61
83.23
64.03
48.58
35.51
36.43
29.83
26.86
16.1
12.1
12
Peak-to-Peak
Resolution
(Bits)
14.40
14.57
14.90
15.05
15.34
15.38
16.02
16.51
17.19
17.74
17.87
18.25
18.65
19.10
19.07
19.35
19.51
20.2
20.7
20.7
The settling time is rounded to the nearest microsecond, which is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time.
The noise values are based on 1000 samples for data rates ≥ 395.5 SPS per channel and based on 100 samples for data rates ≤ 200 SPS per channel.
Table 17. ±10 V Voltage Input RMS Noise Resolution vs. ODR Using a Sinc3 Filter
Default Output Data
Rate (SPS), SING_CYC = 0
and Single Channel
Enabled
125,000
62,500
31,250
25,000
15,625
10,416.7
5000
2500
1000
500
400.6
200
100
59.98
50
Output Data Rate (SPS per
Channel), SING_CYC = 1 or
Multiple Channels Enabled
41,237
20,725
10,389.6
8,316.0
5,201.6
3,469.2
1,666.0
833.2
333.33
166.67
133.51
66.67
33.33
19.99
16.67
Settling
Time 1
24.3 µs
48.3 µs
96.3 µs
120.3 µs
192.3 µs
288.3 µs
600.3 µs
1.2 ms
3 ms
6 ms
7.49 ms
15 ms
30 ms
50.02 ms
60 ms
Notch
Frequency
(Hz)
125,000
62,500
31,250
25,000
15,625
10,417
5000
2500
1000
500.0
400.6
200.0
100.0
59.98
50.00
Rev. A | Page 21 of 52
Noise
(µV rms) 2
1008
176.41
82.49
73.71
57.99
46.93
31.45
22.83
14.35
10.82
9.66
7.30
5.81
4.70
4.48
Effective
Resolution
(Bits)
14.28
16.79
17.89
18.05
18.40
18.70
19.28
19.74
20.41
20.82
20.98
21.39
21.71
22.02
22.09
Noise
(µV p-p)
6652
1164
544.43
486.49
382.73
309.74
207.57
150.68
94.71
71.41
63.76
48.18
38.35
31.02
29.57
Peak-to-Peak
Resolution
(Bits)
11.55
14.07
15.16
15.33
15.67
15.98
16.56
17.02
17.69
18.10
18.26
18.66
18.99
19.30
19.37
AD4115
Default Output Data
Rate (SPS), SING_CYC = 0
and Single Channel
Enabled
20
16.67
10
5
2.5
1
2
Data Sheet
Output Data Rate (SPS per
Channel), SING_CYC = 1 or
Multiple Channels Enabled
6.67
5.56
3.33
1.67
0.83
Settling
Time 1
150 ms
180 ms
300 ms
600 ms
1.2 s
Notch
Frequency
(Hz)
20.00
16.67
10.00
5.00
2.50
Noise
(µV rms) 2
3.30
2.78
2.95
2.63
2.43
Effective
Resolution
(Bits)
22.53
22.78
22.7
22.7
22.7
Noise
(µV p-p)
21.78
18.35
14.9
11.9
11.9
Peak-to-Peak
Resolution
(Bits)
19.81
20.06
20.4
20.7
20.7
The settling time is rounded to the nearest microsecond, which is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time.
The noise values are based on 1000 samples for data rates ≥381 SPS per channel and based on 100 samples for data rates ≤200.3 SPS per channel.
Rev. A | Page 22 of 52
Data Sheet
AD4115
CIRCUIT DESCRIPTION
MULIPLEXER
resistors that enable an input range of ±20 V from a single 5 V
power supply.
The device has 17 voltage input pins, VIN0 to VIN15 and
VINCOM. Each pin connects to the internal multiplexer. The
multiplexer enables these inputs to be configured as input pairs.
The AD4115 can have up to 16 active channels. When more
than one channel is enabled, the channels are automatically
sequenced in order from the lowest enabled channel number to
the highest enabled channel number. The multiplexer output
connects to the input of the integrated true rail-to-rail buffers.
These buffers can be bypassed and the multiplexer output can
be directly connected to the ADC switched capacitor input. The
simplified input circuits are shown in Figure 25.
Enable the input buffers in the corresponding setup configuration
register for the voltage input channels (see Table 29).
Fully Differential Inputs
The differential inputs are paired together in the following
pairs: VIN0 and VIN1, VIN2 and VIN3, VIN4 and VIN5, VIN6
and VIN7, VIN8 and VIN9, VIN10 and VIN11, VIN12 and
VIN13, and VIN14 and VIN15.
Single-Ended Inputs
The user can measure up to 16 different single-ended voltage
inputs. In this case, each voltage input must be paired with the
VINCOM pin. Connect the VINCOM pin externally to the
AVSS pin.
VOLTAGE INPUTS
The AD4115 can be set up to have either 16 single-ended inputs
or eight fully differential inputs. The voltage divider on the AFE
has a division ratio of 10 and consists of precision matched
AVDD
222kΩ
VIN0
222kΩ
AVDD
222kΩ
MULTIPLEXER
1MΩ
+
AVSS
AVDD
VIN1
1MΩ
AVSS
AVDD
222kΩ
VBIAS–
–
222kΩ
222kΩ
AVSS
Figure 25. Simplified Voltage Input Circuit
Rev. A | Page 23 of 52
23874-015
VINCOM
1MΩ
AD4115
Data Sheet
ABSOLUTE INPUT PIN VOLTAGES
The AD4115 voltage input pins are specified for an accuracy of
±10 V, specifically for the differential voltage between any two
voltage input pins.
The voltage input pins have separate specifications for the
absolute voltage that can be applied, and the unique design of
the voltage divider network of the analog front end enables
overvoltage robustness on the AD4115, which means the
allowed overvoltages vary depending on the AVDD supply.
Figure 26 shows the different degrees of robustness that can be
achieved for AVDD = 5 V. Figure 26 provides a visual
representation and guidance on how an overvoltage on a
voltage pin can affect the overall device accuracy.
The guaranteed accuracy section of Figure 26 shows the voltage
range that can be applied to a voltage input pin and achieve
guaranteed accuracy.
The no loss of accuracy sections show the voltage levels that can
be applied without degrading the accuracy of other channels.
The no damage to device sections show the allowable positive
and negative voltages that can be applied to a voltage input pin
without exceeding the absolute maximum. The performance of
other channels is degraded, but the performance recovers when
the overvoltage is removed. This voltage range is specified as an
absolute maximum rating of ±65 V.
Operation beyond the maximum operating conditions for
extended periods can affect product reliability.
AVDD = 5V
+65V
ABSOLUTE MAXIMUM RATING
+30V
NO LOSS OF ACCURACY ON OTHER CHANNELS
+20V
GUARANTEED ACCURACY
–20V
NO LOSS OF ACCURACY ON OTHER CHANNELS
–25V
23874-222
NO DAMAGE TO DEVICE
ABSOLUTE MAXIMUM RATING
When the ADC is configured for bipolar operation, the output
code is offset binary with a negative full-scale voltage that results in
a code of 000 … 000, a zero differential input voltage that results
in a code of 100 … 000, and a positive full-scale input voltage
that results in a code of 111 … 111. The output code for any
analog input voltage is represented with the following equation:
Code = 2N – 1 × ((VIN × 0.1/VREF) + 1)
AD4115 REFERENCE OPTIONS
The AD4115 provides the reference option of either supplying
an external reference to the REF+ and REF− device pins using
AVDD – AVSS as the reference, or allowing use of the internal
2.5 V, low noise, low drift reference. To select the reference
source to be used by the analog input, set the REF_SELx bits,
Bits[5:4], in the corresponding setup configuration register
appropriately. The structure of the Setup Configuration Register 0
is shown in Table 10. By default, the AD4115 uses an external
reference on power-up.
Internal Reference
The AD4115 includes a low noise, low drift, internal voltage
reference that has a 2.5 V output. The internal reference is
output on the REFOUT pin after the REF_EN bit in the ADC
mode register is set and is decoupled to AVSS with a 0.1 μF
capacitor. The AD4115 internal reference is disabled by default
on power-up.
External Reference
NO DAMAGE TO DEVICE
–65V
where:
N = 24 (the number of bits).
VIN is the input voltage.
VREF is the reference voltage.
Figure 26. Absolute Input Pin Voltages, AVDD = 5 V
DATA OUTPUT CODING
When the ADC is configured for unipolar operation, the output
code is natural (straight) binary with a zero differential input
voltage that results in a code of 00 … 00, a midscale voltage that
results in a code of 100 … 000, and a full-scale input voltage
that results in a code of 111 … 111.
The output code for any input voltage is represented with the
following equation:
The AD4115 has a fully differential reference input applied
through the REF+ and REF− pins. Standard low noise, low drift
voltage references, such as the ADR4525, are recommended for
this use. Apply the external reference to the AD4115 reference
pins, as shown in Figure 27. Decouple the output of any external
reference to AVSS. As shown in Figure 27, the ADR4525 output
is decoupled with a 0.1 μF capacitor at the output for stability
purposes. The output is connected to a 4.7 μF capacitor that
acts as a reservoir for any dynamic charge required by the ADC
and is followed by another 0.1 μF decoupling capacitor at the
REF+ input. This capacitor is placed as close as possible to the
REF+ and REF− pins.
The REF− pin is connected directly to the AVSS potential. When
an external reference is used instead of the internal reference
to supply the AD4115, ensure that the REFOUT pin is not
hardwired to AVSS, which can draw a large current on powerup. The internal reference is controlled by the REF_EN bit (Bit 15)
in the ADC mode register, as shown in Table 14. If the internal
reference is not used elsewhere in the application, ensure that
the REF_EN bit is disabled.
Code = (2N × VIN × 0.1)/VREF
Rev. A | Page 24 of 52
Data Sheet
AD4115
AD4115
3V TO 18V
ADR45252
40 REF+
0.1µF
0.1µF
1
2.5V VREF
0.1µF
1
1
4.7µF
1
39 REF–
1
23874-016
1ALL DECOUPLING IS TO AVSS.
2ANY OF THE ADR45x FAMILY REFERENCES CAN BE USED.
ADR4525 ENABLES REUSE OF THE 3.3V ANALOG SUPPLY
NEEDED FOR AVDD TO POWER THE REFERENCE VIN.
Figure 27. ADR4525 Connected to AD4115 REF+ and REF− Pins
The AD4115 has true rail-to-rail, integrated, precision unitygain buffers on both ADC reference inputs. The buffers provide
high input impedance and allow high impedance external sources
to be directly connected to the reference inputs. The integrated
reference buffers can fully drive the internal reference switch
capacitor sampling network to simplify the reference circuit
requirements. Each reference input buffer amplifier is fully
chopped and minimizes the offset error drift and 1/f noise of the
buffer. When using a voltage reference, such as the ADR4525,
these buffers are not required because the reference has proper
decoupling and can drive the reference inputs directly.
CLOCK SOURCE
The AD4115 uses a nominal master clock of 8 MHz and can
source the device sampling clock from one of the following
three sources:
•
•
•
An internal oscillator.
An external crystal. Use a 16 MHz crystal automatically
divided internally to set the 8 MHz clock.
An external clock source.
All output data rates listed in this data sheet relate to a master
clock rate of 8 MHz. Using a lower clock frequency from, for
instance, an external source scales any listed data rate proportionally. To achieve the specified data rates, particularly rates
for rejection of 50 Hz and 60 Hz, use a 8 MHz clock. To select
the master clock source, set the CLOCKSEL bits (Bits[3:2]) in the
ADC mode register, as shown in Table 14. The default
operation on power-up and reset of the AD4115 is to operate
with the internal oscillator. The user can use the SINC3_MAPx
bits in the filter configuration registers to fine tune the output
data rate and filter notch at low output data rates.
output driver. The extent to which the performance is affected
depends on the IOVDD voltage supply. Higher IOVDD
voltages create a wider logic output swing from the driver and
affect performance to a greater extent. This effect is further
exaggerated if the IOSTRENGTH bit of the interface mode
register is set at higher IOVDD levels (see Table 23).
External Crystal
If higher precision, lower jitter clock sources are required, the
AD4115 can use an external crystal to generate the master clock.
The crystal connects to the XTAL1 and XTAL2/CLKIO pins. The
FA-20H, a 16 MHz, 10 ppm, 9 pF crystal from Epson-Toyocom
is available in a surface-mount package and is acceptable for this
use. As shown in Figure 28, insert two capacitors (CX1 and CX2)
from the traces connecting the crystal to the XTAL1 and XTAL2/
CLKIO pins. These capacitors allow circuit tuning. Connect these
capacitors to the DGND pin. The value for these capacitors
depends on the length and capacitance of the trace connections
between the crystal and the XTAL1 and XTAL2/CLKIO pins.
Therefore, the values of these capacitors differ depending on
the PCB layout and the crystal used.
AD4115
CX1
1
XTAL1 12
XTAL2/CLKIO 13
CX2
1
1DECOUPLE
TO DGND
23874-017
BUFFERED REFERENCE INPUT
Figure 28. External Crystal Connections
The internal oscillator runs at 16 MHz and is internally divided
down to 2 MHz for the modulator. The internal oscillator can
be used as the ADC master clock and is the default clock source
for the AD4115, which is specified with an accuracy of −2.5% to
+2.5%.
The external crystal circuitry can be sensitive to the SCLK edges
depending on the SCLK frequency, IOVDD voltage, crystal
circuitry layout, and the crystal used. During crystal startup, any
disturbances caused by the SLCK edges can cause double edges
on the crystal input, which results in invalid conversions until
the crystal voltage reaches a high enough level such that any
interference from the SCLK edges is insufficient to cause
double clocking. To avoid this double clocking, ensure that the
crystal circuitry reaches a sufficient voltage level after startup
before applying any serial clocks.
The internal clock oscillator can be output on the XTAL2/
CLKIO pin. In this case, the clock output is driven to the
IOVDD logic level. This option can affect the AD4115 dc
performance because of the disturbance introduced by the
Because of the nature of the crystal circuitry, it is recommended
to perform empirical testing of the circuit under the required
conditions with the final PCB layout and crystal to ensure
correct operation.
Internal Oscillator
Rev. A | Page 25 of 52
AD4115
Data Sheet
External Clock
The AD4115 can also use an externally supplied clock. In systems
where an externally supplied clock is used, the external clock is
routed to the XTAL2/CLKIO pin. In this configuration, the
XTAL2/ CLKIO pin accepts the externally sourced clock and
routes the clock input to the modulator. The logic level of this
clock input is defined by the voltage applied to the IOVDD pin.
Rev. A | Page 26 of 52
Data Sheet
AD4115
DIGITAL FILTER
The AD4115 has the following three flexible filter options to
optimize noise, settling time, and rejection:
•
•
•
Figure 31 shows the frequency domain filter response for the
sinc3 filter. The sinc3 filter has fast roll-off over frequency and
has wide notches for optimal notch frequency rejection.
The sinc5 + sinc1 filter.
The sinc3 filter.
Enhanced 50 Hz and 60 Hz rejection filters.
0
–10
–20
23874-018
SINC3
Figure 29. Digital Filter Block Diagram
–50
–60
–70
–80
–90
To configure the filter and output data rate, set the appropriate
bits in the filter configuration register for the selected setup. Each
channel can use a different setup and, therefore, a different
filter and output data rate. See the Register Details section for
more information.
SINC5 + SINC1 FILTER
The sinc5 + sinc1 filter is targeted at multiplexed applications
and achieves single-cycle settling at output data rates of
≤10 kSPS. The sinc5 block output is fixed at the maximum rate
of 125 kSPS, and the sinc1 block output data rate can be varied
to control the final ADC output data rate. Figure 30 shows the
frequency domain response of the sinc5 + sinc1 filter at a
50 SPS output data rate. The sinc5 + sinc1 filter has narrow
notches and a slow roll-off over frequency.
0
–20
FILTER GAIN (dB)
–40
–100
–110
–120
0
50
100
150
FREQUENCY (Hz)
23874-020
SINC1
SINC5
FILTER GAIN (dB)
–30
50Hz AND 60Hz
POSTFILTER
Figure 31. Sinc3 Filter Response
The output data rates with the accompanying settling time and
rms noise for the sinc3 filter are shown in Table 17. To fine tune
the output data rate for the sinc3 filter, set the SINC3_MAPx bit in
the appropriate filter configuration register. If this bit is set, the
filter register mapping changes to directly program the sinc3 filter
decimation rate. All other options are eliminated. To calculate the
data rate when on a single channel, use the following equation:
Output Data Rate = fMOD/(32 × FILTCONx[14:0])
where:
fMOD is the modulator rate (MCLK/2) and is equal to 4 MHz.
FILTCONx[14:0] is the contents of the filter configuration
registers with the MSB excluded.
For example, to achieve an output data rate of 50 SPS with the
SINC3_MAPx bit enabled, set the FILTCONx register,
Bits[14:0], to a value of 2500.
–40
–60
SINGLE-CYCLE SETTLING MODE
–80
–120
0
50
100
150
FREQUENCY (Hz)
23874-019
–100
Figure 30. Sinc5 + Sinc1 Filter Response at 50 SPS ODR
The output data rates with the accompanying settling time and
rms noise for the sinc5 + sinc1 filter are shown in Table 16.
SINC3 FILTER
The sinc3 filter achieves optimal single-channel noise performance
at lower rates and is most suitable for single-channel applications.
The sinc3 filter always has a settling time (tSETTLE) equal to the
following equation:
To configure the AD4115 to be in a single-cycle settling mode,
set the SING_CYC bit in the ADC mode register so that only
fully settled data is output. This mode reduces the output data
rate to be equal to the ADC settling time for the selected output
data rate to achieve single-cycle settling. This bit has no effect
on the sinc5 + sinc1 filter at output data rates of ≤10 kSPS or
when multiple channels are enabled.
Figure 32 shows a step on the analog input with single-cycle
settling mode disabled and the sinc3 filter selected. The analog
input requires at least three cycles after the step change for the
output to reach the final settled value.
tSETTLE = 3/Output Data Rate
Rev. A | Page 27 of 52
AD4115
Data Sheet
ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS
ANALOG
INPUT
FULLY
SETTLED
23874-021
ADC
OUTPUT
1/ODR
Figure 32. Step Input Without Single-Cycle Settling
Figure 33 shows the same step on the analog input with singlecycle settling enabled. The analog input requires at least a single
cycle for the output to be fully settled. The output data rate, as
indicated by the RDY signal, reduces to equal the settling time
of the filter at the selected output data rate.
ANALOG
INPUT
The enhanced filters provide rejection of 50 Hz and 60 Hz
simultaneously and allow the user to trade off settling time and
rejection. These filters can operate at up to 27.27 SPS or reject
up to 90 dB of 50 Hz ± 1 Hz and 60 Hz ± 1 Hz interference. These
filters postfilter the output of the sinc5 + sinc1 filter to operate.
For this reason, the user must select the sinc5 + sinc1 filter
when using the enhanced filters to achieve the specified settling
time and noise performance. Table 18 shows the enhanced
filter output data rates with the accompanying settling time,
rejection, and voltage input rms noise and resolution. Figure 34
to Figure 41 show the frequency domain plots of the responses
from the enhanced filters.
FULLY
SETTLED
23874-033
ADC
OUTPUT
tSETTLE
Figure 33. Step Input with Single Cycle Settling
Table 18. Enhanced Filter Output Data Rate, Settling Time, Rejection, and Voltage Input Noise
Output Data
Rate (SPS)
27.27
25
20
16.667
Simultaneous Rejection of 50 Hz
± 1 Hz and 60 Hz ± 1 Hz (dB)1
47
62
85
90
Noise
(µV rms)
6.44
6.09
5.54
5.38
Peak-to-Peak
Resolution (Bits)
19.1
19.2
19.35
19.51
Comments
See Figure 34 and Figure 37
See Figure 35 and Figure 38
See Figure 36 and Figure 39
See Figure 40 and Figure 41
Master clock = 2.00 MHz.
0
–10
–20
–20
–30
–30
–40
–50
–60
–40
–50
–60
–70
–70
–80
–80
–90
–90
–100
–100
0
100
200
300
400
500
FREQUENCY (Hz)
600
Figure 34. 27.27 SPS ODR, 36.67 ms Settling Time
0
100
200
300
400
500
FREQUENCY (Hz)
Figure 35. 25 SPS ODR, 40 ms Settling Time
Rev. A | Page 28 of 52
600
23874-023
FILTER GAIN (dB)
0
–10
23874-022
FILTER GAIN (dB)
1
Settling Time
(ms)
36.67
40
50
60
AD4115
0
–10
–10
–20
–20
–30
–30
–40
–50
–60
–50
–60
–70
–70
–80
–80
–90
–90
–100
200
300
400
500
600
FREQUENCY (Hz)
–100
40
–10
–10
–20
–20
–30
–30
FILTER GAIN (dB)
0
–40
–50
–60
–80
–90
–100
70
FREQUENCY (Hz)
23874-025
–90
–100
40
0
–20
–20
–30
–30
FILTER GAIN (dB)
0
–10
–40
–50
–60
–80
–90
–90
–100
40
–100
40
65
70
500
600
–60
–70
60
400
–50
–80
55
300
–40
–70
23874-026
FILTER GAIN (dB)
0
FREQUENCY (Hz)
200
Figure 40. 16.667 SPS ODR, 60 ms Settling Time
–10
50
100
FREQUENCY (Hz)
Figure 37. 27.27 SPS ODR, 36.67 ms Settling Time (40 Hz to 70 Hz)
45
70
–60
–80
65
65
–50
–70
60
60
–40
–70
55
55
Figure 39. 20 SPS ODR, 50 ms Settling Time (40 Hz to 70 Hz)
0
50
50
FREQUENCY (Hz)
Figure 36. 20 SPS ODR, 50 ms Settling Time
45
45
23874-028
100
Figure 38. 25 SPS ODR, 40 ms Settling Time (40 Hz to 70 Hz)
45
50
55
60
65
70
FREQUENCY (Hz)
Figure 41. 16.667 SPS ODR, 60 ms Settling Time (40 Hz to 70 Hz)
Rev. A | Page 29 of 52
23874-029
0
FILTER GAIN (dB)
–40
23874-027
FILTER GAIN (dB)
0
23874-024
FILTER GAIN (dB)
Data Sheet
AD4115
Data Sheet
OPERATING MODES
The AD4115 has nine operating modes that can be set from the
ADC mode register and interface mode register (see Table 22
and Table 23). These modes include the following:
•
•
•
•
•
•
Continuous conversion mode
Continuous read mode
Single conversion mode
Standby mode
Power-down mode
Four calibration modes
CONTINUOUS CONVERSION MODE
Continuous conversion mode (see Figure 42) is the default
power-up mode. The AD4115 converts continuously, and the
RDY bit in the status register goes low each time a conversion is
complete. If CS is low, the RDY output also goes low when a
conversion is complete. To read a conversion, write to the
communications register to indicate that the next operation is a
read of the data register. When the data-word is read from the
data register, the DOUT/RDY pin goes high. The user can read
this register additional times, if required. However, ensure that
the data register is not accessed at the completion of the next
conversion. Otherwise, the new conversion word is lost.
When several channels are enabled, the ADC automatically
sequences through the enabled channels and performs one
conversion on each channel. When all channels are converted,
the sequence starts again with the first channel. The channels
are converted in order from the lowest enabled channel to the
highest enabled channel. The data register updates as soon as
each conversion is available. The RDY output pulses low each
time a conversion is available and the user can then read the
conversion while the ADC converts the next enabled channel.
If the DATA_STAT bit in the interface mode register is set to 1,
the conversion data and the contents of the status register are
output each time the data register is read. The four LSBs of the
status register indicate the channel to which the conversion
corresponds.
CONTINUOUS READ MODE
In continuous read mode (see Figure 43), it is not required to
write to the communications register before reading ADC data.
Apply only the required number of serial clocks after the RDY
output goes low to indicate the end of a conversion. When the
conversion is read, the RDY output returns high until the next
conversion is available. In this mode, the data can be read only
once. Ensure that the data-word is read before the next
conversion is complete. If the user has not read the conversion
before the completion of the next conversion, or if insufficient
serial clocks are applied to the AD4115 to read the data-word,
the serial output register resets shortly before the next
conversion is complete, and the new conversion is placed in the
output serial register. The ADC must be configured for
continuous conversion mode to use continuous read mode. To
enable continuous read mode, set the CONTREAD bit in the
interface mode register. When this bit is set, the only serial
interface operations possible are reads from the data register. To
exit continuous read mode, issue a dummy read of the ADC data
register command (0x44) while the RDY output is low.
Alternatively, apply a software reset (64 serial clocks with CS = 0
and DIN = 1) to reset the ADC and all register contents. The
dummy read and the software reset are the only commands that
the interface recognizes after the interface is placed in
continuous read mode. Hold DIN low in continuous read mode
until an instruction is to be written to the device.
If multiple ADC channels are enabled, each channel is output
in turn with the status bits appended to the data if the
DATA_STAT bit is set in the interface mode register. The four
LSBs of the status register indicate the channel to which the
conversion corresponds.
SINGLE CONVERSION MODE
In single conversion mode (see Figure 44), the AD4115
performs a single conversion and is placed in standby mode
when the conversion is complete. The RDY output goes low to
indicate the completion of a conversion. When the data-word is
read from the data register, the RDY output goes high. The data
register can be read several times, if required, even when the
RDY output goes high.
If several channels are enabled, the ADC automatically
sequences through the enabled channels and performs a
conversion on each channel. When the first conversion starts,
the RDY output goes high and remains high until a valid
conversion is available and CS is low. When the conversion is
available, the RDY output goes low and the ADC selects the
next channel and begins a conversion. The user can read the
present conversion while the next conversion is performed.
When the next conversion is complete, the data register
updates, which allows the user a limited period in which to read
the conversion. When the ADC performs a single conversion
on each selected channel, the ADC returns to standby mode.
If the DATA_STAT bit in the interface mode register is set to 1,
the contents of the status register and the conversion are output
each time the data register is read. The four LSBs of the status
register indicate the channel to which the conversion corresponds.
Rev. A | Page 30 of 52
Data Sheet
AD4115
CS
0x44
0x44
DIN
DATA
DATA
23874-030
DOUT/RDY
SCLK
Figure 42. SPI Communication in Continuous Conversion Mode
CS
0x02
0x0080
DIN
DATA
DATA
DATA
23874-031
DOUT/RDY
SCLK
Figure 43. SPI Communication in Continuous Read Mode
CS
0x01
0x8010
0x44
DIN
DATA
23874-032
DOUT/RDY
SCLK
Figure 44. SPI Communication in Single Conversion Mode
Rev. A | Page 31 of 52
AD4115
Data Sheet
STANDBY MODE AND POWER-DOWN MODE
In standby mode, most blocks are powered down. The LDO
regulators remain active so that the registers maintain the
individual register contents. The crystal oscillator remains
active if selected. To power down the clock in standby mode,
set the CLOCKSEL bits in the ADC mode register to 00
(internal oscillator).
In power-down mode, all blocks are powered down, including
the LDO regulators. All registers lose the individual register
contents and the GPIO outputs are placed in three-state. To
prevent accidental entry into power-down mode, place the
ADC in standby mode first. Exiting power-down mode
requires a serial interface reset (64 serial clocks with CS = 0 and
DIN = 1). A delay of 500 µs is recommended before issuing a
subsequent serial interface command to allow the LDO
regulator to power up.
CALIBRATION MODES
The AD4115 allows the user to perform a two-point calibration
to eliminate any offset and gain errors. The following four
calibration modes are used to eliminate these offset and gain
errors on a per setup basis:
•
•
•
•
Internal zero-scale calibration mode
Internal full-scale calibration mode
System zero-scale calibration mode
System full-scale calibration mode
Only one channel can be active during calibration. After each
conversion, the ADC conversion result is scaled using the ADC
calibration registers before being written to the data register.
The default value of the offset register is 0x800000, and the
default value of the gain register is 0x5XXXX0. The following
equations show the calculations used to scale the ADC conversion
result. In unipolar mode, the ideal relationship (not considering
the ADC gain error and offset error) is calculated as follows:
Data = ((0.075 × VIN/VREF) × 223 – (Offset − 0x800000)) ×
(Gain/0x400000) × 2
In bipolar mode, the ideal relationship (not considering the
ADC gain error and offset error) is calculated as follows:
Data = ((0.075 × VIN/VREF) × 223 – (Offset − 0x800000)) ×
(Gain/0x400000) + 0x800000
To start a calibration, write the relevant value to the Mode bits
in the ADC mode register Bits[6:4]. The DOUT/RDY pin and
the RDY bit in the status register go high when the calibration
initiates. When the calibration is complete, the contents of the
corresponding offset or gain register update, the RDY bit in the
status register resets, the RDY output pin returns low (if CS is
low), and the AD4115 reverts to standby mode.
During an internal offset calibration both modulator inputs are
connected internally to the selected negative analog input pin,
and the user must ensure that the voltage on the selected negative
analog input pin does not exceed the allowed limits and is free
from excessive noise and interference. A full-scale input voltage
automatically connects to the ADC input to perform an
internal full-scale calibration.
For system calibrations, apply the system zero-scale (offset) and
system full-scale (gain) voltages to the input pins before
initiating the calibration modes. As a result, errors external to
the AD4115 are removed. The calibration range of the ADC
gain for a system full-scale calibration on a voltage input is
from 3.75 × VREF to 10.5 × VREF. If 10.5 × VREF is greater than the
absolute input voltage specification for the applied AVDD, use the
specification as the upper limit instead of 10.5 × VREF (see the
Specifications section).
An internal zero-scale calibration only removes the offset error
of the ADC core. This calibration does not remove error from
the resistive front end. A system zero-scale calibration reduces
the offset error to the order of the noise on that channel.
From an operational point of view, treat a calibration like
another ADC conversion. Always perform an offset calibration,
if required, before a full-scale calibration. Set the system
software to monitor the RDY bit in the status register or the
RDY output to determine the end of a calibration via a polling
sequence or an interrupt driven routine. All calibrations require
a time equal to the settling time of the selected filter and output
data rate to be completed.
Any calibration can be performed at any output data rate.
Lower output data rates result in higher calibration accuracy
and the calibration is accurate for all output data rates. A new
offset calibration is required for a given channel if the reference
source for that channel is changed.
The AD4115 provides access to the on-chip offset and gain
calibration registers to allow the microprocessor to read the
device calibration coefficients and to write the stored
calibration coefficients. A read or write of the offset and gain
registers can be performed at any time except during an
internal or self calibration.
Rev. A | Page 32 of 52
Data Sheet
AD4115
DIGITAL INTERFACE
The programmable functions of the AD4115 are accessible via
the SPI. The serial interface consists of four signals: CS, DIN,
SCLK, and DOUT/RDY. The DIN line transfers data into the
on-chip registers. The DOUT output accesses data from the onchip registers. SCLK is the serial clock input for the device. All
data transfers (either on DIN or on DOUT) occur with respect to
the SCLK signal.
The DOUT/RDY pin also functions as a data ready signal
where the line goes low if CS is low when a new data-word is
available in the data register. The pin resets high when a read
operation from the data register is complete. The RDY output
also goes high before updating the data register to indicate
when not to read from the device to ensure that a data read is
not attempted while the register is updated. Take care to avoid
reading from the data register when the RDY signal is about to
go low. To ensure that no data read occurs, always monitor the
RDY output. Start reading the data register as soon as RDY
goes low and ensure a sufficient SCLK rate such that the read is
completed before the next conversion result. CS is used to select a
device and can be used to decode the AD4115 in systems where
several components are connected to the serial bus.
The timing diagrams in Figure 2 and Figure 3 show interfacing
to the AD4115 using CS to decode the device. Figure 2 shows
the timing for a read operation from the AD4115, and Figure 3
shows the timing for a write operation to the AD4115. The user
can read from the data register several times even though the RDY
output returns high after the first read operation. Ensure that
the read operations are complete before the next output update
occurs. In continuous read mode, the data register can be read
only once.
To operate the serial interface in 3-wire mode, tie CS low. In
this case, the SCLK, DIN, and DOUT/RDY lines are used to
communicate with the AD4115. The end of the conversion can
also be monitored using the RDY bit in the status register.
CHECKSUM PROTECTION
The AD4115 has a checksum mode that can be used to improve
interface robustness. Use the checksum to ensure that only valid
data is written to a register and to allow the data read from a
register to be validated. If an error occurs during a register
write, the CRC_ERROR bit is set in the status register. To
ensure that the register write is complete, read back the register
and verify the checksum.
For CRC checksum calculations during a write operation, the
following polynomial is always used:
x8 + x2 + x + 1
During read operations, the user can select between this
polynomial and a similar exclusive OR (XOR) function. The
XOR function requires less time to process on the host
microcontroller than the polynomial-based checksum. The
CRC_EN bits in the interface mode register enable and disable
the checksum and allow the user to select between the
polynomial checksum and the simple XOR checksum.
The checksum is appended to the end of each read and write
transaction. The checksum calculation for the write transaction
is calculated using the 8-bit command word and the 8-bit to
24-bit data. For a read transaction, the checksum is calculated
using the command word and the 8-bit to 32-bit data output.
Figure 21 and Figure 22 show SPI write and read transactions,
respectively.
If checksum protection is enabled when continuous read mode
is active, an implied read data command of 0x44 occurs before
each data transmission, which must be accounted for when
calculating the checksum value. The checksum protection ensures
a nonzero checksum value even if the ADC data equals 0x000000.
To reset the serial interface, write 64 serial clocks with CS = 0
and DIN = 1. A reset returns the interface to the state in which the
interface expects a write to the communications register. This
operation resets the contents of all registers to the power-on values.
Following a reset, wait 500 µs before addressing the serial interface.
Rev. A | Page 33 of 52
AD4115
Data Sheet
CRC CALCULATION
Polynomial
The checksum, which is eight bits wide, is generated using the
following polynomial:
x8 + x2 + x + 1
To generate the checksum, the data is left shifted by eight bits
to create a number ending in eight Logic 0s. The polynomial is
aligned so that the MSB is adjacent to the leftmost Logic 1 of
the data. An XOR function is applied to the data to produce a
new, shorter number. The polynomial is aligned again so that the
Initial value
MSB is adjacent to the leftmost Logic 1 of the new result and
the procedure is repeated. This process is repeated until the
original data is reduced to a value less than the polynomial.
This value is the 8-bit checksum.
Example of a Polynomial CRC Calculation—24-Bit Word:
0x654321 (Eight Command Bits and 16-Bit Data)
An example of generating the 8-bit checksum using the
polynomial based checksum is as follows:
011001010100001100100001
x8 + x2 + x + 1 =
01100101010000110010000100000000
left shifted eight bits
100000111
polynomial
100100100000110010000100000000
XOR result
100000111
polynomial
100011000110010000100000000
XOR result
100000111
polynomial
11111110010000100000000
XOR result
100000111
polynomial value
1111101110000100000000
XOR result
100000111
polynomial value
111100000000100000000
XOR result
100000111
polynomial value
11100111000100000000
XOR result
100000111
polynomial value
1100100100100000000
XOR result
100000111
polynomial value
100101010100000000
XOR result
100000111
polynomial value
101101100000000
XOR result
100000111
polynomial value
1101011000000
XOR result
100000111
polynomial value
101010110000
XOR result
100000111
polynomial value
1010001000
XOR result
100000111
polynomial value
10000110
Rev. A | Page 34 of 52
checksum = 0x86.
Data Sheet
AD4115
XOR Calculation
01100101
0x65
The checksum, which is eight bits wide, is generated by splitting
the data into bytes and then performing an XOR of the bytes.
01000011
0x43
00100110
XOR result
Example of an XOR Calculation—24-Bit Word: 0x654321
(Eight Command Bits and 16-Bit Data)
00100001
0x21
00000111
CRC
Using the previous polynomial example, divide the checksum
into three bytes (0x65, 0x43, and 0x21) which results in the
following XOR calculation:
Rev. A | Page 35 of 52
AD4115
Data Sheet
INTEGRATED FUNCTIONS
GENERAL-PURPOSE INPUT/OUTPUT
DOUT_RESET
The AD4115 has two general-purpose digital input/output pins
(GPIO0 and GPIO1) and two general-purpose digital output
pins (GPO2 and GPO3). The GPIO0 and GPIO1 pins can be
configured either as inputs or as outputs, but GPO2 and GPO3
are outputs only. To enable the GPIOx and GPOx pins, use the
following bits in the GPIOCON register: IP_EN0 and IP_EN1
(or OP_EN0 and OP_EN1) for GPIO0 and GPIO1, and
OP_EN2_3 for GPO2 and GPO3.
The serial interface uses a shared DOUT/RDY pin. By default,
this pin outputs the signal. During a data read, this pin outputs
the data from the register being read. When the read is complete,
the pin reverts to output the RDY signal after a short fixed period
of time (t7). Note that this time may be too short for some
microcontrollers and can be extended until the CS pin is brought
high. Set the DOUT_RESET bit in the interface mode register
to 1 to extend the time and require that CS must frame each
read operation and complete the serial interface transaction.
When the GPIO0 or GPIO1 pin is enabled as an input, the logic
level at the pin is contained in the GP_DATA0 bit or
GP_DATA1 bit of the GPIOCON register, respectively. When
the GPIO0, GPIO1, GPO2, or GPO3 pin is enabled as an
output, the GP_DATA0, GP_DATA1, GP_DATA2, or
GP_DATA3 bit, respectively, determines the logic level output
at the pin. The logic levels for these pins are referenced to
AVDD and AVSS and the outputs have an amplitude of either
5 V or 3.3 V, depending on the AVDD − AVSS voltage.
The ERROR pin can also be used as a general-purpose output if
the ERR_EN bits in the GPIOCON register are set to 11. In this
configuration, the ERR_DAT bit in the GPIOCON register
determines the logic level output at the ERROR pin. The logic
level for the pin is referenced to IOVDD and DGND, and the
ERROR pin has an active pull-up.
EXTERNAL MULTIPLEXER CONTROL
If an external multiplexer is used to increase the channel count,
the multiplexer logic pins can be controlled using the AD4115
GPIOx and GPOx pins. When the MUX_IO bit is set in the
GPIOCON register, the timing of the GPIOx pins is controlled
by the ADC and the channel change is synchronized with the
ADC, which eliminates any need for external synchronization.
DELAY
The user can insert a programmable delay before the AD4115
starts to take samples. This delay allows an external amplifier or
multiplexer to settle and alleviates the specification requirements
for the external amplifier or multiplexer. Eight programmable
settings, ranging from 0 µs to 8 ms, can be set using the delay bits
in the ADC mode register (Register 0x01, Bits[10:8]).
16-BIT AND 24-BIT CONVERSIONS
By default, the AD4115 generates 24-bit conversions. However,
the width of the conversions can be reduced to 16 bits. Set
Bit WL16 in the interface mode register to 1 to round all data
conversions to 16 bits. Clear this bit to set the width of the data
conversions to 24 bits.
SYNCHRONIZATION
Normal Synchronization
When the SYNC_EN bit in the GPIOCON register is set to 1,
the SYNC pin functions as a synchronization input pin. The
SYNC input allows the user to reset the modulator and the digital
filter without affecting any setup conditions on the device. This
reset allows the user to start gathering samples of the analog
input from a known point in time, that is, the SYNC rising
edge. This pin must be low for at least one master clock cycle to
ensure that synchronization occurs. If multiple channels are
enabled, the sequencer is reset to the first enabled channel.
If multiple AD4115 devices are operated from a common master
clock, the devices can be synchronized so that the corresponding
data registers are updated simultaneously. Synchronization is
typically completed after each AD4115 performs a calibration or
when calibration coefficients are loaded into the device calibration
registers. A falling edge on the SYNC pin resets the digital filter
and the analog modulator and places the AD4115 into a consistent
known state. While the SYNC pin is low, the AD4115 remains in
this state. On the SYNC rising edge, the modulator and filter
are taken out of this reset state and the device starts to gather
input samples again on the next master clock edge.
The device exits reset on the master clock falling edge following
the SYNC low to high transition. Therefore, when multiple devices
are synchronized, take the SYNC pin high on the master clock
rising edge to ensure that all devices begin sampling on the
master clock falling edge. If the SYNC pin is not taken high in
sufficient time, a difference can occur of one master clock cycle
between the devices. That is, the instant at which conversions
are available differs from device to device by a maximum of one
master clock cycle.
The SYNC input can also be used as a start conversion
command for a single channel when in normal synchronization
mode. In this mode, the rising edge of the SYNC input starts a
conversion, and the falling edge of the RDY output indicates
when the conversion is complete. The settling time of the filter
is required for each data register update. When the conversion
is complete, bring the SYNC input low in preparation for the
next conversion start signal.
Rev. A | Page 36 of 52
Data Sheet
AD4115
Alternate Synchronization Mode
ERROR Input/Output
In alternate synchronization mode, the SYNC input operates as
a start conversion command when several AD4115 channels are
enabled. Set the ALT_SYNC bit in the interface mode register to 1
to enable an alternate synchronization scheme. When the
SYNC input is taken low, the ADC completes the conversion
on the enabled channel, selects the next channel in the
sequence, and then waits until the SYNC input is taken high to
start the conversion. The RDY output goes low when the
conversion is complete on the current channel, and the data
register is updated with the corresponding conversion. The
SYNC input does not interfere with the sampling on the
currently selected channel but allows the user to control the
instant at which the conversion begins on the next channel in
the sequence.
The ERROR pin functions as an error input/output pin or as a
general-purpose output pin. The ERR_EN bits in the
GPIOCON register determine the function of the pin.
Alternate synchronization mode can only be used when several
channels are enabled. Do not use this mode when a single
channel is enabled.
ERROR FLAGS
The status register contains three error bits (ADC_ERROR,
CRC_ERROR, and REG_ERROR) that flag errors in the ADC
conversion, errors in the CRC check, and errors caused by
changes in the registers, respectively. The ERROR output can
also indicate that an error has occurred.
ADC_ERROR
The ADC_ERROR bit in the status register flags any errors that
occur during the conversion process. The flag is set when an
overrange or underrange result is output from the ADC. The
ADC also outputs all 0s or all 1s when an undervoltage or
overvoltage occurs, respectively. This flag only resets when the
overvoltage or undervoltage is removed. This flag is not reset by
a read of the data register.
CRC_ERROR
If the CRC value that accompanies a write operation does not
correspond with the information sent, the CRC_ERROR flag is
set. The flag resets as soon as the status register is explicitly read.
REG_ERROR
The REG_ERROR flag is used in conjunction with the
REG_CHECK bit in the interface mode register. When the
REG_CHECK bit is set, the AD4115 monitors the values in
the on-chip registers. If a bit changes, the REG_ERROR bit is
set to 1. For writes to the on-chip registers, set the REG_CHECK
bit to 0. When the registers are updated, the REG_CHECK bit
can be set to 1. The AD4115 calculates a checksum of the on-chip
registers. If one register value has changed, the REG_ERROR bit is
set to 1. If an error is flagged, set the REG_CHECK bit to 0 to
clear the REG_ERROR bit in the status register. The register
check function does not monitor the data register, status
register, or interface mode register.
When the ERR_EN bits are set to 10, the ERROR pin functions as
an open-drain error output. The three error bits in the status
register (ADC_ERROR, CRC_ERROR, and REG_ERROR) are
OR’ed, inverted, and mapped to the ERROR output. Therefore, the
ERROR output indicates that an error has occurred. Read the
status register to identify the error source.
When the ERR_EN bits are set to 01, the ERROR pin functions
as an error input. The error output of another component can
be connected to the AD4115 ERROR input so that the AD4115
indicates when an error occurs on either the device or the
external component. The value on the ERROR input is inverted
and OR’ed with the errors from the ADC conversion, and the
result is indicated via the ADC_ERROR bit in the status register.
The value of the ERROR input is reflected in the ERR_DAT bit
in the GPIO configuration register.
The ERROR input/output is disabled when the ERR_EN bits are
set to 00. When the ERR_EN bits are set to 11, the ERROR pin
operates as a general-purpose output where the ERR_DAT bit
determines the logic level of the pin.
DATA_STAT FUNCTION
The contents of the status register can be appended to each
conversion on the AD4115 using the DATA_STAT bit in the
IFMODE register. This function is useful if several channels are
enabled. Each time a conversion is output, the contents of the
status register are appended. The four LSBs of the status register
indicate to which channel the conversion corresponds. In addition,
the user can determine if any errors are flagged by the error bits.
IOSTRENGTH FUNCTION
The serial interface can operate with a power supply as low as
2 V. However, at this low voltage, the DOUT/RDY pin may not
have sufficient drive strength if there is moderate parasitic
capacitance on the PCB or if the SCLK frequency is high. The
IOSTRENGTH bit in the interface mode register increases the
drive strength of the DOUT/RDY pin.
Rev. A | Page 37 of 52
AD4115
Data Sheet
INTERNAL TEMPERATURE SENSOR
The AD4115 has an integrated temperature sensor that can be
used as a guide for the ambient temperature at which the device
is operating. The ambient temperature can be used for
diagnostic purposes or as an indicator of when the application
circuit must rerun a calibration routine to consider a shift in
operating temperature. Select the temperature sensor using the
multiplexer in the same way as an input channel.
The temperature sensor requires the input buffers to be enabled on
both inputs and for the internal reference to be enabled.
To use the temperature sensor, calibrate the device in a known
temperature (25°C) and take a conversion as a reference point.
The temperature sensor has a nominal sensitivity of 477 μV/K.
The difference in this ideal slope and the slope measured
calibrates the temperature sensor. The temperature sensor is
specified with a ±2°C typical accuracy after calibration at 25°C.
Calculate the temperature with the following equation:
Temperature = (Conversion Result/477 µV) − 273.15
Rev. A | Page 38 of 52
Data Sheet
AD4115
APPLICATIONS INFORMATION
GROUNDING AND LAYOUT
The inputs and reference inputs are differential and most
voltages in the analog modulator are common-mode voltages. The
high common-mode rejection of the device removes commonmode noise on these inputs. The analog and digital supplies to
the AD4115 are independent and separately pinned out to
minimize coupling between the analog and digital sections of the
device. The digital filter provides rejection of broadband noise on
the power supplies, except at integer multiples of the master
clock frequency.
The digital filter also removes noise from the analog inputs
and reference inputs, provided that these noise sources do
not saturate the analog modulator. As a result, the AD4115 is
more immune to noise interference than a conventional high
resolution converter. However, because the resolution of the
AD4115 is high and the noise levels from the converter are low,
take care regarding grounding and layout.
The PCB that houses the ADC must be designed so that the
analog and digital sections are separated and confined to
certain areas of the PCB. A minimum etch technique is optimal
for ground planes and results in optimal shielding.
In any layout, the user must keep in mind the flow of currents
in the system to ensure that the paths for all return currents are
as close as possible to the paths that the currents took to reach
the corresponding destinations.
Avoid running digital lines under the device. This layout
couples noise onto the die and allows the analog ground plane
to run under the AD4115 to prevent noise coupling. The power
supply lines to the AD4115 must use as wide a trace as possible
to provide low impedance paths and reduce glitches on the
power supply line. Shield the fast switching signals, such as
clocks, with digital ground to prevent radiating noise to other
sections of the PCB and never run clock signals near the inputs.
Avoid digital and analog signal crossover. Run traces on
opposite sides of the PCB at right angles to each other. This
layout reduces the effects of feedthrough on the PCB. A
microstrip technique is optimal but is not always possible with
a double sided PCB. In this technique, the component side of
the PCB is dedicated to ground planes and signals are placed on
the solder side.
Ensure that proper decoupling is used when using high resolution
ADCs. The AD4115 has two power supply pins, AVDD and
IOVDD. The AVDD pin is referenced to AVSS, and the
IOVDD pin is referenced to DGND. Decouple AVDD with a
10 µF tantalum capacitor in parallel with a 0.1 µF capacitor to
AVSS on each pin. Place the 0.1 µF capacitor as close as possible
to the device on each supply, ideally directly against the device.
Decouple IOVDD with a 10 µF tantalum capacitor in parallel
with a 0.1 µF capacitor to DGND. Decouple all inputs to AVSS.
If an external reference is used, decouple the REF+ and REF−
pins to AVSS.
The AD4115 has two on-chip LDO regulators. One regulator
regulates the AVDD supply and the other regulates the IOVDD
supply. For the REGCAPA pin, use 1 µF and 0.1 µF capacitors
to decouple to AVSS. Similarly, for the REGCAPD pin, use a
1 µF capacitor to decouple to DGND.
Rev. A | Page 39 of 52
AD4115
Data Sheet
REGISTER SUMMARY
Table 19. Register Summary
Register Name
0x00
COMMS
Bits
[7:0]
Bit 7
WEN
Bit 6
R/W
0x00
Status
[7:0]
RDY
ADC_ERROR CRC_ERROR REG_ERROR
0x01
ADCMODE [15:8] REF_EN
[7:0] Reserved
IFMODE
[15:8]
Reserved
0x02
0x03
0x04
0x06
0x07
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
[7:0]
REGCHECK [23:16]
[15:8]
[7:0]
Data
[23:0]
[15:8]
[7:0]
GPIOCON [15:8]
[7:0]
ID
[15:8]
[7:0]
CH0
[15:8]
[7:0]
CH1
[15:8]
[7:0]
CH2
[15:8]
[7:0]
CH3
[15:8]
[7:0]
CH4
[15:8]
[7:0]
CH5
[15:8]
[7:0]
CH6
[15:8]
[7:0]
CH7
[15:8]
[7:0]
CH8
[15:8]
[7:0]
CH9
[15:8]
[7:0]
CH10
[15:8]
[7:0]
CH11
[15:8]
[7:0]
CH12
[15:8]
[7:0]
CH13
[15:8]
[7:0]
CH14
[15:8]
[7:0]
CH15
[15:8]
[7:0]
SETUPCON0 [15:8]
[7:0]
SETUPCON1 [15:8]
[7:0]
Reserved
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
0x00
R/W
W
Channel
0x80
R
Delay
Reserved
Reserved
DOUT_
RESET
Reserved
WL16
0x2000
R/W
0x0000
R/W
RA
SING_CYC
Mode
Reserved
ALT_SYNC
CLOCKSEL
IOSTRENGTH
CONTREAD
DATA_STAT REG_CHECK Reserved
CRC_EN
REGISTER_CHECK[23:16]
REGISTER_CHECK[15:8]
REGISTER_CHECK[7:0]
Data[23:16]
Data[15:8]
Data[7:0]
Reserved
OP_EN2_3 MUX_IO
SYNC_EN
ERR_EN
ERR_DAT
GP_DATA3
GP_DATA2 IP_EN1
IP_EN0
OP_EN1
OP_EN0 GP_DATA1
GP_DATA0
ID[15:8]
ID[7:0]
CH_EN0
SETUP_SEL0
Reserved
INPUT0[9:8]
INPUT0[7:0]
CH_EN1
SETUP_SEL1
Reserved
INPUT1[9:8]
INPUT1[7:0]
CH_EN2
SETUP_SEL2
Reserved
INPUT2[9:8]
INPUT2[7:0]
CH_EN3
SETUP_SEL3
Reserved
INPUT3[9:8]
INPUT3[7:0]
CH_EN4
SETUP_SEL4
Reserved
INPUT4[9:8]
INPUT4[7:0]
CH_EN5
SETUP_SEL5
Reserved
INPUT5[9:8]
INPUT5[7:0]
CH_EN6
SETUP_SEL6
Reserved
INPUT6[9:8]
INPUT6[7:0]
CH_EN7
SETUP_SEL7
Reserved
INPUT7[9:8]
INPUT7[7:0]
CH_EN8
SETUP_SEL8
Reserved
INPUT8[9:8]
INPUT8[7:0]
CH_EN9
SETUP_SEL9
Reserved
INPUT9[9:8]
INPUT9[7:0]
CH_EN10
SETUP_SEL10
Reserved
INPUT10[9:8]
Input10[7:0]
CH_EN11
SETUP_SEL11
Reserved
INPUT11[9:8]
INPUT11[7:0]
CH_EN12
SETUP_SEL12
Reserved
INPUT12[9:8]
INPUT12[7:0]
CH_EN13
SETUP_SEL13
Reserved
INPUT13[9:8]
INPUT13[7:0]
CH_EN14
SETUP_SEL14
Reserved
INPUT14[9:8]
INPUT14[7:0]
CH_EN15
SETUP_SEL15
Reserved
INPUT15[9:8]
INPUT15[7:0]
Reserved
BI_UNIPOLAR0 REFBUF0+ REFBUF0−
INBUF0
Reserved
REF_SEL0
Reserved
Reserved
BI_UNIPOLAR1 REFBUF1+ REFBUF1−
INBUF1
Reserved
REF_SEL1
Reserved
Rev. A | Page 40 of 52
0x000000 R
0x000000 R
0x0800
R/W
0x38DX
R
0x8001
R/W
0x0001
R/W
0x0001
R/W
0x0001
R/W
0x0001
R/W
0x0001
R/W
0x0001
R/W
0x0001
R/W
0x0001
R/W
0x0001
R/W
0x0001
R/W
0x0001
R/W
0x0001
R/W
0x0001
R/W
0x0001
R/W
0x0001
R/W
0x1000
R/W
0x1000
R/W
Data Sheet
Register Name
Bits
0x22
SETUPCON2 [15:8]
[7:0]
0x23
SETUPCON3 [15:8]
[7:0]
0x24
SETUPCON4 [15:8]
[7:0]
0x25
SETUPCON5 [15:8]
[7:0]
0x26
SETUPCON6 [15:8]
[7:0]
0x27
SETUPCON7 [15:8]
[7:0]
0x28
FILTCON0 [15:8]
[7:0]
0x29
FILTCON1 [15:8]
[7:0]
0x2A
FILTCON2 [15:8]
[7:0]
0x2B
FILTCON3 [15:8]
[7:0]
0x2C
FILTCON4 [15:8]
[7:0]
0x2D
FILTCON5 [15:8]
[7:0]
0x2E
FILTCON6 [15:8]
[7:0]
0x2F
FILTCON7 [15:8]
[7:0]
0x30
OFFSET0
[23:0]
0x31
OFFSET1
[23:0]
0x32
OFFSET2
[23:0]
0x33
OFFSET3
[23:0]
0x34
OFFSET4
[23:0]
0x35
OFFSET5
[23:0]
0x36
OFFSET6
[23:0]
0x37
OFFSET7
[23:0]
0x38
GAIN0
[23:0]
0x39
GAIN1
[23:0]
0x3A
GAIN2
[23:0]
0x3B
GAIN3
[23:0]
0x3C
GAIN4
[23:0]
0x3D
GAIN5
[23:0]
0x3E
GAIN6
[23:0]
0x3F
GAIN7
[23:0]
AD4115
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Reserved
BI_UNIPOLAR2 REFBUF2+
Reserved
REF_SEL2
Reserved
BI_UNIPOLAR3 REFBUF3+
Reserved
REF_SEL3
Reserved
BI_UNIPOLAR4 REFBUF4+
Reserved
REF_SEL4
Reserved
BI_UNIPOLAR5 REFBUF5+
Reserved
REF_SEL5
Reserved
BI_UNIPOLAR6 REFBUF6+
Reserved
REF_SEL6
Reserved
BI_UNIPOLAR7 REFBUF7+
Reserved
REF_SEL7
SINC3_MAP0
Reserved
ENHFILTEN0
Reserved
ORDER0
SINC3_MAP1
Reserved
ENHFILTEN1
Reserved
ORDER1
SINC3_MAP2
Reserved
ENHFILTEN2
Reserved
ORDER2
SINC3_MAP3
Reserved
ENHFILTEN3
Reserved
ORDER3
SINC3_MAP4
Reserved
ENHFILTEN4
Reserved
ORDER4
SINC3_MAP5
Reserved
ENHFILTEN5
Reserved
ORDER5
SINC3_MAP6
Reserved
ENHFILTEN6
Reserved
ORDER6
SINC3_MAP7
Reserved
ENHFILTEN7
Reserved
ORDER7
OFFSET0[23:0]
OFFSET1[23:0]
OFFSET2[23:0]
OFFSET3[23:0]
OFFSET4[23:0]
OFFSET5[23:0]
OFFSET6[23:0]
OFFSET7[23:0]
GAIN0[23:0]
GAIN1[23:0]
GAIN2[23:0]
GAIN3[23:0]
GAIN4[23:0]
GAIN5[23:0]
GAIN6[23:0]
GAIN7[23:0]
Rev. A | Page 41 of 52
Bit 2
Bit 1
Bit 0
REFBUF2−
INBUF2
Reserved
REFBUF3−
INBUF3
Reserved
REFBUF4−
INBUF4
Reserved
REFBUF5−
INBUF5
Reserved
REFBUF6−
INBUF6
Reserved
REFBUF7−
INBUF7
Reserved
ENHFILT0
ODR0
ENHFILT1
ODR1
ENHFILT2
ODR2
ENHFILT3
ODR3
ENHFILT4
ODR4
ENHFILT5
ODR5
ENHFILT6
ODR6
ENHFILT7
ODR7
Reset
0x1000
R/W
R/W
0x1000
R/W
0x1000
R/W
0x1000
R/W
0x1000
R/W
0x1000
R/W
0x0500
R/W
0x0500
R/W
0x0500
R/W
0x0500
R/W
0x0500
R/W
0x0500
R/W
0x0500
R/W
0x0500
R/W
0x800000
0x800000
0x800000
0x800000
0x800000
0x800000
0x800000
0x800000
0x5XXXX0
0x5XXXX0
0x5XXXX0
0x5XXXX0
0x5XXXX0
0x5XXXX0
0x5XXXX0
0x5XXXX0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
AD4115
Data Sheet
REGISTER DETAILS
COMMUNICATIONS REGISTER
Address: 0x00, Reset: 0x00, Name: COMMS
All access to the on-chip registers must start with a write to the communications register. This write determines which register is
accessed next and whether that operation is a write or a read.
Table 20. Bit Descriptions for COMMS
Bits
7
Bit Name
WEN
6
R/W
Settings
0
1
[5:0]
RA
000000
000001
000010
000011
000100
000110
000111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
Description
This bit must be low to begin communications with the ADC.
Reset
0x0
Access
W
This bit determines if the command is a read or write operation.
Write command.
Read command.
The register address bits determine the register to be read from or
written to as part of the current communication.
Status register.
ADC mode register.
Interface mode register.
Register checksum register.
Data register.
GPIO configuration register.
ID register.
Channel Register 0.
Channel Register 1.
Channel Register 2.
Channel Register 3.
Channel Register 4.
Channel Register 5.
Channel Register 6.
Channel Register 7.
Channel Register 8.
Channel Register 9.
Channel Register 10.
Channel Register 11.
Channel Register 12.
Channel Register 13.
Channel Register 14.
Channel Register 15.
Setup Configuration Register 0.
Setup Configuration Register 1.
Setup Configuration Register 2.
Setup Configuration Register 3.
Setup Configuration Register 4.
Setup Configuration Register 5.
Setup Configuration Register 6.
Setup Configuration Register 7.
Filter Configuration Register 0.
Filter Configuration Register 1.
Filter Configuration Register 2.
Filter Configuration Register 3.
Filter Configuration Register 4.
Filter Configuration Register 5.
Filter Configuration Register 6.
Filter Configuration Register 7.
0x0
W
0x00
W
Rev. A | Page 42 of 52
Data Sheet
Bits
Bit Name
AD4115
Settings
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
Description
Offset Register 0.
Offset Register 1.
Offset Register 2.
Offset Register 3.
Offset Register 4.
Offset Register 5.
Offset Register 6.
Offset Register 7.
Gain Register 0.
Gain Register 1.
Gain Register 2.
Gain Register 3.
Gain Register 4.
Gain Register 5.
Gain Register 6.
Gain Register 7.
Reset
Access
STATUS REGISTER
Address: 0x00, Reset: 0x80, Name: Status
The status register is an 8-bit register that contains ADC and serial interface status information. The register can optionally be appended
to the data register by setting the DATA_STAT bit in the interface mode register.
Table 21. Bit Descriptions for STATUS
Bits
7
Bit Name
RDY
Settings
0
1
6
ADC_ERROR
0
1
5
CRC_ERROR
0
1
4
REG_ERROR
0
1
Description
The status of RDY is output to the DOUT/RDY pin when CS is low and a
register is not being read. This bit goes low when the ADC writes a new
result to the data register. In ADC calibration modes, this bit goes low
when the ADC writes the calibration result. RDY is brought high
automatically by a read of the data register.
New data result available.
Awaiting new data result.
By default, this bit indicates if an ADC overrange or underrange occurred.
The ADC result is clamped to 0xFFFFFF for overrange errors and 0x000000
for underrange errors. This bit is updated when the ADC result is written
and is cleared at the next update after removing the overrange or
underrange condition.
No error.
Error.
This bit indicates if a CRC error occurred during a register write. For
register reads, the host microcontroller determines if a CRC error
occurred. This bit is cleared by a read of this register.
No error.
CRC error.
This bit indicates if the content of one of the internal registers changes
from the value calculated when the register integrity check is activated.
The check is activated by setting the REG_CHECK bit in the interface
mode register. This bit is cleared by clearing the REG_CHECK bit.
No error.
Error.
Rev. A | Page 43 of 52
Reset
0x1
Access
R
0x0
R
0x0
R
0x0
R
AD4115
Bits
[3:0]
Bit Name
Channel
Data Sheet
Settings
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Description
These bits indicate which channel was active for the ADC conversion
whose result is currently in the data register. This channel may be
different from the channel currently being converted. The mapping is a
direct map from the channel register. Therefore, Channel 0 results in 0x0
and Channel 15 results in 0xF.
Channel 0.
Channel 1.
Channel 2.
Channel 3.
Channel 4.
Channel 5.
Channel 6.
Channel 7.
Channel 8.
Channel 9.
Channel 10.
Channel 11.
Channel 12.
Channel 13.
Channel 14.
Channel 15.
Reset
0x0
Access
R
ADC MODE REGISTER
Address: 0x01, Reset: 0x2000, Name: ADCMODE
The ADC mode register controls the operating mode of the ADC and the master clock selection. A write to the ADC mode register resets
the filter and the RDY bits and starts a new conversion or calibration.
Table 22. Bit Descriptions for ADCMODE
Bits
15
Bit Name
REF_EN
Settings
0
1
14
13
Reserved
SING_CYC
0
1
[12:11]
[10:8]
Reserved
Delay
000
001
010
011
100
101
110
111
7
Reserved
Description
Enables internal reference and outputs a buffered 2.5 V to the REFOUT
pin.
Disabled.
Enabled.
This bit is reserved. Set this bit to 0.
This bit can be used when only a single channel is active to set the ADC to
only output at the settled filter data rate.
Disabled.
Enabled.
These bits are reserved. Set these bits to 0.
These bits allow a programmable delay to be added after a channel
switch to allow the settling of external circuitry before the ADC starts
processing its input.
0 µs.
8 µs.
32 µs.
80 µs.
200 µs.
400 µs.
1 ms.
2 ms.
This bit is reserved. Set this bit to 0.
Rev. A | Page 44 of 52
Reset
0x0
Access
R/W
0x0
0x1
R/W
R/W
0x0
0x0
R
R/W
0x0
R
Data Sheet
Bits
[6:4]
Bit Name
Mode
AD4115
Settings
000
001
010
011
100
101
110
111
[3:2]
CLOCKSEL
00
01
10
11
[1:0]
Reserved
Description
These bits control the operating mode of the ADC. See the Operating
Modes section for more information.
Continuous conversion mode.
Single conversion mode.
Standby mode.
Power-down mode.
Internal offset calibration.
Internal gain calibration
System offset calibration.
System gain calibration.
These bits select the ADC clock source. Selecting the internal oscillator
also enables the internal oscillator.
Internal oscillator.
Internal oscillator output on the XTAL2/CLKIO pin.
External clock input on the XTAL2/CLKIO pin.
External crystal on the XTAL1 pin and the XTAL2/CLKIO pin.
These bits are reserved. Set these bits to 0.
Reset
0x0
Access
R/W
0x0
R/W
0x0
R
Reset
0x0
0x0
Access
R
R/W
0x0
R/W
0x0
0x0
R
R/W
0x0
R/W
0x0
R/W
INTERFACE MODE REGISTER
Address: 0x02, Reset: 0x0000, Name: IFMODE
The interface mode register configures various serial interface options.
Table 23. Bit Descriptions for IFMODE
Bits
[15:13]
12
Bit Name
Reserved
ALT_SYNC
Settings
0
1
11
IOSTRENGTH
0
1
[10:9]
8
Reserved
DOUT_RESET
0
1
7
CONTREAD
0
1
6
DATA_STAT
0
1
Description
These bits are reserved. Set these bits to 0.
This bit enables a different behavior of the SYNC pin to allow the use of
SYNC as a control for conversions when cycling channels.
Disabled.
Enabled.
This bit controls the drive strength of the DOUT/RDY pin. Set this bit when
reading from the serial interface at high speed with a low IOVDD supply
and moderate capacitance.
Disabled (default).
Enabled.
These bits are reserved. Set these bits to 0.
See the DOUT_RESET section.
Disabled.
Enabled.
This bit enables the continuous read mode of the ADC data register. The ADC
must be configured in continuous conversion mode to use continuous
read mode. For more details, see the Operating Modes section.
Disabled.
Enabled.
This bit enables the status register to be appended to the data register
when read so that channel and status information are transmitted with
the data. Appending the status register is the only way to be sure that the
channel bits read from the status register correspond to the data in the
data register.
Disabled.
Enabled.
Rev. A | Page 45 of 52
AD4115
Bits
5
Bit Name
REG_CHECK
Data Sheet
Settings
0
1
4
[3:2]
Reserved
CRC_EN
00
01
10
1
0
Reserved
WL16
0
1
Description
This bit enables a register integrity checker that can be used to monitor
any change in the value of the user registers. To use this feature, configure all
other registers as desired with this bit cleared. Then, write to this register to
set the REG_CHECK bit to 1. If the contents of any of the registers change,
the REG_ERROR bit is set in the status register. To clear the error, set the
REG_CHECK bit to 0. Neither the interface mode register nor the ADC data
or status register is included in the registers that are checked. If a register must
have a new value written, this bit must first be cleared. Otherwise, an error
is flagged when the new register contents are written.
Disabled.
Enabled.
This bit is reserved. Set this bit to 0.
These bits enable CRC protection of register reads/writes. CRC increases
the number of bytes in a serial interface transfer by one.
Disabled.
XOR checksum enabled for register read transactions. Register writes still
use CRC with these bits set.
CRC checksum enabled for read and write transactions.
This bit is reserved. Set this bit to 0.
This bit changes the ADC data register to 16 bits. The ADC is not reset by a
write to the interface mode register. Therefore, the ADC result is not
rounded to the correct word length immediately after writing to these
bits. The first new ADC result is correct.
24-bit data.
16-bit data.
Reset
0x0
Access
R/W
0x0
0x00
R
R/W
0x0
0x0
R
R/W
REGISTER CHECK
Address: 0x03, Reset: 0x000000, Name: REGCHECK
The register check register is a 24-bit checksum calculated by exclusively OR'ing the contents of the user registers. The REG_CHECK bit
in the interface mode register must be set for this checksum to operate. Otherwise, the register reads 0.
Table 24. Bit Descriptions for REGCHECK
Bits
[23:0]
Bit Name
REGISTER_CHECK
Settings
Description
This register contains the 24-bit checksum of user registers when the
REG_CHECK bit is set in the interface mode register.
Reset
0x000000
Access
R
DATA REGISTER
Address: 0x04, Reset: 0x000000, Name: Data
The data register contains the ADC conversion result. The encoding is offset binary, or it can be changed to unipolar by the
BI_UNIPOLARx bits in the setup configuration registers. Reading the data register brings the RDY bit and the RDY output high if it is low.
The ADC result can be read multiple times. However, because the RDY output is brought high, it is not possible to determine if another
ADC result is imminent. After the command to read the ADC register is received, the ADC does not write a new result into the data
register.
Table 25. Bit Descriptions for Data
Bits
[15:0]
Bit Name
Data
Settings
Description
This register contains the ADC conversion result. If DATA_STAT is set in
the interface mode register, the status register is appended to this
register when read, making this a 32-bit register.
Rev. A | Page 46 of 52
Reset
0x000000
Access
R
Data Sheet
AD4115
GPIO CONFIGURATION REGISTER
Address: 0x06, Reset: 0x0800, Name: GPIOCON
The GPIO configuration register controls the general-purpose I/O pins of the ADC.
Table 26. Bit Descriptions for GPIOCON
Bits
[15:14]
13
Bit Name
Reserved
OP_EN2_3
Settings
0
1
12
MUX_IO
11
SYNC_EN
0
1
[10:9]
ERR_EN
00
01
10
11
8
ERR_DAT
0
1
7
GP_DATA3
0
1
6
GP_DATA2
0
1
Description
Reserved.
GPO2/GPO3 output enable. This bit enables the GPO2 and GPO3 pins. The outputs
are referenced between AVDD and AVSS.
Disabled.
Enabled.
This bit allows the ADC to control an external multiplexer, using GPIO0, GPIO1,
GPO2, and GPO3 in sync with the internal channel sequencing. The analog input
pins used for a channel can still be selected on a per channel basis. Therefore, it is
possible to have a 16-channel multiplexer in front of each analog input pair
(VIN0/VIN1 to VIN14/VIN15), giving a total of 128 differential channels. However,
only 16 channels at a time can be automatically sequenced. Following the sequence
of 16 channels, the user changes the analog input to the next pair of input channels,
and it sequences through the next 16 channels. There is a delay function that allows
extra time for the analog input to settle, in conjunction with any switching of an
external multiplexer (see the delay bits in the ADC mode register).
SYNC input enable. This bit enables the SYNC pin as a sync input. When set low, the
SYNC pin holds the ADC and filter in reset until SYNC goes high. An alternative
operation of the SYNC pin is available when the ALT_SYNC bit in the interface mode
register is set. This mode works only when multiple channels are enabled. In such cases, a
low on the SYNC pin does not immediately reset the filter/modulator. Instead, if the
SYNC pin is low when the channel is due to be switched, the modulator and filter are
prevented from starting a new conversion. Bringing SYNC high begins the next
conversion. This alternative sync mode allows SYNC to be used while cycling
through channels.
Disabled.
Enabled.
ERROR pin mode. These bits enable the ERROR pin as an error input/output.
Disabled.
Enable error input (active low). ERROR is an error input. The inverted readback state
is OR'ed with other error sources and is available in the ADC_ERROR bit in the status
register. The ERROR pin state can also be read from the ERR_DAT bit in this register.
Enable open-drain error output (active low). ERROR is an open-drain error output.
The status register error bits are OR'ed, inverted, and mapped to the ERROR pin.
ERROR pins of multiple devices can be wired together to a common pull-up resistor
so that an error on any device can be observed.
General-purpose output (active low). ERROR is a general-purpose output. The status
of the pin is controlled by the ERR_DAT bit in this register. This output is referenced
between IOVDD and DGND, as opposed to the AVDD and AVSS levels used by the
GPIOx and GPOx pins. The output has an active pull-up resistor in this case.
ERROR pin data. This bit determines the logic level at the ERROR pin if the pin is
enabled as a general-purpose output. This bit reflects the readback status of the pin
if the pin is enabled as an input.
Logic 0.
Logic 1.
GPIO1 data. This bit is the write data for GPIO1.
GPIO1 = 0.
GPIO1 = 1.
GPIO0 data. This bit is the write data for GPIO0.
GPIO0 = 0.
GPIO0 = 1.
Rev. A | Page 47 of 52
Reset
0x0
0x0
Access
R
R/W
0x0
R
0x1
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
AD4115
Bits
5
Bit Name
IP_EN1
Data Sheet
Settings
Description
This bit runs GPIO1 into an input. Input is equal to AVDD and AVSS.
Disabled.
Enabled.
This bit runs GPIO0 into an input. Input is equal to AVDD and AVSS.
Disabled.
Enabled.
This bit runs GPIO1 into an output. Outputs are referenced between AVDD and AVSS.
Disabled.
Enabled.
This bit runs GPIO0 into an output. Outputs are referenced between AVDD and AVSS.
Disabled.
Enabled.
This bit is the readback or write data for GPIO1.
This bit is the readback or write data for GPIO0.
0
1
4
IP_EN0
0
1
3
OP_EN1
0
1
2
OP_EN0
0
1
1
0
GP_DATA1
GP_DATA0
Reset
0x0
Access
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
0x0
R/W
R/W
ID REGISTER
Address: 0x07, Reset: 0x38DX, Name: ID
The ID register returns a 16-bit ID. For the AD4115, this value is 0x38DX, where x is don’t care.
Table 27. Bit Descriptions for ID
Bits
[15:0]
Bit Name
ID
Settings
Description
Product ID. The ID register returns a 16-bit ID code that is specific to the ADC.
Reset
0x38DX
Access
R
CHANNEL REGISTER 0 TO CHANNEL REGISTER 15
Address: 0x10 to 0x1F, Reset: 0x8001, Name: CH0 to CH15
The channel registers are 16-bit registers that select the currently active channels, the selected inputs for each channel, and the setup to
be used to configure the ADC for that channel. The layout for CH0 to CH15 is identical.
Table 28. Bit Descriptions for CH0 to CH15
Bits
15
Bit Name
CH_ENx
Settings
0
1
[14:12]
SETUP_SELx
000
001
010
011
100
101
110
111
[11:10]
[9:0]
Reserved
INPUTx
0000000001
0000010000
Description
This bit enables Channel x. If more than one channel is enabled, the ADC
automatically sequences between them.
Disabled.
Enabled.
These bits identify which of the eight setups is used to configure the ADC for
this channel. A setup comprises a set of four registers: a setup configuration register,
a filter configuration register, an offset register, and a gain register. All channels can
use the same setup, in which case the same 3-bit value must be written to these
bits on all active channels, or up to eight channels can be configured differently.
Setup 0.
Setup 1.
Setup 2.
Setup 3.
Setup 4.
Setup 5.
Setup 6.
Setup 7.
Reserved.
These bits select which input pair is connected to the input of the ADC for this
channel.
VIN0, VIN1.
VIN0, VINCOM.
Rev. A | Page 48 of 52
Reset
0x1
Access
R/W
0x0
R/W
0x0
0x1
R
R/W
Data Sheet
Bits
Bit Name
AD4115
Settings
0000100000
0000110000
0001000011
0001010000
0001100010
0001110000
0010000101
0010010000
0010100100
0010110000
0011000111
0011010000
0011100110
0011110000
0100001001
0100010000
0100101000
0100110000
0101001011
0101010000
0101101010
0101110000
0110001101
0110010000
0110101100
0110110000
0111001111
0111010000
0111101110
0111110000
1000110010
1010110110
Description
VIN1, VIN0.
VIN1, VINCOM.
VIN2, VIN3.
VIN2, VINCOM.
VIN3, VIN2.
VIN3, VINCOM.
VIN4, VIN5.
VIN4, VINCOM.
VIN5, VIN4.
VIN5, VINCOM.
VIN6, VIN7.
VIN6, VINCOM.
VIN7, VIN6.
VIN7, VINCOM.
VIN8, VIN9.
VIN8, VINCOM.
VIN9, VIN8.
VIN9, VINCOM.
VIN10, VIN11.
VIN10, VINCOM.
VIN11, VIN10.
VIN11, VINCOM.
VIN12, VIN13.
VIN12, VINCOM.
VIN13, VIN12.
VIN13, VINCOM.
VIN14, VIN15.
VIN14, VINCOM.
VIN15, VIN14.
VIN15, VINCOM.
Temperature sensor.
Reference.
Reset
Access
SETUP CONFIGURATION REGISTER 0 TO SETUP CONFIGURATION REGISTER 7
Address: 0x20 to 0x27, Reset: 0x1000 Name: SETUPCON0 to SETUPCON7
The setup configuration registers are 16-bit registers that configure the reference selection, input buffers, and output coding of the ADC.
The layout for SETUPCON0 to SETUPCON7 is identical.
Table 29. Bit Descriptions for SETUPCON0 to SETUPCON7
Bits
[15:13]
12
Bit Name
Reserved
BI_UNIPOLARx
Settings
0
1
11
REFBUFx+
0
1
10
REFBUFx−
0
1
Description
These bits are reserved. Set these bits to 0.
Bipolar/unipolar. This bit sets the output coding of the ADC for Setup x.
Unipolar coded output.
Bipolar coded output.
REF+ buffer. This bit enables or disables the REF+ input buffer.
Disabled.
Enabled.
REF− buffer. This bit enables or disables the REF− input buffer.
Disabled.
Enabled.
Rev. A | Page 49 of 52
Reset
0x0
0x1
Access
R
R/W
0x0
R/W
0x0
R/W
AD4115
Bits
[9:8]
Bit Name
INBUFx
Data Sheet
Settings
00
01
10
11
[7:6]
[5:4]
Reserved
REF_SELx
00
10
11
[3:0]
Reserved
Description
Input buffer. This bit enables or disables input buffers.
Disabled.
Reserved.
Reserved.
Enabled.
These bits are reserved. Set these bits to 0.
These bits allow the user to select the reference source for ADC conversion on
Setup 0.
External reference, REF±.
Internal 2.5 V reference, must be enabled via ADCMODE (see Table 22).
AVDD − AVSS.
These bits are reserved. Set these bits to 0.
Reset
0x0
Access
R/W
0x0
0x0
R
R/W
0x0
R
FILTER CONFIGURATION REGISTER 0 TO FILTER CONFIGURATION REGISTER 7
Address: 0x28 to 0x2F, Reset: 0x0500, Name: FILTCON0 to FILTCON7
The filter configuration registers are 16-bit registers that configure the ADC data rate and filter options. Writing to any of these registers resets
any active ADC conversion and restarts converting at the first channel in the sequence. The layout for FILTCON0 to FILTCON7 is identical.
Table 30. Bit Descriptions for FILTCON0 to FILTCON7
Bits
15
Bit Name
SINC3_MAPx
[14:12]
11
Reserved
ENHFILTENx
Settings
0
1
[10:8]
ENHFILTx
010
011
101
110
7
[6:5]
Reserved
ORDERx
00
11
[4:0]
ODRx
00000
00001
00010
00011
00100
00101
00110
00111
Description
If this bit is set, the mapping of the filter register changes to directly
program the decimation rate of the sinc3 filter for Setup x. All other
options are eliminated. This bit allows fine tuning of the output data
rate and filter notch for rejection of specific frequencies. The data
rate when on a single channel equals fMOD/(32 × FILTCON0[14:0]).
These bits are reserved. Set these bits to 0.
This bit enables various postfilters for enhanced 50 Hz/60 Hz
rejection for Setup x. The ORDERx bits must be set to 00 to select the
sinc5 + sinc1 filter for this function to work.
Disabled.
Enabled.
These bits select between various postfilters for enhanced 50 Hz/
60 Hz rejection for Setup x.
27 SPS, 47 dB rejection, 36.7 ms settling.
25 SPS, 62 dB rejection, 40 ms settling.
20 SPS, 86 dB rejection, 50 ms settling.
16.67 SPS, 92 dB rejection, 60 ms settling.
This bit is reserved. Set this bit to 0.
These bits control the order of the digital filter that processes the
modulator data for Setup x.
Sinc5 + sinc1 (default).
Sinc3.
These bits control the output data rate of the ADC and, therefore, the
settling time and noise for Setup x. Rates shown are for a single-channel
enabled sinc5 + sinc 1 filter. See Table 16 for multiple channels
enabled.
125,000 SPS.
125,000 SPS.
62,500 SPS.
62,500 SPS.
31,250 SPS.
25,000 SPS.
15,625 SPS.
10390 (10416.7 SPS for sinc3).
Rev. A | Page 50 of 52
Reset
0x0
Access
R/W
0x0
0x0
R
R/W
0x5
R/W
0x0
0x0
R
R/W
0x0
R/W
Data Sheet
Bits
Bit Name
AD4115
Settings
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
Description
4994 (5000 SPS for sinc3).
2498 (2500 SPS for sinc3).
1000.00 SPS.
500.00 SPS.
395.5 (400.6 SPS for sinc3).
200.00 SPS.
100.00 SPS.
59.87 SPS.
49.92 SPS (50 SPS for sinc3).
20 SPS.
16.67 SPS.
10 SPS.
5 SPS.
2.5 SPS.
2.5 SPS.
Reset
Access
OFFSET REGISTER 0 TO OFFSET REGISTER 7
Address: 0x30 to 0x37, Reset: 0x800000, Name: OFFSET0 to OFFSET7
The offset (zero-scale) registers are 16-bit registers that can be used to compensate for any offset error in the ADC or in the system. The
layout for OFFSET0 to OFFSET7 is identical.
Table 31. Bit Descriptions for OFFSET0 to OFFSET7
Bits
[23:0]
Bit Name
OFFSETx
Settings
Description
Offset calibration coefficient for Setup x.
Reset
0x800000
Access
R/W
GAIN REGISTER 0 TO GAIN REGISTER 7
Address: 0x38 to0x3F, Reset: 0x5XXXX0, Name: GAIN0 to GAIN7
The full-scale gain registers are 16-bit registers that can be used to compensate for any gain error in the ADC or in the system. The layout
for GAIN0 to GAIN7 is identical.
Table 32. Bit Descriptions for GAIN0 to GAIN7
Bits
[23:0]
1
Bit Name
GAINx
Settings
Description
Gain calibration coefficient for Setup x.
X means don’t care.
Rev. A | Page 51 of 52
Reset 1
0x5XXXX0
Access
R/W
AD4115
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
0.30
0.25
0.18
P IN 1
IN D IC ATO R AR E A OP T IO N S
(SEE DETAIL A)
40
31
1
30
0.50
BSC
4.70
4.60 SQ
4.50
EXPOSED
PAD
TOP VIEW
1.00
0.95
0.85
SIDE VIEW
PKG-003653/5050
SEATING
PLANE
0.45
0.40
0.35
21
11
20
10
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-5
02-05-2019-C
6.10
6.00 SQ
5.90
PIN 1
INDICATOR
AREA
Figure 45. 40-Lead Lead Frame Chip Scale Package [LFCSP]
6 mm × 6 mm Body and 0.95 mm Package Height
(CP-40-15)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD4115BCPZ
AD4115BCPZ-RL7
EVAL-AD4115SDZ
EVAL-SDP-CB1Z
1
Temperature Range
−40°C to +105°C
−40°C to +105°C
Package Description
40-Lead Lead Frame Chip Scale Package [LFCSP]
40-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Evaluation Controller Board
Z = RoHS Compliant Part.
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D023874-11/20(A)
Rev. A | Page 52 of 52
Package Option
CP-40-15
CP-40-15
工商网监
湘ICP备2023018690号
