Data Sheet
AD4130-8
32 μA, Ultra Low Power, 24-Bit Sigma-Delta ADC with Integrated PGA and FIFO
FEATURES
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On-chip bias voltage generator for thermocouples
► Low-side power switch for bridge transducers
► Sensor open wire detection
Internal temperature sensor and oscillator
Self and system calibration
Flexible filter options
Simultaneous 50 Hz/60 Hz rejection (on selected filter options)
General-purpose outputs
Diagnostic functionality
Crosspoint multiplexed inputs
► 8 differential/16 pseudo differential inputs
5 MHz SPI (3-wire or 4-wire)
Available in 35-ball, 2.74 mm × 3.6 mm WLCSP
Temperature range: −40°C to +105°C
►
Ultralow current consumption (typical):
► 32 µA: continuous conversion mode (gain = 128)
► 5 µA: duty cycling mode (ratio = 1/16)
► 0.5 µA: standby mode
► 0.1 µA: power-down mode
Built-in features for system level power savings:
► Current saving duty cycle ratio: 1/4 or 1/16
► Smart sequencer and per channel configuration minimizes
host processor load
► Deep embedded FIFO minimizes host processor load (depth
of 256 samples)
► Autonomous FIFO interrupt functionality, threshold detection
► Single supply as low as 1.71 V increasing battery length
RMS noise: 25 nV rms at 1.17 SPS (gain = 128) – 48 nV/√Hz
Up to 22 noise free bits (gain = 1)
Output data rate: 1.17 SPS to 2.4 kSPS
Operates from 1.71 V to 3.6 V single supply or ±1.8 V split
supplies
Band gap reference with 15 ppm/°C maximum drift
PGA with rail-to-rail analog input
Adaptable sensor interfacing functionality:
► Matched programmable excitation currents for RTDs
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APPLICATIONS
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Smart transmitters
Wireless battery and harvester powered sensor nodes
Portable instrumentation
Temperature measurement: thermocouple, RTD, thermistors
Pressure measurement: bridge transducers
Healthcare and wearables
FUNCTIONAL BLOCK DIAGRAM
Figure 1. Functional Block Diagram
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Data Sheet
AD4130-8
TABLE OF CONTENTS
Features................................................................ 1
Applications........................................................... 1
Functional Block Diagram......................................1
General Description...............................................4
Companion Products..........................................4
Specifications........................................................ 5
ADC and AFE Specifications..............................5
Analog Input Specifications................................ 6
Reference Specifications....................................6
Sensor Biasing Specifications............................ 7
Diagnostics Specifications..................................8
Rejection Specifications..................................... 8
Logic Input and Output Specifications................9
Power Specifications........................................ 10
Timing Specifications....................................... 12
Absolute Maximum Ratings.................................18
Thermal Characteristics................................... 18
Electrostatic Discharge (ESD) Ratings.............18
ESD Caution.....................................................18
Pin Configuration and Function Descriptions...... 19
Typical Performance Characteristics................... 22
Offset Error and Gain Error.............................. 22
INL Error and Oscillator....................................23
Noise................................................................ 24
Analog Input Currents...................................... 25
Supply Currents................................................27
Reference Input Currents................................. 28
Internal Reference and Temperature Sensor... 29
Excitation Currents........................................... 30
Resolution........................................................ 31
FFT...................................................................32
Terminology......................................................... 33
Analog Input..................................................... 33
ADC..................................................................33
Reference.........................................................33
Temperature Sensor.........................................33
Noise and Resolution.......................................... 35
2.5 V Reference............................................... 35
1.25 V Reference............................................. 37
Noise Spectral Density..................................... 40
Theory of Operation.............................................41
Overview.......................................................... 41
ADC Core......................................................... 41
ADC Master Clock............................................42
ADC Reference................................................ 42
Analog Front End............................................. 42
Programmable Gain Amplifier.......................... 44
Other Features................................................. 45
Power Supplies................................................ 45
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Power-Down Modes......................................... 46
Digital Interface....................................................47
Accessing the Register Map.............................47
Device Reset.................................................... 48
ADC Configuration and Operations..................... 49
Bipolar/Unipolar Configuration......................... 49
Status Bits........................................................ 49
Smart Channel Sequencer............................... 50
ADC Conversion Modes...................................51
Data Ready Signal........................................... 53
Continuous Read Mode....................................53
System Synchronization...................................55
ADC Calibration................................................55
Digital Filters........................................................58
Sinc3 and Sinc4 Filters......................................58
Averaging Filters.............................................. 58
Post Filters....................................................... 58
Output Data Rate............................................. 59
50 Hz and 60 Hz Rejection...............................60
Sequencer........................................................ 61
Diagnostics.......................................................... 66
Signal Chain Check..........................................66
Reference Detection.........................................66
ADC Errors....................................................... 66
Overvoltage/Undervoltage Detection............... 66
Power Supply Monitors.................................... 67
Master Clock Counter.......................................67
SPI Diagnostics................................................ 67
CRC Protection................................................ 67
FIFO Diagnostics..............................................68
Burnout Currents.............................................. 68
Temperature Sensor.........................................69
Diagnostics and Standby Mode........................69
FIFO.................................................................... 70
FIFO Modes..................................................... 70
FIFO Readback................................................ 71
FIFO Interrupt...................................................74
Clearing the FIFO.............................................75
Applications Information...................................... 76
Power Schemes............................................... 76
Recommended Decoupling.............................. 76
Input Filters.......................................................76
Microprocessor Interfacing............................... 76
Unused Pins..................................................... 76
Power-Up and Initialization...............................77
Layout and Grounding......................................77
Assembly Guidelines........................................77
AD4130-8 Registers............................................ 78
AD4130-8 Register Summary.......................... 78
Rev. 0 | 2 of 108
Data Sheet
AD4130-8
TABLE OF CONTENTS
Registers Details.............................................. 80
Outline Dimensions........................................... 108
Ordering Guide...............................................108
Evaluation Boards.......................................... 108
REVISION HISTORY
5/2022—Revision 0: Initial Version
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Rev. 0 | 3 of 108
Data Sheet
AD4130-8
GENERAL DESCRIPTION
The AD4130-8 is an ultra low power, high precision, measurement
solution for low bandwidth battery operated applications. The fully
integrated analog front end (AFE) includes a multiplexer for up
to 16 single-ended or eight differential inputs, programmable gain
amplifier (PGA), 24-bit sigma-delta (Σ-Δ) analog-to-digital converter
(ADC), on-chip reference and oscillator, selectable filter options,
smart sequencer, sensor biasing and excitation options, diagnostics, and newly added features to improve the battery-operated
lifetime (more than 5 years on a coin cell), that is, a first in, first out
(FIFO) buffer and duty cycling.
The AD4130-8 allows users to measure low frequency signals
with a current consumption of 28.5 μA (gain = 1) and 32.5 μA
(gain = 128) while continuously converting, and even lower average
currents when using one of the duty cycling options. The AD4130-8
can be configured to have 8 differential inputs or 16 single-ended or
pseudo differential inputs, which connect to a crosspoint multiplexer, where any input pair can become a measurement channel input
to the PGA and ADC.
The AD4130-8 is designed to allow the user to operate from a
single analog supply voltage from 1.71 V to 3.6 V. In battery
applications, operation as low as 1.71 V can extend the system
lifetime as the AFE can continue its operation, even as the battery
voltage dissipates. The digital supply can be separate and range
from 1.65 V to 3.6 V.
Together with the reduced current consumption, the integration of
an on-chip FIFO buffer can be used in tandem with the smart
sequencer, to enable the AD4130-8 to become an autonomous
measurement system, which allows the microcontroller to sleep for
extended periods.
Intelligent interrupt functionality gives the user a greater confidence
in both error detection and safety. The user can enable an interrupt
signal to trigger when the samples in the FIFO reach a predefined
value or when a user programmable threshold is exceeded.
The following key analog functions are offered on the AD4130-8
to allow simple and effective connection to transducers used for
measuring temperature, load, and pressure:
The low-side power switch (PDSW) can be used to power down
bridge sensors between conversions. The PDSW can be controlled within the sequencer on a per channel basis, allowing
optimum timing and energy savings in the overall system. The
PDSW can also allow higher powered analog sensors to be used
in a low power system.
► Voltage bias for thermocouples (the VBIAS source sets the
common-mode voltage of a channel to AVDD/2).
► The smart sequencer allows the conversion of each enabled
preconfigured channel in a predetermined order, allowing a mix
of transducer, system checks and diagnostic measurements to
be interleaved. The sequencer eliminates need for repetitive
serial interface communication with the device. Sixteen channels
can be configured in the sequence, each of them selecting from
eight predefined ADC setups that allow selection of gain, filter
type, output data rate, buffering, timing, and reference source.
►
High levels of integrated front-end functionality coupled with small
package options allow smaller end solutions. For example, the
AD4130-8 integrates a low thermal drift band gap reference in
addition to accepting an external differential reference, which can
be internally buffered.
In safety critical applications the AD4130-8 includes diagnostic
functionality such as open wire detection via burnout currents,
internal temperature sensor, reference detection, and analog input
overvoltage and undervoltage detection. Added diagnostics are
included on the digital interface like cyclic redundancy check (CRC)
and serial interface checks for a robust communication link.
COMPANION PRODUCTS
Low Noise, Low Dropout Regulators: ADP150ACBZ‑3.3 and
ADP150ACBZ‑1.8
► Regulated Charge-Pump Inverters: LTC1983ES6‑3 and
ADP7182AUJZ‑1.8
► Voltage Reference: ADR391
► Low Power Microcontrollers: MAX32670 (precision), MAX32655
(BLE), MAX32663A (ECG)
►
PGA. Due to the programmable gain (from 1 to 128) and the
high input impedance with low input current, the PGA allows
direct interfacing to transducers with low output amplitudes like
resistive bridges, thermocouples, and resistance temperature
detectors (RTDs).
► The capacitive PGA allows full common-mode input range, giving designers greater margin for widely varying input common
modes. A wider common-mode input range improves the overall
resolution and is highly effective in ratio metric measurements.
► Low drift precision current sources. The IEXC0 and IEXC1 current source can be used to excite 2‑, 3‑, and 4‑wire RTDs.
Excitation current output options include 100 nA, 10 μA, 20 μA,
50 μA, 100 μA, 150 μA, and 200 μA.
►
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Rev. 0 | 4 of 108
Data Sheet
AD4130-8
SPECIFICATIONS
AVDD = 1.71 V to 3.6 V, IOVDD = 1.65 V to 3.6 V, AVSS = DGND = 0 V, REFIN1(+) = 2.5 V (for AVDD − AVSS ≥ 2.7 V), REFIN1(+) = 1.25 V
(for AVDD − AVSS < 2.7 V), REFIN1(−) = AVSS, internal master clock (MCLK) (MCLK frequency (fMCLK) = 76.8 kHz), PGA enabled (default),
reference buffers bypassed (default), temperature range = TMIN to TMAX, and decoupling as per the Recommended Decoupling section, unless
otherwise noted.
ADC AND AFE SPECIFICATIONS
Table 1. ADC and AFE Specifications
Parameter1
Min
SAMPLING DYNAMICS
Output Data Rate (ODR)
Active Time2
1.17
STATIC PERFORMANCE
No Missing Codes2
Resolution and Update Rate2
RMS Noise and Update Rate2
Noise Spectral Density2
Integral Nonlinearity (INL)2
Unit
Test Conditions/Comments
2400
SPS
See the Output Data Rate section
Continuous conversion mode
DUTY_CYC_RATIO = 1/43
DUTY_CYC_RATIO = 1/163
Bits
Bits
ppm of FSR1
ppm of FSR1
FS4 > 2, sinc4 filter
FS4 > 8, sinc3 filter
See the Noise and Resolution section
See the Noise and Resolution section
See the Noise and Resolution section
Gain = 1
Gain > 15
µV
µV
µV
Gain = 1, PGA bypass7
Gain = 1 to 16
Gain = 32 to 128
30
(140/gain) + 90
nV/°C
nV/°C
Gain = 1, PGA bypass7
Gain = 1 to 128
+0.015
Gain = 110, TA = 25°C
Gain = 1, PGA bypass7
Gain > 1
0.12
%
%
%
%
1
2
3
ppm/°C
ppm/°C
ppm/°C
Gain = 1, PGA bypass7
Gain = 1 to 16
Gain = 32 to 128
24
24
−5
−15
±2
±4
±2
±10
±2
In order of noise
3
120/gain
After Internal and System Calibration
Offset Error Drift vs. Temperature8
After Internal Calibration11
After System Calibration11
Gain Error Drift vs. Temperature
Max
100%
25%
6.25%
Offset Error6
Before Calibration
Gain Error6, 9
Before Calibration
Typ
−0.015
−0.12
0.5
0.5
0.01
In order of noise
0.1
0.1
0.1
+5
+15
1
See the Terminology section.
2
These specifications are not production tested but are supported by characterization data at the initial product release.
3
Duty cycling mode is enabled by setting MODE = 0b1001 in the ADC_CONTROL register. The DUTY_CYC_RATIO bit can be found in the same register. See the Duty
Cycling Mode and Duty Cycling Mode Timing sections.
4
FS is the decimal equivalent of the FS, Bits[10:0] in the filter registers.
5
The nonlinearity for gain > 1 is production tested for gain = 32 and voltage reference (VREF )= 2.5 V. For the other conditions, this specification is supported by
characterization data at the initial product release.
6
Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system full-scale
calibration reduces the gain error to the order of the noise for the programmed gain and output data rate.
7
PGA_BYP_n = 1. The PGA_BYP_n bit can be found in each CONFIG_n register. See the Programmable Gain Amplifier section for more details.
8
Recalibration at any temperature removes these errors.
9
Gain error applies to both positive and negative full-scale. A factory calibration is performed at gain = 1 and TA = 25°C (PGA_BYP_n = 0).
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Rev. 0 | 5 of 108
Data Sheet
AD4130-8
SPECIFICATIONS
Table 1. ADC and AFE Specifications
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
10
This gain error is factory calibrated at ambient temperature and at a gain of 1 (PGA_BYP_n = 0).
11
CAL_RANGE_X2 = 1 for VREF > 2 V. The CAL_RANGE_X2 bit can be found in the MISC register. See the Internal Gain Calibration section for more details.
ANALOG INPUT SPECIFICATIONS
Table 2. Analog Input Specifications
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
ANALOG INPUT VOLTAGE2
Differential Input Voltage Ranges
Absolute Analog Input (AIN) Voltage Limits
ANALOG INPUT CURRENT2
Absolute Input Current
Gain = 1
Gain = 1
Gain > 1
Differential Input Current
Gain = 1
Gain = 1
Gain > 1
Analog Input Current Drift
Gain = 1, Gain > 1
Gain = 1
SYSTEM CALIBRATION2
Calibration Limits
Full Code
Zero Code
Input Span
±VREF/gain
AVDD + 0.05
V
V
±0.5
±2.5
±0.5
+3
nA
nA
nA
PGA bypass4
±0.5
±1.5
±0.5
+3
nA
nA
nA
PGA bypass4
AVSS − 0.05
−3
−1
−3
−1
VREF = REFIN1(+) – REFIN1(−), or internal
reference
PGA on3
+1
+1
2
2
15
pA/°C
pA/°C
1.05 × VREF/gain
−1.05 × VREF/gain
0.8 × VREF/gain
2.1 × VREF/gain
V
V
V
1
See the Terminology section.
2
These specifications are not production tested but are supported by characterization data at the initial product release.
PGA bypass4
DATA = 0xFFFFFF
DATA = 0x000000
3
PGA_BYP_n = 0, when VREF > (AVDD − AVSS – 200 mV), the input differential range cannot exceed (AVDD − AVSS – 200 mV)/gain.
4
PGA_BYP_n = 1. The PGA_BYP_n bit can be found in each CONFIG_n register. See the Programmable Gain Amplifier section for more details.
REFERENCE SPECIFICATIONS
Table 3. Reference Specifications
Parameter1
Min
Typ
Max
Unit
REFERENCE OUTPUT
Initial Accuracy
Output Current Load Capability
Load Regulation Sourcing and Sinking
2.5
1.25
2
2
±1
90
Power Supply Rejection
Output Voltage Noise (0.1 Hz to 10 Hz)
95
40
Temperature Coefficient (TC) (Drift)2
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2.5 − 0.2%
1.25 – 0.45%
2.5 + 0.2%
1.25 + 0.45%
15
15
V
V
ppm/°C
ppm/°C
mA
μV/mA
dB
µV p-p
Test Conditions/Comments
Internal reference enabled, load capacitance
(CL) = 1 nF
TA = 25°C
TA = 25°C
TA = −40°C to + 105°C, VREF = 2.5 V
TA = −40°C to +105°C, VREF = 1.25 V
Change in output voltage (ΔVOUT)/change in output
current (ΔILOAD)
TA = 25°C
Rev. 0 | 6 of 108
Data Sheet
AD4130-8
SPECIFICATIONS
Table 3. Reference Specifications
Parameter1
Min
Output Voltage Noise Density
Turn On Settling Time
REFERENCE INPUTS
External REFIN Voltage2
Absolute REFINx pins Voltage Limits2
Typ
Max
800
280
0.5
AVSS − 0.05
AVSS + 0.1
Reference Input Current
Absolute Input Current
−11
−4
±7
±0.2
10
1.6
Reference Input Current Drift2
Normal Mode Rejection
Common-Mode Rejection
Unit
Test Conditions/Comments
nV/√Hz
µs
TA = 25°C
TA = 25°C
Reference input (REFIN) = REFIN1(+) – REFIN1(−)
AVDD − AVSS
AVDD + 0.05
AVDD – 0.1
V
V
V
+11
+4
21
20
nA
nA
pA/°C
pA/°C
90
Reference buffers disabled3
Reference buffers enabled3
Reference buffers disabled3
Reference buffers enabled3
Reference buffers disabled3
Reference buffers enabled3
Same as for analog inputs
dB
1
See the Terminology section.
2
These specifications are not production tested but are supported by characterization data at the initial product release.
3
The REF_BUFP_n and REF_BUFM_n bits can be found in each CONFIG_n register. See the Reference Buffers section for more details.
SENSOR BIASING SPECIFICATIONS
Table 4. Sensor Biasing Specifications
Parameter1
Min
EXCITATION CURRENT SOURCES
(IEXC0 and IEXC1)
Output Current
Initial Tolerance
Current Drift2
Current Matching2, 3
Max
Unit
−1.6
−3.2
Line Regulation
Load Regulation
10/20/50/100/
150/200/0.1
±1
50
±0.5
±1
3
5
0.1
0.3
0.1
2.5
AVSS + 0.05
LOW-SIDE POWER SWITCH2
On Resistance (RON)
Allowable Current
+1.6
+3.2
25
60
AVDD − 0.27
µA
Selectable on a per channel basis
%
ppm/°C
%
%
ppm/°C
ppm/°C
%/V
%/V
%/V
%/V
V
TA = 25°C
10 μA/20 μA/50 μA/100 μA/150 μA/200 μA
100 nA
10 μA/20 μA/50 μA/100 μA/150 μA/200 μA
100 nA
10 μA/20 μA/50 μA/100 μA/150 μA/200 μA
100 nA
10 μA/20 μA/50 μA/100 μA/150 μA/200 μA
100 nA
2% accuracy
Available on any analog input pin
(AVDD + AVSS)/2
V
3.7
6.7
µs/nF
µs/nF
Dependent on the capacitance connected to AINx
AVDD = 3.3 V, AVSS = DGND
AVDD = 1.8 V, AVSS = DGND
Ω
mA
Continuous current
10
15
30
1
See the Terminology section.
2
These specifications are not production tested but are supported by characterization data at the initial product release.
3
Matching between IOUT0 and IOUT1, VOUT = 0 V.
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Test Conditions/Comments
Available on any analog input pin
Current Drift Matching2
Output Compliance
BIAS VOLTAGE (VBIAS) GENERATOR
VBIAS
Start-Up Time
Typ
Rev. 0 | 7 of 108
Data Sheet
AD4130-8
SPECIFICATIONS
DIAGNOSTICS SPECIFICATIONS
Table 5. Diagnostics Specifications
Parameter1, 2
TEMPERATURE SENSOR
Accuracy
Nominal Sensitivity3
Reading at 25°C
REFERENCE
Reference Detect Threshold
REFIN1(+) Overvoltage Detect Level
REFIN1(−) Undervoltage Detect Level
AIN OVERVOLTAGE (OV) AND UNDERVOLTAGE (UV)
AIN OV Detect Level
AIN UV Detect Level
BURNOUT CURRENTS
AIN Current
1
Min
Typ
Max
Unit
±1
860.66
258
°C
µV/K
mV
Test Conditions/Comments
2.5 V external reference, gain = 1
After calibration at 25 °C
REFIN = REFIN1(+) – REFIN1(−)
0.7
AVDD + 0.05
1
AVSS − 0.05
V
V
V
AVSS − 0.08
V
V
AVDD + 0.08
0.5, 2, 4
µA
See the Terminology section.
2
These specifications are not production tested but are supported by characterization data at the initial product release.
3
Guaranteed by design.
REJECTION SPECIFICATIONS
Table 6. Rejection Specifications
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
dB
dB
dB
External MCLK, fMCLK = 76.8 kHz, AIN = 1 V/gain
Gain = 1, gain = 1 and PGA bypass2
Gain = 2 to 16
Gain = 32 to 128
POWER SUPPLY REJECTION (AVDD)
96
94
102
COMMON-MODE REJECTION3, 4, 5
At DC
86
112
108
90
135
122
dB
dB
dB
Sinc3 Filter
At 50 Hz and 60 Hz
At 50 Hz
At 60 Hz
Sinc3 + REJ60 Filter
At 50 Hz and 60 Hz
Sinc3 + Sinc1 Averaging Filter
At 50 Hz
At 60 Hz
Sinc4 + Sinc1 Averaging Filter
At 50 Hz
At 60 Hz
Post Filters
At 50 Hz and 60 Hz
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115
115
115
dB
dB
dB
115
dB
120
120
dB
dB
115
115
dB
dB
125
125
125
120
dB
dB
dB
dB
AIN = 1 V, gain = 1
AIN = 1 V/gain, gain = 2 to 16
AIN = 1 V/gain, gain = 32 to 128
Input frequency (fIN) = notch frequency (fNOTCH) ± 1 Hz
10 SPS (FS = 240)
50 SPS (FS = 48)
60 SPS (FS = 40)
fIN = fNOTCH ± 1 Hz
50 SPS (FS = 48)
fIN = fNOTCH ± 1 Hz
40 SPS (FS = 6, first notch at 50 Hz)
48 SPS (FS = 5, first notch at 60 Hz)
fIN = fNOTCH ± 1 Hz
36.36 SPS (FS = 6, first notch at 60 Hz)
43.63 SPS (FS = 5, first notch at 50 Hz)
fIN = fNOTCH ± 1 Hz
Post Filter 1, ODR = 26.087 SPS
Post Filter 2, ODR = 24 SPS
Post Filter 3, ODR = 19.355 SPS
Post Filter 4, ODR = 16.21 SPS
Rev. 0 | 8 of 108
Data Sheet
AD4130-8
SPECIFICATIONS
Table 6. Rejection Specifications
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
NORMAL MODE REJECTION3, 4
Sinc3 Filter
External Clock
At 50 Hz and 60 Hz
At 50 Hz
At 60 Hz
Internal Clock
At 50 Hz and 60 Hz
At 50 Hz
At 60 Hz
Averaging Filters
External Clock
At 50 Hz
At 60 Hz
Internal Clock
At 50 Hz
At 60 Hz
Post Filters
External Clock
At 50 Hz and 60 Hz
Internal Clock
At 50 Hz and 60 Hz
fIN = fNOTCH ± 1 Hz
100
65
95
98
dB
dB
dB
dB
10 SPS (FS = 240)
50 SPS (FS = 48), Sinc3 + REJ60 filter
50 SPS (FS = 48)
60 SPS (FS = 40)
84
58
79
81
dB
dB
dB
dB
10 SPS (FS = 240)
50 SPS (FS = 48), Sinc3 + REJ60 filter
50 SPS (FS = 48)
60 SPS (FS = 40)
fIN = fNOTCH ± 0.5 Hz
40
42
dB
dB
FS = 6
FS = 5
30
31
dB
dB
fIN = fNOTCH ± 1 Hz
46
62
86
91
dB
dB
dB
dB
Post Filter 1, ODR = 26.087 SPS
Post Filter 2, ODR = 24 SPS
Post Filter 3, ODR = 19.355 SPS
Post Filter 4, ODR = 16.21 SPS
40
54
73
77
dB
dB
dB
dB
Post Filter 1, ODR = 26.087 SPS
Post Filter 2, ODR = 24 SPS
Post Filter 3, ODR = 19.355 SPS
Post Filter 4, ODR = 16.21 SPS
1
See the Terminology section.
2
PGA_BYP_n = 1. The PGA_BYP_n bit can be found in each CONFIG_n register. See Programmable Gain Amplifier section for more details.
3
These specifications are not production tested but are supported by characterization data at the initial product release.
4
FS is the decimal equivalent of the FS, Bits[10:0] in the filter registers.
5
When gain > 1, the common-mode voltage is between (AVSS + 0.1 + 0.5/gain) and (AVDD − 0.1 − 0.5/gain).
LOGIC INPUT AND OUTPUT SPECIFICATIONS
Table 7. Logic Input and Output Specifications
Parameter
LOGIC INPUTS1, 2
Input Low Voltage (VINL)
Input High Voltage (VINH)
Voltage Hysteresis
Current
Pin Capacitance
analog.com
Min
Typ
0
0.7 × IOVDD
Max
Unit
Test Conditions/Comments
0.3 × IOVDD
IOVDD
V
V
V
µA
pF
1.65 V ≤ IOVDD < 3.6 V
1.65 V ≤ IOVDD < 3.6 V
1.65 V ≤ IOVDD < 3.6 V
Input voltage (VIN) = IOVDD or DGND
Per digital pin
0.5
−1
+1
10
Rev. 0 | 9 of 108
Data Sheet
AD4130-8
SPECIFICATIONS
Table 7. Logic Input and Output Specifications
Parameter
Min
LOGIC OUTPUTS1, 2 (INCLUDING CLK)
Output Low Voltage (VOL)
Output High Voltage (VOH)
Floating State Leakage Current
Floating State Output Capacitance
Data Output Coding3
CLOCK
Internal Cock
Frequency
Duty Cycle2
Wake-Up Time2, 4
External Clock2
Frequency
Duty Cycle
DIGITAL OUTPUTS (P1 to P4)5
Output Low Voltage (VOL)2
Output High Voltage (VOH)2
1
Typ
Max
Unit
Test Conditions/Comments
0
IOVDD – 0.35
0.4
IOVDD
Sink current (ISINK) = 100 µA
Source current (ISOURCE) = 100 µA
−1
+1
V
V
µA
pF
10
Offset binary
Straight binary
76.8 – 2%
Bipolar bit = 0b1, default setting
Bipolar bit = 0b0
76.8
50:50
850
76.8 + 2%
kHz
%
µs
76.8
45:55 to 55:45
kHz
%
0
AVDD – 0.6
0.4
AVDD
V
V
ISINK = 100 µA
ISOURCE = 100 µA
See Pin Configuration and Function Descriptions section.
2
These specifications are not production tested but are supported by characterization data at the initial product release.
3
The bipolar bit can be found in the ADC_CONTROL register. See the Data Output Coding section for more details.
4
See also Out of Standby Mode Timing section for further details.
5
General-purpose output pins used as digital pins require AVSS = DGND and AVDD = IOVDD. See the General-Purpose Output section.
POWER SPECIFICATIONS
Table 8. Power Specifications
Parameter
POWER SUPPLY VOLTAGE
AVDD to AVSS
IOVDD to DGND
AVSS to DGND
AVDD to DGND
IOVDD to AVSS
POWER SUPPLY CURRENTS1
AVDD Current
External Reference
Gain = 1
Gain = 1 to 16
Gain = 32 to 128
Increase due to Reference Buffer4,
Increase due to Internal Reference4
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Min
Typ
1.71
1.65
–1.8
0.9
Max
Unit
3.6
3.6
0
V
V
V
V
V
5.4
Test Conditions/Comments
Internal oscillator enabled
20
25
7.5
2.5
29
8.5
3
0.25
6.5
1.75
0.45
23
30
35
8
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
PGA bypass2
Continuous conversion mode current
DUTY_CYC_RATIO = 1/43
DUTY_CYC_RATIO = 1/163
Continuous conversion mode current
DUTY_CYC_RATIO = 1/43
DUTY_CYC_RATIO = 1/163
Per reference buffer
Continuous conversion mode current
DUTY_CYC_RATIO = 1/43
DUTY_CYC_RATIO = 1/163
Rev. 0 | 10 of 108
Data Sheet
AD4130-8
SPECIFICATIONS
Table 8. Power Specifications
Parameter
Min
Increase due to VBIAS on4
IOVDD Current
Increase due to FIFO
POWER-DOWN CURRENTS1
Standby Mode Current
AVDD
IOVDD
Power-Down Mode Current
AVDD
IOVDD
OPERATING TEMPERATURE RANGE
TMIN
TMAX
Typ
Max
Unit
Test Conditions/Comments
1
3.5
1.8
1.4
50
1.2
6.9
µA
µA
µA
µA
nA
Continuous conversion mode current
DUTY_CYC_RATIO = 1/43
DUTY_CYC_RATIO = 1/163
0.2
0.35
1.3
3.5
µA
µA
Analog low dropout (LDO) regulator on
Digital LDO regulator on
0.01
0.13
1
1
µA
µA
Analog LDO regulator off
Digital LDO regulator off
105
°C
°C
Wafer level chip scale package (WLCSP)
−40
1
The digital inputs are equal to IOVDD or DGND with excitation currents disabled.
2
PGA_BYP_n = 1. The PGA_BYP_n bit can be found in each CONFIG_n register. See the Programmable Gain Amplifier section for more details.
3
Duty cycling mode is enabled by setting MODE = 0b1001 in the ADC_CONTROL register. The DUTY_CYC_RATIO bit can be found in the same register. See the Duty
Cycling Mode and Duty Cycling Mode Timing sections.
4
These specifications are not production tested but are supported by characterization data at the initial product release.
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Rev. 0 | 11 of 108
Data Sheet
AD4130-8
SPECIFICATIONS
TIMING SPECIFICATIONS
AVDD = 1.71 V to 3.6 V, IOVDD = 1.65 V to 3.6 V, AVSS = DGND = 0 V, Input Logic 0 = DGND = 0 V, Input Logic 1 = IOVDD, internal MCLK
(fMCLK = 76.8 kHz), temperature range = TMIN to TMAX, and decoupling as outlined in the Recommended Decoupling section, unless otherwise
noted. All digital input signals are specified with rise time (tR) = fall time (tF) = 5 ns (10% to 90% of IOVDD and timed from a voltage level of
IOVDD/2.
Table 9. Timing Specifications
Parameter1
Symbol
Min
tSCK
tSCKH
tSCKL
tDIN_SET
tDIN_HOL
tDOUT_VALID
tDOUT_HOL
tDOUT_DIS_DEL
200
90
90
10
10
Max
Unit
REGISTER ACCESS IN 3-WIRE MODE2, 3, 4
SCLK Cycle Time
SCLK High Pulse Width
SCLK Low Pulse Width
DIN Data Setup Time
DIN Data Hold Time
SCLK Falling Edge to DOUT Becomes Available
SCLK Falling Edge to DOUT Remains Available
SCLK Rising Edge to DOUT Disable Delay5
DOUT_DIS_DEL = 06
DOUT_DIS_DEL = 16
Delay Between Consecutive Write Operations7 (Last SCLK Rising to First SCLK Falling)
Data Ready8 High Time if Data Ready is Low and the Next Conversion is Available
Last SCLK Rising for SW Reset Serial Peripheral Interface (SPI) Transaction to First SCLK Falling for Next SPI
Transaction
REGISTER ACCESS IN 4-WIRE MODE2, 3, 9
CS Falling Edge to DOUT Enable Time10
CS Setup Time: CS Falling Edge to First SCLK Falling Edge
CS Hold Time: Last SCK Rising Edge to CS Rising Edge Delay
CS Rising Edge to DOUT Disable Time10
CS High Pulse Width (Between Read/Write Operations)
CS Rising Edge for SW Reset SPI Transaction to CS Falling Edge for Next SPI Transaction
CONTINUOUS READ MODE11
Data Ready8 Falling Edge to First SCLK Falling Edge
SCLK Falling Edge to New DOUT Becomes Available
SYNCHRONIZATION MODE12
SYNC Low Pulse Width
STANDBY MODE
Wake-Up Time from SPI Write to Exit Standby Mode13
DUTY CYCLING
Wake Up Time
tWR_DEL
tRDYH
tRESET_DELAY
tDOUT_EN
tCS_SET
tCS_HOL
tDOUT_DIS
tCS_PW
tRESET_DELAY
10
ns
ns
ns
ns
ns
ns
ns
10
100
3/fMCLK
4/fMCLK
160/fMCLK
ns
ns
sec
sec
sec
80
4/fMCLK
80
0
0
80
20
160/fMCLK
tRDYL_SCKL
tDOUT_VALID
20
tSYNC_PW
4/fMCLK
80
ns
ns
ns
ns
ns
sec
ns
ns
sec
tWU_STBY
36/fMCLK
sec
tWU_DUTY
32/fMCLK
sec
1
These specifications are not production tested but are supported by characterization data at the initial product release.
2
The device operates with SPI Mode 3: SCLK idles high, the falling edge of SCLK is the drive edge for DOUT, and the rising edge of SCLK is the sample edge for DIN.
3
CSB_EN = 0b0 (default) in the ADC_CONTROL register (3-wire mode). Change this bit to 1 to enable 4-wire mode.
4
See 3-Wire Mode Timing Diagrams.
5
CS pin held low.
6
This bit can be found in the ADC_CONTROL register and it is only active if CSB_EN = 0b0 in the same register.
7
Applies only when SYNC is high, or MM_CRC_ERR_EN = 0b1 and only for ADC_CONTROL and error register writes.
8
For the data ready signal related timing specifications, the INT pin is considered (INT_PIN_SEL = 0b00 in the IO_CONTROL register). See the Data Ready Signal section.
9
See 4-Wire Mode Timing Diagrams.
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Data Sheet
AD4130-8
SPECIFICATIONS
Table 9. Timing Specifications
Parameter1
Symbol
Min
Max
Unit
10
In 4-wire mode (CSB_EN = 0b1), the DOUT pin changes from tristate (CS pin high) to enabled after the CS falling edge, then changes back to tristate following the CS
rising edge. In 3-wire mode, CS pin can still be used to enable (CS pin low) and disable (CS pin high) the DOUT pin.
11
Set CONT_READ = 0b1 in the ADC_CONTROL register to enable continuous read mode. See the Continuous Read Mode Timing Diagram and Continuous Read Mode
sections for details.
12
See the System Synchronization section.
13
Internal oscillator is kept alive. See the internal clock wake-up time specification in the Table 7 and Out of Standby Mode Timing sections for further details.
Table 10. FIFO Timing Specifications
Parameter1
Symbol
Min
tBSY
tINT_RD
tQUIET1
tDOUT_VALID
tDOUT_HOL
tQUIET2
tCLR9
tSYNC_PW
4/fMCLK
1.5/fMCLK
0
Max
Unit
FIFO RELATED2
FIFO Ready Signal3 High Time when FIFO Is Busy
FIFO Interrupt Signal4 Rising Edge to FIFO Read Start (CS Falling Edge or SCLK Falling Edge)5
FIFO Quiet Time Between Write and Read Access (FIFO Ready Signal3 Falling Edge to FIFO Read Start6)
SCLK Falling Edge to DOUT Becomes Available
SCLK Falling Edge to DOUT Remains Available
FIFO Quiet Time Between Read and Write Access (FIFO Read End7 to FIFO Ready Signal3 Rising Edge)
FIFO Clear Delay (After SYNC Low or After Write to FIFO_CONTROL Register)8
SYNC Low Pulse Width to Clear FIFO
1
These specifications are not production tested but are supported by characterization data at the initial product release.
2
See the FIFO Timing Diagrams and FIFO sections.
3
For the FIFO ready signal related timing specifications, the DOUT pin is considered.
4
For the FIFO interrupt signal related timing specifications, the INT pin is considered (INT_PIN_SEL = 0b00 in the IO_CONTROL register).
5
This specification applies to the FIFO watermark interrupt.
6
CS falling edge (4-wire mode) or SCLK falling edge (3-wire mode and CS tied low)
7
CS rising edge (4-wire mode) or SCLK rising edge (3-wire mode and CS tied low)
8
See the Clearing the FIFO section.
9
Guaranteed by design.
80
10
4/fMCLK
8/fMCLK
4/fMCLK
sec
sec
ns
ns
ns
sec
sec
sec
3-Wire Mode Timing Diagrams
Figure 2. Write Cycle Timing Diagram, 3-Wire Mode (CSB_EN Bit Set to 0), CS Pin Tied Low
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Rev. 0 | 13 of 108
Data Sheet
AD4130-8
SPECIFICATIONS
Figure 3. Read Cycle Timing Diagram, 3-Wire Mode (CSB_EN Bit Set to 0), CS Pin Tied Low
Figure 4. Delay Between Consecutive Serial Operations, 3-Wire Mode (CSB_EN Bit Set to 0), CS Pin Tied Low
Figure 5. Write Cycle Timing Diagram, 3-Wire Mode (CSB_EN Bit Set to 0), CS Pin Used to Tristate the DOUT Pin
Figure 6. 3-Wire Mode Read Cycle Timing Diagram, 3-Wire Mode (CSB_EN Bit Set to 0), CS Pin Used to Tristate the DOUT Pin
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Data Sheet
AD4130-8
SPECIFICATIONS
4-Wire Mode Timing Diagrams
Figure 7. Write Cycle Timing Diagram, 4-Wire Mode (CSB_EN Bit Set to 1)
Figure 8. Read Cycle Timing Diagram, 4-Wire Mode (CSB_EN Bit Set to 1)
Figure 9. Data Ready High Time when Data Ready is Initially Low and the Next Conversion is Available
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Data Sheet
AD4130-8
SPECIFICATIONS
Continuous Read Mode Timing Diagram
Figure 10. Continuous Read Mode Timing
FIFO Timing Diagrams
Figure 11. FIFO Timing with Watermark Interrupt
Figure 12. FIFO Readback Timing Diagram
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Rev. 0 | 16 of 108
Data Sheet
AD4130-8
SPECIFICATIONS
Figure 13. FIFO Clear Timing Diagram
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Data Sheet
AD4130-8
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 11. Absolute Maximum Ratings
Parameter
Rating
AVDD to AVSS
IOVDD to DGND
IOVDD to AVSS
AVSS to DGND
AINx to AVSS
REFIN1(+), REFIN1(−) to AVSS
Digital Inputs1 to DGND
Digital Outputs1 to DGND
AINx/Digital Input Current
Storage Temperature Range
Junction Temperature (TJ)
Lead Temperature, Soldering Reflow
−0.3 V to +3.96 V
−0.3 V to +3.96 V
−0.3 V to +5.94 V
−1.98 V to +0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to IOVDD + 0.3 V
−0.3 V to IOVDD + 0.3 V
10 mA
−65°C to +150°C
150°C
260°C, as per JEDEC J‑STD‑020
1
See the Pin Configuration and Function Descriptions section for a list of the
digital input and digital output pins.
Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
Absolute maximum ratings are tested individually only, not in combination, and they all apply for any given configuration.
THERMAL CHARACTERISTICS
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to PCB
thermal design is required.
Thermal resistance values specified in Table 12 were calculated
based on JEDEC specifications and must be used in compliance
with JESD51-12.
Table 12. Thermal Resistance
Package Type1
θJA
θJB
θJC_TOP
ΨJB
ΨJT
Unit
CB-35-3
46.2
11
0.32
4.4
0.2
°C/W
1
The values in Table 12 were calculated based on the standard JEDEC 2S2P
thermal test board with 6 × 11 thermal vias. See the JEDEC JESD51 series.
For WLCSP devices, using ΨJB or ΨJT is a more appropriate way
to estimate the worst-case junction temperature of the device in
the system environment if an accurate thermal measurement of the
board temperature near the device under test (DUT) or directly on
the package top surface operating in the system environment is
available.
Using the parameters listed in Table 12 in accordance with JEDEC
standards in the JESD51 series is recommended.
The AD4130-8 can be damaged when TJ limits are exceeded. See
Table 11 for the absolute maximum junction temperature specification. Monitoring the ambient temperature does not guarantee that
TJ is within the specified maximum temperature limits. In applications with high power dissipation and/or poor thermal resistance, TJ
must be monitored using the internal temperature sensor.
ELECTROSTATIC DISCHARGE (ESD) RATINGS
The following ESD information is provided for handling of ESD-sensitive devices in an ESD protected area only.
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
Field induced charged device model (FICDM) per ANSI/ESDA/JEDEC JS-002.
Machine model (MM) per ANSI/ESD STM5.2. MM voltage values
are for characterization only.
ESD Ratings for AD4130-8
Table 13. AD4130-8, 35-Ball WLCSP
ESD Model
Withstand Threshold (V)
Class
HBM
4000
3A
FICDM
500
C2a
MM
400
C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although
this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
θJA, θJB, and θJC are mainly used to compare the thermal performance of the package of the device with other semiconductor
packages when all test conditions listed are similar. θJA, θJB, and
θJC can be used for first order approximation of the junction temperature in the system environment.
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Rev. 0 | 18 of 108
Data Sheet
AD4130-8
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 14. Pin Configuration
Table 14. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
A1
A2
AVDD
INT
S
DO
A3
DIN
DI
A4
SCLK
DI
A5
CS
DI
B1
REGCAPA
S
B2
SYNC
DI
B3
DOUT
DO
B4
CLK
DI/O
B5
IOVDD
S
Analog Supply Voltage, Relative to AVSS. See the Power Supplies section.
Interrupt Pin. The INT pin functions as a data ready signal by default when the FIFO is disabled. See the Data Ready Signal
section. When the FIFO is enabled, the INT pin can be configured to a FIFO interrupt signal (see the FIFO Interrupt section).
Serial Data Logic Input. Data on the DIN pin is transferred to the control registers within the ADC, with the register selection bits
(RS, Bits[5:0]) of the COMMS register identifying the appropriate register. See the Digital Interface section.
Serial Clock Logic Input. This serial clock input is for data transfers to and from the ADC. The serial clock can be continuous with
all data transmitted in a continuous train of pulses. Alternatively, SCLK can be a gated clock with the information transmitting to or
from the ADC in smaller batches of data. See the Digital Interface section.
Chip Select Active Low Logic Input. Use CS to select the ADC in systems with more than one device on the serial bus, or as
a frame synchronization signal in communicating with the device. CS can be hardwired low if the SPI diagnostics are unused,
allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT interfacing with the device. See the Digital Interface
section.
Analog LDO Regulator Output. Decouple the REGCAPA pin to AVSS with a 0.1 µF capacitor. It is not recommended to connect any
additional load to the REGCAPA pin. See the Internal LDOs section.
Synchronization Logic Input. The SYNC pin is a logic input that allows synchronization of the digital filters and analog modulators
when using multiple AD4130-8 devices. See the System Synchronization section. The SYNC pin can also be used to clear the
FIFO. See the Clearing the FIFO section.
Serial Data Logic Output. The DOUT pin functions as a serial data output pin to readback the content of any register with read
access. See the Digital Interface section.
Clock Input and Clock Logic Output. The internal clock can be made available at this pin. Alternatively, the internal clock can be
disabled, and the ADC can be driven by an external clock. See the ADC Master Clock section. The CLK pin can also be used as
the interrupt source for the data ready signal or FIFO interrupt (see the Data Ready Signal section and FIFO Interrupt section). If
not in use, tie the CLK pin to DGND.
Serial Interface Supply Voltage, 1.65 V to 3.6 V. See the Power Supplies section.
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Rev. 0 | 19 of 108
Data Sheet
AD4130-8
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 14. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
C1
AVSS
S
C2
C3, C4
PSW
NC
AI
N/A2
C5
D1
DGND
REFOUT
S
AO
D2
AIN13/IOUT/
VBIAS
AI/O
Analog Supply Voltage Reference. The voltage on AVDD is referenced to AVSS. AVSS is either tied to DGND or it can be taken
below 0 V to provide a dual power supply to the AD4130-8. The minimum AVSS is −1.8 V and the differential between AVDD and
AVSS must be between 1.71 V and 3.6 V. See the Power Supplies section.
Low-Side Power Switch to AVSS. See the Power-Down Switch section.
No Connect. These pins must be mechanically soldered to the PCB. These pins can be connected to DGND or left electrically
floating.
Digital/Common Ground Reference Point. See the Power Supplies section.
Internal Reference Output. The buffered output of the internal voltage reference is available on the REFOUT pin. A 1 nF capacitor
is required on the REFOUT pin when the internal reference is active. See the ADC Reference section.
Analog Input 13 (AIN13) (Default)/Output of Internal Excitation Current Source/Bias Voltage.
D3
AIN8/IOUT/VBIAS
AI/O
D4
AIN2/IOUT/
VBIAS/P1
AI/O
Output of Internal Excitation Current Source (IOUT). The internal programmable excitation current source can be made available
at the IOUT pin. Either IOUT1 or IOUT0 can be switched to this output.
Bias Voltage (VBIAS). A bias voltage midway between the analog power supply rails can be generated at the VBIAS pin.
Analog Input 8 (AIN8) (Default)/Output of Internal Excitation Current Source/Bias Voltage.
Output of Internal Excitation Current Source (IOUT). The internal programmable excitation current source can be made available
at the IOUT pin. Either IOUT1 or IOUT0 can be switched to this output.
Bias Voltage (VBIAS). A bias voltage midway between the analog power supply rails can be generated at the VBIAS pin.
Analog Input 2 (AIN2) (Default)/Output of Internal Excitation Current Source/Bias Voltage/General Purpose Output 1.
D5
REGCAPD
S
E1
AIN15/IOUT/
VBIAS/REFIN2(−)
AI/O
Output of Internal Excitation Current Source (IOUT). The internal programmable excitation current source can be made available
at the IOUT pin. Either IOUT1 or IOUT0 can be switched to this output.
Bias Voltage (VBIAS). A bias voltage midway between the analog power supply rails can be generated at the VBIAS pin.
General-Purpose Output 1 (P1). The P1 pin can be used as a general-purpose output, referenced between AVSS and AVDD. When
AVSS is tied to DGND and IOVDD is tied to AVDD, the P1 pin can operate like a digital output.
Digital LDO Regulator Output. Decouple the REGCAPD pin to DGND with a 0.1 µF capacitor. It is not recommended to connect
any additional load to the REGCAPD pin. See the Internal LDOs section.
Analog Input 15 (AIN15) (Default)/Output of Internal Excitation Current Source/Bias Voltage/Negative Reference Input.
AI/O
Output of Internal Excitation Current Source (IOUT). The internal programmable excitation current source can be made available
at the IOUT pin. Either IOUT1 or IOUT0 can be switched to this output.
Bias Voltage (VBIAS). A bias voltage midway between the analog power supply rails can be generated at the VBIAS pin.
Negative Reference Input (REFIN2(−)). The REFIN2(−) pin can be anywhere between AVSS and AVDD – 0.5 V.
Analog Input 12 (AIN12) (Default)/Output of Internal Excitation Current Source/Bias Voltage.
E2
AIN12/IOUT/
VBIAS
E3
AIN7/IOUT/VBIAS
AI/O
E4
AIN3/IOUT/
VBIAS/P2
AI/O
E5
AIN0/IOUT/VBIAS
analog.com
AI/O
Output of Internal Excitation Current Source (IOUT). The internal programmable excitation current source can be made available
at the IOUT pin. Either IOUT1 or IOUT0 can be switched to this output.
Bias Voltage (VBIAS). A bias voltage midway between the analog power supply rails can be generated at the VBIAS pin.
Analog Input 7 (AIN7) (Default)/Output of Internal Excitation Current Source/Bias Voltage.
Output of Internal Excitation Current Source (IOUT). The internal programmable excitation current source can be made available
at the IOUT pin. Either IOUT1 or IOUT0 can be switched to this output.
Bias Voltage (VBIAS). A bias voltage midway between the analog power supply rails can be generated at the VBIAS pin.
Analog Input 3 (AIN3) (Default)/Output of Internal Excitation Current Source/Bias Voltage/General Purpose Output 2.
Output of Internal Excitation Current Source (IOUT). The internal programmable excitation current source can be made available
at the IOUT pin. Either IOUT1 or IOUT0 can be switched to this output.
Bias Voltage (VBIAS). A bias voltage midway between the analog power supply rails can be generated at the VBIAS pin.
General-Purpose Output 2 (P2). The P2 pin can be used as a general-purpose output, referenced between AVSS and AVDD. When
AVSS is tied to DGND and IOVDD is tied to AVDD, the P2 pin can operate like a digital output.
Analog Input 0 (AIN0) (Default)/Output of Internal Excitation Current Source/Bias Voltage.
Output of Internal Excitation Current Source (IOUT). The internal programmable excitation current source can be made available
at the IOUT pin. Either IOUT1 or IOUT0 can be switched to this output.
Rev. 0 | 20 of 108
Data Sheet
AD4130-8
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 14. Pin Function Descriptions
Pin No.
F1
Mnemonic
AIN14/IOUT/
VBIAS/REFIN2(+)
F2
AIN10/IOUT/
VBIAS
Type1
Description
AI/O
Bias Voltage (VBIAS). A bias voltage midway between the analog power supply rails can be generated at the VBIAS pin.
Analog Input 14 (AIN14) (Default)/Output of Internal Excitation Current Source/Bias Voltage/Positive Reference Input.
AI/O
Output of Internal Excitation Current Source (IOUT). The internal programmable excitation current source can be made available
at the IOUT pin. Either IOUT1 or IOUT0 can be switched to this output.
Bias Voltage (VBIAS). A bias voltage midway between the analog power supply rails can be generated at the VBIAS pin.
Positive Reference Input (REFIN2(+)). An external reference can be applied between REFIN2(+) and REFIN2(−). REFIN2(+) can
be anywhere between AVDD and AVSS + 0.5 V. The nominal reference voltage (REFIN2(+) to REFIN2(−)) is 2.5 V, but the device
functions with a reference from 0.5 V to AVDD.
Analog Input 10 (AIN10) (Default)/Output of Internal Excitation Current Source/Bias Voltage.
F3
REFIN1(+)
AI
F4
AIN5/IOUT/
VBIAS/P4
AI/O
F5
AIN1/IOUT/VBIAS
AI/O
G1
AIN11/IOUT/VBIAS AI/O
G2
AIN9/IOUT/VBIAS
AI/O
G3
G4
REFIN1(−)
AIN6/IOUT/VBIAS
AI
AI/O
G5
AIN4/IOUT/
VBIAS/P3
AI/O
Output of Internal Excitation Current Source (IOUT). The internal programmable excitation current source can be made available
at the IOUT pin. Either IOUT1 or IOUT0 can be switched to this output.
Bias Voltage (VBIAS). A bias voltage midway between the analog power supply rails can be generated at the VBIAS pin.
Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−). The REFIN1(+) pin can be
anywhere between AVDD and AVSS + 0.5 V. The device functions with a reference from 0.5 V to AVDD. See the ADC Reference
section.
Analog Input 5 (AIN5) (Default)/Output of Internal Excitation Current Source/Bias Voltage/General-Purpose Output 4.
Output of Internal Excitation Current Source (IOUT). The internal programmable excitation current source can be made available
at the IOUT pin. Either IOUT1 or IOUT0 can be switched to this output.
Bias Voltage (VBIAS). A bias voltage midway between the analog power supply rails can be generated at the VBIAS pin.
General-Purpose Output 4 (P4). The P4 pin can be used as a general-purpose output, referenced between AVSS and AVDD. When
AVSS is tied to DGND and IOVDD is tied to AVDD, the P4 pin can operate like a digital output.
Analog Input 1 (AIN1) (Default)/Output of Internal Excitation Current Source/Bias Voltage.
Output of Internal Excitation Current Source (IOUT). The internal programmable excitation current source can be made available
at the IOUT pin. Either IOUT1 or IOUT0 can be switched to this output.
Bias Voltage (VBIAS). A bias voltage midway between the analog power supply rails can be generated at the VBIAS pin.
Analog Input 11 (AIN11) (Default)/Output of Internal Excitation Current Source/Bias Voltage.
Output of Internal Excitation Current Source (IOUT). The internal programmable excitation current source can be made available
at the IOUT pin. Either IOUT1 or IOUT0 can be switched to this output.
Bias Voltage (VBIAS). A bias voltage midway between the analog power supply rails can be generated at the VBIAS pin.
Analog Input 9 (AIN9) (Default)/Output of Internal Excitation Current Source/Bias Voltage.
Output of Internal Excitation Current Source (IOUT). The internal programmable excitation current source can be made available
at the IOUT pin. Either IOUT1 or IOUT0 can be switched to this output.
Bias Voltage (VBIAS). A bias voltage midway between the analog power supply rails can be generated at the VBIAS pin.
Negative Reference Input. The REFIN1(−) pin can be anywhere between AVSS and AVDD − 0.5 V. See the ADC Reference section.
Analog Input 6 (AIN6) (Default)/Output of Internal Excitation Current Source/Bias Voltage.
Output of Internal Excitation Current Source (IOUT). The internal programmable excitation current source can be made available
at the IOUT pin. Either IOUT1 or IOUT0 can be switched to this output.
Bias Voltage (VBIAS). A bias voltage midway between the analog power supply rails can be generated at the VBIAS pin.
Analog Input 4 (AIN4) (Default)/Output of Internal Excitation Current Source/Bias Voltage/General Purpose Output 3.
Output of Internal Excitation Current Source (IOUT). The internal programmable excitation current source can be made available
at the IOUT pin. Either IOUT1 or IOUT0 can be switched to this output.
Bias Voltage (VBIAS). A bias voltage midway between the analog power supply rails can be generated at the VBIAS pin.
General-Purpose Output 3 (P3). The P3 pin can be used as a general-purpose output, referenced between AVSS and AVDD. When
AVSS is tied to DGND and IOVDD is tied to AVDD, the P3 pin can operate like a digital output.
1
AO is analog output, S is supply, AI is analog input, AI/O is analog input or output, DI is digital input, DO is digital output, and DI/O is digital input or output.
2
N/A means not applicable.
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Rev. 0 | 21 of 108
Data Sheet
AD4130-8
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 3.3 V, IOVDD = 1.8 V, AVSS = DGND = 0 V, VREF = 2.5 V (internal), internal MCLK, TA = 25°C, sinc3 filter, FS = 48, gain = 1, PGA
enabled, reference buffers bypassed, and decoupling as outlined in the Recommended Decoupling section, unless otherwise noted.
OFFSET ERROR AND GAIN ERROR
Figure 15. Offset Error vs. Temperature (Gain = 1, Before Calibration)
Figure 18. Gain Error vs. Temperature (Gain = 1, Factory Calibrated)
Figure 16. Offset Error vs. Temperature (Gain = 8, Before Calibration)
Figure 19. Gain Error vs. Temperature (Gain = 8, Before Calibration)
Figure 17. Offset Error vs. Temperature (Gain = 32, Before Calibration)
Figure 20. Gain Error vs. Temperature (Gain = 32, Before Calibration)
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Rev. 0 | 22 of 108
Data Sheet
AD4130-8
TYPICAL PERFORMANCE CHARACTERISTICS
INL ERROR AND OSCILLATOR
Figure 21. INL Error vs. Differential Input Amplitude for Various Gains (Sinc3
Filter, ODR = 50 SPS, Internal 2.5 V Reference)
Figure 24. INL Error vs. Differential Input Amplitude for Various Gains and
Temperatures (Sinc3 Filter, ODR = 50 SPS, Internal 2.5 V Reference)
Figure 22. INL Error vs. Differential Input Amplitude for Various Gains (Sinc3
Filter, ODR = 50 SPS, External 2.5 V Reference)
Figure 25. INL Error vs. Differential Input Amplitude for Various Gains and
Temperatures (Sinc3 Filter, ODR = 50 SPS, External 2.5 V Reference)
Figure 23. INL Error vs. Differential Input Amplitude for Various Gains (Sinc3
Filter, ODR = 50 SPS, AVDD = 1.8 V, Internal 1.25 V Reference)
Figure 26. Internal Oscillator Error vs. Temperature
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Rev. 0 | 23 of 108
Data Sheet
AD4130-8
TYPICAL PERFORMANCE CHARACTERISTICS
NOISE
Figure 27. Noise Histogram Plot (Sinc3 Filter, ODR = 50 SPS, Gain = 1)
Figure 28. RMS Noise vs. Analog Input Voltage (Sinc3 Filter, ODR = 50 SPS,
Gain = 1 and Gain = 1 with PGA Bypass, 2.5 V Reference)
Figure 29. RMS Noise vs. Analog Input Voltage (Sinc3 Filter, ODR = 50 SPS,
Gain = 8, Gain = 16 and Gain = 32, 1.25 V Reference)
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Figure 30. Noise Histogram Plot (Sinc4 Filter, ODR = 240 SPS, Gain = 1,
Internal 1.25 V Reference)
Figure 31. RMS Noise vs. Analog Input Voltage (Sinc3 Filter, ODR = 50 SPS,
Gain = 8, Gain = 16 and Gain = 32, 2.5 V Reference)
Figure 32. NSD vs. Output Data Rate for Various Gains (Sinc3 Filter, External
2.5 V Reference)
Rev. 0 | 24 of 108
Data Sheet
AD4130-8
TYPICAL PERFORMANCE CHARACTERISTICS
ANALOG INPUT CURRENTS
Figure 33. Absolute AINP Current vs. Differential AIN Voltage (VDIFF) for
Various Temperatures (Gain = 1, VCM = AVDD/2)
Figure 36. Absolute AINM Current vs. VDIFF for Various Temperatures
(Gain = 1, VCM = AVDD/2)
Figure 34. Absolute AINP Current vs. AIN Common-Mode Voltage (VCM) for
Various Temperatures (Gain = 1, VDIFF = 0 V)
Figure 37. Absolute AINM Current vs. VCM for Various Temperatures
(Gain = 1, VDIFF = 0 V)
Figure 35. Differential AIN Current vs. VDIFF for Various Temperatures
(Gain = 1, VCM = AVDD/2)
Figure 38. Differential AIN Current vs. VCM for Various Temperatures
(Gain = 1, VCM = AVDD/2)
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Rev. 0 | 25 of 108
Data Sheet
AD4130-8
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 39. Absolute AINP Current vs. Normalized Differential AIN Voltage
(VDIFF/Gain) for Various Temperatures (Gain = 2 to 128, VCM = AVDD/2)
Figure 42. Absolute AINM Current vs. VDIFF/Gain for Various Temperatures
(Gain = 2 to 128, VCM = AVDD/2)
Figure 40. Absolute AINP Current vs. Normalized AIN Common-Mode Voltage
(VCM/Gain) for Various Temperatures (Gain = 2 to 128, VDIFF = 0 V)
Figure 43. Absolute AINM Current vs. VCM/Gain for Various Temperatures
(Gain = 2 to 128, VDIFF = 0 V)
Figure 41. Differential AIN Current vs. VDIFF/Gain for Various Temperatures
(Gain = 2 to 128, VCM = AVDD/2)
Figure 44. Differential AIN Current vs. VCM/Gain for Various Temperatures
(Gain = 2 to 128, VDIFF = 0 V)
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Rev. 0 | 26 of 108
Data Sheet
AD4130-8
TYPICAL PERFORMANCE CHARACTERISTICS
SUPPLY CURRENTS
Figure 45. AVDD Current vs. Temperature for Various Gains
Figure 47. IOVDD Current vs. Temperature
Figure 46. Duty Cycling Current Consumption (AVDD and IOVDD),
DUTY_CYC_RATIO = 1/4 (I_AVDD is AVDD Current, I_IOVDD is IOVDD Current)
Figure 48. Duty Cycling Current Consumption (AVDD and IOVDD),
DUTY_CYC_RATIO = 1/16
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Rev. 0 | 27 of 108
Data Sheet
AD4130-8
TYPICAL PERFORMANCE CHARACTERISTICS
REFERENCE INPUT CURRENTS
Figure 49. Reference Input Current vs. Temperature (Reference Buffer On,
External 2.5 V Reference)
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Figure 50. Reference Input Current vs. Temperature (Reference Buffer
Bypass, External 2.5 V Reference)
Rev. 0 | 28 of 108
Data Sheet
AD4130-8
TYPICAL PERFORMANCE CHARACTERISTICS
INTERNAL REFERENCE AND TEMPERATURE SENSOR
Figure 51. 2.5 V Internal Reference Voltage Histogram
Figure 54. 1.25 V Internal Reference Voltage Histogram
Figure 52. 2.5 V Internal Reference Voltage vs. Temperature
Figure 55. 1.25 V Internal Reference Voltage vs. Temperature
Figure 53. 1.25 V (AVDD = 1.8 V) and 2.5 V (AVDD = 3.3 V) Internal Reference
Voltage vs. Load Current
Figure 56. Temperature Sensor Error vs. Ambient Temperature after
Calibration at 25°C
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Rev. 0 | 29 of 108
Data Sheet
AD4130-8
TYPICAL PERFORMANCE CHARACTERISTICS
EXCITATION CURRENTS
Figure 57. Excitation Current Initial Accuracy Histogram (100 μA)
Figure 60. Excitation Current Initial Matching Histogram (100 μA)
Figure 58. Excitation Current vs. Temperature (100 μA)
Figure 61. Excitation Current Matching vs. Temperature (100 μA)
Figure 59. Output Compliance for Various IEXC Sources (AVDD = 3.3 V, VLOAD
is Load Voltage)
Figure 62. Output Compliance for Various IEXC Sources (AVDD = 1.71 V)
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Rev. 0 | 30 of 108
Data Sheet
AD4130-8
TYPICAL PERFORMANCE CHARACTERISTICS
RESOLUTION
Figure 63. Peak-to-Peak Resolution vs. Output Data Rate (Settled) for Various
Gains (Sinc3 Filter)
Figure 65. Peak-to-Peak Resolution vs. Output Data Rate (Settled) for Various
Gains (Sinc4 Filter)
Figure 64. Peak-to-Peak Resolution vs. Output Data Rate (Settled) for Various
Gains (Sinc3 + Sinc1 Filter)
Figure 66. Peak-to-Peak Resolution vs. Output Data Rate (Settled) for Various
Gains (Sinc4 + Sinc1 Filter)
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Rev. 0 | 31 of 108
Data Sheet
AD4130-8
TYPICAL PERFORMANCE CHARACTERISTICS
FFT
Figure 67. FFT, −0.5 dBFS vs. Shorted Inputs, 10 Hz Input Tone, Sinc3 Filter,
ODR = 240 SPS, Gain = 1, Internal Reference
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Figure 68. FFT, −0.5 dBFS vs. Shorted Inputs, 10 Hz Input Tone, Sinc3 Filter,
ODR = 240 SPS, Gain = 1, External Reference
Rev. 0 | 32 of 108
Data Sheet
AD4130-8
TERMINOLOGY
ANALOG INPUT
AINP
AINP refers to the positive analog input.
AINM
AINM refers to the negative analog input.
Same Conversion Output Data Rate
(1CNV_ODR)
The same conversion output data rate is the rate at which ADC
conversions are available using multiple channels with the same
filter settings and taking one sample per channel.
REFERENCE
Input Span
Line Regulation
The input span specification defines the minimum and maximum
input voltages from zero to full scale that the analog input can
accept and still calibrate gain accurately.
Line regulation refers to the change in output voltage in response to
a given change in supply voltage and is expressed in μV/V.
ADC
Integral Nonlinearity (INL) Error
INL is the maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. The endpoints of the
transfer function are zero scale (not to be confused with bipolar
zero), a point 0.5 LSB below the first code transition (000 ... 000
to 000 ... 001), and full scale, a point 0.5 LSB above the last code
transition (111 ... 110 to 111 ... 111). The error is expressed in ppm
of the full-scale range.
Offset Error
Offset error is the difference between the ideal midscale input
voltage (0 V) and the actual voltage producing the midscale output
code.
Load Regulation
Load regulation refers to the change in output voltage in response
to a given change in load current and is expressed in μV/mA.
Voltage Reference (VREF) Temperature
Coefficient (TC)
VREF TC is a measure of the change in the reference output voltage
with a change in the ambient temperature of the device, normalized
by the output voltage at 25°C. VREF TC is specified using the box
method, which defines TC as the maximum change in the reference
output over a given temperature range expressed in ppm/°C, as
follows:
VREF TC =
VREF_MAX − VREF_MIN
VREF_NOM × TEMP_RANGE
× 106ppm/°C
Gain Error
where:
VREF_MAX is the maximum reference voltage output measured over
the full temperature range.
VREF_MIN is the minimum reference voltage output measured over
the full temperature range.
VREF_NOM is the nominal reference voltage output at ambient temperature (25°C).
TEMP_RANGE is the difference between the maximum and minimum operating temperature of the reference.
Full-Scale Range (FSR)
Voltage Reference (VREF) Noise Spectral
Density (NSD)
The full-scale range is the input range the AD4130-8 can accept
based on the choice of reference voltage and gain value. For a
differential input signal, FSR = 2 × VREF/gain.
VREF NSD is a measurement of the internally generated thermal
noise characterized as a spectral density nV/√Hz.
Offset Calibration Range
In the system calibration modes, the AD4130-8 calibrates offset
with respect to the analog input. The offset calibration range specification defines the range of voltages that the AD4130-8 can accept
and still calibrate offset accurately.
Full-Scale Calibration Range
The full-scale calibration range is the range of voltages that the
AD4130-8 can accept in the system calibration mode and still
calibrate full scale correctly.
Output Data Rate (ODR)
The output data rate is the rate at which ADC conversions are
available on a single settled channel when the ADC is continuously
converting.
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TEMPERATURE SENSOR
Accuracy
The temperature sensor accuracy is the deviation of the internal
measured temperature vs. the real ambient temperature normalized
to a 25°C measurement. Temperature sensor accuracy is measured
in °C.
Rev. 0 | 33 of 108
Data Sheet
AD4130-8
TERMINOLOGY
Sensitivity
The temperature sensor sensitivity is the output voltage change due
to a change in ambient temperature and is expressed in µV/K or
LSB/K.
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Rev. 0 | 34 of 108
Data Sheet
AD4130-8
NOISE AND RESOLUTION
Table 15 through Table 34 show the rms and peak-to-peak noise,
effective resolution, and noise-free (peak-to-peak) resolution of the
AD4130-8 for various output data rates, gain settings, and filters.
The numbers given are for the bipolar input range with an external
reference of 2.5 V for the 3.3 V operations and 1.25 V for the
1.8 V operations, with the reference buffers in bypass mode. These
numbers are typical and are generated with a differential input
voltage of 0 V when the ADC is continuously converting on a single
channel. It is important to note that the effective resolution is calculated using the rms noise, whereas the peak-to-peak resolution
(shown in parentheses) is calculated based on peak-to-peak noise
(shown in parentheses). The peak-to-peak resolution represents
the resolution for which there is no code flicker.
Effective Resolution = Log2(Input Range/RMS Noise)
Peak-to-Peak Resolution = Log2(Input Range/Peak-to-Peak Noise)
2.5 V REFERENCE
Sinc3
Table 15. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate, Expressed in µVRMS (µVP-P)
ODR
FS (Dec.) (SPS)
Gain = 1
f3dB (Hz) PGA_BYP = 1
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
2047
1.17
0.3
0.29 (0.6)
0.18 (0.4)
0.12 (0.3)
0.09 (0.25)
0.05 (0.12)
0.03 (0.07)
0.05 (0.14)
0.03 (0.08)
0.02 (0.07)
480
5
1.3
0.19 (0.4)
0.3 (0.79)
0.14 (0.4)
0.14 (0.35)
0.08 (0.22)
0.12 (0.35)
0.09 (0.24)
0.08 (0.23)
0.04 (0.09)
240
10
2.6
0.33 (0.99)
0.67 (2.19)
0.33 (0.99)
0.2 (0.65)
0.17 (0.6)
0.12 (0.45)
0.14 (0.5)
0.12 (0.39)
0.06 (0.19)
160
15
3.92
0.57 (1.99)
0.79 (2.38)
0.45 (1.59)
0.28 (1.09)
0.3 (1.04)
0.19 (0.6)
0.16 (0.58)
0.11 (0.4)
0.1 (0.36)
80
30
7.86
0.81 (3.18)
1.01 (3.77)
0.62 (2.38)
0.46 (2.04)
0.38 (1.42)
0.31 (1.28)
0.23 (0.96)
0.17 (0.72)
0.15 (0.63)
48
50
13.15
1.16 (5.36)
1.47 (6.56)
0.81 (3.38)
0.58 (2.83)
0.53 (2.36)
0.39 (1.8)
0.29 (1.44)
0.23 (1.01)
0.2 (0.95)
40
60
15.78
1.18 (5.56)
1.35 (6.36)
0.92 (4.37)
0.65 (2.98)
0.54 (2.53)
0.41 (1.91)
0.34 (1.55)
0.23 (1.04)
0.22 (1.03)
20
120
31.8
1.61 (8.74)
2.21 (11.1)
1.27 (6.26)
0.86 (4.67)
0.71 (3.65)
0.65 (3.44)
0.51 (2.81)
0.37 (1.87)
0.29 (1.51)
10
240
64.8
2.71 (17.5)
3.35 (18.1)
1.98 (11)
1.41 (7.75)
1.16 (5.96)
0.98 (5.58)
0.74 (4.19)
0.54 (3.23)
0.45 (2.52)
5
480
133.44
6.28 (37.4)
6.71 (37)
3.91 (22.9)
2.55 (14.5)
2.02 (11.1)
1.84 (10.6)
1.31 (7.46)
0.89 (4.72)
0.73 (4.05)
3
800
231.2
23.7 (132)
23.1 (118)
13.4 (69.4)
6.86 (38.7)
4.43 (27.1)
3.76 (22.9)
2.25 (13.6)
1.55 (8.48)
1.26 (7.55)
2
1
1200
2400
361.2
626.4
103 (572)
100 (636)
52.2 (278)
25.8 (146)
13.7 (73.1)
8.88 (47.9)
5.04 (28.2)
3.02 (17.2)
2.05 (10.9)
770 (4,154)
773 (4,357)
384 (2,068)
209 (1,089)
96.2 (587)
54. (321)
25.6 (133)
13.7 (80)
8.34 (46.4)
Table 16. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate, Expressed in Bits
FS (Dec.) ODR (SPS)
Gain = 1
PGA_BYP = 1
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
2047
1.17
24.03 (21.3)
24.1 (22.3)
23.8 (22)
23.8 (21.1)
23.7 (21)
23.5 (20.8)
21.75 (19)
21.3 (18.6)
20.7 (18)
480
5
24.02 (22.2)
24 (21.3)
24.1 (21.4)
23.1 (20.4)
22.9 (20.1)
21.3 (18.6)
20.85 (18.1)
19.9 (17.2)
20.1 (17.4)
240
10
23.85 (21.1)
22.9 (20.1)
22.9 (20.2)
22.6 (19.9)
21.8 (19.1)
21.3 (18.6)
20.1 (17.4)
19.4 (16.65)
19.45 (16.7)
160
15
23.1 (20.4)
22.6 (19.9)
22.4 (19.7)
22.2 (19.5)
21 (18.3)
20.6 (17.9)
19.9 (17.15)
19.45 (16.7)
18.6 (15.85)
80
30
22.6 (19.8)
22.2 (19.5)
21.9 (19.2)
21.4 (18.7)
20.7 (18)
19.9 (17.2)
19.35 (16.6)
18.8 (16.1)
18 (15.3)
48
50
22.1 (19.3)
21.7 (18.9)
21.6 (18.8)
21 (18.3)
20.2 (17.5)
19.6 (16.9)
19 (16.3)
18.4 (15.65)
17.6 (14.9)
40
60
22 (19.3)
21.8 (19.1)
21.4 (18.7)
20.9 (18.2)
20.2 (17.4)
19.5 (16.8)
18.8 (16.1)
18.4 (15.65)
17.4 (14.7)
20
120
21.6(18.8)
21.2 (18.4)
20.9 (18.2)
20.5 (17.7)
19.7 (17)
18.9 (16.2)
18.2 (15.5)
17.7 (15)
17 (14.3)
10
240
20.8 (18.1)
20.5 (17.8)
20.3 (17.5)
19.8 (17.0)
19 (16.3)
18.3 (15.6)
17.7 (14.95)
17.15 (14.4)
16.4 (13.7)
5
480
19.6 (16.9)
19.5 (16.8)
19.3 (16.6)
18.9 (16.2)
18.2 (15.5)
17.4 (14.7)
16.9 (14.15)
16.4 (13.7)
15.7 (13)
3
800
17.7 (15)
17.7 (15)
17.5 (14.8)
17.5 (14.8)
17.1 (14.4)
16.3 (13.6)
16.1 (13.35)
15.6 (12.9)
14.9 (12.2)
2
1200
15.6 (12.9)
15.6 (12.9)
15.6 (12.8)
15.6 (12.8)
15.5 (12.8)
15.1 (12.4)
14.9 (12.2)
14.6 (11.95)
14.2 (11.5)
1
2400
12.6 (10)
12.7 (9.9)
12.7 (9.9)
12.5 (9.8)
12.7 (9.9)
12.5 (9.8)
12.6 (9.85)
12.5 (9.75)
12.2 (9.5)
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Rev. 0 | 35 of 108
Data Sheet
AD4130-8
NOISE AND RESOLUTION
Sinc4
Table 17. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate, Expressed in µVRMS (µVP-P)
ODR
FS (Dec.) (SPS)
Gain = 1
f3dB (Hz) PGA_BYP = 1
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
10
240
55.68
2.33 (13.5)
3.15 (16.7)
1.78 (10.7)
1.22 (6.85)
1.1 (6.43)
0.87 (4.52)
0.68 (3.6)
0.48 (2.85)
0.39 (2.19)
8
300
70.2
2.98 (17.3)
3.32 (19.1)
2.05 (11.5)
1.45 (8)
1.16 (6.43)
1.04 (5.29)
0.8 (4.25)
0.57 (3.01)
0.45 (2.4)
4
600
144
4.65 (30.6)
5.75 (35.8)
3.61 (20.1)
2.64 (14.3)
2.19 (12.5)
2.01 (10.4)
1.34 (8.32)
0.99 (6.04)
0.79 (4.78)
2
1200
301.2
10.7 (61.2)
12.9 (69.5)
8.14 (49.7)
5.92 (32.3)
5.21 (32.6)
4.53 (26)
3.06 (18.2)
2.02 (11.1)
1.69 (9.81)
1
2400
544.8
74.2 (423)
73.9 (423)
38.7 (230)
22.5 (127)
15.6 (87.1)
13.3 (76.6)
7.7 (43.1)
5. (27.6)
4.13 (25.9)
Table 18. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate, Expressed in Bits
ODR
FS (Dec.) (SPS)
Gain = 1
PGA_BYP = 1
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
10
240
21 (18.3)
20.6 (17.9)
20.4 (17.7)
20 (17.2)
19.1 (16.4)
18.4 (15.7)
17.8 (15.1)
17.3 (14.6)
16.6 (13.9)
8
300
20.7 (18)
20.5 (17.8)
20.2 (17.5)
19.7 (17)
19 (16.3)
18.2 (15.5)
17.6 (14.9)
17.1 (14.4)
16.4 (13.7)
4
600
20 (17.3)
19.7 (17)
19.4 (16.7)
18.9 (16.1)
18.1 (15.4)
17.2 (14.5)
16.8 (14.1)
16.3 (13.5)
15.6 (12.9)
2
1200
18.8 (16.1)
18.6 (15.8)
18.2 (15.5)
17.7 (15)
16.9 (14.1)
16.1 (13.4)
15.6 (12.9)
15.2 (12.5)
14.5 (11.8)
1
2400
16 (13.3)
16 (13.3)
16 (13.3)
15.8 (13.)
15.3 (12.6)
14.5 (11.8)
14.3 (11.6)
13.9 (11.2)
13.2 (10.5)
Sinc3 + Sinc1 (Averaging Filter)
Table 19. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate, Expressed in µVRMS (µVP-P)
ODR
FS (Dec.) (SPS)
f3dB (Hz)
Gain = 1
PGA_BYP = 1
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
96
2.5
1.36
0.34 (0.79)
0.52 (1.39)
0.26 (0.7)
0.12 (0.35)
0.11 (0.3)
0.07 (0.2)
0.07 (0.19)
0.06 (0.15)
0.03 (0.1)
30
8
4.36
0.56 (1.79)
0.78 (2.38)
0.51 (1.49)
0.22 (0.7)
0.28 (0.82)
0.15 (0.48)
0.12 (0.4)
0.11 (0.34)
0.1 (0.35)
6
40
21.85
1.29 (5.56)
1.84 (8.54)
1.05 (4.77)
0.76 (3.08)
0.58 (2.46)
0.52 (2.45)
0.37 (1.56)
0.31 (1.42)
0.24 (1)
5
48
26.22
1.61 (7.35)
2. (8.34)
1.24 (6.06)
0.84 (3.73)
0.7 (3.05)
0.58 (2.57)
0.47 (2.06)
0.33 (1.64)
0.24 (1.11)
2
120
65.7
10.5 (54.2)
11.3 (53)
5.78 (28.5)
3.04 (15.4)
1.75 (9.06)
1.3 (6.47)
0.91 (4.84)
0.61 (2.83)
0.49 (2.5)
1
240
130.8
83.6 (515)
81.2 (456)
41.6 (223)
20.8 (111)
10.6 (60.7)
5.62 (33.4)
2.97 (15.6)
1.7 (10.6)
1.09 (5.99)
Table 20. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate, Expressed in Bits
ODR
FS (Dec.) (SPS)
Gain = 1
PGA_BYP = 1
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
96
2.5
23.8 (21.1)
23.2 (20.5)
23.2 (20.5)
23.5 (20.8)
22.5 (19.7)
22.1 (19.4)
21.2 (18.5)
20.4 (17.7)
20.4 (17.7)
30
8
23.2 (20.5)
22.6 (19.9)
22.3 (19.5)
22.6 (19.9)
21.2 (18.4)
20.9 (18.2)
20.3 (17.6)
19.5 (16.8)
18.5 (15.8)
6
40
21.9 (19.2)
21.4 (18.7)
21.2 (18.5)
20.7 (17.9)
20 (17.3)
19.2 (16.5)
18.7 (16.)
18 (15.2)
17.3 (14.6)
5
48
21.6 (18.9)
21.3 (18.5)
21 (18.2)
20.5 (17.8)
19.8 (17.1)
19.1 (16.3)
18.4 (15.6)
17.8 (15.1)
17.3 (14.6)
2
120
18.9 (16.1)
18.8 (16)
18.7 (16)
18.7 (15.9)
18.5 (15.7)
17.9 (15.2)
17.4 (14.7)
17 (14.2)
16.3 (13.6)
1
240
15.9 (13.1)
15.9 (13.2)
15.9 (13.2)
15.9 (13.2)
15.9 (13.1)
15.8 (13)
15.7 (13)
15.5 (12.8)
15.1 (12.4)
Sinc4 + Sinc1 (Averaging Filter)
Table 21. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate, Expressed in µVRMS (µVP-P)
ODR
FS (Dec.) (SPS)
f3dB
(Hz)
Gain = 1
PGA_BYP = 1
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
10
21.82
13.02
0.93 (3.38)
1.31 (5.36)
0.77 (3.38)
0.51 (2.19)
0.49 (1.96)
0.45 (1.81)
0.28 (1.08)
0.23 (0.87)
0.16 (0.63)
6
36.36
21.7
1.52 (6.76)
1.61 (7.15)
0.96 (4.07)
0.68 (2.63)
0.57 (2.68)
0.57 (2.72)
0.4 (1.68)
0.3 (1.29)
0.27 (1.03)
analog.com
Rev. 0 | 36 of 108
Data Sheet
AD4130-8
NOISE AND RESOLUTION
Table 21. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate, Expressed in µVRMS (µVP-P)
ODR
FS (Dec.) (SPS)
f3dB
(Hz)
Gain = 1
PGA_BYP = 1
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
5
43.64
26.04
1.55 (6.95)
1.89 (9.14)
1.08 (5.07)
0.81 (3.82)
0.68 (3.13)
0.54 (2.41)
0.45 (1.94)
0.32 (1.41)
0.28 (1.28)
2
109.1
62.25
2.78 (13.5)
3.3 (15.1)
2.05 (11.1)
1.36 (6.71)
1.33 (7.45)
1.12 (6.26)
0.84 (4.27)
0.55 (2.85)
0.46 (2.23)
1
218.18
129.9
8.34 (46.5)
8.78 (49.5)
5.04 (28.3)
3.2 (17.5)
2.63 (14.5)
2.29 (12.7)
1.6 (8.45)
1.04 (5.49)
0.81 (4.28)
Table 22. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate, Expressed in Bits
ODR
FS (Dec.) (SPS)
Gain = 1
PGA_BYP = 1
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
10
21.82
22.4 (19.6)
21.9 (19.1)
21.6 (18.9)
21.3 (18.5)
20.3 (17.6)
19.4 (16.7)
19.1 (16.4)
18.4 (15.7)
17.9 (15.2)
6
36.36
21.7 (18.9)
21.6 (18.9)
21.3 (18.6)
20.8 (18.1)
20.1 (17.3)
19.1 (16.3)
18.6 (15.9)
18 (15.3)
17.2 (14.4)
5
43.64
21.6 (18.9)
21.3 (18.6)
21.1 (18.4)
20.5 (17.8)
19.8 (17.1)
19.1 (16.4)
18.4 (15.7)
17.9 (15.2)
17.1 (14.4)
2
109.1
20.8 (18.1)
20.5 (17.8)
20.2 (17.5)
19.8 (17.1)
18.9 (16.1)
18.1 (15.4)
17.5 (14.8)
17.1 (14.4)
16.4 (13.7)
1
218.18
19.2 (16.5)
19.1 (16.4)
18.9 (16.2)
18.6 (15.9)
17.9 (15.1)
17.1 (14.3)
16.6 (13.9)
16.2 (13.5)
15.6 (12.8)
Post Filters
Table 23. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate, Expressed in µVRMS (µVP-P)
ODR
(SPS)
f3dB
(Hz)
Gain = 1
PGA_BYP = 1
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
Post Filter 4 16.21
12.54
1.12 (4.37)
1.17 (3.97)
0.66 (2.58)
0.53 (1.79)
0.35 (1.19)
0.36 (1.32)
0.31 (1.15)
0.2 (0.67)
0.17 (0.64)
Post Filter 3 19.355
13.08
1.18 (4.37)
1.44 (5.56)
0.85 (3.28)
0.71 (2.38)
0.45 (1.71)
0.47 (1.79)
0.28 (1.14)
0.23 (0.82)
0.2 (0.89)
Post Filter 2 24
14.7
1.2 (4.77)
1.64 (7.55)
0.99 (3.97)
0.62 (2.38)
0.54 (2.21)
0.41 (1.69)
0.36 (1.62)
0.2 (0.8)
0.19 (0.81)
Post Filter 1 26.087
16.68
1.2 (4.57)
1.48 (5.96)
0.84 (3.68)
0.68 (2.63)
0.54 (2.31)
0.48 (1.94)
0.38 (1.58)
0.22 (0.91)
0.21 (0.83)
Filter Type
Table 24. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate, Expressed in Bits
Filter Type
ODR
(SPS)
Gain = 1
PGA_BYP = 1
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
Post Filter 4
16.21
22.1 (19.4)
22 (19.3)
21.9 (19.1)
21.2 (18.5)
20.8 (18.1)
19.7 (17)
19 (16.3)
18.6 (15.9)
17.9 (15.1)
Post Filter 3
19.355
22 (19.3)
21.7 (19)
21.5 (18.8)
20.7 (18)
20.4 (17.7)
19.4 (16.6)
19.1 (16.4)
18.4 (15.7)
17.6 (14.9)
Post Filter 2
24
22 (19.3)
21.5 (18.8)
21.3 (18.6)
21 (18.2)
20.1 (17.4)
19.6 (16.8)
18.7 (16)
18.6 (15.9)
17.6 (14.9)
Post Filter 1
26.087
22 (19.3)
21.7 (19)
21.5 (18.8)
20.8 (18.1)
20.1 (17.4)
19.3 (16.6)
18.7 (15.9)
18.4 (15.7)
17.5 (14.8)
1.25 V REFERENCE
Sinc3
Table 25. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate, Expressed in µVRMS (µVP-P)
ODR
FS (Dec.) (SPS)
Gain = 1
f3dB (Hz) PGA_BYP = 1
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
2047
1.17
0.3
0.12 (0.3)
0.23 (0.6)
0.08 (0.2)
0.08 (0.22)
0.04 (0.11)
0.05 (0.14)
0.04 (0.11)
0.02 (0.05)
0.02 (0.06)
480
5
1.3
0.26 (0.7)
0.27 (0.7)
0.21 (0.55)
0.09 (0.22)
0.08 (0.22)
0.09 (0.24)
0.08 (0.21)
0.04 (0.13)
0.06 (0.17)
240
10
2.6
0.46 (1.49)
0.57 (2.09)
0.3 (0.99)
0.23 (0.75)
0.2 (0.68)
0.15 (0.55)
0.12 (0.39)
0.09 (0.3)
0.08 (0.28)
160
15
3.92
0.51 (1.79)
0.68 (2.28)
0.35 (1.24)
0.34 (1.19)
0.26 (0.92)
0.22 (0.83)
0.2 (0.71)
0.12 (0.41)
0.1 (0.33)
80
30
7.86
0.75 (3.18)
0.84 (3.48)
0.71 (3.18)
0.38 (1.81)
0.35 (1.48)
0.33 (1.2)
0.2 (0.83)
0.16 (0.64)
0.14 (0.57)
48
50
13.15
1.01 (4.57)
1.33 (5.76)
0.81 (3.38)
0.53 (2.38)
0.44 (1.95)
0.35 (1.53)
0.31 (1.58)
0.22 (1.07)
0.19 (0.9)
40
60
15.78
1.14 (5.46)
1.33 (6.16)
0.92 (4.37)
0.64 (3.2)
0.54 (2.6)
0.46 (2.16)
0.34 (1.57)
0.24 (1.01)
0.2 (0.95)
20
120
31.8
1.67 (8.64)
2.25 (12.1)
1.32 (6.8)
0.87 (4.47)
0.72 (3.75)
0.61 (3.04)
0.51 (2.68)
0.39 (1.9)
0.29 (1.46)
analog.com
Rev. 0 | 37 of 108
Data Sheet
AD4130-8
NOISE AND RESOLUTION
Table 25. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate, Expressed in µVRMS (µVP-P)
ODR
FS (Dec.) (SPS)
Gain = 1
f3dB (Hz) PGA_BYP = 1
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
10
240
64.8
2.51 (14.4)
3.03 (16.1)
1.85 (10.7)
1.27 (6.9)
1.09 (6.3)
0.96 (5)
0.74 (4.01)
0.5 (2.81)
0.44 (2.41)
5
480
133.44
4.26 (25.1)
5.32 (31.9)
3.06 (16.7)
2.31 (14.9)
1.93 (10.9)
1.71 (9.58)
1.2 (6.97)
0.88 (4.64)
0.74 (4.06)
3
800
231.2
12 (66)
13.1 (70.6)
7.4 (43.6)
4.62 (27.5)
3.59 (21.4)
3.25 (17.7)
2.12 (12)
1.43 (8.37)
1.16 (6.99)
2
1200
361.2
51.7 (269)
49.3 (297)
25.6 (130)
13.4 (71.8)
8.74 (49.3)
6.15 (33.6)
3.93 (22.3)
2.57 (13.6)
2.09 (12)
1
2400
626.4
402 (2,306)
370 (2,051)
200 (1,068)
98. (530)
51.2 (283)
27.4 (149)
14.2 (76.8)
8.68 (47.9)
6.01 (34.3)
Table 26. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate, Expressed in Bits
FS (Dec.) ODR (SPS)
Gain = 1
PGA_BYP = 1
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
2047
1.17
24.3 (21.6)
23.4 (20.7)
24 (21.3)
22.8 (20.1)
22.9 (20.2)
21.6 (18.9)
20.8 (18.1)
21.2 (18.5)
2 (17.3)
480
5
23.2 (20.5)
23.2 (20.4)
22.5 (19.8)
22.8 (20)
22 (19.3)
20.8 (18.)
20.1 (17.4)
19.8 (17)
18.4 (15.7)
240
10
22.4 (19.7)
22.1 (19.3)
22 (19.3)
21.4 (18.7)
20.6 (17.9)
20 (17.3)
19.5 (16.7)
18.7 (16)
17.9 (15.2)
160
15
22.2 (19.5)
21.9 (19.1)
21.8 (19)
20.8 (18.1)
20.2 (17.5)
19.5 (16.8)
18.6 (15.9)
18.3 (15.6)
17.6 (14.9)
80
30
21.7 (18.9)
21.5 (18.8)
20.7 (18)
20.7 (17.9)
19.8 (17)
18.9 (16.1)
18.6 (15.9)
17.9 (15.2)
17.1 (14.4)
48
50
21.2 (18.5)
20.8 (18.1)
20.6 (17.8)
20.2 (17.5)
19.5 (16.7)
18.8 (16)
17.9 (15.2)
17.4 (14.7)
16.7 (14)
40
60
21.1 (18.3)
20.8 (18.1)
20.4 (17.7)
19.9 (17.2)
19.2 (16.4)
18.4 (15.7)
17.8 (15.1)
17.3 (14.6)
16.6 (13.9)
20
120
20.5 (17.8)
20.1 (17.4)
19.9 (17.1)
19.5 (16.7)
18.7 (16.)
18 (15.3)
17.2 (14.5)
16.6 (13.9)
16 (13.3)
10
240
19.9 (17.2)
19.7 (16.9)
19.4 (16.6)
18.9 (16.2)
18.1 (15.4)
17.3 (14.6)
16.7 (14)
16.3 (13.5)
15.5 (12.7)
5
480
19.2 (16.4)
18.8 (16.1)
18.6 (15.9)
18. (15.3)
17.3 (14.6)
16.5 (13.8)
16 (13.3)
15.4 (12.7)
14.7 (12)
3
800
17.7 (14.9)
17.5 (14.8)
17.4 (14.6)
17 (14.3)
16.4 (13.7)
15.6 (12.8)
15.2 (12.4)
14.7 (12)
14 (11.3)
2
1200
15.6 (12.8)
15.6 (12.9)
15.6 (12.9)
15.5 (12.8)
15.1 (12.4)
14.6 (11.9)
14.3 (11.6)
13.9 (11.2)
13.2 (10.5)
1
2400
12.6 (9.89)
12.7 (10)
12.6 (9.89)
12.6 (9.92)
12.6 (9.85)
12.5 (9.75)
12.4 (9.7)
12.1 (9.41)
11.7 (8.94)
Sinc4
Table 27. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate, Expressed in µVRMS (µVP-P)
ODR
FS (Dec.) (SPS)
Gain = 1
f3dB (Hz) PGA_BYP = 1
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
10
240
55.68
2.27 (12.4)
2.71 (14.5)
1.69 (9.19)
1.22 (7.1)
1.02 (5.59)
0.89 (4.45)
0.7 (3.96)
0.51 (2.77)
0.41 (2.47)
8
300
70.2
2.59 (15.2)
3.25 (17.3)
2.03 (11.2)
1.41 (8.2)
1.2 (6.46)
1.04 (5.85)
0.82 (4.59)
0.55 (3.45)
0.46 (2.59)
4
600
144
4 (24.4)
4.95 (27.7)
3.3 (18.)
2.34 (12.7)
2.12 (12.5)
1.86 (10.1)
1.24 (6.8)
0.9 (4.86)
0.79 (4.74)
2
1200
301.2
7.07 (39.)
10.1 (56.1)
6.42 (33.3)
5.41 (30.2)
4.56 (24.8)
4.41 (25.7)
2.82 (16)
2 (11.6)
1.65 (9.33)
1
2400
544.8
38.3 (209)
44.7 (259)
24 (135)
16.6 (106)
12.5 (73.3)
11.4 (59.2)
7.47 (45.4)
4.76 (29.9)
4.04 (23.6)
Table 28. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate, Expressed in Bits
ODR
FS (Dec.) (SPS)
Gain = 1
PGA_BYP = 1
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
10
240
20.1 (17.3)
19.8 (17.1)
19.5 (16.8)
19 (16.2)
18.2 (15.5)
17.4 (14.7)
16.8 (14)
16.2 (13.5)
15.5 (12.8)
8
300
19.9 (17.2)
19.6 (16.8)
19.2 (16.5)
18.8 (16.)
18 (15.3)
17.2 (14.5)
16.5 (13.8)
16.1 (13.4)
15.4 (12.7)
4
600
19.3 (16.5)
18.9 (16.2)
18.5 (15.8)
18 (15.3)
17.2 (14.4)
16.4 (13.6)
15.9 (13.2)
15.4 (12.7)
14.6 (11.9)
2
1200
18.4 (15.7)
17.9 (15.2)
17.6 (14.8)
16.8 (14.1)
16.1 (13.3)
15.1 (12.4)
14.8 (12)
14.3 (11.5)
13.5 (10.8)
1
2400
16 (13.3)
15.8 (13.)
15.7 (12.9)
15.2 (12.5)
14.6 (11.9)
13.7 (11.)
13.4 (10.6)
13 (10.3)
12.2 (9.52)
analog.com
Rev. 0 | 38 of 108
Data Sheet
AD4130-8
NOISE AND RESOLUTION
Sinc3 + Sinc1 (Averaging Filter)
Table 29. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate, Expressed in µVRMS (µVP-P)
ODR
FS (Dec.) (SPS)
f3dB (Hz)
Gain = 1
PGA_BYP = 1
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
96
2.5
1.36
0.29 (0.79)
0.35 (0.99)
0.17 (0.5)
0.14 (0.37)
0.11 (0.3)
0.1 (0.26)
0.08 (0.21)
0.04 (0.11)
0.06 (0.17)
30
8
4.36
0.43 (1.29)
0.57 (1.79)
0.52 (1.49)
0.31 (0.94)
0.31 (0.92)
0.21 (0.64)
0.19 (0.65)
0.11 (0.35)
0.1 (0.3)
6
40
21.85
1.41 (5.76)
1.42 (6.46)
1.11 (4.97)
0.78 (3.45)
0.61 (2.63)
0.54 (2.27)
0.44 (1.98)
0.28 (1.18)
0.26 (1.05)
5
48
26.22
1.5 (7.75)
2.12 (9.34)
1.18 (5.71)
0.77 (3.7)
0.69 (3.14)
0.62 (2.73)
0.46 (2.12)
0.35 (1.51)
0.27 (1.2)
2
120
65.7
5.81 (28.3)
5.87 (28.8)
3.4 (17.6)
1.93 (9.76)
1.46 (7.86)
1.13 (5.9)
0.84 (4.68)
0.58 (2.8)
0.47 (2.28)
1
240
130.8
39.4 (218)
42.1 (230)
20.1 (111)
10.8 (59.6)
5.52 (29.9)
3.33 (19.7)
1.97 (10.2)
1.2 (6.82)
0.98 (5.81)
Table 30. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate, Expressed in Bits
ODR
FS (Dec.) (SPS)
Gain = 1
PGA_BYP = 1
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
96
2.5
23.1 (20.4)
22.9 (20.2)
22.8 (20.1)
22.3 (19.6)
21.5 (18.7)
20.8 (18.1)
20. (17.3)
20.1 (17.4)
18.4 (15.7)
30
8
22.5 (19.8)
22.1 (19.4)
21.2 (18.5)
21 (18.2)
20 (17.3)
19.6 (16.9)
18.7 (15.9)
18.5 (15.8)
17.7 (15.)
6
40
20.8 (18.)
20.8 (18.)
20.1 (17.4)
19.6 (16.9)
19. (16.3)
18.2 (15.4)
17.5 (14.7)
17.1 (14.4)
16.2 (13.5)
5
48
20.7 (17.9)
20.2 (17.4)
20 (17.3)
19.6 (16.9)
18.8 (16.1)
18 (15.2)
17.4 (14.6)
16.8 (14.1)
16.2 (13.4)
2
120
18.7 (16.)
18.7 (16.)
18.5 (15.8)
18.3 (15.6)
17.7 (15.)
17.1 (14.4)
16.5 (13.8)
16 (13.3)
15.4 (12.6)
1
240
16 (13.2)
15.9 (13.1)
15.9 (13.2)
15.8 (13.1)
15.8 (13.1)
15.5 (12.8)
15.3 (12.6)
15 (12.3)
14.3 (11.6)
Sinc4 + Sinc1 (Averaging Filter)
Table 31. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate, Expressed in µVRMS (µVP-P)
ODR
FS (Dec.) (SPS)
f3dB
(Hz)
Gain = 1
PGA_BYP = 1
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
10
21.82
13.02
1.15 (4.37)
1.43 (5.36)
0.69 (2.78)
0.54 (1.91)
0.52 (2.24)
0.38 (1.61)
0.3 (1.15)
0.23 (0.88)
0.17 (0.59)
6
36.36
21.7
1.32 (6.26)
1.64 (6.66)
1.17 (4.87)
0.75 (3.48)
0.64 (2.81)
0.55 (2.4)
0.44 (1.97)
0.28 (1.2)
0.24 (0.96)
5
43.64
26.04
1.45 (6.66)
2.1 (8.54)
1. (4.62)
0.82 (3.5)
0.69 (2.52)
0.54 (2.48)
0.5 (2.17)
0.38 (1.73)
0.29 (1.26)
2
109.1
62.25
2.41 (13.2)
3.24 (19.)
2.06 (9.74)
1.33 (7.05)
1.19 (6.)
1.04 (4.96)
0.81 (4.63)
0.55 (2.79)
0.48 (2.48)
1
218.18
129.9
5.58 (32.6)
6.35 (34.4)
3.96 (20.3)
2.65 (15.2)
2.38 (12.9)
2.09 (11.8)
1.49 (7.97)
0.97 (5.65)
0.87 (4.96)
Table 32. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate, Expressed in Bits
ODR
FS (Dec.) (SPS)
Gain = 1
PGA_BYP = 1
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
30
21.82
21.1 (18.3)
20.7 (18.)
20.8 (18.1)
20.2 (17.4)
19.2 (16.5)
18.7 (16.)
18 (15.3)
17.4 (14.7)
16.9 (14.1)
6
36.36
20.9 (18.1)
20.5 (17.8)
20 (17.3)
19.7 (17.)
18.9 (16.2)
18.1 (15.4)
17.4 (14.7)
17.1 (14.4)
16.3 (13.6)
5
43.64
20.7 (18.)
20.2 (17.5)
20.3 (17.5)
19.6 (16.8)
18.8 (16.1)
18.1 (15.4)
17.3 (14.5)
16.7 (14.)
16 (13.3)
2
109.1
20 (17.3)
19.6 (16.8)
19.2 (16.5)
18.8 (16.1)
18 (15.3)
17.2 (14.5)
16.6 (13.8)
16.1 (13.4)
15.3 (12.6)
1
218.18
18.8 (16.1)
18.6 (15.9)
18.3 (15.5)
17.9 (15.1)
17 (14.3)
16.2 (13.5)
15.7 (13.)
15.3 (12.6)
14.4 (11.7)
Post Filters
Table 33. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate, Expressed in µVRMS (µVP-P)
f3dB
(Hz)
Gain = 1
PGA_BYP = 1
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
Post Filter 4 16.21
12.54
1.11 (3.87)
1.24 (4.57)
0.78 (2.63)
0.55 (2.06)
0.34 (1.32)
0.33 (1.21)
0.28 (1.09)
0.2 (0.67)
0.2 (0.76)
Post Filter 3 19.355
13.08
1.02 (3.77)
1.39 (5.27)
0.7 (2.73)
0.51 (2.01)
0.53 (2.06)
0.42 (1.68)
0.33 (1.39)
0.23 (0.92)
0.2 (0.78)
Post Filter 2 24
14.7
1.11 (4.57)
1.33 (5.66)
0.85 (3.63)
0.59 (2.33)
0.52 (2.02)
0.42 (1.82)
0.37 (1.5)
0.2 (0.76)
0.19 (0.85)
Post Filter 1 26.087
16.68
1.3 (5.46)
1.42 (6.16)
0.84 (3.28)
0.54 (2.36)
0.48 (1.95)
0.48 (1.99)
0.38 (1.58)
0.26 (1.06)
0.23 (0.91)
Filter Type
ODR
(SPS)
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Rev. 0 | 39 of 108
Data Sheet
AD4130-8
NOISE AND RESOLUTION
Table 34. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate, Expressed in Bits
Filter Type
ODR
(SPS)
Gain = 1
PGA_BYP = 1
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
Post Filter 4
16.21
21.1 (18.4)
21 (18.2)
20.6 (17.9)
20.1 (17.4)
19.8 (17.1)
18.9 (16.1)
18.1 (15.4)
17.6 (14.9)
16.6 (13.8)
Post Filter 3
19.355
21.2 (18.5)
20.8 (18.1)
20.8 (18.1)
20.2 (17.5)
19.2 (16.5)
18.5 (15.8)
17.9 (15.2)
17.4 (14.6)
16.6 (13.9)
Post Filter 2
24
21.1 (18.4)
20.8 (18.1)
20.5 (17.8)
20 (17.3)
19.2 (16.5)
18.5 (15.8)
17.7 (15.)
17.6 (14.8)
16.6 (13.9)
Post Filter 1
26.087
20.9 (18.2)
20.8 (18.)
20.5 (17.8)
20.1 (17.4)
19.3 (16.6)
18.3 (15.6)
17.7 (14.9)
17.2 (14.5)
16.4 (13.6)
NOISE SPECTRAL DENSITY
The noise spectral density is derived from the 2.5 V reference rms noise values for the sinc3 filter at a lower ODR, divided by 1.15 times the
square root of the input bandwidth.
Table 35. Input Referred Noise Spectral Density, Expressed in nV/√Hz
Gain = 1
PGA_BYP = 1
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
303
369
214
152
123
99
85
64
48
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Rev. 0 | 40 of 108
Data Sheet
AD4130-8
THEORY OF OPERATION
Figure 69. Detailed Block Diagram
OVERVIEW
ADC CORE
The AD4130-8 is an ultra low power, 24-bit ADC that incorporates
a Σ-Δ modulator, an input crosspoint multiplexer (X-MUX), a PGA
stage, an internal reference and reference buffers, and on-chip
digital filtering, which is intended for the measurement of high
dynamic range, low frequency signals, such as those in pressure
transducers, weigh scales, and temperature measurement applications. Each block of the AD4130-8 and its functionality is optimized
for low power operations in battery-powered applications. Included
on chip is a suite of integrated functions to connect and power
multiple sensors, such as excitation currents, a low-side power
switch, bias voltage, and burnout currents. The combination of a
smart sequencer, duty cycling ability, and FIFO buffer allows the
rest of the system to sleep while the AD4130-8 autonomously
gathers measurements according to the predefined configuration.
User defined interrupt functionality allows the microcontroller to
wake when a problem occurs, or the FIFO is ready to be read.
The AD4130-8 contains a Σ-Δ-based ADC core, composed of a
MASH22 Σ-Δ modulator (fMOD = 38.4 kHz), followed by a digital
filter. The ADC core inherently rejects frequencies at 38.4 kHz.
The Σ-Δ ADC highly digital architecture is ideally suited for modern fine-line CMOS processes, thereby allowing easy addition of
digital functionality without significantly increasing the cost. Using
oversampling, quantization noise shaping, digital filtering, and decimation, a Σ-Δ ADC offers several advantages over the other architectures, especially for high resolution, low frequency applications.
Refer to MT-022 and MT-023 for a deep dive in Σ-Δ ADC theory.
Digital Filter
The AD4130-8 offers several digital filter options. The option selected affects the input bandwidth, output data rate, achievable noise
performance, settling time, and 50 Hz and 60 Hz rejection. The
device filter options are listed in Table 36. See the Digital Filters
section for full details.
Table 36. AD4130-8 Filter Options
Filter Type
FS Range (Hex)
Output Data Rate (SPS)1
Comments
ADC frequency (fADC) = fMCLK / 32 / FS.
Sinc4
0x01 to 0xA
2400 to 240
Sinc4 + Sinc1
0x01 to 0xA
Sinc3
Sinc3 + REJ60
Sinc3 + Sinc1
0x01 to 0x7FF
0x01 to 0x7FF
0x01 to 0x7FF
Sinc3 + Post Filters
N/A2
Averaging filter. Sinc4 plus averaging by 8. fADC = fMCLK / (32 × FS × (4 + AVG −1)), where
AVG = 8.
2400 to 1.17
fADC = fMCLK/32/FS.
2400 to 1.17
FS = 0d48 can be set to simultaneously reject 50 Hz and 60 Hz at 50 SPS ODR.
240 to 0.117 (Dec.: 1 to 2047) Averaging filter. Sinc3 plus averaging by 8. Recommended for FS from 0x01 to 0xCC only
(minimum ODR = 1.17). fADC = fMCLK/(32 × FS × (3 + AVG −1)), where AVG = 8.
16.21, 19.355, 24, 26.087
Low latency with good 50 Hz and 60 Hz rejection.
1
Assuming accurate fMCLK = 76.8 kHz.
2
N/A means not applicable.
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218.18 to 21.8
Rev. 0 | 41 of 108
Data Sheet
AD4130-8
THEORY OF OPERATION
ADC MASTER CLOCK
The Σ-Δ ADC core needs a 76.8 kHz MCLK to operate the internal
modulator (fMOD = fMCLK/2 = 38.4 kHz). The device has an internal
oscillator to generate the MCLK. The internal clock is selected by
default and can be made available at the CLK pin if a clock source
is required for external circuitry. An external clock applied to the
CLK pin can also be selected as the MCLK source for the device.
Using an external clock can enable several ADCs to be driven
from a common clock, allowing simultaneous conversions to be
performed. The external clock can be either 76.8 kHz or 153.6 kHz
when the internal divide by two option is selected.
Use the MCLK_SEL bits in the ADC_CONTROL register to select
the appropriate option according to Table 37 (see the ADC Control
Register section). Refer to Figure 69 for a block diagram of the
AD4130-8 ADC clock connection scheme.
Table 37. MCLK Source Options
MCLK_SEL
MCLK Source
Source Clock Frequency (kHz)
0b00 (Default)
0b01
0b10
0b11
Internal, output off
Internal, output on
External, divider off
External, divider on
76.8
76.8
76.8
153.6
The CLK pin, if not used, can instead be selected as the interrupt
source using the INT_PIN_SEL bit in the IO_CONTROL register
(see the Input/Output Control Register section for details). Note that
the interrupt setting takes priority on the CLK_SEL bit setting in the
ADC_CONTROL register.
designed to reduce the supply current consumption (IDD) contribution of the internal reference continuously turning on and off. In the
scenario that duty cycling is used and the internal reference is used
to power a sensor, it is recommended to keep the reference on
during the standby phase by enabling the STBY_REFCORE_EN bit
to 1 in the MISC register. See the Standby Mode section for more
details on the blocks that can be kept active when in standby during
duty cycling.
An external voltage reference can be supplied at the two external
reference input options: REFIN1(±) or REFIN2(±). The external
reference option can be useful when ratio-metric measurement is
required on some channels, such as when interfacing to an RTD
temperature sensor.
Refer to Figure 69 for a simplified schematic of the AD4130-8 ADC
reference connection scheme.
Reference Buffers
Reference buffers are also included on chip, and they can be
used with the internal reference or an externally applied reference.
The buffers bypass option allows full rail-to-rail reference input up
to the analog supply value, whereas the buffers enabled option
allows for a lower reference input current. Both options have similar
AVDD current. See Table 3 for related specifications. Reference
buffers can be enabled on a per channel basis, in each CONFIG_n
register.
ANALOG FRONT END
ADC REFERENCE
Analog Input Multiplexer
The AD4130-8 requires a precision reference voltage for the ADC
core. The reference source for the AD4130-8 can be selected for
each ADC setup (see the ADC Configuration and Operations section for full details) using the REF_SEL bits in each the CONFIG_n
register (see Table 48).
The device can have 8 differential or 16 pseudo differential analog
inputs. The AD4130-8 uses flexible multiplexing; thus, any analog
input pin can be selected as a positive input (AINP) and any analog
input pin can be selected as a negative input (AINM), as described
in Figure 70. This feature allows the user to perform diagnostics,
such as checking that pins are connected. This feature also simplifies PCB design. For example, the same PCB can accommodate
2-wire, 3-wire, and 4-wire RTDs.
The AD4130-8 integrates a band gap voltage reference that can
be configured to give a 1.25 V or a 2.5 V low noise voltage
reference (see the specifications in Table 3). The internal reference
is disabled by default. To enable the internal reference, set the
INT_REF_EN bit in the ADC_CONTROL register to 1. The 2.5 V internal reference is selected by default. A 1 nF capacitor is required
on the REFOUT pin when the internal reference is active. Note
that when the AVDD supply is set to below 2.5 V, the internal
reference of 1.25 V is selected by setting the INT_REF_VAL bit in
the ADC_CONTROL register to 1. This bit has effect only when the
internal reference is enabled. The internal reference value is set to
2.5 V by default.
When entering and exiting standby mode (that is, while using duty
cycling mode) while using the internal reference, and providing that
the reference is not loaded by any external circuitry other than its
decoupling, it is recommended to set the STBY_REFHOL_EN bit
to 1 in the MISC register. This enables the reference holder that is
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Rev. 0 | 42 of 108
Data Sheet
AD4130-8
THEORY OF OPERATION
The user can decide to turn off the excitation currents automatically
when the device is in standby mode by setting the STB_EN_IEXC
bit to 1 in the MISC register.
Note that the on-chip reference does not need to be enabled when
using the excitation currents.
Bias Voltage Generator
A bias voltage generator is included on the AD4130-8. The bias
voltage is selectable on all analog input channels. It biases the
selected input pin to (AVDD − AVSS)/2. This function is useful in
thermocouple applications, as the voltage generated by the thermocouple must be biased around some dc voltage if the ADC operates
from a single power supply. The bias voltage generator is controlled
using the V_BIAS bitfield in the VBIAS_CONTROL register. The
power-up time of the bias voltage generator is dependent on the
load capacitance. See Table 4 for more details.
Secondary Reference Input
Two of the AD4130-8 inputs can be reconfigured to become the
reference inputs instead.
General-Purpose Output
Figure 70. Analog Input Multiplexer Circuit
The on-chip multiplexer increases the channel count of the device
and guarantees that all channel changes are synchronized with the
conversion process.
The channel inputs are configured using the AINP_m, Bits[4:0]
and the AINM_m, Bits[4:0] in the CHANNEL_m registers. The
device can be configured to have 8 differential inputs, 16 pseudo
differential inputs, or a combination of both.
When using differential inputs, use adjacent analog input pins to
form the input pair. Using adjacent pins minimizes any mismatch
between the channels.
Excitation Currents
The device contains two excitation currents, IEXC0 and IEXC1, that
can be set independently to 100 nA, 10 µA, 20 µA, 50 µA, 100 µA,
150 µA, and 200 µA by setting the I_OUT0_n and I_OUT1_n
bitfields in the CONFIG_n registers. See Table 4 for excitation
currents specifications.
IEXC0 and IEXC1 can be configured to operate on any channel
by setting the I_OUT0_CH_m and I_OUT1_CH_m bitfields in the
CHANNEL_m registers. In addition, both currents can be output
to the same analog input pin. The user can select the front-end
settling time (SETTLE_n bits in the FILTER_n register) when multiplexing between channels, after which the conversion process
begins.
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The AD4130-8 has four general-purpose outputs (GPOs), the P1
to P4 pins. These outputs are enabled using the GPO_CTRL_Px
bits in the IO_CONTROL register (see Table 39). The pins can be
pulled high or low using the GPO_DATA_Px bits in the register;
that is, the value at the pin is determined by the setting of the
GPO_DATA_Px bits. These pins can be used as general-purpose
outputs, referenced between AVSS and AVDD.
When AVSS is tied to DGND and IOVDD is tied to AVDD, these pins
can operate as digital outputs with logic levels determined by AVDD
rather than by IOVDD. In this configuration, some GPOs can be
repurposed for different uses. The P2 (AIN3) pin can be selected
to function as the interrupt source (see the Data Ready Signal
section). The P4 pin (AIN5) can be selected to flag when the device
is in standby mode (see the Power-Down Modes section).
Power-Down Switch
A low-side power switch (PSW) allows the user to power-down
bridges that are interfaced to the ADC. In bridge applications such
as strain gauges and load cells, the bridge itself consumes the
majority of the current in the system. For example, a 350 Ω load
cell requires 8.6 mA of current when excited with a 3 V supply. To
minimize the current consumption of the system, the bridge can be
disconnected, when not being used, using the bridge power-down
switch. See Table 4 for the switch specifications. The control of the
PSW can be automated by using the channel sequencer. Every
channel configuration has a dedicated PDSW_m bitfield in the
CHANNEL_m register.
Rev. 0 | 43 of 108
Data Sheet
AD4130-8
THEORY OF OPERATION
PROGRAMMABLE GAIN AMPLIFIER
The analog input range is ±VREF/gain. See Table 38.
When the gain stage is enabled, the output from the multiplexer is
applied to the input of the PGA. The presence of the PGA means
that signals of small amplitude can be gained within the AD4130-8
and still maintain excellent noise performance. The PGA can be
programmed to have a gain of 1, 2, 4, 8, 16, 32, 64, or 128 by using
the PGA bits in the respective CONFIG_n register.
Table 38. Absolute Input Range Examples
It is also possible to bypass the PGA by enabling the PGA_BYP_n
bit in each CONFIG_n register. Once this bit is set to 1, the PGA
is bypassed, so the gain control is not available and a gain of
1 is used. PGA bypass mode can be used to save power and
reduce the noise even further, at the expense of higher analog input
current. See the Power Specifications section and the Analog Input
Currents section for further details.
2.5 V Reference
1.25 V Reference
PGA
Gain
Unipolar
Bipolar
Unipolar
Bipolar
1
32
128
0 to 2.5 V
0 to 78.12 mV
0 to 19.53 mV
±2.5 V
±78.12 mV
±19.53 mV
0 to 1.25 V
0 to 39.06 mV
0 to 9.76 mV
±1.25 V
±39.06 mV
±9.76 mV
For high reference values, for example, VREF = AVDD, the analog
input range must be limited. Consult Table 2 for more details on
these limits.
Table 39. IO_CONTROL Register
Addr. Name
0x03
Bits
Bit 7
IO_CONT [15:8]
ROL
[7:0] GPO_DATA_
P4
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Bit 6
GPO_DATA_
P3
Bit 5
Bit 4
RESERVED
SYNCB_CLE
INT_PIN_SEL
0x0000
AR
GPO_DATA_ GPO_CTRL_ GPO_CTRL_ GPO_CTRL_ GPO_CTRL_
P1
P4
P3
P2
P1
GPO_DATA_
P2
Bit 3
Bit 2
Bit 1
Bit 0
Reset
RW
R/W
Rev. 0 | 44 of 108
Data Sheet
AD4130-8
THEORY OF OPERATION
OTHER FEATURES
Calibration
Both internal calibration and system calibration are available on
chip; therefore, the user has the option of removing offset or
gain errors internal to the device only, or removing the offset or
gain errors of the complete end system. See the ADC Calibration
section.
Sequencer
The AD4130-8 allows up to 16 channels, and up to eight different
ADC setups to be preconfigured and selected for each channel.
The sequencer automatically converts all enabled channels. See
the Smart Channel Sequencer section for full details.
Diagnostics
The AD4130-8 includes numerous diagnostics features that allow a
high level of fault coverage in an application, such as:
►
►
►
►
►
►
Reference detection
Overvoltage/undervoltage detection
ADC functionality checks
CRC on SPI communications
CRC on the memory map
SPI read/write checks
The low supply range option is advantageous for battery-powered
operation, with the AD4130-8 performance still achievable with a
single supply for both AVDD and IOVDD as low as 1.71 V.
See the Power Schemes section and Recommended Decoupling
section.
Internal LDOs
The two internal LDOs power the analog and digital domains
separately. A decoupling capacitor of 0.1 μF is required on the
REGCAPA and REGCAPD pins, which are the outputs of the AVDD
and IOVDD LDOs, respectively.
Power-On Reset
The AD4130-8 is designed to generate a power-on reset (POR)
signal when the IOVDD voltage is first applied, as shown in Figure
71. A POR resets the state of the user configuration registers. If
IOVDD and the digital LDOs drops below its specified operating
range, a POR occurs. A drop on AVDD and the analog LDO does
not trigger a reset of the device.
The POR_FLAG in the status register (see Table 46) is set to 1 if
IOVDD or the digital LDO supply dips below the threshold, and is
cleared when the user reads the status register.
See the Diagnostics section for full details.
FIFO Buffer
The AD4130-8 has an on-chip FIFO buffer to facilitate storage of up
to 256 conversion results. See the FIFO section for full details.
POWER SUPPLIES
The device has two independent power supply pins: AVDD and
IOVDD.
AVDD is referred to AVSS and powers the internal analog regulator
that supplies the ADC. The AVDD − AVSS supply range is from
1.71 V to 3.6 V.
AVSS is either tied to DGND or it can be taken below 0 V to provide
a dual power supply to the AD4130-8. For example, AVSS can be
tied to −1.8 V and AVDD can be tied to +1.8 V, providing a ±1.8 V
supply to the ADC. The AVSS supply range is from −1.8 V to 0 V
with respect to DGND.
IOVDD is referred to DGND and sets the interface logic levels on
the SPI, and powers an internal regulator for operation of the digital
processing. The digital IOVDD supply can vary between 1.65 V to
3.6 V with respect to DGND.
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Figure 71. POR Timing Diagram
After power-on or software reset, the AD4130-8 default configuration is as follows:
Channel: in the CHANNEL_0 register, the channel is enabled,
AIN0 is selected as the positive input, and AIN1 is selected as
the negative input. SETUP_m = 0 is selected.
► ADC setup (SETUP_m bitfield): in the CONFIG_0 register, the
excitation and burnout currents are off, the reference buffers are
disabled, the external reference is selected, and the PGA gain is
set to 1. In the FILTER_0 register, the sinc3 standalone filter is
selected with FS, Bits[10:0] = 0x30.
► ADC control: in the ADC_CONTROL register (see Table 45),
the AD4130-8 is in continuous conversion mode with continuous
read disabled and the data coding set to offset binary, and the
internal oscillator is enabled and selected as the master clock
source. The internal reference is disabled, the CS pin is disabled
(3-wire mode), and the status register content is not appended to
the data output.
► Diagnostics: the only diagnostic enabled is the SPI_IGNORE_ERR function.
►
Rev. 0 | 45 of 108
Data Sheet
AD4130-8
THEORY OF OPERATION
Note that only a few of the register setting options are shown;
this list is just an example. For full register information, see the
AD4130-8 Registers section.
POWER-DOWN MODES
The AD4130-8 has multiple power-down modes that can be selected using the MODE bits in the ADC_CONTROL register (see
Table 45). The MODE bits also select the different ADC conversion
modes. In Table 40, only the power-down mode options are listed.
Table 40. Power-Down Mode Options
MODE
ADC Conversion Mode
0b0010
0b0011
0b0100
Standby
Power-down
Idle
Power-Down Mode
Power-down mode is the lowest power mode of the AD4130-8. All
blocks are powered down, with no register information retained.
To go to power-down mode, the device must be in standby mode.
Otherwise, the device goes to continuous conversion mode. This
procedure serves as a safety feature to prevent accidental/unwanted transitions to power-down mode.
To exit power-down mode, the user must reset the device. See the
Device Reset section.
Idle Mode
The modulator and digital filter are held in reset in idle mode.
All user registers retain their content as previously configured.
Note that in idle mode, there is no significant change in current
consumption with respect to continuous conversion mode.
Standby Mode
In standby mode and in standby during duty cycling, the register
contents are retained, and the RDYB bit in the status register (see
Table 46) is set to 1. The same standby signal can be driven to
the P4 pin (AIN5) by setting the STBY_OUT_EN bit in the MISC
register to 1.
In the MISC register, the user can select which functionality is kept
enabled in standby mode, as follows:
►
►
►
►
►
►
►
The diagnostic functionality can be kept enabled by setting
the STBY_EN_DIAGNOSTICS bit to 1. Some diagnostics also
require the internal oscillator to be enabled. Therefore, if those
errors are enabled in the ERROR_EN register and STBY_EN_
DIAGNOSTICS = 1, the internal oscillator is kept enabled.
The GPO signals can be kept enabled by setting the
STBY_GPO_EN bit to 1.
The power-down switch can be kept enabled by setting the
STBY_PDSW_EN bit to 1.
The burnout currents can be kept enabled by setting the
STBY_BURNOUT_EN bit to 1.
The VBIAS can be kept enabled by setting the STBY_VBIAS_EN
bit to 1.
The excitation currents can be kept enabled by setting the
STBY_IEXC_EN bit to 1.
The internal reference can be kept enabled by setting the
STBY_REFHOL_EN bit and the STBY_INTREF_EN bit to 1.
To exit standby mode, write to the MODE bits in the ADC_CONTROL register to select a different mode of operation. See the Out
of Standby Mode Timing section for further details.
To exit idle mode, write to the MODE bits in the ADC_CONTROL
register to select a different mode of operation.
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Rev. 0 | 46 of 108
Data Sheet
AD4130-8
DIGITAL INTERFACE
state and aborts any current operation. This operation does not
reset the device registers to their default value (see the Device
Reset section).
The AD4130-8 has a 4-wire (CS, SCLK, DIN, and DOUT) or 3‑wire
(SCLK, DIN, and DOUT) SPI that is compatible with QSPI™ and
MICROWIRE™ interface standards, as well as most digital signal
processors (DSPs). The interface operates in SPI Mode 3 and can
be operated with CS tied low (3‑wire). In SPI Mode 3, SCLK idles
high, the falling edge of SCLK is the drive edge, and the rising edge
of SCLK is the sample edge as described in Figure 72. This means
that data on DIN is clocked in on the rising edge of SCLK, and data
on DOUT is clocked out on the falling edge of SCLK. To readback
DOUT, use the rising edge of SCLK or follow the tDOUT_VALID timing
to sample the DOUT signal. The SCLK pin has a Schmitt-triggered
input, making the interface suitable for opto-isolated applications.
Additional interface pins are INT and SYNC.
When the read or write operation to the selected register is complete, the interface returns to its default state, where it expects a
write operation to the communications register.
Figure 73 and Figure 74 show writing to and reading from a register
by first writing the 8-bit command to the communications register,
followed by the data for the addressed register. The data length on
DOUT varies from 8-bit, 16-bit, 24-bit, and 32‑bit, depending on the
register selected and the SPI CRC being enabled.
Timing specifications can be found in Table 9 and Table 10.
Figure 72. SPI Mode 3, SCLK Edges
Figure 73. Writing to a Register (8-Bit Command with Register Address
Followed by Data)
The logic level of the AD4130-8 digital interface is set by the IOVDD
voltage, and can range from 1.65 V to 3.6 V.
ACCESSING THE REGISTER MAP
The communications register (COMMS) controls access to the
full register map of the ADC. This register is an 8-bit, write only
register (see Table 41). On power-up or after a software reset,
the digital interface defaults to a state where it expects a write
to the communications register. Therefore, all communications to
the device must start with a write operation to the communications
register.
Figure 74. Reading from a Register (8-Bit Command with Register Address
Followed by Data)
The data written to the communications register determines whether the next operation is a read or write operation (R/W bit), and
which register is accessed (RS, Bits[5:0]). The MSB in the 8-bit
COMMS register must be set to 0 to enable a write (WEN bit). If
WEN is set to 1 during the transaction, the device does not clock on
to subsequent bits in the register.
Device Identification
Reading the ID register is the recommended method for verifying
the correct communication with the device. The ID register is
a read-only register. The communication register and ID register
details are described in Table 42 and in the Identification Register
section.
In situations where the interface synchronization is lost, if CS is
used, returning CS high resets the digital interface to its default
Table 41. Communications Register
Reg.
Name
Bits
Bit 7
Bit 6
0x00
COMMS
[7:0]
WEN
R/W
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RS[5:0]
Reset
RW
0x00
W
Reset
RW
0x041
R
Table 42. ID Register
Reg.
0x05
1
Name
ID
[7:0]
Bit 5
RESERVED
Bit 4
Bit 3
Bit 2
SILICON_ID
Bit 1
MODEL_ID
Bit 0
See Identification Register section for details.
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Rev. 0 | 47 of 108
Data Sheet
AD4130-8
DIGITAL INTERFACE
DEVICE RESET
The circuitry and serial interface of the AD4130-8 can be reset
by writing 64 consecutive 1s to the device. This action resets the
logic, the digital filter, and the analog modulator, and all on-chip
registers are reset to their default values. A reset is useful if the
serial interface becomes asynchronous due to noise on the SCLK
line.
Figure 75 shows a software reset timing diagram.
This delay is shown in Figure 75, and represented by tRESET_DELAY
in Table 9. If the digital host attempts to perform an SPI transaction
before the device is ready, the transaction may not succeed and
the SPI_IGNORE_ERR bit in the error register is set. The SPI_IGNORE_ERR is a read and write 1 to clear (R/W1C) type of bit. The
POR_FLAG bit in the status register (see Table 46) is set to 1 when
the reset is initiated, and then is set to 0 when the bit is read.
A reset is automatically performed at power-up as shown in Figure
71.
The AD4130-8 requires a minimum delay between any reset event
and a register read/write transaction.
Figure 75. Software Reset Timing Diagram
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Rev. 0 | 48 of 108
Data Sheet
AD4130-8
ADC CONFIGURATION AND OPERATIONS
The AD4130-8 is flexible in its configurability and modes of operations.
Table 43. ADC Data Output Coding Options
Bipolar Bit
Data Output Coding
Output Code Equation1
BIPOLAR/UNIPOLAR CONFIGURATION
0b0
0b1 (default)
Straight binary
Offset binary
Code = (2N × VIN × Gain)/VREF
Code = 2N − 1 × ((VIN × Gain/VREF) + 1)
The analog inputs to the AD4130-8 can accept either unipolar or
bipolar input voltage ranges. Unipolar and bipolar signals on the
AINP input are referenced to the voltage on the AINM input. The
input voltages on AINP and AINM need to be between AVDD and
AVSS, following the specifications in Table 2.
1
N = 24, VIN is the differential input voltage, and Gain is the gain setting (1 to
128).
Table 44 shows the expected correspondence between input signals and the relative output coding depending on the choice for the
bipolar bit in the ADC_CONTROL register.
Data Output Coding
The bipolar bit in the ADC_CONTROL register (see Table 45) determines the data output coding of the ADC data, and how the device
applies the offset and gain coefficients in the postprocessing. See
the ADC Calibration section.
By default, the bipolar bit is set to 1, which corresponds to offset
binary coding. This configuration is better used to represent bipolar
input voltages from −VREF/gain to VREF/gain. If the bipolar bit is set
to 1 for a unipolar input configuration, the input (AINP − AINM with
AINP ≥ AINM) is represented by an output code between 0x800000
(zero scale) and 0xFFFFFF (full scale).
When the bipolar bit is set to 0, the data output coding changes
to natural (straight) binary. This configuration is better used to
represent unipolar input voltages from 0 V to VREF/gain. If the
bipolar bit is set to 0 for a bipolar input configuration, all cases
where AINP < AINM are clamped at 0x000000 (zero scale).
Note that the value of the bipolar bit also affects the way the device
interprets threshold values in the FIFO settings.
Table 43 shows the data output coding options and respective
output code equations for any analog input voltage.
Table 44. Ideal Output Codes for a Given Input Differential Signal
AINP − AINM
Bipolar Bit = 0b0
Bipolar Bit = 0b1
Negative Full Scale
Zero Scale
Mid Scale
(Positive) Full Scale
0x000000
0x000000
0x800000
0xFFFFFF
0x000000
0x800000
N/A1
0xFFFFFF
1
N/A means not applicable.
STATUS BITS
The contents of the status register (see Table 46) can be appended
to each conversion on the AD4130-8. This function is useful if
several channels are enabled. Each time a conversion is output,
the contents of the status register are appended and the format
for reading the data register becomes: DATA[23:0], STATUS[7:0].
The four LSBs of the status register (CH_ACTIVE bitfield) indicate
to which channel the conversion corresponds. In addition, the user
can check the POR_FLAG bit and determine if any errors are
being flagged via the MASTER_ERR bit. To append the status
register contents to every conversion, the DATA_STATUS bit in the
ADC_CONTROL register is set to 1 (see Table 45).
Table 45. ADC_CONTROL Register
Addr.
Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
0x01
ADC_CON
TROL
[15:8]
RESERVED
BIPOLAR
[7:0]
RESERVED
DUTY_CY
C_RATIO
INT_REF_VA DOUT_DIS_ CONT_REA DATA_STAT
L
DEL
D
US
MODE
CSB_EN
Bit 0
Reset
INT_REF_E 0x4000
N
CLK_SEL
RW
R/W
Table 46. Status Register
Addr. Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
0x00
[7:0]
RDY
MASTER_ERR
RESERVED
POR_FLAG
Bit 5
Bit 4
STATUS
Bit 3
Bit 2
Bit 1
Bit 0
CH_ACTIVE
Reset
RW
0x10
R
Table 47. CHANNEL_m Register (m = 0 to 15)
Addr.
0x09 to
0x18
Name
CHANNEL
_m (m = 0
to 15)
Bits
[23:16] ENABLE_m
[15:8]
[7:0]
1
Bit 7
Bit 6
SETUP_m
Bit 3
Bit 2
PDSW_m THRES_EN_
m
AINP_m[2:0]
I_OUT1_CH_m
Bit 1
Bit 0
AINP_m[4:3]
Reset
RW
0xXXXXXX1
R/W
AINM_m
I_OUT0_CH_m
The CHANNEL_0 default value is 0x800100. The default value of all other channels is 0x000100.
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Rev. 0 | 49 of 108
Data Sheet
AD4130-8
ADC CONFIGURATION AND OPERATIONS
in all conversion modes. Sequencing starts from the lowest enabled
channel in increasing order up to the largest enabled channel.
When each enabled channel is selected, the time required to start
the first conversion is equal to the front-end settling time for the
selected channel (SETTLE_n bits in the FILTER_n register). See
Figure 94 for an example.
SMART CHANNEL SEQUENCER
The AD4130-8 allows up to 16 channels to be configured and enabled in the CHANNEL_m registers. Each enabled channel becomes
part of an automatic sequence that can be left running while the
host processor sleeps.
The CHANNEL_m registers allow the user to do the following:
►
►
►
►
►
ADC Setups
Select the plus and minus inputs (AINP_m and AINM_m bitfields)
Assign the excitation currents to specific pins (I_OUT0_CH_m
and I_OUT1_CH_m bitfields)
Select the ADC setup (SETUP_m bitfield)
Enable the power-down switch and thresholds (PDSW_m and
THRES_EN_m bitfields)
Enable the channel to become part of the sequence (ENABLE_m bitfield).
For each channel, a predefined ADC setup can be selected (SETUP_m bits in the CHANNEL_m registers). The AD4130-8 allows up
to eight different ADC setups, with each ADC setup consisting of
configuration, filter, gain, and offset settings.
For example, SETUP_m = 0 (ADC Setup 0) consists of the
CONFIG_0 register, FILTER_0 register, OFFSET_0 register, and
GAIN_0 register. Figure 76 shows the grouping of these registers.
Table 48 through Table 51 show the four registers that are associated with each ADC setup.
See Table 47 for details.
When multiple channels are enabled with different configurations
selected, the AD4130-8 automatically cycles through the channels
Table 48. CONFIG_n Register (n = 0 to 7)
Addr.
Name
Bits
0x19 to
0x20
CONFIG_ [15:8]
n (n = 0 to
7)
[7:0]
Bit 7
Bit 6
Bit 5
Bit 4
I_OUT1_n
REF_BUFP_
n
Bit 3
Bit 2
Bit 1
I_OUT0_n
REF_BUFM
_n
Bit 0
BURNOUT_n
REF_SEL_n
PGA_n
Reset
RW
0x0000
R/W
PGA_BYP_
n
Table 49. FILTER_n Register (n = 0 to 7)
Addr.
Name
Bits
0x21 to
0x28
FILTER_n [23:16]
(n = 0 to
7)
[15:8]
[7:0]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
SETTLE_n
Bit 2
Bit 1
Bit 0
REPEAT_n
FILTER_MODE_n
RESERVED
FS_n[7:0]
Reset
RW
0x002030 R/W
FS_n[10:8]
Table 50. OFFSET_n Register (n = 0 to 7)
Addr.
Name
Bits
0x29 to
0x30
OFFSET_ [23:16]
n (n = 0 to
7)
[15:8]
[7:0]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OFFSET_n[23:16]
Reset
RW
0x800000 R/W
OFFSET_n[15:8]
OFFSET_n[7:0]
Table 51. GAIN_n Register (n = 0 to 7)
Addr.
Name
Bits
0x31 to
0x38
GAIN_n (n
= 0 to 7)
[23:16]
GAIN_n[23:16]
[15:8]
[7:0]
GAIN_n[15:8]
GAIN_n[7:0]
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Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
RW
0xXXXXXX
R/W
Rev. 0 | 50 of 108
Data Sheet
AD4130-8
ADC CONFIGURATION AND OPERATIONS
Figure 76. ADC Setup Register Grouping
Configuration Registers
ADC CONVERSION MODES
The CONFIG_n registers allow the user to do the following:
There are multiple conversion modes available on the AD4130‑8
that can be selected using the MODE bits in the ADC_CONTROL
register (see Table 45). The MODE bits also select the different
power-down modes. In Table 52, only the ADC conversion mode
options are listed.
►
►
►
►
►
►
Set the PGA gain (PGA_n bitfield)
Set the PGA mode (PGA_BYP_n bitfield)
Select the reference source (REF_SEL_n bitfield)
Enable the reference buffers (REF_BUFP_n and REF_BUFM_n
bitfields)
Enable and select the burnout currents (BURNOUT_n bitfield)
Enable and select the excitation currents (I_OUT1_n and
I_OUT2_n bitfields)
See Table 48 for details.
Filter Registers
Table 52. ADC Conversion Mode Options
MODE
ADC Conversion Mode
0b0000 (Default)
0b0001
0b1001
0b1010
0b1011
Continuous conversion
Single sequence
Duty cycling
Single sequence + idle by SYNC
Single sequence + STBY by SYNC
The FILTER_n registers allow the user to do the following:
Continuous Conversion Mode
Select the digital filter at the output of the ADC modulator
(FILTER_MODE_n bitfield)
► Select the FS value applied to the filter (FS_n, Bits[10:0])
► Select how many times to convert on this ADC setup, from 1 to
32 times (REPEAT_n bitfield)
► Set the front-end settling time (SETTLE_n bitfield), to allow the
sensor output to reach a settled value before conversion starts.
Continuous conversion mode is the default mode. The ADC continuously converts on each enabled channel. When the sequence is
complete, the ADC starts again with the lowest enabled channel.
►
See Table 49 for details.
Offset and Gain Registers
Offset and gain settings are used to make adjustments to the data
output after a calibration on the channel associated to that ADC
setup is performed. Programming the gain and offset registers is
optional for any use case, as indicated by the dashed lines between
the register blocks in Figure 76. If an internal or system offset
or full-scale calibration is performed, the gain and offset registers
for the selected channel are automatically updated. See the ADC
Calibration section for more details. See Table 50 and Table 51.
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Single Sequence Modes
In single sequence mode, the AD4130-8 performs a single sequence of conversions and is placed in standby mode after the
conversions are complete. If more than one channel is enabled, the
ADC automatically sequences through the enabled channels once,
before entering standby mode. Select MODE = 0b0001 to enable
the single sequence mode. When the AD4130-8 is converting in
single sequence mode, SPI writes are ignored.
The single sequence conversion can also be controlled externally
using the SYNC pin. Select MODE = 0b1010 in the ADC_CONTROL register to enable the single sequence + idle by SYNC
mode. In this mode, the SYNC pin can be pulsed low to take
the device out of idle mode and initiate a new single sequence.
In idle mode, the modulator and digital filter are held in reset.
Rev. 0 | 51 of 108
Data Sheet
AD4130-8
ADC CONFIGURATION AND OPERATIONS
Select MODE = 0b1011 in the ADC_CONTROL register to enable
the single sequence + STBY by SYNC mode. In this mode, the
SYNC pin can be pulsed low to take the device out of standby
and initiate a new sequence of conversions. In standby, the register
content is retained. When in single sequence + standby by SYNC
mode, the REPEAT_n bits functionality is available. See the System
Synchronization section.
Note that the time in between SYNC pin pulses must be greater
than the single sequence conversions time to allow the device to go
into idle or standby mode in between SYNC pin pulses and avoid
timing issues, as shown in Figure 77 or Figure 79. The SYNC pin
rate can be used to determine the sample rate per channel in the
sequence. See the System Synchronization section.
Figure 77. Example of Single Sequence + Idle by SYNC Mode Diagram
Figure 78. Duty Cycling Mode Diagram
Figure 79. Example of Single Sequence + STBY by SYNC Mode Diagram
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Data Sheet
AD4130-8
ADC CONFIGURATION AND OPERATIONS
Duty Cycling Mode
In duty cycling mode, the device continuously cycles autonomously
between active and standby modes for added savings in power
consumption. The ADC converts on each enabled channel and then
enters standby mode. When a cycle is complete, the cycle begins
again with an ADC conversion on the lowest enabled channel.
Set the MODE bitfield in the ADC_CONTROL register to 1001
to enable autonomous duty cycling mode. In this mode, the duty
cycling ratio is set to 1/4 by default, which means that the device
is active ~25% of the time and in standby the rest of the time. The
autonomous duty cycle ratio can be changed to 1/16 by setting the
DUTY_CYC_RATIO bitfield value in the ADC_CONTROL register to
1. See Figure 78.
When in duty cycling mode, the REPEAT_n bits functionality is not
available. See the Duty Cycling Mode Timing section.
When using the internal reference for conversions on some or all of
the channels in the duty cycling sequence, it is recommended to set
the STBY_REFHOL_EN bit to 1 in the MISC register, to reduce the
impact of the internal reference continuously turning on and off. See
the Standby Mode section for more details on the blocks that can
be kept active when in standby during duty cycling.
Table 53. Ready Interrupt Pin Options1
INT_PIN_SEL
Pin Options
0b00 (Default)
0b01
0b10
0b11
INT
CLK
P2
DOUT2
1
FIFO disabled. When the FIFO is enabled, the INT_PIN_SEL bitfield is used to
assign the selected FIFO interrupt to a pin as per Table 70.
2
Pin behaves as a shared DOUT and data ready signal functionality.
If the ADC result in the data register is not read, the data ready
signal stays low until the next conversion is about to become
available. The minimum data ready high time if data ready is low
and the next conversion is available is called tRDYH and can be
found in Table 9 and Figure 9.
When the continuous read mode is disabled (see the Continuous
Read Mode section) the same data can be read again, if required,
while the data ready signal is high, although subsequent reads
must not occur close to the next output update. When continuous
read mode is enabled, an ADC result can be read only once.
Configuring a pin as a data ready interrupt takes priority over other
pin control on that pin. For example, enabling the CLK pin as CLK
via the CLK_SEL bit in the ADC_CONTROL register (see Table 45)
is ignored if the CLK pin is enabled as interrupt.
Enabling the P2 pin as a GPO via the GPO_CTRL_P2 bit in the
IO_CONTROL register is ignored if P2 is enabled as an interrupt.
When P2 is enabled as a data ready signal, all GPO pins are
automatically kept enabled in standby mode.
When the FIFO is enabled, the data ready signal becomes a FIFO
ready signal that refers to the FIFO being ready to be read (low)
or busy while being accessed by the device (high). This signal
appears automatically on DOUT when the FIFO is enabled and
cannot be redirected to other pins. See the FIFO Ready Signal
section.
CONTINUOUS READ MODE
Figure 80. Example of Duty Cycling Mode vs. Continuous Conversion Mode
Current Consumption
DATA READY SIGNAL
When an ADC conversion completes, the RDYB bit in the status
register (see Table 46) changes from 1 to 0. A data ready signal
indicating that the ADC result is in the data register and ready to be
readback can also be generated internally and directed to a pin of
choice by configuring the INT_PIN_SEL bits in the IO_CONTROL
register (see Table 39), as per Table 53. By default, the AD4130-8
has a dedicated INT pin for the data ready signal. The data ready
signal returns high after a read of the ADC.
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Continuous read mode is a different interface mode to access ADC
data. In continuous read mode, it is not required to write to the
COMMS register to read the data register. In this mode, the data
ready signal acts as a framing signal for the output data. SCLKs are
ignored until the data ready signal goes low to indicate the end of
a conversion. Apply the required number of SCLKs after the data
ready signal goes low to read the conversion result in the data
register. When the conversion result is read, the data ready signal
returns high until the next conversion result is available. In this
mode, the data can be read only once. Ensure that each sample
data is read before the next conversion is complete. If the user
has not read the previous conversion result before the completion
of the next conversion, or if insufficient serial clocks are applied
to read the result, the serial output register is reset when the next
Rev. 0 | 53 of 108
Data Sheet
AD4130-8
ADC CONFIGURATION AND OPERATIONS
conversion is complete, and the new conversion result is placed in
the output serial register.
To enable continuous read mode, set the CONT_READ bit in the
ADC_CONTROL register (see Table 45). When this bit is set, the
only serial interface operations possible are reads from the data
register. Therefore, the write to this register is the last in the
sequence of configuration writes to the device.
To exit continuous read mode, write a read data command (0x42)
while the data ready signal is low. If CRC is enabled, a presumed
CRC command byte of 0x42 precedes the data and must be considered when validating CRC, but no CRC is needed when sending
the 0x42 command. Alternatively, to exit continuous read mode,
apply a software reset, that is, 64 SCLKs with CS = 0 and DIN = 1
(see Figure 75). This resets the ADC and all register contents.
These are the only commands that the interface recognizes after
it is placed in continuous read mode. DIN must be held low in
continuous read mode until an instruction is to be written to the
device.
If multiple ADC channels are enabled, each channel is output
in turn, with the status register content being appended to the
data if DATA_STATUS bit is set in the ADC_CONTROL register.
The status register includes the channel to which the conversion
corresponds.
The continuous read mode is disabled when the FIFO is enabled.
Figure 81. Enter Continuous Read Mode Diagram (DATA_STATUS = 0)
Figure 82. Exit Continuous Read Mode Diagram (CRC Disabled)
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Rev. 0 | 54 of 108
Data Sheet
AD4130-8
ADC CONFIGURATION AND OPERATIONS
SYSTEM SYNCHRONIZATION
The SYNC pin input can facilitate several operations. By default,
if held low, this pin can keep the modulator, the digital filter, and
the calibration control logic in a reset state, without affecting any of
the configuration conditions on the device. This allows the user to
start gathering samples of the analog input from a known point in
time, that is, the rising edge of SYNC. Take SYNC low for at least
tSYNC_PW to implement the synchronization function (see the Timing
Specifications section). SYNC does not affect the digital interface
but does reset the data ready signal to a high state if it is low. A
falling edge on the SYNC pin resets the digital filter and the analog
modulator and places the AD4130-8 into a consistent, known state.
While the SYNC pin is low, the AD4130-8 is maintained in this
state. On the SYNC rising edge, the modulator and filter exit this
reset state, and the device starts to gather input samples again.
The SYNC pin is sampled on the falling edge of MCLK. Therefore,
for applications where deterministic timing is required, it is recommended that the SYNC pin changes value on the external MCLK
(CLK) rising edge.
Initiate Conversions
The SYNC pin can be used as a start conversion command. Hold
SYNC pin low at power-up and while configuring the AD4130-8.
Then, when ready, use the rising edge of SYNC to start the
conversion or series of conversions depending on the ADC mode
selected. The falling edges of the data ready signal indicate when
each conversion is complete, and the ADC result can be read from
the data register.
Synchronize Multiple AD4130-8 Devices
The SYNC pin can be used to synchronize multiple AD4130-8
devices operated from a common external MCLK, so that their data
registers are updated simultaneously. This functionality is available
at power-up by default. A low pulse on the SYNC pin connected to
multiple devices is normally issued after each AD4130-8 performs
its own calibration or has calibration coefficients loaded into its
calibration registers. The conversions from the AD4130-8 devices
are then synchronized.
The device exits reset on the MCLK falling edge following the
SYNC low to high transition. Therefore, when multiple devices are
being synchronized, pull the SYNC pin high on the MCLK rising
edge to ensure that all devices begin sampling on the MCLK falling
edge. If the SYNC pin is not taken high in sufficient time, it is
possible to have a difference of one master clock cycle between
the devices; that is, the instant at which conversions are available
differs from device to device by a maximum of one master clock
cycle.
Other Synchronization Modes
The SYNC pin functionality can be changed to take the device out
of idle when in single sequence + idle by SYNC mode, or take the
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device out of standby when in single sequence + STBY by SYNC
mode. See the ADC Conversion Modes section for more details.
The SYNC pin can also be used to clear the FIFO instead by
setting the SYNCB_CLEAR bit in the IO_CONTROL register to 1
(see Table 39). See the Clearing the FIFO section for more details.
ADC CALIBRATION
After each conversion, the ADC conversion result is scaled using
the ADC calibration coefficients stored in the OFFSET_n and
GAIN_n registers before being written to the data register. The
postprocessing time needed for this activity is called digital postprocessing (DPP) time. The default value of the OFFSET_n registers
is 0x800000 and the nominal value of the GAIN_n registers is
0x555555.
Both internal calibration and system calibration are available in
the AD4130-8 to update the OFFSET_n and GAIN_n registers;
therefore, the user has the option of removing offset or gain errors
internal to the device only and removing the offset or gain errors of
the complete end system.
The AD4130-8 provides four calibration modes as shown in Table
54 that can be used to eliminate the offset and gain errors on a per
ADC setup basis.
Table 54. ADC Calibration Mode Options
MODE
ADC Calibration Mode
0b0101
0b0110
0b0111
0b1000
Internal offset calibration (zero scale)
Internal gain calibration (full scale)
System offset calibration (zero scale)
System gain calibration (full scale)
An internal or system offset calibration reduces the offset error to
the order of the noise. The gain error is factory calibrated at ambient temperature and at a gain of 1 with PGA_BYP_n = 0. Therefore,
internal gain calibrations at a gain of 1 with PGA_BYP_n = 0 are not
supported on the AD4130-8. For other gain values, a system gain
calibration reduces the gain error to the order of the noise.
Only one channel can be active during calibration. From an operational point of view, treat a calibration like another ADC conversion.
Set the system software to monitor the RDYB bit in the status
register (see Table 46) or the data ready signal to determine the
end of a calibration via a polling sequence or an interrupt driven
routine. To start a calibration, write the relevant value to the MODE
bits in the ADC_CONTROL register (see Table 45). The data ready
signal goes high and the RDYB bit in the status register is set to
1 when the calibration initiates. When the calibration is complete,
the content of the corresponding OFFSET_n or GAIN_n registers
is updated, the RDYB bit in the status register is set to 0, the data
ready signal returns low (if CS is low), and the AD4130-8 reverts to
idle mode.
A calibration can be performed at any output data rate. Using
lower output data rates results in better calibration accuracy also
for higher output data rates. A new calibration is required for a
Rev. 0 | 55 of 108
Data Sheet
AD4130-8
ADC CONFIGURATION AND OPERATIONS
given channel if the reference source or the gain for that channel is
changed (using the PGA_n bitfields of the CONFIG_n registers).
The following equations show the calculations that are used to
scale data based on offset and gain calibration coefficients.
In unipolar mode (bipolar bit = 0b0 in the ADC_CONTROL register):
DATA =
0.75 × VIN
VREF
× 2N‐1 −
OFFSET_n − 0x800000
×
GAIN_n
0x400000
×2
In bipolar mode (bipolar bit = 0b1 in the ADC_CONTROL register):
DATA =
0.75 × VIN
VREF
× 2N‐1 −
OFFSET_n − 0x800000
×
GAIN_n
0x400000
+ 0x800000
where:
DATA is the code written in the data register after postprocessing.
VIN is the differential voltage at the input of the converted channel
(AINP − AINM).
N is the number of bits of the ADC (24).
OFFSET_n is the hexadecimal code written in the relative OFFSET_n register of the converted channel.
GAIN_n is the hexadecimal code written in the relative GAIN_n
register of the converted channel.
The AD4130-8 provides the user with access to the on-chip calibration registers, allowing the microprocessor to read the calibration
coefficients of the device or to write its own calibration coefficients.
A read or write of the OFFSET_n and GAIN_n registers can be
performed at any time except during an internal or system calibration. The values in the calibration registers are 24 bits wide. The
input span and offset of the device can also be manipulated using
these registers. See the System Calibration Span and Offset Limits
section for more details.
The AD4130-8 can run background checks during calibration.
To enable this functionality, set the ADC_ERR_EN bit in the ERROR_EN register to 1. If an error occurs, the ADC_ERR bit in the
error register is set. See the ADC Errors section for more details.
If the user is concerned about verifying that a valid reference is in
place every time a calibration is performed, check the status of the
REF_DETECT_ERR bit at the end of the calibration cycle.
Internal Gain Calibration
To perform an internal gain calibration, a full-scale input voltage
generated internally, is automatically connected to the PGA inputs.
A gain calibration is recommended each time the gain of a channel
is changed to minimize the full-scale error caused by the new
gain setting. When performing internal calibrations, the internal gain
calibration must be performed before the internal offset calibration.
Therefore, write the value 0x800000 to the OFFSET_n register of
the selected channel before performing the internal gain calibration,
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which ensures that the OFFSET_n register is at its default value. If
the reference voltage is higher than 2 V, set the CAL_RANGE_X2
bit in the MISC register to 1 to improve the outcome of the internal
gain calibration. The AD4130-8 is factory calibrated at ambient
temperature and with a gain of 1 with PGA_BYP_n = 0, and the
resulting gain coefficients are loaded to the GAIN_n registers of the
device as default value. The device does not support further internal gain calibrations at a gain of 1 (PGA_BYP_n = 0). An internal
gain calibration requires a time equal to four first conversions of the
selected configuration on that channel to be completed.
Internal Offset Calibration
During an internal offset calibration, the selected positive analog
input pin is disconnected, and it is connected internally to the
selected negative analog input pin. For this reason, it is necessary
to ensure that the voltage on the selected negative analog input
pin does not exceed the allowed limits and is free from excessive
noise and interference. When performing internal calibrations, the
internal gain calibration must be performed before the internal offset
calibration. An internal offset calibration requires a time equal to the
first conversion of the selected configuration on that channel to be
completed.
System Offset Calibration
A system offset calibration expects the system zero-scale voltages
to be applied to the ADC pins before enabling the calibration mode.
As a result, offset errors external to the ADC are removed. When
performing system calibrations, system offset calibration must be
performed before the system gain calibration. Internal calibrations
must be performed before completing system calibrations. A system offset calibration requires a time equal to the first conversion of
the selected configuration on that channel to be completed.
System Gain Calibration
A system gain calibration expects the system full-scale voltages to
be applied to the ADC pins before enabling the calibration mode.
As a result, gain errors external to the ADC are removed. When
performing system calibrations, system offset calibration must be
performed before the system gain calibration. Internal calibrations
must be performed before completing system calibrations. A system gain calibration requires a time equal to the first conversion of
the selected configuration on that channel to be completed.
System Calibration Span and Offset Limits
System calibration can be used to compensate for offset or gain
errors in the external circuit and to manipulate the input span and
offset of the device. Whenever system calibration is performed,
the amount of input offset and span adjustments that can be
accommodated is limited.
The input span is the difference between the input voltage that
corresponds to full code and the input voltage that corresponds
Rev. 0 | 56 of 108
Data Sheet
AD4130-8
ADC CONFIGURATION AND OPERATIONS
to zero code. The range of input span achievable with system
calibration has a minimum value of 0.8 × VREF/gain and a maximum
value of 2.1 × VREF/gain.
The input span and offset adjustment must also account for the
limitation on the positive full code voltage (1.05 × VREF/gain) and
negative zero code voltage (−1.05 × VREF/gain). See Table 2.
Therefore, in determining the limits for system offset (zero scale)
and gain (full scale) calibrations, the user must ensure that the
offset after adjustment plus the maximum positive span range after
adjustment does not exceed 1.05 × VREF/gain.
The amount of offset and span adjustment that can be accommodated depends also on whether the configuration is unipolar or
bipolar. This is best illustrated by looking at a few examples.
If the device is used in unipolar configuration (AINP ≥ AINM), with
a required span of 0.8 × VREF/gain, the offset range that the system
calibration can handle is from −1.05 × VREF/gain to +0.25 × VREF/
gain, as shown in Figure 83.
Figure 84. Example of Bipolar Span and Offset Calibration Limits
If the device is used in bipolar configuration with a required span
of ±VREF/gain, the offset range the system calibration can handle is
from −0.05 × VREF/gain to +0.05 × VREF/gain. Similarly, if the device
is used in bipolar configuration and required to remove an offset of
±0.2 × VREF/gain, the span range that the system calibration can
handle is ±0.85 × VREF/gain.
Figure 83. Example of Unipolar Span and Offset Calibration Limits
If the device is used in unipolar configuration with a required span
of VREF/gain, the offset range that the system calibration can handle
is from −1.05 × VREF/gain to +0.05 × VREF/gain. Similarly, if the
device is used in unipolar configuration and required to remove an
offset of 0.2 × VREF/gain, the span range that the system calibration
can handle is 0.85 × VREF/gain.
If the device is used in bipolar configuration, with a required span
of ±0.4 × VREF/gain, the offset range that the system calibration can
handle is from −0.65 × VREF/gain to +0.65 × VREF/gain, as shown in
Figure 84.
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Rev. 0 | 57 of 108
Data Sheet
AD4130-8
DIGITAL FILTERS
The AD4130-8 offers great flexibility in the digital filter scheme. The
device has several filter options. The option selected affects the
output data rate, first conversion time, input bandwidth, and 50 Hz
and 60 Hz rejection. The FILTER_MODE_n bits in each FILTER_n
register select between the filter types as shown in Table 56.
filters can be used in averaging mode selecting sinc3 + sinc1 or
sinc4 + sinc1 in the FILTER_MODE_n bitfield of the FILTER_n
register. The sinc1 filter places additional notches starting at
Depending on the filter selected, only certain FS values are allowed. The FS value determines the output data rate for all filters
except the post filters. See Table 56 for a list of allowed FS values
for the correspondent selected filter. See the Output Data Rate
section for more details.
where:
fNOTCH_STD is the first notch from sinc3 or sinc4 standalone filters.
Avg = 8.
SINC3 AND SINC4 FILTERS
When the AD4130-8 is powered up, the sinc3 filter is selected by
default. This filter allows the full range of ODR values, gives good
noise performance, short first conversion time, and can offer 50 Hz
and 60 Hz (±1 Hz) rejection.
A sinc4 filter can be used instead of the sinc3 filter. This filter is only
available for ODR from 240 SPS to 2.4 kSPS, so it cannot achieve
natural 50 Hz and/or 60 Hz rejection, but the filter has excellent
noise performance with a slightly longer conversion time.
By programming the correct FS, the sinc standalone filters can achieve good rejection at the respective notch frequency (fNOTCH_STD).
The sinc3 and sinc4 filters place the first notch at
fNOTCH_STD = fMCLK/(32 × FS[10:0])
where:
fMCLK is the master clock frequency (76.8 kHz).
FS[10:0] is the decimal equivalent of the FS_n bits in the FILTER_n
register.
AVERAGING FILTERS
fNOTCH_AVG = fNOTCH_STD/Avg
In averaging mode, there is almost no difference in the first conversion time on a new channel and subsequent conversions time on
the same channel. The conversion time is near constant when
converting on a single channel or when converting on several
channels using the same filter.
POST FILTERS
The post filters can be applied after the sinc3 filter to provide
rejection of 50 Hz and 60 Hz simultaneously and allow the user
to trade off first conversion time and rejection. Each post filter
operates at a specific ODR and can achieve simultaneous 50 Hz
and 60 Hz rejection, as shown in Table 55. These filters can be
selected in each FILTER_MODE_n bitfield. The FS, Bits[10:0] do
not influence the ODR when the post filters are selected.
Table 55. Post Filters: Output Data Rate and Rejection
Post Filter
ODR (SPS)
Rejection1
1
2
3
4
26.087
24
19.355
16.21
53 dB at 50 Hz, 58 dB at 60 Hz
70 dB at 50 Hz, 70 dB at 60 Hz
99 dB at 50 Hz, 103 dB at 60 Hz
103 dB at 50 Hz, 109 dB at 60 Hz
1
The 50 Hz/60 Hz rejection is measured with a stable fMCLK = 76.8 kHz, in a
band of ±0.5 Hz around 50 Hz and 60 Hz.
In averaging mode, a sinc1 filter is included after the sinc3 or sinc4
filter. The sinc1 filter averages by 8 (average). Both standalone
Table 56. FILTER_MODE_n Bits and Filter Types
FILTER_
MODE_n
Filter Type
FS Range (Hex)
ODR Range (SPS)
Comments
0000
Sinc4
2400 to 240
0001
Sinc4 + sinc1
0010 (Default)
Sinc3
0011
Sinc3 + REJ60
0100
Sinc3 + sinc1
Excellent noise performance, long first conversion time, no natural 50/60 Hz
rejection. FS > 0d10 is forced to FS = 0d10.
Sinc4 plus averaging by 8 filter. No first conversion delay. FS > 0d10 is forced
to FS = 0d10.
Good noise performance, moderate 50 Hz/ 60 Hz rejection, moderate first
conversion time.
With FS = 0d48, achieves simultaneous 50 Hz and 60 Hz rejection at 50 SPS
ODR.
Sinc3 plus averaging by 8 filter. No first conversion delay. Recommended for
FS from 0x01 to 0xCC only (minimum ODR = 1.17).
0101
0110
0111
1000
Sinc3 + Post Filter 1
Sinc3 + Post Filter 2
Sinc3 + Post Filter 3
Sinc3 + Post Filter 4
0x01 to 0xA
(Dec.: 1 to 10)
0x01 to 0xA
(Dec.: 1 to 10)
0x01 to 0x7FF
(Dec.: 1 to 2047)
0x01 to 0x7FF
(Dec.: 1 to 2047)
0x01 to 0x7FF
(Dec.: 1 to 2047)
Not applicable
Not applicable
Not applicable
Not applicable
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218.18 to 21.8
2400 to 1.17
2400 to 1.17
240 to 0.117
26.087
24
19.355
16.21
No first conversion delay, good 50 Hz and 60 Hz rejection. FS value does not
apply.
Rev. 0 | 58 of 108
Data Sheet
AD4130-8
DIGITAL FILTERS
REPEAT_n function (CONFIG_n register) is used, or when in continuous conversion mode with only one channel enabled. When expressed in Hz, the ODR is called fADC (fADC = 1 Hz, ODR = 1 SPS),
where:
fADC = 1/tCNV
where:
tCNV is the conversion time on a settled channel (after the first
conversion on a new channel for subsequent conversions on the
same channel, that channel is considered settled).
tCNV is also the time between subsequent data ready signal high to
low transitions on a settled channel.
Figure 85. Sinc3 and Sinc4 Filter Response (FS = 0d10)
The DPP time needed for each conversion is already accounted for
in the tCNV for a settled channel.
Table 57. Conversion Time and ODR on Settled Channels
Filter Type
tCNV (MCLK Cycles) 1
ODR (SPS)1
Sinc4
32 × FS
352 × FS
32 × FS
32 × FS
320 × FS
2944
3200
3968
4736
2400/FS
218.18/FS
2400/FS
2400/FS
240/FS
26.087
24
19.355
16.21
Sinc4 + sinc1
Sinc3
Sinc3 + REJ60
Sinc3 + sinc1
Sinc3 + Post Filter 1
Sinc3 + Post Filter 2
Sinc3 + Post Filter 3
Sinc3 + Post Filter 4
1
Figure 86. Post Filter 1 and Post Filter 2 Response
FS is the decimal equivalent of the FS, Bits[10:0] binary value.
Filters Bandwidth
The 3 dB bandwidth (f3dB) depends on the type of filter selected and
its settings. See the Noise and Resolution section for a list of f3dB
values for different FS values. Table 56 lists the allowed FS values
for each filter type.
Step Change on a Single Channel
When conversions are performed on a single channel and a step
change occurs, the ADC does not detect the change in the analog
input straight away, but it continues to output conversions at the
programmed output data rate as shown in Figure 88. The filter type
determines how many conversions are needed before the output
data accurately reflects the analog input.
Figure 87. Post Filter 3 and Post Filter 4 Response
OUTPUT DATA RATE
The ODR is the rate at which ADC conversions are available
on a single settled channel when the ADC is continuously converting. The ODR corresponds, for example, to the case where the
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Table 58 shows the minimum number of conversions needed to settle a step change when converting the same channel. This number
applies if the step change is synchronized with the conversion. If
the step change occurs while the ADC is processing a conversion,
the ADC takes an additional conversion after the step change to
generate a fully settled result.
Rev. 0 | 59 of 108
Data Sheet
AD4130-8
DIGITAL FILTERS
Figure 88. Effect of an Asynchronous Step Change in the Analog Input on the ADC Output
Table 58. Number of Intermediate Conversions Needed to Settle a Step
Change when Converting the Same Channel
Filter Type
Minimum
Maximum
Sinc4
Sinc3 and sinc3 + REJ60
Sinc4 + sinc1 and sinc3 + sinc1
Sinc3 + post filters
3
2
1
0
4
3
2
1
50 HZ AND 60 HZ REJECTION
By programming the correct FS, the standalone sinc filters can achieve good rejection at the respective notch frequency (fNOTCH_STD).
The sinc4 filter has limited FS options and cannot achieve natural
50 Hz and/or 60 Hz rejection.
See the Rejection Specifications section.
Sinc3 and Sinc3 + REJ60 Rejection
By programming the FS to 0d48 for a sinc3 filter, it is possible to
achieve a notch at 50 Hz. ODR in this case is 50 SPS.
Sinc3 simultaneous 50 Hz/60 Hz rejection is also achieved when
FS, Bits[10:0] is set to 0d240. Notches are placed at 10 Hz and
multiples of 10 Hz, thereby giving simultaneous 50 Hz and 60 Hz
rejection. ODR in this case is 10 SPS. See Table 59 and Figure 89.
Figure 89. Simultaneous 50 Hz and 60 Hz Rejection for Sinc3 with
ODR = 10 SPS
If the FS value for sinc3 + REJ60 filter is selected to be 0d48 for
an ODR = 50 SPS, the first main notch is a 50 Hz and the first
additional notch is at 60 Hz. This configuration allows to achieve
simultaneous 50 Hz and 60 Hz rejection. Figure 90 shows the
frequency response of the sinc3 filter with this configuration.
Table 59. Sinc3 Filter Rejection Performance
Filter Type
FS (Dec.)
ODR (SPS)
Rejection (dB)1
Sinc3
240
48
40
48
10
50
60
50
100 (50 Hz and 60 Hz)
95 (50 Hz only)
98 (60 Hz only)
80 (50 Hz)
65 (60 Hz)
Sinc3 + REJ60
1
The 50 Hz/60 Hz rejection is measured with a stable fMCLK = 76.8 kHz, in a
band of ±1 Hz around 50 Hz and/or 60 Hz.
For the sinc3 filter, there is the option to select additional rejection by setting FILTER_TYPE to sinc3 + REJ60 (0b0011). When
sinc3 + REJ60 filter is selected, an additional notch is added at 6/5
of the main notch:
fNOTCH_REJ60 = 6/5 × fNOTCH_STD
where fNOTCH_STD
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Figure 90. Sinc3 and Sinc3 + REJ60 Filter Response (50 SPS ODR)
is the first notch from sinc3 filter.
Rev. 0 | 60 of 108
Data Sheet
AD4130-8
DIGITAL FILTERS
Post Filters Rejection
First Conversion on a New Channel
Post filters offer good simultaneous rejection at 50 Hz and 60 Hz.
See Table 55 and the Rejection Specifications section.
When a channel change occurs, the modulator and filter reset, the
X-MUX needs to switch to the new channel, and the new filter
needs to settle before being able to generate the first conversion
result.
Averaging Filters Rejection
The sinc1 filter places additional notches at multiples of:
fNOTCH_AVG = fNOTCH_STD/Avg
where:
fNOTCH_STD is the first notch from the sinc3 or sinc4 filter.
Avg is the averaging factor (average = 8).
So, programming the FS to 0d6 for the sinc4 + sinc1 or sinc3 + sinc1
averaging filter, to achieve a fNOTCH_STD at 400 Hz, the sinc1 filter
places an fNOTCH_AVG at 50 Hz. This can be achieved with both the
sinc4 + sinc1 and sinc3 + sinc1 filters. See Figure 91 and Table 60.
In each specific application, a user might want to allow an adjustable front-end settling time (SETTLE_n bits in the FILTER_n
registers) to allow for the excitation current to settle or a sensor to
power up. This time cannot be less than 32 MCLK cycles to allow
for the X-MUX to settle. In addition,
Sinc4 filter requires 4 times tCNV and a certain processing time
due to FS value to output the first result.
► Sinc3 and sinc3 + REJ60 filters require 3 times tCNV and a certain
processing time due to FS value to output the first result.
► Averaging and post filters require the same tCNV and a certain
processing time due to FS value to output the first result. These
filters operate with a minimum first conversion delay with respect
to subsequent conversions, compared to standalone filters.
►
The subsequent conversions on the same channel occur in
tCNV = 1/fADC, and the processing time is already accounted for.
There is always a delay in the first data ready event on a new
channel with respect to the subsequent data ready events on the
same channel.
The predefined front-end settling time (tSETTLE), the ideal first conversion time, and the processing time add up to determine the
conversion time of the first conversion:
t1st_CNV = tSETTLE +t1st_CNV_IDEAL + DPP Time
Figure 91. Sinc3 + Sinc1 and Sinc4 + Sinc1 Filter Response (FS = 6)
Table 60. Averaging Filters Rejection Performance
Filter Type
FS (Dec.)
ODR (SPS)
Rejection (dB)1
Sinc3 + sinc1
6
5
6
5
40
48
36.36
43.64
40 (50 Hz only)
42 (60 Hz only)
40 (50 Hz only)
42 (60 Hz only)
Sinc4 + sinc1
1
The 50 Hz/60 Hz rejection is measured with a stable fMCLK = 76.8 kHz, in a
band of ±0.5 Hz around 50 Hz and/or 60 Hz.
SEQUENCER
When multiple channels are enabled, the on-chip sequencer is
automatically used. The device automatically sequences between
all enabled channels. There can be cases where the conversions
on a channel are repeated using the repeat function, and channels
that are converted only once.
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where:
t1st_CNV is the first conversion time on a new channel.
tSETTLE is the front-end settling time before the first conversion on a
new channel due to the SETTLE_n bits selection, as per Table 61.
t1st_CNV_IDEAL is the ideal conversion time on a new channel. For the
standalone filters, the first conversion time differs from the settled
conversion time as shown in Table 62.
DPP Time is the digital postprocessing time expressed in MCLK
cycles and it depends on the filter type and FS value, except for the
post filters where it is a constant, as per Table 63.
Table 61. Programmable tSETTLE Values
SETTLE_n
MCLK Cycles Before First
Conversion Starts
tSETTLE
0b000 (Default)
0b001
0b010
0b011
0b100
0b101
0b110
0b111
32
64
128
256
512
1024
2048
4096
416.6 μs
833.3 μs
1.66 ms
3.33 ms
6.66 ms
13.33 ms
26.66 ms
53.33 ms
Rev. 0 | 61 of 108
Data Sheet
AD4130-8
DIGITAL FILTERS
Table 62. Conversion and First Conversion Time (MCLK Cycles)
Filter Type1
tCNV (MCLK Cycles)
t1st_CNV_IDEAL (MCLK
Cycles)
Sinc4
32 × FS
352 × FS
32 × FS
32 × FS
320 × FS
2944
3200
3968
4736
4 × tCNV
tCNV
3 × tCNV
3 × tCNV
tCNV
tCNV
tCNV
tCNV
tCNV
Sinc4 + sinc1
Sinc3
Sinc3 + REJ60
Sinc3 + sinc1
Sinc3 + Post Filter 1
Sinc3 + Post Filter 2
Sinc3 + Post Filter 3
Sinc3 + Post Filter 4
1
FS is the decimal equivalent of the FS, Bits[10:0] binary value.
Table 63. DPP Time (MCLK Cycles)
Filter Type
FS1 = 1 (or FS = 0)
FS > 1
Sinc4
28 (364.6 μs)
62 (807.3 μs)
28
28
62
69 (898.4 μs)
62
62
62
62
62
69
Sinc4 + sinc1
Sinc3
Sinc3 + REJ60
Sinc3 + sinc1
Sinc3 + Post Filters
1
FS is the decimal equivalent of the FS, Bits[10:0] binary value.
completed (Figure 94), whereas the data ready signal high to
low transitions always follow the additional DPP time needed to
postprocess the converted data. In practice, there is an overlap
of the new channel tSETTLE and the previous channel DPP time.
Therefore, the conversion time of the current channel (intended as
the time between two data ready signal high to low transitions) can
be calculated as per t1st_CNV on that channel minus the DPP time of
the previous channel, as shown in Figure 94.
A special case (shown in Figure 93) occurs if all channels in the
sequence share the same ADC Setup n (in particular SETTLE_n,
FILTER_MODE_n, and FS_n bitfields in the FILTER_n register),
and only one sample per channel is collected before switching to
the next channel (REPEAT_n set to 0 in the FILTER_n register).
In this case, after the first conversion, the same conversion output
data rate (1CNV_ODR) settles to a fixed value determined by 1/
t1CNV, where:
t1CNV = tSETTLE +t1st_CNV_IDEAL
In this configuration, when continuous conversion mode is enabled,
it is possible to calculate the sample rate per channel by dividing
the 1CNV_ODR by the number of enabled channels sharing the
same configuration in the sequence.
Note that the filter behavior is still dictated by the FILTER_MODE_n
and FS_n bitfields. Therefore, the filter profile and rejection does
not change with the 1CNV_ODR or sample rate per channel values.
Sequencer Timing
When in a sequence, different channels can have different configurations. A channel switch occurs after the actual conversion is
Table 64. First Conversion Time and Conversion Time on a Settled Channel, by Filter Types1
Filter type
t1st_CNV
tCNV
Sinc4
tSETTLE + (4 × 32 × FS + DPP Time)/fMCLK
tSETTLE + ((4 + Avg – 1) × 32 × FS + DPP Time)/fMCLK
tSETTLE + (3 × 32 × FS + DPP Time)/fMCLK
tSETTLE + ((3 + Avg – 1) × 32 × FS + DPP Time)/fMCLK
tSETTLE + 38.33 ms + DPP Time/fMCLK
tSETTLE + 41.67 ms + DPP Time/fMCLK
tSETTLE + 51.67 ms + DPP Time/fMCLK
tSETTLE + 61.67 ms + DPP Time/fMCLK
(32 × FS)/fMCLK
((4 + Avg – 1) × 32 × FS)/fMCLK
(32 × FS)/fMCLK
((3 + Avg – 1) × 32 × FS)/fMCLK
38.33 ms
41.67 ms
51.67 ms
61.67 ms
Sinc4 + sinc1
Sinc3 and sinc3 + REJ60
Sinc3 + sinc1
Sinc3 + Post Filter 1
Sinc3 + Post Filter 2
Sinc3 + Post Filter 3
Sinc3 + Post Filter 4
1
tSETTLE is the front-end settling time of a new channel due to the SETTLE_n bits selection. fMCLK is the master clock frequency (76.8 kHz). Avg is 8. FS is the decimal
equivalent of the FS, Bits[10:0] in the filter register. DPP Time is the digital postprocessing time expressed in MCLK cycles.
analog.com
Rev. 0 | 62 of 108
Data Sheet
AD4130-8
DIGITAL FILTERS
Figure 92. Example of Repeat Conversion on the Same Channel
Figure 93. Example of Standard Sequencing Through Multiple Channels with Same Configuration and No Repeat Conversion
Figure 94. Example of Smart Sequencing
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Rev. 0 | 63 of 108
Data Sheet
AD4130-8
DIGITAL FILTERS
Figure 95. Example of Autonomous Duty Cycling Mode
Duty Cycling Mode Timing
The autonomous duty cycling mode on the AD4130-8 uses the conversion time of the sequence and the DUTY_CYC_RATIO bitfield
settings to calculate the standby time.
The effective active time depends on the enabled channels in the
sequence and their chosen configuration as follows:
n
tACTIVE − Σ tSETTLEn + t1st_CNV_IDEAL
0
where:
tACTIVE is the effective active time during duty cycling.
n is the number of channels enabled.
tSETTLE is the front-end settling time before the first conversion on a
new channel due to the SETTLE_n bits selection, as per Table 61.
t1st_CNV_IDEAL is the ideal conversion time on a new channel. For the
standalone filters, the first conversion time differs from the settled
conversion time as shown in Table 62. See Figure 95.
DPP time does not contribute to the effective active time in duty
cycling mode. This applies also to the DPP time associated with
the last enabled channel. The duty cycling wake-up time (tWU_DUTY)
does not affect the active time and can be visualized as overlapping
with the first tSETTLE of the active sequence, as shown in Figure 95.
The standby time during autonomous duty cycling mode corresponds to the P4 pin low in Figure 95 and is calculated by the
device as follows:
where:
tSTBY_DUTY is the time that the device spends in standby when
autonomous duty cycling mode is enabled.
Standby Ratio is 3 for 1/4 duty cycle and 15 for 1/16 duty cycle,
depending on the DUTY_CYC_RATIO bit in the ADC_CONTROL
register.
n is the number of channels enabled.
t1st_CNV_IDEAL is the ideal conversion time on a new channel. For the
standalone filters, the first conversion time differs from the settled
conversion time as shown in Table 62.
tWU_DUTY is the duty cycling wake-up time (see Table 9).
Out of Standby Mode Timing
By default, the internal oscillator is powered down in standby mode,
and reenabled when exiting standby mode. The internal oscillator
takes some time to wake up and settle to the correct frequency,
as shown in Figure 96 (see also Table 7). tSETTLE can be used
to adjust the time allowed for the input signal to settle before the
signal acquisition starts.
When the internal oscillator is kept alive in standby mode, the
standby mode wake-up time corresponds to tWU_STBY in Table 9.
The internal oscillator is kept alive by default when selecting the
duty cycling mode.
n
tSTBY_DUTY = Standby Ratio × Σ t1st_CNV_IDEALn .
− tWU_DUTY
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Rev. 0 | 64 of 108
Data Sheet
AD4130-8
DIGITAL FILTERS
Figure 96. Out of Standby Mode Diagram
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Rev. 0 | 65 of 108
Data Sheet
AD4130-8
DIAGNOSTICS
The AD4130-8 has numerous diagnostic functions on chip. Use
these features to ensure among others:
Read/write operations are to valid registers only
► Only valid data is written to the on-chip registers
► The external reference, if used, is present
► The ADC modulator and filter are working within specification
►
SIGNAL CHAIN CHECK
Functions such as the reference and power supply voltages can
be selected as inputs to the ADC. The AD4130-8 can therefore
check the voltages connected to the device. The AD4130-8 also
generates an internal signal of around 10 mV that can be applied
internally to a channel by selecting the V_MV_P to V_MV_M option
in the CHANNEL_m register. The PGA can be checked using this
function. As the PGA setting is increased, for example, the signal
as a percent of the analog input range is reduced by a factor of two.
This allows the user to check that the PGA is functioning correctly.
REFERENCE DETECTION
The AD4130-8 includes on-chip circuitry (simplified in Figure 97) to
detect if there is a valid reference for conversions or calibrations
when the user selects an external reference as the reference
source. This feature is valuable in applications such as RTDs or
strain gauges where the reference is derived externally.
Figure 97. Reference Detect Circuitry
The reference detect threshold value can be found in Table 5. This
feature is enabled when the REF_DETECT_ERR_EN bit in the
ERROR_EN register is set to 1. If the voltage between the selected
REFINx(+) and REFINx(−) pins goes below the threshold in Table
5, or either the REFINx(+) or REFINx(−) inputs are open circuit, the
AD4130-8 detects that it no longer has a valid reference. In this
case, the REF_DETECT_ERR bit in the error register is set to 1.
The MASTER_ERR bit in the status register is also set to 1 (see
Table 46).
versions or calibration. The functions can be enabled using the
ADC_ERR_EN bit in the ERROR_EN register. With these functions
enabled, the ADC_ERR bit is set to 1 if an error occurs.
The ADC_ERR flag is set for one or more of the following:
Conversion error when there is an overflow or underflow in the
digital filter. In this case, the ADC conversion also clamps to all
0s or all 1s.
► Modulator saturation error when the modulator outputs 20 consecutive 1s or 0s.
► Calibration error when during offset calibration, the resulting
offset coefficient are outside the 0x07FFFF to 0xF7FFFF range.
In this case, the OFFSET_n register is not updated and the
ADC_ERR flag is set to 1. Also, during a gain calibration, overflow of the digital filter is checked. If an overflow occurs, the error
flag is set to 1, and the GAIN_n register is not updated.
►
The ADC_ERR flag is updated with the update of the data register
and can be cleared only by writing a 1 to it.
OVERVOLTAGE/UNDERVOLTAGE DETECTION
The overvoltage/undervoltage monitors check the absolute voltage
on the AINx analog input pins and the REFINx input pins.
For the AINx pins, the absolute voltage must be within specification
to meet the data sheet specifications. If the ADC is operated outside the data sheet limits, linearity degrades. Figure 98 shows the
simplified block diagram of the AINx circuitry to detect overvoltage
and undervoltage.
The positive (AINP) and negative (AINM) analog inputs can
be separately checked for overvoltages and undervoltages. The
AINP_OV_UV_ERR_EN and AINM_OV_UV_ERR_EN bits in the
ERROR_EN register enable the overvoltage/undervoltage diagnostics respectively on AINP and AINM. An overvoltage is flagged
when the voltage on AINx exceeds AVDD while an undervoltage is
flagged when the voltage on AINx goes below AVSS.
The error flags are AINP_OV_UV_ERR and AINM_OV_UV_ERR
bits in the error register and they flag an overvoltage and/or undervoltage error on any enabled AINP and AINM respectively.
If the user is concerned about verifying that a valid reference is in
place every time a calibration is performed, check the status of the
REF_DETECT_ERR bit at the end of the calibration cycle.
The reference detect flag may be set when the device exits of
standby mode. Therefore, read the error register after exiting standby mode and write 1 to clear the REF_DETECT_ERR bit if set.
ADC ERRORS
The ADC conversion process and calibration process can also be
monitored by theAD4130-8. These diagnostics check the analog
input used as well as the modulator and digital filter during conanalog.com
Figure 98. Analog Input Overvoltage/Undervoltage Monitors
Rev. 0 | 66 of 108
Data Sheet
AD4130-8
DIAGNOSTICS
The ΔV threshold value can be found in Table 5.
The external reference voltage can also be monitored for overvoltage/undervoltage enabling the REF_OV_UV_ERR_EN bit in the
ERROR_EN register. An overvoltage is flagged when the voltage
on REFINx(+) exceeds AVDD while an undervoltage is flagged
when the voltage on REFINx(−) goes below AVSS. The error flag
REF_OV_UV_ERR in the error register is set to 1 in any of the two
conditions.
When this function is enabled, the corresponding flags can be set in
the error register. These bits are R/W1C.
POWER SUPPLY MONITORS
Along with converting external voltages, the ADC can monitor the
voltage on the AVDD pin and the IOVDD pin. When the inputs of
AVDD to AVSS or IOVDD to DGND are selected, the voltage (AVDD
to AVSS or IOVDD to DGND) is internally attenuated by 6, and the
resulting voltage is applied to the Σ-Δ modulator. This is useful to
monitor variations in the power supply voltage.
MASTER CLOCK COUNTER
A stable MCLK to the ADC is important as the output data rate, filter
first conversion time, and the filter notch frequencies are dependent
on the master clock. The AD4130-8 allows the user to monitor the
master clock. When the MCLK_CNT_EN bit in the ERROR_EN
register is set, the MCLK_COUNT register increments by 1 every
131 master clock cycles. The user can monitor this register over
a fixed period. The master clock frequency can be determined
from the result in the MCLK_COUNT register. The MCLK_COUNT
register wraps around after it reaches its maximum value.
SPI DIAGNOSTICS
SPI Clock Counter
The SPI SCLK counter counts the number of SCLK pulses used in
each read and write operation. CS must frame every read and write
operation when this function is used. All read and write operations
are multiples of eight SCLK pulses. If the SCLK counter counts the
SCLK pulses and the result is not a multiple of eight, an error is
flagged. The SPI_SCLK_CNT_ERR bit in the error register is set to
1. If a write operation is being performed and the SCLK contains an
insufficient number of SCLK pulses, the value is not written to the
addressed register and the write operation is aborted.
The SCLK counter is enabled by setting the SPI_SCLK_
CNT_ERR_EN bit in the ERROR_EN register.
SPI Read/Write Errors
Along with the SCLK counter, the AD4130-8 can also check the
read and write operations to ensure that valid registers are being
addressed.
71 cause the SPI_READ_ERR bit to be set to 1 and the readback
data for that register is all 0s.
When the SPI_WRITE_ERR_EN bit in the ERROR_EN register is
set to 1, attempts to write to read-only registers and to registers at
addresses not listed in Table 71 cause the SPI_WRITE_ERR bit to
be set to 1, and the write transaction is aborted.
This function, along with the SCLK counter and the CRC protection,
makes the serial interface more robust. Invalid registers are not
written to or read from. An incorrect number of SCLK pulses
can cause the serial interface to go asynchronous and incorrect
registers to be accessed. The AD4130-8 protects against these
issues via the diagnostics.
SPI Ignore Error
At certain times, the on-chip registers are not accessible. During
power-up, when the on-chip registers are set to their default values,
they cannot be accessed via SPI. The user must wait tRESET_DELAY
until this operation is complete before writing to registers. When
offset or gain calibrations are being performed, registers cannot be
accessed. When in single sequence mode, during conversion and
before the last conversion finishes, registers cannot be accessed.
The SPI_IGNORE_ERR bit in the error register indicates when
the on-chip registers cannot be written to. This diagnostic is enabled by default. The function can be disabled using the SPI_IGNORE_ERR_EN bit in the ERROR_EN register.
Any write operations performed when SPI_IGNORE_ERR is set to
1 in the error register are ignored. This bit is R/W1C.
CRC PROTECTION
The AD4130-8 features optional CRC to provide error detection on
interface transactions, memory map content, and read-only memory
(ROM) content.
CRC Calculation
The AD4130-8 uses the CRC-8 standard with the following polynomial:
x8 + x2 + x + 1
To generate the checksum, the data is left shifted by eight bits to
create a number ending in eight Logic 0s. The polynomial is aligned
so that its MSB is adjacent to the leftmost Logic 1 of the data. An
XOR (exclusive OR) function is applied to the data to produce a
new, shorter number. The polynomial is again aligned so that its
MSB is adjacent to the leftmost Logic 1 of the new result, and the
procedure is repeated. This process is repeated until the original
data is reduced to a value less than the polynomial. This is the 8-bit
checksum.
When the SPI_READ_ERR_EN bit in the ERROR_EN register is
set to 1, attempts to read registers at addresses not listed in Table
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Rev. 0 | 67 of 108
Data Sheet
AD4130-8
DIAGNOSTICS
SPI CRC Protection
Memory Map CRC Protection
The AD4130-8 has a CRC mode that can be used to improve
interface robustness. Using the CRC ensures that only valid data
is written to a register and allows data read from a register to be
validated. If an error occurs during a register write, the CRC_ERR
bit is set to 1 in the error register and the write transaction is aborted. However, to ensure that the register write was successful, read
back the register and verify the checksum. The CRC_ERR_EN bit
in the ERROR_EN register enables and disables the SPI CRC.
For added robustness, a CRC calculation is performed on the onchip registers as well. The status register, data register, ID register,
error register, MCLK_COUNT register, FIFO_STATUS register, and
FIFO_DATA register are not included in this check because their
contents change continuously, or they are read-only registers. The
CRC is performed at a rate of 1/300 seconds. Each time that the
memory map is accessed, the CRC is recalculated. Events that
cause the CRC to be recalculated are
The SPI checksum is appended to the end of each read and write
transaction. For a write transaction, the checksum is calculated
using the 8-bit command word and the 8-bit to 24-bit data. For
a read transaction, the checksum is calculated using the 8-bit
command word and the 8-bit to 32-bit data output. Figure 99
and Figure 100 show SPI write and read transactions with CRC
enabled, respectively.
A user write command
► An offset/full-scale calibration
► When the device is operated in single sequence mode and the
ADC goes into standby mode following the completion of the
conversion
► When exiting continuous read mode (the CONT_READ bit in the
ADC_CONTROL register is set to 0)
►
The memory map CRC function is enabled by setting the MM_
CRC_ERR_EN bit in the ERROR_EN register to 1. If an error
occurs, the MM_CRC_ERR bit in the error register is set to 1.
ROM CRC Protection
On power-up, all registers are set to default values. These default
values are held in ROM. For added robustness, at power-up, a
CRC calculation is performed on the ROM contents as well.
The ROM CRC function is enabled by setting the ROM_CRC_
ERR_EN bit in the ERROR_EN register to 1. If an error occurs, the
ROM_CRC_ERR bit in the error register is set to 1.
Figure 99. SPI Write Transaction with CRC
When this function is enabled, the internal master clock, if enabled,
remains active in the standby mode.
FIFO DIAGNOSTICS
On power-up, the FIFO is disabled. When enabled, the FIFO_STATUS register (see Table 69) and/or the FIFO_HEADER can be used
to track the status of the FIFO and flag a number of errors on write/
read operations, thresholds and watermark being reached, and
overrun and empty flags. For more details, see the FIFO section.
BURNOUT CURRENTS
Figure 100. SPI Read Transaction with CRC
If SPI CRC is enabled when continuous read mode is active, there
is an implied read data command of 0x42 before every data transmission that must be accounted for when calculating the checksum
value. This ensures a nonzero checksum value even if the ADC
data equals 0x000000.
The AD4130-8 contains two constant current generators that can
be programmed to 0.5 µA, 2 µA, or 4 µA. One generator sources
current from AVDD to AINP, and one sinks current from AINM to
AVSS, as shown in Figure 101. These currents enable open wire
detection to check if a sensor is connected.
See the CRC on FIFO Data section.
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Data Sheet
AD4130-8
DIAGNOSTICS
TEMPERATURE SENSOR
The AD4130-8 has an integrated temperature sensor that is useful
to monitor the die temperature at which the device is operating.
This can be used for diagnostic purposes or as an indicator of when
the application circuit needs to rerun a calibration routine to take
into account a shift in operating temperature.
The temperature sensor is accessible through the X-MUX as an
internal channel and can be selected using the AINP, Bits[4:0] and
AINM, Bits[4:0] in each CHANNEL_m register.
The equation for the temperature sensor is as follows:
Temperature (°C) = (Conversion (μV) / Sensitivity (μV/K)) – 273.15
Figure 101. Burnout Currents
The currents are switched to the selected analog input pair. Both
currents are either on or off. The burnout bits in the configuration
register enable/disable the burnout currents along with setting the
amplitude. Use these currents to verify that an external transducer
is still operational before attempting to take measurements on that
channel. After the burnout currents are turned on, they flow in the
external transducer circuit, and a measurement of the input voltage
on the analog input channel can be taken.
If the resulting voltage measured is near full scale, the user must
verify why this is the case. A near full-scale reading can mean that
the front-end sensor is open circuit. It can also mean that the frontend sensor is overloaded and is justified in outputting full scale, or
that the reference may be absent and the REF_DETECT_ERR bit
is set, thus clamping the data to all 1s. When a conversion is close
to full scale, the user must check these three cases before making
a judgment.
where:
Conversion (μV) is the conversion result from the temperature
sensor converted to Volts using the equations in Table 43.
Sensitivity (V/°C) is the sensitivity of the temperature sensor. The
nominal sensitivity can be found in Table 5.
To improve the temperature sensor accuracy, operate the device in
a known temperature (25°C) and take a conversion as a reference
point. The difference between the nominal sensitivity and the one
measured for the device can be used to calibrate the temperature
sensor to higher accuracy.
The temperature sensor specifications can be found in Table 5 and
Figure 57. See the Terminology section.
DIAGNOSTICS AND STANDBY MODE
The diagnostic functionality can be disabled when in standby mode
by setting the STB_EN_DIAGNOSTICS bit in the MISC register
to 1. Some diagnostics also require the internal oscillator to be
enabled, so if those errors are enabled in the ERROR_EN register
and the STB_EN_DIAGNOSTICS = 1, the internal oscillator is kept
enabled. See the Standby Mode section.
If the voltage measured is 0 V, it may indicate that the transducer
has short circuited.
For normal operations, these burnout currents are turned off by
setting the burnout bits to zero. The current sources work over the
normal absolute input voltage range specifications with buffers on.
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Data Sheet
AD4130-8
FIFO
The AD4130-8 has ultra low power performance. Further system
power saving can be achieved by putting the host processor and
other peripherals to sleep when not in use. The AD4130-8 has an
on-chip FIFO buffer to facilitate storage of up to 256 conversion
results. Data can be collected continuously using the FIFO and the
processor can be awakened via an interrupt from the AD4130-8
when data exceeds a specified threshold, when the FIFO has
reached a predefined number of samples, or when the FIFO is full.
The FIFO data is saved in 32-bit format, made of an 8-bit data for
the FIFO_HEADER followed by a 24-bit data for the FIFO_DATA
(conversion result). Figure 102 shows the basic structure of the
FIFO.
Write FIFO_MODE = 0b00 to exit any of the other FIFO modes.
Watermark Mode
In watermark mode, the FIFO collects data until the watermark
level is reached. The watermark level specifies the number of
conversions to store in the FIFO and is set by writing to the
watermark bitfield in the FIFO_CONTROL register. The watermark
bitfield default value is 0, which corresponds to 256 samples to fill
the FIFO. Once the watermark is reached, the user must read all
the data from the FIFO before the next ADC result is written to
the FIFO. Otherwise, a FIFO write error occurs (FIFO_WRITE_ERR
bit is set to 1 in the FIFO_STATUS register, see Table 69) and
conversion results are lost. The FIFO is not updated with new
ADC data until the FIFO is completely read, as shown in Table
65. Clearing the FIFO is recommended after reading the FIFO in
watermark mode.
See the FIFO Readback section for details on how to calculate the
time needed to readback the FIFO. Depending on the channels and
smart sequencer configuration, and the SCLK speed for the FIFO
readback, the watermark value may have to be limited to avoid data
loss.
See the FIFO Watermark Interrupt section.
Streaming Mode
Figure 102. FIFO Structure
FIFO MODES
The FIFO can be set to one of the three modes described in this
section by selecting the correspondent FIFO_MODE bits value in
the FIFO_CONTROL register.
In streaming mode, the FIFO always contains the most recent ADC
data. Unlike the watermark mode, the FIFO continues to store ADC
results even when the watermark level is reached, and FIFO is
not read. When the FIFO is filled with 256 conversions, the older
conversions are overwritten with new ADC results, as shown in
Table 66. In this mode, data can be read back at any time unless
the FIFO is being updated with new ADC result. In streaming mode,
the FIFO is eventually overrun and the OVERRUN_FLAG bit in the
FIFO_STATUS register is set to 1 (see Table 69).
Disabled
The FIFO is disabled by default. When the FIFO is disabled, it is
held in reset, so any old data is lost. The FIFO is disabled by setting
the FIFO_MODE bits in the FIFO_CONTROL register to 0b00.
Table 65. Example of FIFO Buffer Filling Up with Conversion Results in Watermark Mode with Watermark = 0 (256 Samples) and Data Not Read Back When Full
FIFO
Address
Conversion 1
Conversion 2
… Conversion 255
Conversion 256
Conversion 257
Conversion 258
…
255
Empty
Empty
… Empty
Empty
Empty
…
1
…
Empty
0
(FIFO_HEADER (1),
FIFO_DATA (1))
…
(FIFO_HEADER (2),
FIFO_DATA (2))
(FIFO_HEADER (1),
FIFO_DATA (1))
… (FIFO_HEADER (255),
FIFO_DATA (255))
… …
… (FIFO_HEADER (2),
FIFO_DATA (2))
… (FIFO_HEADER (1),
FIFO_DATA (1))
(FIFO_HEADER (256),
FIFO_DATA (256))
(FIFO_HEADER (255),
FIFO_DATA (255))
…
(FIFO_HEADER (2),
FIFO_DATA (2))
(FIFO_HEADER (1),
FIFO_DATA (1))
(FIFO_HEADER (256),
FIFO_DATA (256))
(FIFO_HEADER (255),
FIFO_DATA (255))
…
(FIFO_HEADER (2),
FIFO_DATA (2))
(FIFO_HEADER (1),
FIFO_DATA (1))
…
254
(FIFO_HEADER (256),
FIFO_DATA (256))
(FIFO_HEADER (255),
FIFO_DATA (255))
…
(FIFO_HEADER (2),
FIFO_DATA (2))
(FIFO_HEADER (1),
FIFO_DATA (1))
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…
…
…
…
Rev. 0 | 70 of 108
Data Sheet
AD4130-8
FIFO
Table 66. Example of FIFO Buffer Filling Up with Conversion Results in Streaming Mode with Watermark = 0 (256 Samples) and Data Not Read Back When Full
FIFO
Address
Conversion 1
Conversion 2
… Conversion 255
Conversion 256
Conversion 257
Conversion 258
…
255
Empty
Empty
… Empty
Empty
Empty
…
1
…
Empty
0
(FIFO_HEADER (1),
FIFO_DATA (1))
…
(FIFO_HEADER (2),
FIFO_DATA (2))
(FIFO_HEADER (1),
FIFO_DATA (1))
… (FIFO_HEADER (255),
FIFO_DATA (255))
… …
… (FIFO_HEADER (2),
FIFO_DATA (2))
… (FIFO_HEADER (1),
FIFO_DATA (1))
(FIFO_HEADER (257),
FIFO_DATA (257))
(FIFO_HEADER (256),
FIFO_DATA (256))
…
(FIFO_HEADER (3),
FIFO_DATA (3))
(FIFO_HEADER (2),
FIFO_DATA (2))
(FIFO_HEADER (258),
FIFO_DATA (258))
(FIFO_HEADER (257),
FIFO_DATA (257))
…
(FIFO_HEADER (4),
FIFO_DATA (4))
(FIFO_HEADER (3),
FIFO_DATA (3))
…
254
(FIFO_HEADER (256),
FIFO_DATA (256))
(FIFO_HEADER (255),
FIFO_DATA (255))
…
(FIFO_HEADER (2),
FIFO_DATA (2))
(FIFO_HEADER (1),
FIFO_DATA (1))
…
…
…
…
Table 67. FIFO_CONTROL Register
Reg.
Name
Bits
0x3A
FIFO_CO
NTROL
[23:16]
[15:8]
[7:0]
Bit 7
Bit 6
Bit 5
Bit 4
RESERVED
ADD_FIFO_S
TATUS
RESERVED FIFO_WRITE FIFO_READ THRES_HIGH THRES_LOW
_ERR_INT_ _ERR_INT_ _INT_EN
_INT_EN
EN
EN
WATERMARK
FIFO READBACK
The FIFO buffer is read by using the COMMS register to read
Address 0x3D. The complete FIFO read command is 0x7D. This is
followed by an 8-bit field, # samples (N), to indicate the number of
samples to be read, where 0x00 corresponds to 256 samples. The
FIFO content then appears on the DOUT pin once the appropriate
number of SCLKs is provided. When reading the last value in
the FIFO, the EMPTY_FLAG bit in the FIFO_HEADER and in the
FIFO_STATUS register is set to 1 (see Table 69). If attempts to read
the FIFO continue, the EMPTY_FLAG bit remains set and the data
read is all 0s. The FIFO read is terminated by toggling CS high or
when the number of samples read reaches the specified amount in
the FIFO command.
By default, the FIFO_HEADER is enabled and the FIFO_STATUS
append is disabled, so the FIFO readback diagram looks like Figure
103. If the FIFO_STATUS append is enabled, the FIFO readback
diagram looks like Figure 104.
The time available to the user to read the FIFO depends on the
time the next two ADC conversions in the sequence take.
tFIFO_READ = Σ ConvTime_n – (tBSY + tQUIET1 + tQUIET2)
where:
tFIFO_READ is the maximum time available for the FIFO readback
that avoids data loss.
Σ ConvTime_n with (n = 0 − 1) is the conversion time of the next
two conversions in the sequence. Note that the conversion time can
be different based on the channels enabled. See the 50 Hz and
60 Hz Rejection section for more details on how to calculate the
ADC conversion time for a given channel in the sequence.
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Bit 3
Bit 2
ADD_FIFO
_HEADER
OVERRUN
_INT_EN
Bit 1
Bit 0
Reset
FIFO_MODE
WATERMARK
_INT_EN
RW
0x040200 R/W
EMPTY
_INT_E
N
tBSY + tQUIET1 + tQUIET2 is 8 MCLK cycles as a minimum. See Figure
12 and Table 10.
The number of SCLK cycles needed to complete a FIFO readback
is equal to:
# SCLK cycles = FIFO read command length +
# samples (N) × samples length
where:
FIFO read command length is equal to 16 SCLK cycles.
# samples (N) is the number of FIFO samples to read specified in
the FIFO read command.
samples length is equal to 24 SCLK cycles if the FIFO_HEADER is
disabled, or 32 SCLK cycles if the FIFO_HEADER is enabled.
When the SPI takes control of the FIFO for the readback, the
device does not have access to the FIFO to write new data to it. If
the FIFO readback takes longer than tFIFO_READ to complete, there
can be data loss from the converted sequence.
FIFO Ready Signal
When the FIFO is enabled, a FIFO ready signal is automatically
shared to the DOUT pin. When this signal is high, it indicates that
the FIFO is busy. The ADC is accessing the FIFO to write new data
to it. When this signal is low, it indicates that the FIFO is available
to be read by the user. When in watermark mode, the FIFO ready
signal remains high until the number of samples stored in the FIFO
reaches the watermark value. Then, the FIFO ready signal goes
low to flag the user that a read command can be sent. When in
streaming mode, the FIFO ready signal flags when the FIFO is busy
after every conversion.
Rev. 0 | 71 of 108
Data Sheet
AD4130-8
FIFO
Table 68. FIFO Header Format
Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset RW
FIFO_HEADER
[7:0]
RESERVED
THRESHOLD_FLAG
WATERMARK_FLAG
EMPTY_FLAG
CH[3]
CH[2]
CH[1]
CH[0]
0x00
R
Table 69. FIFO_STATUS Register
Reg.
Name
0x3B
FIFO_STATUS [7:0]
Bits
Bit 7
Bit 6
Bit 5
Bit 4
FIFO Header
FIFO_HEADER is enabled by default and is stored with each
conversion result in the FIFO with the format shown in Table 68.
FIFO_HEADER can be disabled by setting the ADD_FIFO_HEADER bit in FIFO_CONTROL register to 0. Figure 105 shows reading
the data with FIFO_HEADER disabled.
FIFO_HEADER has the following bits of information:
The CH, Bits[3:0] hold the channel number for the data
FIFO_HEADER is appended to.
► The EMPTY_FLAG bit is set to 1 in the FIFO_HEADER associated with the last data sample from the FIFO being read so it can
be interpreted as the trigger to stop reading back the FIFO.
► The WATERMARK_FLAG bit is set to 1 in the FIFO_STATUS
register when the FIFO contains a number of samples greater
than or equal to the indicated samples in the watermark field
of the FIFO_CONTROL register. Therefore, it is flagged in
FIFO_HEADER for every sample stored in excess of and equal
to the watermark value.
► The THRESHOLD_FLAG bit is set to 1 if the THRES_EN_m
bit is set to 1 in the relative CHANNEL_m register, and the
ADC conversion result for that channel exceeds threshold values
specified by the threshold range using the THRES_HIGH_VAL
and THRES_LOW_VAL bitfields in the FIFO_THRESHOLD register. The THRESHOLD_FLAG bit in FIFO_HEADER is non
sticky. Therefore, it is relevant for every sample.
►
FIFO Status
The FIFO_STATUS register content (see Table 69) can be enabled
to be added and read before the FIFO_DATA and during the #
samples (N) byte (see Figure 104), by setting ADD_FIFO_STATUS
bit to 1 in the FIFO_CONTROL register (see Table 67). This way,
the user can detect an error earlier on and abort the FIFO_DATA
readback.
The FIFO_STATUS register contains errors and flags to help with
the FIFO operations when the FIFO is enabled.
A FIFO empty flag is triggered (EMPTY_FLAG bit is set to 1) in the
FIFO_STATUS register as the first bit of the last data sample from
the FIFO is being read. If attempting to read an empty FIFO, this
flag is set to 1 in the FIFO_STATUS register. This flag clears when
the FIFO is written with at least one ADC conversion.
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Bit 3
Bit 2
Bit 1
Bit 0
Reset RW
MASTER_ FIFO_WRITE_ FIFO_READ_ THRES_HIGH THRES_LOW OVERRUN_ WATERMARK_ EMPTY_ 0x01
ERR
ERR
ERR
_FLAG
_FLAG
FLAG
FLAG
FLAG
R
A FIFO watermark flag is triggered (WATERMARK_FLAG set to 1)
in the FIFO_STATUS register when the FIFO contains a number
of samples greater than or equal to the indicated samples in the
watermark field of the FIFO_CONTROL register. The watermark
flag clears as soon as the remaining samples in the FIFO are
detected to be less than the value in the watermark field.
A FIFO overrun flag (OVERRUN_FLAG bit is set to 1) occurs if
ADC data is lost and is not stored in the FIFO. In watermark mode,
this occurs when the FIFO is not emptied out before a new sample
must be stored. In streaming mode, ADC data is lost when oldest
data in the FIFO is discarded to make way for new data as the
FIFO was already full. The overrun flag clears when the FIFO is
emptied by reading all the content or clearing the FIFO.
A FIFO threshold flag is triggered (THRES_HIGH_FLAG and/or
THRES_LOW_FLAG bitfields is set to 1) if the ADC conversion
result exceeds the threshold values specified. Unlike THRESHOLD_FLAG in FIFO_HEADER, the THRES_HIGH_FLAG and
THRES_LOW_FLAG bitfields are sticky. That is, once these bitfields are set, they remain set despite the next ADC conversion
result. The threshold flags can be cleared by reading all the data in
the FIFO, or by clearing the FIFO.
A FIFO read error (FIFO_READ_ERR set to 1) only occurs when
attempts are made to read the FIFO data while the ADC is updating
internally (writing to the FIFO). The FIFO_DATA transmitted is all
0s when reading from the FIFO, the FIFO_HEADER information is
also all 0s if this error occurred. This error clears when a FIFO read
request is successfully granted or the FIFO is emptied.
A FIFO write error (FIFO_WRITE_ERR set to 1) occurs when
conversion data is not written to the FIFO due to ongoing read of
the FIFO by the user. An ADC FIFO write can be delayed by up
to one conversion cycle if the user is still reading the FIFO data.
However, if the user is still reading data following one conversion
delay, a FIFO write error is asserted. When in watermark mode, a
FIFO write error can occur if the FIFO reaches a number of entries
equal to the watermark specified and an attempt to write new data
to it is made. This error clears when all the content of the FIFO is
read or by clearing the FIFO.
The master error bit in the FIFO_STATUS register is shared with
the STATUS register and follows the same behavior.
Rev. 0 | 72 of 108
Data Sheet
AD4130-8
FIFO
CRC on FIFO Data
The CRC on FIFO data is calculated as follows:
When reading back FIFO data, a 16-bit CRC can be enabled
by setting the SPI_CRC_ERR to 1 in the error register. This is
only possible when FIFO_STATUS is disabled (ADD_FIFO_STATUS = 0) and FIFO_HEADER is enabled (ADD_FIFO_HEADER = 1) in the FIFO_CONTROL register (default settings). See
Table 67 and Figure 106.
►
CRC data is sent after reading out samples of data equal to the
watermark specified. Thus, in watermark mode, the CRC check is
performed on all data as the FIFO length equals the watermark.
While in streaming mode, the CRC is calculated on blocks of
watermark samples.
The CRC can detect up to 3-bit errors for up to 32571 bits and can
be used for the full FIFO depth of 256. The CRC must be initialized
to 0xFFFF.
First CRC sent is computed based on: (1) FIFO read command
(0x7d) plus number of data to read; (2) ADC data read out
► Succeeding CRC is solely based on ADC data read out
The 16-bit CRC polynomial to be used for checks is
x16 + x15 + x13 + x9 + x7 + x6 + x5 + x3 + x1 + 1
Figure 103. FIFO Readback Default (FIFO_STATUS Append Off and FIFO_HEADER Append On)
Figure 104. FIFO Readback (FIFO_STATUS Append On and FIFO_HEADER Append On)
Figure 105. FIFO Readback (FIFO_STATUS Append On and FIFO_HEADER Append Off)
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Rev. 0 | 73 of 108
Data Sheet
AD4130-8
FIFO
Figure 106. FIFO Readback (FIFO_STATUS Append Off and FIFO_HEADER Append On, CRC On)
FIFO INTERRUPT
The AD4130-8 FIFO buffer can adopt multiple interrupt modes by
configuring the FIFO_CONTROL register. The interrupt signal sent
to the FIFO interrupt pin is the logic OR of all the enabled interrupt
options in the FIFO_CONTROL register. See the FIFO Interrupt Pin
section on how to select the pin to direct the interrupt signal to.
FIFO Watermark Interrupt
The FIFO watermark interrupt is enabled by default and can be
disabled by setting the WATERMARK_INT_EN bit to 0 in the
FIFO_CONTROL register. The number of samples needed to trigger a FIFO watermark interrupt is equal to the value specified
in the watermark bitfield. The exception is the value 0, which is
the default value. In this case, the FIFO needs to be filled to the
maximum depth of 256 entries before triggering an interrupt. The
FIFO watermark interrupt signal is active high and stays asserted
while the number of samples in the FIFO is equal or greater than
the value specified in the watermark register. The FIFO watermark
interrupt signal is deasserted when the flag is cleared as soon as
the remaining samples in the FIFO are detected to be less than
watermark entries.
FIFO Data Threshold Interrupt
The THRES_HIGH_FLAG and THRES_LOW_FLAG bits in the
FIFO_STATUS register (see Table 69) can be enabled to trigger a
FIFO data threshold interrupt by setting the THRES_HIGH_INT_EN
bit and/or the THRES_LOW_INT_EN bit to 1 in the FIFO_CONTROL register. Both options are disabled by default and can be
enabled separately.
The threshold values for the FIFO data threshold interrupt can
be specified in the THRES_HIGH_VAL and THRES_LOW_VAL
bitfields in the FIFO_THRESHOLD register. These values need to
be consistent with polarity setting specified by the bipolar bit in the
ADC_CONTROL register.
After updating the threshold values, it is recommended to clear the
FIFO by writing to FIFO_CONTROL register, so that the next set
of conversions in the FIFO assume the updated threshold values.
Doing this also clears the FIFO data threshold interrupt signal
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and the THRES_HIGH_FLAG and THRES_LOW_FLAG bits in the
FIFO_STATUS register.
Note that threshold comparison has hysteresis of 1 LSB with
respect to the threshold value set. When a conversion triggers
THRES_HIGH_FLAG or THRES_LOW_FLAG to be set to 1, succeeding conversions must have DATA, Bits[23:12] at least 2 LSBs
greater than the THRES_LOW_VAL bitfield, and 2 LSBs lower
than THRES_HIGH_VAL bitfield for the THRES_LOW_FLAG and
THRES_HIGH_FLAG bits to return to 0.
FIFO Empty Interrupt
The EMPTY_FLAG bit in the FIFO_STATUS register (see Table
69) can be enabled to trigger a FIFO empty interrupt by setting
the EMPTY_INT_EN bit to 1 in the FIFO_CONTROL register. This
option is disabled by default. The FIFO empty interrupt clears when
the FIFO empty error clears in the FIFO_STATUS register, which is
when the FIFO is written with at least one ADC conversion.
FIFO Write/Read Error Interrupt
The FIFO_WRITE_ERR and FIFO_READ_ERR bits in the
FIFO_STATUS register (see Table 69) can be enabled to trigger
a FIFO write interrupt and/or a FIFO read interrupt by setting the
FIFO_WRITE_ERR_INT_EN and/or FIFO_READ_ERR_ INT_EN
bits to 1 in the FIFO_CONTROL register. This option is disabled by
default.
The FIFO write/read error interrupt signals are deasserted as soon
as the error flags clear in the FIFO_STATUS register.
FIFO Overrun Interrupt
The OVERRUN_FLAG bit in the FIFO_STATUS register (see Table
69) can be enabled to trigger an interrupt by setting the OVERRUN_INT_EN bit to 1 in the FIFO_CONTROL register. This option
is disabled by default.
The FIFO overrun interrupt signal is deasserted as soon as the
error flag clears in the FIFO_STATUS register, which is when the
FIFO is emptied.
Rev. 0 | 74 of 108
Data Sheet
AD4130-8
FIFO
FIFO Interrupt Pin
When the FIFO is enabled, a FIFO interrupt signal can be generated internally and directed to a pin of choice by configuring the
INT_PIN_SEL bits in the IO_CONTROL register (see Table 39) as
per Table 70.
Configuring a pin as interrupt takes priority over other pin controls
on that pin. That is, enabling the CLK pin as a CLK input via the
CLK_SEL bit in the ADC_CONTROL register is ignored if the CLK
pin is enabled as an interrupt. Enabling the P2 pin as a GPO output
via the GPO_CTRL_P2 bit in the IO_CONTROL is ignored if P2 is
enabled as an interrupt. When P2 is enabled as an interrupt pin, the
GPO pins are also automatically enabled in standby mode.
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Table 70. FIFO Interrupt Pin Options
INT_PIN_SEL
Pin Options1
0b00 (Default)
0b01
0b10
0b11
INT
CLK
P2
N/A2
1
FIFO enabled. When the FIFO is disabled, the INT_PIN_SEL bitfield is used to
assign the ready signal to a pin as per Table 53.
2
N/A means not applicable.
CLEARING THE FIFO
When the FIFO is enabled, any write to the FIFO_CONTROL
register clears the FIFO. It is also possible to use the SYNC pin
to initiate a FIFO clear by setting the SYNCB_CLEAR bit to 1 in
the IO_CONTROL register (see Table 39). Clearing the FIFO using
the SYNC pin guarantees that the sequencer restarts from the first
channel. See Figure 11, Figure 13, and Table 10.
Rev. 0 | 75 of 108
Data Sheet
AD4130-8
APPLICATIONS INFORMATION
POWER SCHEMES
The AD4130-8 allows for different power schemes depending on
the requirements.
Single-Supply Operation (AVSS = DGND)
When the AD4130-8 is powered from a single supply that is
connected to AVDD and IOVDD, AVSS and DGND can be shorted
together on one single ground plane. With this setup, an external
level shifting circuit is required when using truly bipolar inputs to
shift the common-mode voltage. Recommended regulators include
the ADP150, which has a 3.3 V output and low quiescent current.
When AVDD and IOVDD are connected to the same source, their
minimum value is limited by the minimum AVDD = 1.71 V.
Split Supply Operation (AVSS ≠ DGND)
The AD4130-8 can operate with AVSS set to a negative voltage,
allowing true bipolar inputs to be applied. This allows a truly
fully differential input signal centered around 0 V to be applied
to the AD4130-8 without the need for an external level shifting
circuit. For example, with a 3.6 V split supply, AVDD = +1.8 V and
AVSS = −1.8 V. In this use case, the AD4130-8 internally level shifts
the signals, allowing the digital output to function between DGND
(nominally 0 V) and IOVDD.
When using a split supply for AVDD and AVSS, the absolute maximum ratings must be considered (see the Absolute Maximum
Ratings section).
The AD4130-8 also has two on-board LDO regulators, one that
regulates the AVDD supply and one that regulates the IOVDD supply.
For the REGCAPA pin, it is recommended to add a 0.1 µF capacitor
to AVSS. Similarly, for the REGCAPD pin, it is recommended to add
a 0.1 µF capacitor to DGND.
INPUT FILTERS
An external antialiasing filter is required to reject any interference at
the modulator frequency (fMOD = fMCLK/2 = 38.4 kHz) and multiples
of the modulator frequency. In addition, some filtering may be needed for electromagnetic interference (EMI) purposes. The analog
inputs are buffered, and the reference inputs can be buffered, which
allows the user to connect any RC combination to the reference or
analog input pins.
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD4130-8 is via a serial bus that
uses a standard protocol compatible with DSPs and microcontrollers. The communications channel requires a 4‑wire serial interface
consisting of a clock signal, a data input signal, a data output
signal, and a synchronization signal.
The SPI of the AD4130-8 is designed to be easily connected to
industry-standard DSPs and microcontrollers. Figure 107 shows the
AD4130-8 connected to the MAX32670. The MAX32670 has an
integrated SPI port that can be connected directly to the SPI pins of
the AD4130-8.
Keep in mind that when AVSS ≠ DGND, the GPOs cannot be used
as digital output pins.
Separate Positive Supplies Operation
When trying to minimize the power consumption, AVDD and IOVDD
can be connected to separate sources to be independently lowered
to their minimum values. AVDD can be as low as 1.71 V, while
IOVDD can be as low as 1.65 V. For example, IOVDD can be
powered by the same source of the processor interface, while AVDD
can have its own source.
RECOMMENDED DECOUPLING
Good decoupling is important when using high resolution ADCs.
The AD4130-8 has two power supply pins, AVDD and IOVDD. The
AVDD pin is referenced to AVSS, and the IOVDD pin is referenced to
DGND. Decouple AVDD with a 1 µF tantalum capacitor in parallel
with a 0.1 µF capacitor to AVSS. Decouple IOVDD with a 1 µF
tantalum capacitor in parallel with a 0.1 µF capacitor to DGND.
Place the 0.1 µF capacitors as close as possible to the device
on each supply, ideally right up against the device. All analog
inputs must be decoupled to AVSS. If an external reference is used,
decouple the REFINx(+) and REFINx(−) pins to AVSS.
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Figure 107. Example of MAX32670 μC SPI Connection to AD4130-8
Digital Pins
It is recommended that a weak pull-up resistor to IOVDD is placed
on CS (when in use), SYNC, and SCLK lines to keep the interface
disabled while powering up the device. It is recommended that a
weak pull-down resistor is placed on the DIN line.
UNUSED PINS
When not in use, the following digital pins must be treated with
care. Connect SYNC to IOVDD directly or with a weak pull‑up
resistor. Connect CS and CLK to DGND with a weak pull‑down
resistor.
When not in use, the analog pins (AINx, REFINx(±), REFOUT,
PSW) can be left electrically floating, but must be soldered to the
PCB for mechanical stability.
Rev. 0 | 76 of 108
Data Sheet
AD4130-8
APPLICATIONS INFORMATION
POWER-UP AND INITIALIZATION
Power up the AD4130-8 by following the recommended power supply sequencing as follows: DGND, AVSS (if different from DGND),
IOVDD, AVDD, REFINx(+) and REFINx(−), AINx, Digital Inputs. See
also Digital Pins section.
Upon power-up, wait for the tRESET_DELAY timing before attempting
an SPI transaction (see the Power-On Reset section). The device
has a power-on reset function. However, any glitches during power-up can cause corruption of the registers. Therefore, a reset in
the initialization routine is advisable. Write 64 consecutive ones
to the device to perform a software reset (see the Device Reset
section). If the digital host attempts to perform an SPI transaction
before the device is ready, the transaction is invalid and the
SPI_IGNORE_ERR bit in the ERROR register is set. The SPI_IGNORE_ERR is an R/W1C type of bit.
After the device initializes, the digital interface can be accessed
to configure the device, including selecting the reference scheme
according to the application. Regardless of the voltage reference
scheme used, it is recommended to let the voltage reference settle
after configuring the device to ensure it achieves its specifications.
The recommended configuration flow is as follows:
1. Select Interface mode: write to ADC_CONTROL register (select
3-wire or 4-wire mode, clock source, enable CRC, data + status, and so on).
2. Setup configuration: Eight possible ADC setup options. Write
to the CONFIG_n and FILTER_n registers (select configuration,
filter order, output data rate, and so on).
3. Channel configuration: write to the CHANNEL_m registers
(select positive and negative input and setup for each ADC
channel, enable open wire detection in GPIO configuration, and
so on).
4. Setup ADC mode: write to the ADC_CONTROL register (select
ADC operating mode, clock source, enable CRC, data + status,
and so on) to start conversions.
LAYOUT AND GROUNDING
The analog inputs and reference inputs are differential and, therefore, most of the voltages in the analog modulator are commonmode voltages. The high common-mode rejection of the device
removes common-mode noise on these inputs. The analog and
digital supplies to the AD4130-8 are independent and separately
pinned out to minimize coupling between the analog and digital
sections of the device. The digital filter provides rejection of broadband noise on the power supplies, except at integer multiples of the
master clock frequency.
The digital filter also removes noise from the analog and reference
inputs, provided that these noise sources do not saturate the
analog modulator. As a result, the AD4130-8 is more immune to
noise interference than a conventional high resolution converter.
However, given that the resolution of the AD4130-8 is high and
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the noise levels from the converter are so low, care must be taken
regarding grounding and layout.
The PCB that houses the ADC must be designed so that the analog
and digital sections are separated and confined to certain areas of
the board. A minimum etch technique is generally best for ground
planes because it results in the best shielding.
In any layout, the user must keep in mind the flow of currents
in the system, ensuring that the paths for all return currents are
as close as possible to the paths the currents took to reach their
destinations.
Place the decoupling capacitors as close to the package as possible (ideally directly against the device).
Avoid running digital lines under the device because this couples
noise onto the die and allows the analog ground plane to run under
the AD4130-8 to prevent noise coupling. The power supply lines
to the AD4130-8 must use as wide a trace as possible to provide
low impedance paths and reduce glitches on the power supply
line. Shield fast switching signals like clocks with digital ground to
prevent radiating noise to other sections of the board and never
run clock signals near the analog inputs. Avoid crossover of digital
and analog signals. Run traces on opposite sides of the board at
right angles to each other. This reduces the effects of feedthrough
on the board. A microstrip technique is by far the best but is
not always possible with a double-sided board. In this technique,
the component side of the board is dedicated to ground planes,
whereas signals are placed on the solder side.
If using the AD4130-8 with split supply operation, a separate plane
must be used for AVSS.
ASSEMBLY GUIDELINES
For the WLCSP, heat is transferred through the solder balls to the
PCB. Thermal impedance is dependent on PCB construction. More
copper layers and ground via enable heat to be removed more
effectively.
The PCB level reliability of the device is directly linked to the PCB
type and design used. Using a PCB material that matches the
coefficient of thermal expansion (CTE) of the silicon (for example,
ceramic) provides the optimal mechanical performance. For organic
material PCBs (for example, FR4) where the CTE is different from
that of the silicon, the use of underfill can increase the mechanical
performance. For organic PCB thickness >0.8 mm, consider using
underfill. Particular attention must be given to the underfill material
selection to match the material properties with the application use
conditions.
Consider using low alpha material in the system assembly to
reduce the soft error rate (SER).
The AN-617 Application Note provides information on PCB layout
and assembly for the WLCSP.
Rev. 0 | 77 of 108
Data Sheet
AD4130-8
AD4130-8 REGISTERS
The AD4130-8 has programmable user configuration registers that are used to configure the device. Table 71 contains the complete list of the
AD4130-8 user configuration registers. Table 71 shows a complete list of the user configuration registers. See the AD4130-8 Register Summary
and Registers Details sections for details about the functions of each of the bits. The access column specifies whether the register comprises
only read-only bits (R) or a mix of read only and read/write bits (R/W). Read-only bits cannot be overwritten by an SPI write transaction,
whereas read/write bits can. Table 71 also shows if each register is a single byte or multibyte register. See the Digital Interface section for a
detailed description of how to communicate with the AD4130-8.
Table 71. User Configuration Register Names and Descriptions1
Address
Name
Description
Length
Reset
Access
N/A2
COMMS
STATUS
ADC_CONTROL
DATA
IO_CONTROL
VBIAS_CONTROL
ID
ERROR
ERROR_EN
MCLK_COUNT
CHANNEL_m (m = 0 to 15)
CONFIG_n (n = 0 to 7)
FILTER_n (n = 0 to 7)
OFFSET_n (n = 0 to 7)
GAIN_n (n = 0 to 7)
MISC
FIFO_CONTROL
FIFO_STATUS
FIFO_THRESHOLD
FIFO_DATA
Communication register
Status register
ADC control register
Data register
Input/output control register
VBIAS control register
Identification register
Error register
Error enable register
MCLK count register
Channel m configuration registers
Configuration registers (ADC Setup n)
Filter configuration registers (ADCs Setup n)
Offset registers (ADC Setup n)
Gain registers (ADC Setup n)
Miscellaneous register
FIFO control register
FIFO status register
FIFO threshold register
FIFO data register
Single byte
Single byte
Two bytes
Three bytes
Two bytes
Two bytes
Single byte
Two bytes
Two bytes
Single byte
Three bytes
Two bytes
Three bytes
Three bytes
Three bytes
Two bytes
Three bytes
Single byte
Three bytes
Three bytes
N/A
0x10
0x4000
0x000000
0x0000
0x0000
0x04
0x0000
0x0040
0x00
0xXXXXXX3
0x0000
0x002030
0x800000
0xXXXXXX4
0x0000
0x040200
0x01
0xFFF000
0x000000
W
R
R/W
R
R/W
R/W
R
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09 to 0x18 by 1
0x19 to 0x20 by 1
0x21 to 0x28 by 1
0x29 to 0x30 by 1
0x31 to 0x38 by 1
0x39
0x3A
0x3B
0x3C
0x3D
1
Blank cells are not applicable.
2
N/A means not applicable.
3
CHANNEL_0 default value is 0x800100. All other channels default value is 0x000100.
4
Nominal value: 0x555555. The AD4130-8 is factory calibrated at ambient temperature and with a gain of 1 and PGA_BYP_n = 0, and the resulting gain coefficient is loaded
to the GAIN_n registers of the device as default value.
AD4130-8 REGISTER SUMMARY
Table 72. User Configuration Register Summary1
Addr. Name
Bits
Bit 7
Bit 6
N/A2
COMMS
[7:0]
WEN
R/W
0x00
STATUS
[7:0]
RDY
MASTER_ERR
RESERVED
0x01
ADC_CON
TROL
[15:8]
RESERVED
BIPOLAR
INT_REF_VA DOUT_DIS_ CONT_REA DATA_STADEL
L
D
TUS
[7:0]
RESERVED
DUTY_CY
C_RATIO
MODE
0x02
DATA
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Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RS[5:0]
POR_FLAG
[23:16]
DATA[23:16]
[15:8]
DATA[15:8]
[7:0]
DATA[7:0]
CH_ACTIVE
CSB_EN
INT_REF_
EN
Reset
R/W
N/A
W
0x10
R
0x4000
R/W
0x000000
R
CLK_SEL
Rev. 0 | 78 of 108
Data Sheet
AD4130-8
AD4130-8 REGISTERS
Table 72. User Configuration Register Summary1
Addr. Name
0x03
Bits
0x04
VBIAS_CO [15:8]
NTROL
0x05
ID
[7:0]
0x06
ERROR
[15:8]
[7:0]
[7:0]
ERROR_EN
0x09
to
0x18
MCLK_CO
UNT
CHANNEL
_m (m = 0
to 15)
VBIAS_12
VBIAS_11
VBIAS_10
VBIAS_9
VBIAS_8
VBIAS_7
VBIAS_6
VBIAS_5
VBIAS_4
VBIAS_3
VBIAS_2
VBIAS_1
VBIAS_0
RESERVED
MISC
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MODEL_ID
AINP_OV_U
V_ERR
SPI_IGNO SPI_SCLK_C SPI_READ_ SPI_WRITE
RE_ERR
NT_ERR
ERR
_ERR
MCLK_CNT AINP_OV_U
RESERVED
_EN
V_ERR_EN
AINM_OV_U
V_ERR
SPI_CRC_E
RR
AINM_OV_U
V_ERR_EN
ADC_ERR_E SPI_IGNO SPI_SCLK_C SPI_READ_ SPI_WRITE
RE_ERR_E NT_ERR_EN ERR_EN
_ERR_EN
N
N
SPI_CRC_E
RR_EN
ADC_ERR
[23:16] ENABLE_m
SETUP_m
PDSW_m
R/W
0x0000
R/W
0x0X3
R
REF_DETE 0x0000
CT_ERR
ROM_CRC
_ERR
REF_DETE 0x0040
CT_ERR_E
N
MM_CRC_E ROM_CRC
RR_EN
_ERR_EN
THRES_EN_
m
I_OUT1_CH_m
[23:16]
0x0000
R/W
R/W
R
AINP_m[4:3]
0xXXXXXX4 R/W
BURNOUT_n
0x0000
R/W
0x002030
R/W
0x800000
R/W
AINM_m
I_OUT0_CH_m
I_OUT1_n
REF_BUF
M_n
R/W
0x00
AINP_m[2:0]
REF_BUFP_
n
Reset
REF_OV_UV
_ERR
MM_CRC_E
RR
REF_OV_UV
_ERR_EN
MCLK_COUNT
I_OUT0_n
REF_SEL_n
PGA_n
SETTLE_n
PGA_BYP_
n
REPEAT_n
FILTER_MODE_n
RESERVED
FS_n[10:8]
FS_n[7:0]
OFFSET_n[23:16]
[15:8]
OFFSET_n[15:8]
[7:0]
OFFSET_n[7:0]
[23:16]
GAIN_n[23:16]
[15:8]
GAIN_n[15:8]
[7:0]
0x39
SILICON_ID
RESERVED
OFFSET_n [23:16]
(n = 0 to 7)
GAIN_n (n
= 0 to 7)
INT_PIN_SEL
VBIAS_13
[7:0]
0x31
to
0x38
Bit 0
VBIAS_14
[15:8]
0x29
to
0x30
Bit 1
VBIAS_15
CONFIG_n [15:8]
(n = 0 to 7)
FILTER_n
(n = 0 to 7)
Bit 2
SYNCB_CLE
AR
[7:0]
[7:0]
Bit 3
GPO_CTRL GPO_CTRL_ GPO_CTRL
_P3
P2
_P1
[7:0]
0x21
to
0x28
Bit 4
GPO_DATA GPO_DATA_ GPO_DATA GPO_DATA_ GPO_CTRL
_P4
P3
_P2
P1
_P4
[15:8]
0x19
to
0x20
Bit 5
RESERVED
[15:8]
[7:0]
0x08
Bit 6
IO_CONTR [15:8]
OL
[7:0]
0x07
Bit 7
0xXXXXXX5 R/W
GAIN_n[7:0]
[15:8]
RESERVED
PD_ALDO
[7:0]
STBY_DIAG
NOSTICS_E
N
STBY_GP
O_EN
CAL_RANGE
_X2
STBY_PDSW STBY_BUR
_EN
NOUT_EN
RESERVED
STBY_VBIA STBY_IEXC
S_EN
_EN
STBY_OUT 0x0000
_EN
STBY_REFH STBY_INT
OL_EN
REF_EN
R/W
Rev. 0 | 79 of 108
Data Sheet
AD4130-8
AD4130-8 REGISTERS
Table 72. User Configuration Register Summary1
Addr. Name
0x3A
Bits
Bit 7
Bit 6
FIFO_CON [23:16]
TROL
[15:8]
Bit 5
0x3C
RESERVED
FIFO_WRI
TE_ERR_I
NT_EN
ADD_FIFO_
STATUS
FIFO_READ_ THRES_HI THRES_LO
ERR_INT_EN GH_INT_EN W_INT_EN
FIFO_READ_ THRES_HI
ERR
GH_FLAG
1
THRES_LO
W_FLAG
Bit 1
Bit 0
Reset
R/W
ADD_FIFO_
FIFO_MODE
0x040200
HEADER
OVERRUN_I WATERMAR EMPTY_IN
NT_EN
K_INT_EN
T_EN
R/W
OVERRUN_
FLAG
R
WATERMAR EMPTY_FL 0x01
K_FLAG
AG
THRES_HIGH_VAL[11:4]
THRES_HIGH_VAL[3:0]
[7:0]
FIFO_DATA
Bit 2
WATERMARK
FIFO_STAT [7:0]
MASTER_ER FIFO_WRI
US
R
TE_ERR
FIFO_THR [23:16]
ESHOLD
[15:8]
0x3D
Bit 3
RESERVED
[7:0]
0x3B
Bit 4
0xFFF000
R/W
0x000000
R
THRES_LOW_VAL[11:8]
THRES_LOW_VAL[7:0]
[23:16]
FIFO_DATA[23:16]
[15:8]
FIFO_DATA[15:8]
[7:0]
FIFO_DATA[7:0]
Blank cells are not applicable.
2
N/A means not applicable.
3
See Identification Register section for details.
4
CHANNEL_0 default value is 0x800100. All other channels default value is 0x000100.
5
Nominal value: 0x555555. The AD4130-8 is factory calibrated at ambient temperature and with a Gain of 1 and PGA_BYP_n = 0, and the resulting gain coefficient is loaded
to the GAIN_n registers of the device as default value.
REGISTERS DETAILS
Communication Register
Address: N/A, Reset: 0x10, Name: COMMS
All communications to the device must start with a write operation to the communications register.
Table 73. Bit Descriptions for COMMS Register
Bits
Bit Name
7
WEN
Settings
Description
Write Enable Bit. A 0 must be written to this bit so that the write to the communications register occurs. If a 1 is the first bit written, the
device does not clock on to subsequent bits in the register. It stays at this bit location until a 0 is written to this bit. As soon as a 0 is
written to the WEN bit, the next seven bits are loaded to the communications register.
0 Communication Allowed.
1 No Communication Allowed.
6
R/W
A 0 in this bit location indicates that the next operation is a write to a specified register. A 1 in this position indicates that the next
operation is a read from the designated register.
0 Write Operation.
1 Read Operation.
5:0
RS[5:0]
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Register address bits. These address bits select which registers of the device are being selected during this serial interface
communication. See Table 72 for a list of all registers and relative addresses.
Rev. 0 | 80 of 108
Data Sheet
AD4130-8
AD4130-8 REGISTERS
Status Register
Address: 0x00, Reset: 0x10, Name: STATUS
ADC and interface status information register.
Figure 108.
Table 74. Bit Descriptions for Status Register
Bits
Bit Name
7
RDYB
Settings
Description
Reset
Access
Active Low ADC Data Ready Indicator. The RDYB bit is used to indicate availability of ADC data.
Because the RDYB bit is treated as an interrupt event, when it is set to 0, the data ready pin goes low.
Conversely, the data ready pin automatically clears (goes high) when the RDYB bit is set to 1.
0x0
R
0x0
R
0 ADC Data Ready. The RDYB bit is set to 0 when the ADC writes a new result to the DATA register, or
in any ADC calibration mode when the ADC writes to the OFFSET_n and GAIN_n registers. The RDYB
bit is set back to 1 automatically by a read of the data register. A read of OFFSET_n register or GAIN_n
register does not affect this bit.
1 Data Not Ready. The RDYB bit is set to 1 to indicate that the ADC is placed into idle or standby mode,
to indicate a new calibration started, or to indicate that a new conversion started and new data is not
yet available. The RDYB bit is set to 1 in continuous conversion mode. Asserting the SYNC pin (taking
it low) also sets the RDYB bit to 1 if the data register is not read after a conversion result. The RDYB bit
is set to 1 four MCLK cycles before the next conversion result is written to indicate that the data register
is about to be updated, and therefore, is not read. If the data register is being read when an ADC result
is written, that write is aborted. There is no mixing of data values, but one ADC conversion is missed.
6
MASTER_ERR
Master Error Bit. This bit is set when any of the errors in the error register are set to 1. The
MASTER_ERR bit of the FIFO_STATUS register is also set to 1 when this MASTER_ERR bit is set to
1. This bit is automatically cleared once there are no errors in the error register.
0 No Error Detected.
1 Master Error Detected.
5
RESERVED
Reserved.
0x0
R
4
POR_FLAG
POR Event Detected Bit. A POR is triggered at power-up or when the IOVDD and/or digital LDO power
supply dips below the threshold value. This bit is set to 1 when a POR event occurs and is cleared
when the user reads the status register.
0x1
R
0x0
R
0 No POR Event Detected.
1 POR Event Detected.
[3:0]
CH_ACTIVE
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ADC Data Result Channel Indicator. These bits indicate which channel was active for the ADC conversion whose result is currently in the data register. This may be different from the channel currently
being converted. These values are a direct map from the CHANNEL_m register currently active.
CHANNEL_0 results in CH_ACTIVE = 0b0000 while CHANNEL_15 results in CH_ACTIVE = 0b1111.
Rev. 0 | 81 of 108
Data Sheet
AD4130-8
AD4130-8 REGISTERS
ADC Control Register
Address: 0x01, Reset: 0x4000, Name: ADC_CONTROL
Controls the operation mode of the ADC.
Figure 109.
Table 75. Bit Descriptions for ADC_CONTROL Register
Bits Bit Name
Settings
Description
Reset
Access
15
RESERVED
Reserved.
0x0
R
14
BIPOLAR
Bipolar Data Coding Enable Bit. Set the output coding of the ADC. This is a digital correction–the ADC
conversion is performed on a bipolar input span.
0x1
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0 Straight Binary (Unipolar) Coding. Input range: 0 V to VREF/gain.
VREF/gain: 0xFFFFFF
0: 0x000000
1 Offset Binary (Bipolar) Coding. Input range: −VREF/gain to VREF/gain
VREF/gain: 0xFFFFFF
0: 0x800000
−VREF/gain: 0x000000
13
INT_REF_VAL
Internal Reference Value Bit. Specifies the voltage of the internal precision reference. This bit must be
used in conjunction with the INT_REF_EN bit in this same register.
0 2.5 V.
1 1.25 V.
12
DOUT_DIS_DEL
DOUT Pin Disable Delay Bit. This bit controls the SCLK inactive edge to the DOUT pin disable time
when the CSB_EN bit is set to 0 in the ADC_CONTROL register.
0 Delay = 10 ns.
1 Delay = 100 ns.
11
CONT_READ
Continuous Read Mode Enable Bit. This bit enables the continuous read of the data register. In
continuous read mode, it is not required to write to the COMMS register before reading ADC data.
Instead, apply the required number of SCLKs after the data ready signal goes low. The data ready
signal acts as a framing signal during continuous read. SCLKs are ignored until the data ready signal
goes low. This means that each ADC result can be read once. In addition, if a read is still in progress
four MCLK cycles before the next conversion, the read is abandoned, and the data ready signal is
deasserted (set high). If CRC is active, it is possible to determine that a read is not valid. To exit
continuous read mode, issue a software reset command (64 1s) or write a read data command (0x42).
No CRC is required if CRC is enabled. This feature is disabled if the FIFO is enabled.
0 Continuous Read Mode Disabled.
1 Continuous Read Mode Enabled.
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Rev. 0 | 82 of 108
Data Sheet
AD4130-8
AD4130-8 REGISTERS
Table 75. Bit Descriptions for ADC_CONTROL Register
Bits Bit Name
10
DATA_STATUS
Settings
Description
Reset
Access
Data Status Enable Bit. When this bit is set to 1, the status register content is appended to the data
register output so that the channel status information is transmitted with the data. Thus, the format for
reading the data register becomes (DATA, Bits[23:0], STATUS, Bits[7:0]). This aids in identifying the
channel associated with the conversion being read in the data register, as well as correlate statuses
with the data being read.
0x0
R/W
0x0
R/W
0x0
R/W
0 Status Not Appended.
1 Status Appended to Data.
9
CSB_EN
CS Pin Enable Bit. This bit controls the CS pin functionality and the SPI mode.
0 CS Pin Functionality Disabled. SPI interface in 3-wire mode. The interface is reset on last rising edge
of SCLK. Therefore, when reading from the device, the DOUT pin is disabled on the last rising edge of
SCLK (assuming that data ready signal is configured to be sent out to the INT pin). This timing can be
changed via the DOUT_DIS_DEL bit in the ADC_CONTROL register. Attention must be paid to supply
the correct number of clocks for the appropriate register in a write or read command. Register sizes can
be 8-bit/16-bit/24-bit and enabling CRC and appending statuses in some cases also increases the data
width. The CS pin must be tied low to keep the DOUT pin enabled. The CS pin can still be held high to
tristate the DOUT pin.
1 CS Pin Functionality Enabled. SPI interface in 4-wire mode. The interface is reset on the rising edge
of CS. Therefore, when reading from the device, the DOUT pin switches from data output functionality
to data ready interrupt functionality on the rising edge of CS (assuming that the data ready signal
is configured to be sent out to the DOUT pin). The user can enable the SPI_WRITE_ERR bit,
SPI_READ_ERR bit, and SPI_SCLK_CNT_ERR bit, as these are only valid when CS is enabled. When
CS is high, the DOUT pin is tristated.
8
INT_REF_EN
Internal Reference Enable Bit. When the internal precision reference is enabled, the value seen at the
REFOUT pin depends on the setting of INT_REF_VAL bit in this same register.
0 Internal Reference Disabled (Default).
1 Internal Reference Enabled.
7
RESERVED
Reserved.
0x0
R
6
DUTY_CYC_RATIO
Duty Cycle Ratio Bit. This bit controls the ratio for which the device is in standby. Duty cycling mode
uses the conversion time of all active channels (disregarding digital postprocessing time and wake-up
time) as time reference for active time, and the standby time is derived as multiples of that. For this bit
to be effective, the MODE bitfield in this register must be set to duty cycling mode (0b1001).
0x0
R/W
0x0
R/W
0 1/4 Duty Cycle. The device is active 1/4 of the time and in standby for 3/4 of the time.
1 1/16 Duty Cycle. The device is active 1/16 of the time and in standby for 15/16 of the time.
[5:2] MODE
Control the Mode of Operation for ADC.
0000 Continuous Conversion Mode.
0001 Single Sequence Mode.
0010 Standby Mode.
0011 Power-Down Mode. To go to power-down mode, the device must be in standby mode. Otherwise, the
device goes to continuous conversion mode. This procedure serves as a safety feature to prevent
accidental/unwanted transitions to power-down mode.
0100 Idle Mode. The digital filter and the modulator are held in reset. There is no change to anything else.
0101 Internal Offset Calibration (Zero Scale). The device returns to idle mode once calibration is completed.
0110 Internal Gain Calibration (Full Scale). The device returns to idle mode once calibration is completed.
0111 System Offset Calibration (Zero Scale). The device returns to idle mode once calibration is completed.
1000 System Gain Calibration (Full Scale). The device returns to idle mode once calibration is completed.
1001 Duty Cycling Mode. The device cycles between converting the selected sequence and standby based
on the DUTY_CYC_RATIO bit in this register.
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Rev. 0 | 83 of 108
Data Sheet
AD4130-8
AD4130-8 REGISTERS
Table 75. Bit Descriptions for ADC_CONTROL Register
Bits Bit Name
Settings
Description
Reset
Access
0x0
R/W
1010 Single Sequence + idle by SYNC Mode. The device cycles between converting the selected sequence
and idle mode based on the SYNC pin pulses from high to low.
1011 Single Sequence + STBY by SYNC Mode. The device cycles between converting the selected
sequence and standby based on the SYNC pin pulses from high to low.
1100 to 1111 Reserved.
[1:0] MCLK_SEL
Master Clock Selection Bits.
00 Internal 76.8 kHz–Output Off. Internal clock used as clock source, but not available at the CLK pin.
01 Internal 76.8 kHz–Output On. Internal clock used as clock source, and available at the CLK pin.
10 External 76.8 kHz. External CLK pin used as clock source.
11 External 153.6 kHz. External CLK pin used as clock source after being divided by 2 internally.
ADC Conversion Result Register
Address: 0x02, Reset: 0x000000, Name: DATA
Stores latest ADC result.
Figure 110.
Table 76. Bit Descriptions for DATA Register
Bits
Bit Name
[23:0]
DATA
Settings
Description
Reset
Access
ADC Conversion Result. This register contains the result of the latest ADC conversion.
0x0
R
Input/Output Control Register
Address: 0x03, Reset: 0x0000, Name: IO_CONTROL
Controls some of the input/output ports.
Figure 111.
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Rev. 0 | 84 of 108
Data Sheet
AD4130-8
AD4130-8 REGISTERS
Table 77. Bit Descriptions for IO_CONTROL Register
Bits
Bit Name
[15:11]
RESERVED
10
SYNCB_CLEAR
Settings
Description
Reset
Access
Reserved.
0x0
R
SYNC Clear Bit. This bit allows clearing the FIFO via the SYNC pin pulse.
0x0
R/W
0x0
R/W
0 Disabled. Clearing of FIFO contents via SYNC is disabled.
1 Enabled. Clearing of FIFO contents via SYNC is enabled.
[9:8]
INT_PIN_SEL
Data Ready/FIFO Interrupt Pin Selection Bits. These bits select what pin the Data ready/FIFO
interrupt signal is sent to. When the FIFO is disabled, the data ready signal acts as the
interrupt event. Otherwise, the FIFO interrupt event is determined by the configuration of the
FIFO_CONTROL register.
00 INT Pin. The data ready/FIFO interrupt signal is sent to the INT pin.
01 CLK Pin. The data ready/FIFO interrupt signal is sent to the CLK pin. This setting takes priority on
the CLK_SEL bit setting in the ADC_CONTROL register.
10 P2 (AIN3) Pin. The data ready/FIFO interrupt signal is sent to the P2 pin. This setting takes priority
on the GPO_CTRL_P2 bit of the IO_CONTROL register.
11 DOUT Pin (FIFO Disabled). The data ready signal is sent to the DOUT pin. This option is unused
for the FIFO interrupt signal.
7
GPO_DATA_P4
Data Driven to P4. When the pin is configured as an output in GPO_CTRL_P4.
0x0
R/W
6
GPO_DATA_P3
Data Driven to P3. When the pin is configured as an output in GPO_CTRL_P3.
0x0
R/W
5
GPO_DATA_P2
Data Driven to P2. When the pin is configured as an output in GPO_CTRL_P2.
0x0
R/W
4
GPO_DATA_P1
Data Driven to P1. When the pin is configured as an output in GPO_CTRL_P1.
0x0
R/W
3
GPO_CTRL_P4
Controls Whether AIN5 is Input or Output (P4). Functions as standby pin (via the STBY_OUT_EN
bit in the MISC register) and takes highest priority and overrides its other functions.
0x0
R/W
0x0
R/W
Controls Whether AIN3 is Input or Output (P2). Functions as an interrupt pin (via the INT_PIN_SEL 0x0
bit of the IO_CONTROL Register) and takes highest priority and overrides its other functions.
R/W
0 GPIO Has Specific Input Function.
1 GPIO Functions as Output.
2
GPO_CTRL_P3
Controls Whether AIN4 is Input or Output (P3).
0 GPIO Has Specific Input Function.
1 GPIO Functions as Output.
1
GPO_CTRL_P2
0 GPIO Has Specific Input Function.
1 GPIO Functions as Output.
0
GPO_CTRL_P1
Controls Whether AIN2 is Input or Output (P1).
0x0
R/W
0 GPIO Has Specific Input Function.
1 GPIO Functions as Output.
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Rev. 0 | 85 of 108
Data Sheet
AD4130-8
AD4130-8 REGISTERS
VBIAS Control Register
Address: 0x04, Reset: 0x0000, Name: VBIAS_CONTROL
Select output VBIAS on the analog input pins.
Figure 112.
Table 78. Bit Descriptions for VBIAS_CONTROL Register
Bits
Bit Name
15
VBIAS_15
Settings
Description
Reset
Access
Enable/Disable VBIAS for AIN15.
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0 VBIAS Disabled on This Pin.
1 VBIAS Enabled on This Pin.
14
VBIAS_14
Enable/Disable VBIAS for AIN14.
0 VBIAS Disabled on This Pin.
1 VBIAS Enabled on This Pin.
13
VBIAS_13
Enable/Disable VBIAS for AIN13.
0 VBIAS Disabled on This Pin.
1 VBIAS Enabled on This Pin.
12
VBIAS_12
Enable/Disable VBIAS for AIN12.
0 VBIAS Disabled on This Pin.
1 VBIAS Enabled on This Pin.
11
VBIAS_11
Enable/Disable VBIAS on AIN11.
0 VBIAS Disabled on This Pin.
1 VBIAS Enabled on This Pin.
10
VBIAS_10
Enable/Disable VBIAS on AIN10.
0 VBIAS Disabled on This Pin.
1 VBIAS Enabled on This Pin.
9
VBIAS_9
Enable/Disable VBIAS on AIN9.
0 VBIAS Disabled on This Pin.
1 VBIAS Enabled on This Pin.
8
VBIAS_8
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Enable/Disable VBIAS on AIN8.
Rev. 0 | 86 of 108
Data Sheet
AD4130-8
AD4130-8 REGISTERS
Table 78. Bit Descriptions for VBIAS_CONTROL Register
Bits
Bit Name
Settings
Description
Reset
Access
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0 VBIAS Disabled on This Pin.
1 VBIAS Enabled on This Pin.
7
VBIAS_7
Enable/Disable VBIAS on AIN7.
0 VBIAS Disabled on This Pin.
1 VBIAS Enabled on This Pin.
6
VBIAS_6
Enable/Disable VBIAS on AIN6.
0 VBIAS Disabled on This Pin.
1 VBIAS Enabled on This Pin.
5
VBIAS_5
Enable/Disable VBIAS on AIN5.
0 VBIAS Disabled on This Pin.
1 VBIAS Enabled on This Pin.
4
VBIAS_4
Enable/Disable VBIAS on AIN4.
0 VBIAS Disabled on This Pin.
1 VBIAS Enabled on This Pin.
3
VBIAS_3
Enable/Disable VBIAS on AIN3.
0 VBIAS Disabled on This Pin.
1 VBIAS Enabled on This Pin.
2
VBIAS_2
Enable/Disable VBIAS on AIN2.
0 VBIAS Disabled on This Pin.
1 VBIAS Enabled on This Pin.
1
VBIAS_1
Enable/Disable VBIAS on AIN1.
0 VBIAS Disabled on This Pin.
1 VBIAS Enabled on This Pin.
0
VBIAS_0
Enable/Disable VBIAS on AIN0.
0 VBIAS Disabled on This Pin.
1 VBIAS Enabled on This Pin.
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Rev. 0 | 87 of 108
Data Sheet
AD4130-8
AD4130-8 REGISTERS
Identification Register
Address: 0x05, Reset: 0x04, Name: ID
Returns an 8-bit ID of the device.
Figure 113.
Table 79. Bit Descriptions for ID Register
Bits
Bit Name
[7:4]
RESERVED
[3:2]
SILICON_ID
[1:0]
MODEL_ID
Settings
Description
Reset
Access
Reserved.
0x0
R
Silicon ID.
0x1
R
0x0
R
00 24-Bit WLCSP Model ID. These bits are set by default for each model and are read only.
Error Register
Address: 0x06, Reset: 0x0000, Name: ERROR
Each error bit in this register must be enabled in the ERROR_EN register to work as expected. All bits in this register are R/W1C.
Figure 114.
Table 80. Bit Descriptions for ERROR Register
Bits
Bit Name
Settings
Description
Reset
Access
[15:12]
RESERVED
Reserved.
0x0
R
11
AINP_OV_UV_ERR
AINP Overvoltage and/or Undervoltage Error Flag. When set, this bit indicates that an
overvoltage and/or undervoltage error on AINP is detected. Enable this error flag in the
ERROR_EN register.
0x0
R/W1C
0 No Error Detected.
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Data Sheet
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AD4130-8 REGISTERS
Table 80. Bit Descriptions for ERROR Register
Bits
Bit Name
Settings
Description
Reset
Access
0x0
R/W1C
External Reference Overvoltage and/or Undervoltage Error Flag. When set, this bit indicates 0x0
that an overvoltage and/or undervoltage is detected on the external reference. Enable this
error flag in the ERROR_EN register.
R/W1C
1 AINP OV/UV Error Detected.
10
AINM_OV_UV_ERR
AINM Overvoltage and/or Undervoltage Error Flag. When set, this bit indicates that an
overvoltage and/or undervoltage error on AINM is detected. Enable this error flag in the
ERROR_EN register.
0 No Error Detected.
1 AINM OV/UV Error Detected.
9
REF_OV_UV_ERR
0 No Error Detected.
1 REFIN OV/UV Error Detected.
8
REF_DETECT_ERR
External Reference Detection Error Flag. When set, this bit indicates that the external
reference voltage (REFINx(+) – REFINx(−)) is less than the threshold. Enable this error flag
in the ERROR_EN register.
0x0
R/W1C
0x0
R/W1C
0x0
R/W1C
0x0
R/W1C
SPI Read Error Flag. When set, this bit indicates that an SPI read is performed on an invalid 0x0
address. Enable this error flag in the ERROR_EN register.
R/W1C
0 No Error Detected.
1 REFIN Error Detected.
7
ADC_ERR
ADC Error Flag. This error sets when one of the following ADC conversion/calibration errors
is detected: ADC conversion result is clamped at positive full scale; ADC conversion result
is clamped at negative full scale; ADC offset/gain calibration result outside specified range;
modulator is in saturation. Enable this error flag in the ERROR_EN register.
0 No Error Detected.
1 ADC Error Detected.
6
SPI_IGNORE_ERR
SPI Ignore Error Flag. When set, this bit indicates that an SPI access is made at a time
when it is ignored (such as while the ROM content is being downloaded). Enable this error
flag in the ERROR_EN register.
0 No Error Detected.
1 SPI Error Detected.
5
SPI_SCLK_CNT_ERR
SPI SCLK Count Error Flag. When set, this bit indicates that the SCLKs on a given SPI
frame are not multiples of eight. Enable this error flag in the ERROR_EN register.
0 No Error Detected.
1 SCLK Count Error Detected.
4
SPI_READ_ERR
0 No Error Detected.
1 SPI Read Error Detected.
3
SPI_WRITE_ERR
SPI Write Error Flag. When set, this bit indicates that an SPI write is performed on an invalid 0x0
address. Enable this error flag in the ERROR_EN register.
R/W1C
0 No Error Detected.
1 SPI Write Error Detected.
2
SPI_CRC_ERR
SPI CRC Error Flag. When set, this bit indicates that a CRC error on the SPI communication 0x0
is detected. Enable this error flag in the ERROR_EN register.
R/W1C
0 No Error Detected.
1 SPI CRC Error Detected.
1
MM_CRC_ERR
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Memory Map CRC Error Flag. When this error is enabled, periodic CRC checks on the
memory map are performed. When set, this bit indicates that a change in the memory
map contents (without actual writes) is detected. Enable this error flag in the ERROR_EN
register.
0x0
R/W1C
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Data Sheet
AD4130-8
AD4130-8 REGISTERS
Table 80. Bit Descriptions for ERROR Register
Bits
Bit Name
Settings
Description
Reset
Access
0 No Error Detected.
1 Memory Map CRC Error Detected.
0
ROM_CRC_ERR
ROM CRC Error Flag. A CRC calculation is performed on the ROM contents upon power-up. 0x0
When set, this bit indicates that the ROM contents changed. Enable this error flag in the
ERROR_EN register.
R/W1C
0 No Error Detected.
1 ROM CRC Error Detected.
Error Enable Register
Address: 0x07, Reset: 0x0040, Name: ERROR_EN
Each bit in this register enables a flag in the error register.
Figure 115.
Table 81. Bit Descriptions for ERROR_EN Register
Bits
Bit Name
[15:13]
12
Settings
Description
Reset
Access
RESERVED
Reserved.
0x0
R
MCLK_CNT_EN
MCLK Counter Enable Bit. The counter value is reported via the MCLK_COUNT
register.
0x0
R/W
AINP Overvoltage and/or Undervoltage Error Enable Bit. When set to 1, this bit enables 0x0
the AINP overvoltage error seen in the error register.
R/W
0 MCLK Counter Disabled.
1 MCLK Counter Enabled.
11
AINP_OV_UV_ERR_EN
0 AINP OV/UV Error Disabled.
1 AINP OV/UV Error Enabled.
10
AINM_OV_UV_ERR_EN
AINM Overvoltage and/or Undervoltage Error Enable Bit. When set to 1, this bit enables 0x0
the AINM overvoltage/undervoltage error seen in the error register.
R/W
0 AINM OV/UV Error Disabled.
1 AINM OV/UV Error Enabled.
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Data Sheet
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AD4130-8 REGISTERS
Table 81. Bit Descriptions for ERROR_EN Register
Bits
Bit Name
9
REF_OV_UV_ERR_EN
Settings
Description
Reset
Access
External Reference Overvoltage and/or Undervoltage Error Enable Bit. When set to 1,
this bit enables the external reference overvoltage/undervoltage error seen in the error
register.
0x0
R/W
External Reference Detect Error Enable Bit. When set to 1, this bit enables the external 0x0
reference error seen in the error register.
R/W
0 REFIN OV/UV Error Disabled.
1 REFIN OV/UV Error Enabled.
8
REF_DETECT_ERR_EN
0 REFIN Error Disabled.
1 REFIN Error Enabled.
7
ADC_ERR_EN
ADC Conversion/Calibration Checks Enable Bit. When set to 1, this bit enables
ADC_ERR seen in the error register.
0x0
R/W
SPI Ignore Error Check Enable Bit. Enabled by default. The error is reported via the
0x1
SPI_IGNORE_ERR in the error register. An error is flagged if the user writes to the
memory map during power-up while fuses are copied across, or if the user writes to the
memory map while offset or gain calibration is performed.
R/W
0 ADC Error Disabled.
1 ADC Error Enabled.
6
SPI_IGNORE_ERR_EN
0 SPI Ignore Error Disabled.
1 SPI Ignore Error Enabled.
5
SPI_SCLK_CNT_ERR_EN
SPI SCLK Count Check Enable Bit. To enable this function, CSB_EN must also be set
to 1 in ADC_CONTROL. The SPI SCLK counter counts the number of SCLK pulses
used in each read and write operation. CS must frame every read and write operation
when this function is used. All read and write operations are multiples of eight SCLK
pulses. If the SCLK counter counts the SCLK pulses and the result is not a multiple of
eight, an error is flagged; the SPI_SCLK_CNT_ERR bit in the error register is set. If a
write operation is performed, and the SCLK contains an insufficient number of SCLK
pulses, the value is not written to the addressed register and the write operation is
aborted.
0x0
R/W
SPI Read Error Check Enable Bit. To enable this function, CSB_EN must also be set
0x0
to 1 in ADC_CONTROL. The error is reported via SPI_READ_ERR in the error register.
The SPI_READ_ERR bit is flagged if the user attempts to read an invalid address.
R/W
0 SPI SCLK Error Disabled.
1 SPI SCLK Error Enabled.
4
SPI_READ_ERR_EN
0 SPI Read Error Disabled.
1 SPI Read Error Enabled.
3
SPI_WRITE_ERR_EN
SPI Write Error Check Enable Bit. To enable this function, CSB_EN must also be a 1
in ADC_CONTROL. The error is reported via SPI_WRITE_ERR in the error register.
The SPI_WRITE_ERR bit is flagged if the user attempts to write to either an invalid or
read-only address.
0x0
R/W
0x0
R/W
0 SPI Write Error Disabled.
1 SPI Write Error Enabled.
2
SPI_CRC_ERR_EN
SPI CRC Error Check Enable Bit. Using the checksum ensures that only valid data is
written to a register and allows data read from a register to be validated. If an error
occurs during a register write, the CRC_ERR bit is set in the error register. However,
to ensure that the register write is successful, read back the register and verify the
checksum.
0 SPI CRC Check is Disabled.
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Data Sheet
AD4130-8
AD4130-8 REGISTERS
Table 81. Bit Descriptions for ERROR_EN Register
Bits
Bit Name
Settings
Description
Reset
Access
0x0
R/W
ROM ECC/CRC Check Enable Bit. ROM CRC is always performed on power-up and
0x0
this bit enables reporting of error. The error is reported via ROM_CRC_ERR in the error
register.
R/W
1 SPI CRC Check is Enabled.
1
MM_CRC_ERR_EN
Dynamic CRC Check of Memory Map Enable Bit. The error is reported via
MM_CRC_ERR in the error register. Memory map CRC is performed on all memory map contents except for read-only registers (for example, status, data, and
MCLK_COUNT). The CRC is performed every 426.6 μs (2.4 kHz). Any future memory
write to memory map recalculates CRC. This happens for following cases: user write;
offset/gain calibration; when the MODE bits change from single sequence to idle at the
end of single sequence mode conversions; when exiting continuous read mode, the
CONT_READ bit changes to 0 in ADC_CONTROL.
0 MM CRC Check Disabled.
1 MM CRC Check Enabled.
0
ROM_CRC_ERR_EN
0 ROM CRC/ECC Check Disabled.
1 ROM CRC/ECC Check Enabled.
MCLK Counter Register
Address: 0x08, Reset: 0x00, Name: MCLK_COUNT
Returns the MCLK count value when functionality is enabled.
Figure 116.
Table 82. Bit Descriptions for MCLK_COUNT Register
Bits
Bit Name
[7:0]
MCLK_COUNT
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Settings
Description
Reset
Access
MCLK Counter Value. This register allows the user to determine the frequency of the internal/external oscillator. Internally a clock counter increments every 131 pulses of the master clock
(fMCLK = 76.8 kHz), giving it an update rate of 586.26 Hz. The 8‑bit counter wraps around on
reaching its maximum value. Enable the MCLK counter functionality using the MCLK_CNT_EN bit in
the ERROR_EN register.
0x00
R
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Data Sheet
AD4130-8
AD4130-8 REGISTERS
Channel m Configuration Registers (m = 0 to 15)
Address: 0x09 to 0x18 (in Increments of 1), Reset: 0x800100 (CHANNEL_0), 0x000100 (All Other Channels), Name: CHANNEL_m
(m = 0 to 15)
These registers allow the user to enable channels in the automated sequence, select plus and minus inputs, determine the availability of
excitation currents on specific inputs, and enable thresholds for the FIFO. They also allow the user to select the ADC Setup n associated with
each channel. An ADC setup is made up of configuration, filter, offset, and gain registers.
Figure 117.
Table 83. Bit Descriptions for CHANNEL_m Registers
Bits
Bit Name
23
ENABLE_m
Settings
Description
Reset
Access
Enable Bit for Channel m. This bit enables the relative channel to take part in the sequence. 0x1 (CHANNEL_0)
By default, only the ENABLE_0 bit for CHANNEL_0 is set to 1, and all the other ENABLE_m 0x0 (CHANNEL_m)
bits are set to 0. The order of conversions starts with the lowest enabled channel, then cycles
through successively higher channel numbers, before wrapping around to the lowest channel
again. When the ADC writes a result for a particular channel, the four LSBs of the status
register are set to the channel number (range: 0 to 15). This allows the user to identify the
channel that corresponds to the data being read.
R/W
0 Channel Disabled.
1 Channel Enabled.
[22:20]
SETUP_m
ADC Setup Select Bits for Channel m. An ADC setup comprises a set of four corresponding
registers: (CONFIG_n, FILTER_n, OFFSET_n, and GAIN_n). For example, if a channel has
a SETUP_m value of 0, its settings come from CONFIG_0, FILTER_0, OFFSET_0, and
GAIN_0. All channels can use the same setup, in which case the same 3-bit value is written
to these bits on all active channels, or up to eight channels can be configured differently.
0x0
R/W
0 ADC Setup 0. CONFIG_0/FILTER_0/OFFSET_0/GAIN_0 configuration used to configure
ADC for this channel.
1 ADC Setup 1. CONFIG_1/FILTER_1/OFFSET_1/GAIN_1 configuration used to configure
ADC for this channel.
2 ADC Setup 2. CONFIG_2/FILTER_2/OFFSET_2/GAIN_2 configuration used to configure
ADC for this channel.
3 ADC Setup 3. CONFIG_3/FILTER_3/OFFSET_3/GAIN_3 configuration used to configure
ADC for this channel.
4 ADC Setup 4. CONFIG_4/FILTER_4/OFFSET_4/GAIN_4 configuration used to configure
ADC for this channel.
5 ADC Setup 5. CONFIG_5/FILTER_5/OFFSET_5/GAIN_5 configuration used to configure
ADC for this channel.
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Data Sheet
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AD4130-8 REGISTERS
Table 83. Bit Descriptions for CHANNEL_m Registers
Bits
Bit Name
Settings
Description
Reset
Access
6 ADC Setup 6. CONFIG_6/FILTER_6/OFFSET_6/GAIN_6 configuration used to configure
ADC for this channel.
7 ADC Setup 7. CONFIG_7/FILTER_7/OFFSET_7/GAIN_7 configuration used to configure
ADC for this channel.
19
PDSW_m
Power-Down Switch Bit for Channel m. This bit enables the option to connect the PSW pin to 0x0
AVSS on a per-channel basis, except when the device is in power-down or standby mode. If
this bit is 1, the power-down switch is enabled for this channel, and anything connected to the
PSW pin is shorted to AVSS. In power-down mode, the switch is opened automatically (that
is, disabled). While the device is in standby mode, the functionality of this bit is disabled if the
STBY_PDSW_EN bit in the MISC register is set to 0.
R/W
0 Power-Down Switch Off. The power-down switch is always disabled for this channel.
1 Power-Down Switch On. This allows the PSW pin to sink current.
18
THRES_EN_m
FIFO Threshold Interrupt Enable Bit for Channel m. When this bit is set to 1, the conversion
0x0
data from this channel is monitored for threshold crossing per THRES_LOW_VAL and
THRES_HIGH_VAL of the FIFO_THRESHOLD register. This bit has no effect when the FIFO
is disabled.
R/W
[17:13]
AINP_m
Positive Analog Input Select for Channel m. These bits select which of the analog inputs is
connected to the positive input for this channel.
R/W
0x0
00000 AIN0.
00001 AIN1.
00010 AIN2.
00011 AIN3.
00100 AIN4.
00101 AIN5.
00110 AIN6.
00111 AIN7.
01000 AIN8.
01001 AIN9.
01010 AIN10.
01011 AIN11.
01100 AIN12.
01101 AIN13.
01110 AIN14.
01111 AIN15.
10000 Temperature Sensor.
10001 AVSS.
10010 Internal Reference.
10011 DGND.
10100 (AVDD − AVSS)/6+. Use in conjunction with (AVDD − AVSS)/6− to monitor supply AVDD − AVSS.
10101 (AVDD − AVSS)/6−. Use in conjunction with (AVDD − AVSS)/6+ to monitor supply AVDD − AVSS.
10110 (IOVDD − DGND)/6+. Use in conjunction with (IOVDD − DGND)/6− to monitor IOVDD − DGND.
10111 (IOVDD − DGND)/6−. Use in conjunction with (IOVDD − DGND)/6+ to monitor IOVDD − DGND.
11000 (ALDO − AVSS)/6+. Use in conjunction with (ALDO − AVSS)/6− to monitor the analog LDO.
11001 (ALDO − AVSS)/6−. Use in conjunction with (ALDO − AVSS)/6+ to monitor the analog LDO.
11010 (DLDO − DGND)/6+. Use in conjunction with (DLDO − DGND)/6− to monitor the digital LDO.
11011 (DLDO − DGND)/6−. Use in conjunction with (DLDO − DGND)/6+ to monitor the digital LDO.
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Data Sheet
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AD4130-8 REGISTERS
Table 83. Bit Descriptions for CHANNEL_m Registers
Bits
Bit Name
Settings
Description
Reset
Access
0x1
R/W
0x0
R/W
11100 V_MV_P. Use in conjunction with V_MV_M to apply a tens of mVP-P signal to the ADC.
11101 V_MV_M. Use in conjunction with V_MV_P to apply a tens of mVP-P signal to the ADC
11110 Reserved.
11111 Reserved.
[12:8]
AINM_m
Negative Analog Input Select for Channel m. These bits select which of the analog inputs is
connected to the negative input for this channel.
00000 AIN0.
00001 AIN1.
00010 AIN2.
00011 AIN3.
00100 AIN4.
00101 AIN5.
00110 AIN6.
00111 AIN7.
01000 AIN8.
01001 AIN9.
01010 AIN10.
01011 AIN11.
01100 AIN12.
01101 AIN13.
01110 AIN14.
01111 AIN15.
10000 Temperature Sensor.
10001 AVSS.
10010 Internal Reference.
10011 DGND.
10100 (AVDD − AVSS)/6+. Use in conjunction with (AVDD − AVSS)/6− to monitor supply AVDD − AVSS.
10101 (AVDD − AVSS)/6−. Use in conjunction with (AVDD − AVSS)/6+ to monitor supply AVDD − AVSS.
10110 (IOVDD − DGND)/6+. Use in conjunction with (IOVDD − DGND)/6− to monitor IOVDD − DGND.
10111 (IOVDD − DGND)/6−. Use in conjunction with (IOVDD − DGND)/6+ to monitor IOVDD − DGND.
11000 (ALDO − AVSS)/6+. Use in conjunction with (ALDO − AVSS)/6− to monitor the analog LDO.
11001 (ALDO − AVSS)/6−. Use in conjunction with (ALDO − AVSS)/6+ to monitor the analog LDO.
11010 (DLDO − DGND)/6+. Use in conjunction with (DLDO − DGND)/6− to monitor the digital LDO.
11011 (DLDO − DGND)/6−. Use in conjunction with (DLDO − DGND)/6+ to monitor the digital LDO.
11100 V_MV_P. Use in conjunction with V_MV_M to apply a tens of mVP-P signal to the ADC.
11101 V_MV_M. Use in conjunction with V_MV_P to apply a tens of mVP-P signal to the ADC.
11110 Reserved.
11111 Reserved.
[7:4]
I_OUT1_CH_m
Excitation Current 1 Selection for Channel m.
0000 I_OUT1 is available on AIN0.
0001 I_OUT1 is available on AIN1.
0010 I_OUT1 is available on AIN2.
0011 I_OUT1 is available on AIN3.
0100 I_OUT1 is available on AIN4.
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Data Sheet
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AD4130-8 REGISTERS
Table 83. Bit Descriptions for CHANNEL_m Registers
Bits
Bit Name
Settings
Description
Reset
Access
0x0
R/W
0101 I_OUT1 is available on AIN5.
0110 I_OUT1 is available on AIN6.
0111 I_OUT1 is available on AIN7.
1000 I_OUT1 is available on AIN8.
1001 I_OUT1 is available on AIN9.
1010 I_OUT1 is available on AIN10.
1011 I_OUT1 is available on AIN11.
1100 I_OUT1 is available on AIN12.
1101 I_OUT1 is available on AIN13.
1110 I_OUT1 is available on AIN14.
1111 I_OUT1 is available on AIN15.
[3:0]
I_OUT0_CH_m
Excitation Current 0 Selection for Channel m.
0000 I_OUT0 is available on AIN0.
0001 I_OUT0 is available on AIN1.
0010 I_OUT0 is available on AIN2.
0011 I_OUT0 is available on AIN3.
0100 I_OUT0 is available on AIN4.
0101 I_OUT0 is available on AIN5.
0110 I_OUT0 is available on AIN6.
0111 I_OUT0 is available on AIN7.
1000 I_OUT0 is available on AIN8.
1001 I_OUT0 is available on AIN9.
1010 I_OUT0 is available on AIN10.
1011 I_OUT0 is available on AIN11.
1100 I_OUT0 is available on AIN12.
1101 I_OUT0 is available on AIN13.
1110 I_OUT0 is available on AIN14.
1111 I_OUT0 is available on AIN15.
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Data Sheet
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AD4130-8 REGISTERS
Configuration n Registers (n = 0 to 7)
Address: 0x19 to 0x20 (in Increments of 1), Reset: 0x0000, Name: CONFIG_n (n = 0 to 7)
These registers allow the user to configure excitation currents and burnout current values, reference mode and buffers, and the PGA mode for
up to seven different ADC setups to be selected in the CHANNEL_m registers.
Figure 118.
Table 84. Bit Descriptions for CONFIG_n Registers
Bits
Bit Name
[15:13]
I_OUT1_n
Settings
Description
Reset
Access
Value for Excitation Current Source 1 for ADC Setup n.
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
000 Off.
001 10 μA.
010 20 μA.
011 50 μA.
100 100 μA.
101 150 μA.
110 200 μA.
111 100 nA
[12:10]
I_OUT0_n
Value for Excitation Current Source 0 for ADC Setup n.
000 Off.
001 10 μA.
010 20 μA.
011 50 μA.
100 100 μA.
101 150 μA.
110 200 μA.
111 100 nA
[9:8]
BURNOUT_n
Value for the Burnout Current for ADC Setup n.
00 Burnout Current Off.
01 Burnout Current = 0.5 μA.
10 Burnout Current = 2 μA.
11 Burnout Current = 4 μA.
7
REF_BUFP_n
Buffer Settings for REFIN(+) for ADC setup n.
0 Buffer Bypass on REFIN(+).
1 Buffer ON for REFIN(+).
6
REF_BUFM_n
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Buffer Settings for REFIN(−) for ADC setup n.
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Data Sheet
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AD4130-8 REGISTERS
Table 84. Bit Descriptions for CONFIG_n Registers
Bits
Bit Name
Settings
Description
Reset
Access
0x0
R/W
0x0
R/W
0x0
R/W
0 Buffer Bypass on REFIN(−).
1 Buffer ON for REFIN(−).
[5:4]
REF_SEL_n
Reference Select for ADC setup n.
00 REFIN1(+), REFIN1(−).
01 REFIN2(+), REFIN2(−)
10 REFOUT, AVSS. Internal reference.
11 AVDD, AVSS.
[3:1]
PGA_n
PGA Gain Control, for ADC setup n. Controls the gain of the PGA. If PGA_BYP_n of the same
CONFIG_n register is set, the PGA_n bits are ignored, and the gain is fixed at 1.
000 Gain = 1.
001 Gain = 2.
010 Gain = 4.
011 Gain = 8.
100 Gain = 16.
101 Gain = 32.
110 Gain = 64.
111 Gain = 128.
0
PGA_BYP_n
PGA Bypass Mode Bit. When this bit is set, the PGA is on bypass mode and the settings in the PGA
field of the same CONFIG_n register are ignored.
0 PGA Bypass Disabled.
1 PGA Bypass Enabled.
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Data Sheet
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Filter n Registers (n = 0 to 7)
Address: 0x21 to 0x28 (in Increments of 1), Reset: 0x002030, Name: FILTER_n (n = 0 to 7)
These registers allow the user to configure up to seven different options for the digital filter to be selected in the CHANNEL_m registers by
specifying the SETUP_m bitfields.
Figure 119.
Table 85. Bit Descriptions for FILTER_n Registers
Bits
Bit Name
[23:21]
SETTLE_n
Settings
Description
Reset
Access
Front-End Settling Time for ADC Setup n. To accommodate varying settling times of inputs,
the user can configure the SETTLE_n bits so that the device waits for the appropriate time
before the conversion on that channel starts. This is useful if there are excitation currents made
available on an AINx input, or the PDSW is enabled for the channel being converted. This
front-end settling time applies every time after a channel change. It does not apply for the
subsequent repeated conversions determined by the REPEAT_n bits values.
0x0
R/W
Conversion Repetitions on a Channel for ADC Setup n. Conversions for a given channel are
repeated on the number indicated in the REPEAT_n bits. When REPEAT_n is 0, no repetition is
done and the channel is converted only once. When REPEAT_n is at N, a channel is converted
N+1 times before converting the next channel. These bits are not in use when duty cycling or
any calibration mode is enabled.
0x0
R/W
Filter Select for ADC Setup n.
0x2
R/W
000 32 MCLK cycles (416.6 μs).
001 64 MCLK cycles (833.3 μs).
010 128 MCLK cycles (1.66 ms).
011 256 MCLK cycles (3.33 ms).
100 512 MCLK cycles (6.66 ms).
101 1024 MCLK cycles (13.33 ms).
110 2048 MCLK cycles (26.66 ms).
111 4096 MCLK cycles (53.33 ms).
[20:16]
REPEAT_n
[15:12]
FILTER_MODE_n
0000 Sinc4. Sinc4 standalone filter
0001 Sinc4 + sinc1. Sinc4 averaging mode filter.
0010 Sinc3. Sinc3 standalone filter
0011 Sinc3 + REJ60. This enables the generation of an additional notch at 6/5 of the main notch
frequency. If the first main notch is set at 50 Hz (FS = 48), this mode enables simultaneous
50 Hz/60 Hz rejection at a 50 SPS update rate.
0100 Sinc3 + sinc1. Sinc3 averaging mode filter.
0101 Sinc3 + Post Filter 1. ODR (Hz) = 26.087 SPS.
0110 Sinc3 + Post Filter 2. ODR (Hz) = 24 SPS.
0111 Sinc3 + Post Filter 3. ODR (Hz) = 19.355 SPS.
1000 Sinc3 + Post Filter 4. ODR (Hz) = 16.21 SPS.
1001 to 1111 Reserved.
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Data Sheet
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AD4130-8 REGISTERS
Table 85. Bit Descriptions for FILTER_n Registers
Bits
Bit Name
11
[10:0]
Settings
Description
Reset
Access
RESERVED
Reserved.
0x0
R
FS_n
Filter Select Bits for ADC Setup n. These bits control the output data rate (ODR) of the ADC for
ADC setup n. FS = 0 is treated as FS = 1.
0x30
R/W
Offset n Registers (n = 0 to 7)
Address: 0x29 to 0x30 (in Increments of 1), Reset: 0x800000, Name: OFFSET_n (n = 0 to 7)
These registers store the result of offset calibration for the corresponding ADC Setup n selected in the CHANNEL_m registers.
Figure 120.
Table 86. Bit Descriptions for OFFSET_n Registers
Bits
Bit Name
[23:0]
OFFSET_n
Settings
Description
Reset
Offset Compensation Register for ADC Setup n. The results of an internal or system offset calibration 0x800000
gets written into the OFFSET_n register indicated by the SETUP_m bits in the CHANNEL_m register
of the active channel. Only one channel can be active during a calibration. The default/reset value of
the OFFSET_n registers is 0x800000.
Access
R/W
Gain n Registers (n = 0 to 7)
Address: 0x31 to 0x38 (in increments of 1), Reset: 0xXXXXXX, Name: GAIN_n (n = 0 to 7)
These registers store the result of gain calibration for the corresponding ADC Setup n selected in the CHANNEL_m registers.
Figure 121.
Table 87. Bit Descriptions for GAIN_n Registers
Bits
Bit Name
[23:0]
GAIN_n
analog.com
Settings
Description
Reset
Access
Gain Compensation Register for ADC Setup n. The results of an internal or system gain calibration
get written into the GAIN_n register indicated by the Setup n bits in the CHANNEL_m register of
the active channel. Only one channel can be active during a calibration. The nominal value of the
GAIN_n registers is 0x555555. The device is factory calibrated at ambient temperature and with a
gain of 1 and PGA_BYP_n = 0, and the resulting gain coefficient is loaded to the GAIN_n registers
of the device as default/reset value.
0xXXXXXX
R/W
Rev. 0 | 100 of 108
Data Sheet
AD4130-8
AD4130-8 REGISTERS
Miscellaneous Register
Address: 0x39, Reset: 0x0000, Name: MISC
Includes settings for oscillator, LDO, calibration and standby mode configuration.
Figure 122.
Table 88. Bit Descriptions for MISC Register
Bits
Bit Name
15
RESERVED
14
PD_ALDO
Settings
Description
Reset
Access
Reserved. Always write 0 to this bit.
0x0
R/W
Enable/Disable Analog LDO.
0x0
R/W
0x0
R/W
0x0
R
0 Analog LDO On.
1 Analog LDO Off.
13
CAL_RANGE_X2
Calibration Range Control. This bit can be used for internal gain calibrations when the
reference is higher than 2 V. When set to 1, this bit doubles the resistive string output
voltage and improves the outcome of internal gain calibration.
0 Disabled.
1 Enabled.
[12:9]
RESERVED
Reserved.
8
STBY_OUT_EN
Route Standby Signal to GPO. When set to 1, values for GPO_CTRL_P4 and
0x0
GPO_DATA_P4 are ignored, and the active low standby signal gets driven on the
P4. When the device is in standby, the P4 pin is low. When the device is converting, the
P4 pin is high. When STBY_OUT_EN is set to 1, GPO_CTRL_P4 and GPO_DATA_P4
determine if P4 is enabled and its value, respectively.
R/W
0 No Signal to P4 (AIN5).
1 Standby Signal to P4 (AIN5).
7
STBY_DIAGNOSTICS_EN
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Keep Diagnostics Alive in Standby Mode. Diagnostics remain active in standby mode
if enabled via the ERROR_EN register. Certain errors like the overvoltage/undervoltage
detection errors (refer to the ERROR_EN register) require an oscillator to be running to
function properly. When in standby mode, however, the internal oscillator can be turned
off to save power if there is no enabled feature that makes use of it. Setting this bit
compels the device to keep the internal oscillator alive, provided the appropriate errors
are also enabled (for example, at least one overvoltage/undervoltage error), and that
the user selected to operate with the internal oscillator per the CLK_SEL bits of the
ADC_CONTROL register.
0x0
R/W
Rev. 0 | 101 of 108
Data Sheet
AD4130-8
AD4130-8 REGISTERS
Table 88. Bit Descriptions for MISC Register
Bits
Bit Name
Settings
Description
Reset
Access
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0 Diagnostics Disabled in Standby Mode.
1 Diagnostics Enabled in Standby Mode.
6
STBY_GPO_EN
Keep GPO Signals Alive in Standby Mode. GPOs remain active in standby mode if
enabled via the IO_CONTROL register
0 GPO Disabled in Standby Mode.
1 GPO Enabled in Standby Mode.
5
STBY_PDSW_EN
Keep PDSW Alive in Standby Mode.
0 Power-Down Switch Disabled in Standby Mode.
1 Power-Down Switch Enabled in Standby Mode. The PDSW_m settings in the CHANNEL_m registers determine if the power-down switch closes or opens when the device
is in standby for the channels using ADC Setup n.
4
STBY_BURNOUT_EN
Keep Burnout Current Sources Alive in Standby Mode.
0 Burnout Currents Disabled in Standby Mode.
1 Burnout Currents Enabled in Standby mode. The BURNOUT_n settings in the CONFIG_n register determines if the burnout current is enabled when device is in standby
for the channels using ADC Setup n.
3
STBY_VBIAS_EN
Keep VBIAS Alive in Standby Mode.
0 VBIAS Disabled in Standby Mode.
1 VBIAS Enabled in Standby Mode. The VBIAS settings in the VBIAS register determine if
VBIAS is enabled for the respective AINx pin.
2
STBY_IEXC_EN
Keep Excitation Current Sources Alive in Standby Mode.
0 Excitation Currents Disabled in Standby Mode.
1 Excitation Currents Enabled in Standby Mode. If set to 1, the I_OUT0_n or I_OUT1_n
bits in the CONFIG_n register determines if the excitation current is enabled when
device is in standby for the channels using Setup n. The excitation current value
specified on the corresponding I_OUT0_n or I_OUT1_n field goes to the channels
specified on the I_OUT0_CH_m and I_OUT1_CH_m fields of the CHANNEL_m register
even in standby.
1
STBY_REFHOL_EN
Keep Reference Holder Alive in Standby Mode.
0 Reference Holder Disabled in Standby Mode.
1 Reference Holder Enabled in Standby Mode.
0
STBY_INTREF_EN
Keep Reference Alive in Standby Mode.
0 Internal Reference and REFOUT Buffer Disabled in Standby Mode.
1 Internal Reference and REFOUT Buffer Enabled in Standby Mode
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Rev. 0 | 102 of 108
Data Sheet
AD4130-8
AD4130-8 REGISTERS
FIFO Control Register
Address: 0x3A, Reset: 0x040200, Name: FIFO_CONTROL
Control bits for operating the FIFO buffer.
Figure 123.
Table 89. Bit Descriptions for FIFO_CONTROL Register
Bits
Bit Name
[23:20]
19
Settings
Description
Reset
Access
RESERVED
Reserved.
0x0
R
ADD_FIFO_STATUS
Add FIFO Status Bit. When this bit is set to 1, the FIFO_STATUS bits
are appended once before the FIFO_DATA stream during a FIFO read command. If the ADD_FIFO_HEADER bit from this register is also set to 1, the
FIFO_STATUS bits are added once to the FIFO_HEADER + FIFO_DATA
readback stream. Each sample has its own header, but the status is only
appended once.
0x0
R/W
0x1
R/W
0x0
R/W
0 No FIFO Status.
1 Add FIFO Status.
18
ADD_FIFO_HEADER
Add FIFO Header Bit. When this bit is set to 1, the FIFO_HEADER bits are
appended before the FIFO_DATA bits during a FIFO read command. Each
sample has its own header.
0 No FIFO Header.
1 Add FIFO Header.
[17:16]
FIFO_MODE
FIFO Mode Setting Bits. These bits control the mode of operation for the
FIFO.
00 Disabled. The FIFO is disabled by default, and the ADC data is read through
data register.
01 Watermark Mode. This mode stores the first N conversions (N = watermark)
in the FIFO. Newer conversions are discarded and only stored until after
the FIFO contents up to the watermark are read entirely. Reading the data
from the FIFO clears it. In this mode, OVERRUN_FLAG is set to 1 in
FIFO_STATUS register if newer data was discarded because the FIFO was
not read out in time.
10 to 11 Streaming Mode. This mode stores the newest conversions. When the FIFO
depth is reached (irrespective of the watermark value), the older data is
analog.com
Rev. 0 | 103 of 108
Data Sheet
AD4130-8
AD4130-8 REGISTERS
Table 89. Bit Descriptions for FIFO_CONTROL Register
Bits
Bit Name
Settings
Description
Reset
Access
automatically discarded to make way for the new one. In this mode, OVERRUN_FLAG is set to 1 in FIFO_STATUS register if older data was discarded
because the FIFO was full.
15
RESERVED
Reserved. Always write 0 to this bit.
0x0
R/W
14
FIFO_WRITE_ERR_INT_EN
FIFO Write Error Interrupt Enable Bit. When this bit is set to 1,
FIFO_WRITE_ERR from the FIFO_STATUS register is allowed to trigger an
interrupt event in the selected interrupt pin.
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
FIFO Overrun Interrupt Enable Bit. When this bit is set to 1, OVERRUN_FLAG 0x0
from the FIFO_STATUS register is allowed to trigger an interrupt event in the
selected interrupt pin.
R/W
0 FIFO Write Error Interrupt Disabled.
1 FIFO Write Error Interrupt Enabled.
13
FIFO_READ_ERR_INT_EN
FIFO Read Error Interrupt Enable Bit. When this bit is set to 1,
FIFO_READ_ERR from the FIFO_STATUS register is allowed to trigger an
interrupt event in the selected interrupt pin.
0 FIFO Read Error Interrupt Disabled.
1 FIFO Read Error Interrupt Enabled.
12
THRES_HIGH_INT_EN
FIFO High Threshold Interrupt Enable Bit. When this bit is set to 1,
THRES_HIGH_FLAG from the FIFO_STATUS register is allowed to trigger
an interrupt event in the selected interrupt pin.
0 FIFO High Threshold Interrupt Disabled.
1 FIFO High Threshold Interrupt Enabled.
11
THRES_LOW_INT_EN
FIFO Low Threshold Interrupt Enable Bit. When this bit is set to 1,
THRES_LOW_FLAG from the FIFO_STATUS register is allowed to trigger
an interrupt event in the selected interrupt pin.
0 FIFO Low Threshold Interrupt Disabled.
1 FIFO Low Threshold Interrupt Enabled.
10
OVERRUN_INT_EN
0 FIFO Overrun Interrupt Disabled.
1 FIFO Overrun Interrupt Enabled.
9
WATERMARK_INT_EN
FIFO Watermark Interrupt Enable Bit. When this bit is set to 1, WATER0x1
MARK_FLAG from the FIFO_STATUS register is allowed to trigger an interrupt
event in the selected interrupt pin.
R/W
0 FIFO Watermark Interrupt Disabled.
1 FIFO Watermark Interrupt Enabled.
8
EMPTY_INT_EN
FIFO Empty Interrupt Enable Bit. When this bit is set to 1, EMPTY_FLAG bit
from the FIFO_STATUS register is allowed to trigger an interrupt event in the
selected interrupt pin. This interrupt triggers together with the EMPTY_FLAG
bit.
0x0
R/W
0x0
R/W
0 FIFO Empty Interrupt Disabled.
1 FIFO Empty Interrupt Enabled.
[7:0]
WATERMARK
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Watermark Value. These bits indicate the number of samples before the
WATERMARK_FLAG is asserted in the FIFO_STATUS register.
0x00: 256 conversions (entire FIFO length).
0x01: 1 conversion (not recommended).
...
0xFF: 255 conversions.
Rev. 0 | 104 of 108
Data Sheet
AD4130-8
AD4130-8 REGISTERS
FIFO Status Register
Address: 0x3B, Reset: 0x01, Name: FIFO_STATUS
Contains error flags for the FIFO, which are only triggered when the FIFO is either in watermark mode or streaming mode.
Figure 124.
Table 90. Bit Descriptions for FIFO_STATUS Register
Bits
Bit Name
7
MASTER_ERR
Settings
Description
Reset
Access
Master Error Bit. This bit is set to 1 when any of the errors in the error register are set. The
MASTER_ERR bit of the status register is also set to 1 when this MASTER_ERR bit is set to 1.
0x0
R
FIFO Write Error Bit. This bit is set to indicate that an ADC conversion was not written
0x0
successfully in the FIFO. For watermark mode, the bit is set to 1 when an ADC conversion is
not written due to an ongoing FIFO read request or an ADC conversion is not written as the
watermark is reached, and the FIFO is not emptied out to make room for new conversions. That
is, the FIFO is treated full when the watermark is reached and remains so until after the FIFO is
emptied (see the FIFO MODE bits from the FIFO_CONTROL register for details). For this case,
this bit behaves like the OVERRUN_FLAG error in the FIFO_STATUS register. For streaming
mode, the bit is set to 1 when an ADC conversion is not written due to an ongoing FIFO read
request. For both FIFO modes, this bit is set to 0 when the FIFO is emptied. The interrupt due
to this error sets and clears together with the error flag.
R
0 No Error Detected.
1 Master Error Detected.
6
FIFO_WRITE_ERR
0 No Error Detected.
1 FIFO Write Error Detected.
5
FIFO_READ_ERR
FIFO Read Error Bit. This bit is set to 1 when a read request on the FIFO fails due to an ADC
conversion currently being written on the FIFO. This bit is set to 0 when a FIFO read request is
granted or the FIFO is emptied. An interrupt associated with this error sets and clears together
with the error bit.
0x0
R
0x0
R
FIFO Threshold Low Flag Bit. This flag indicates if a conversion is lower than or equal to the low 0x0
threshold value set by the THRES_LOW_VAL bits in the FIFO_THRESHOLD register. When
R
0 No Error Detected.
1 FIFO Read Error Detected.
4
THRES_HIGH_FLAG
FIFO Threshold High Flag Bit. This flag indicates if a conversion is higher than or equal
to the high threshold value set by the THRES_HIGH_VAL bits in the FIFO_THRESHOLD
register. When THRES_EN_m of the CHANNEL_m register is set, this bit is set to 1 if the
conversion data for CHANNEL_m stored in the FIFO is higher than or equal to the value in
THRES_HIGH_VAL bits in the FIFO_THRESHOLD register. This bit is set to 0 when the FIFO
is emptied. An interrupt associated with this flag sets and clears together with the bit.
0 Flag Not Triggered.
1 FIFO High Threshold Flag Triggered.
3
THRES_LOW_FLAG
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Rev. 0 | 105 of 108
Data Sheet
AD4130-8
AD4130-8 REGISTERS
Table 90. Bit Descriptions for FIFO_STATUS Register
Bits
Bit Name
Settings
Description
Reset
Access
0x0
R
0x0
R
FIFO Empty Flag Bit. This bit is set to 1 when the FIFO becomes empty. The FIFO goes empty 0x1
on the following conditions: when the FIFO is enabled and not yet initialized with data; as the
last entry of the FIFO is being read; on a successful clear command on the FIFO; if the FIFO is
disabled, this flag is set to 1 by default. This bit is set to 0 when there is at least one entry in the
FIFO. An interrupt associated with this flag sets and clears together with the bit.
R
THRES_EN_m of CHANNEL_m register is set, this bit is set to 1 if the conversion data for
CHANNEL_m stored in the FIFO is lower than or equal to the value in THRES_LOW_VAL bits
in the FIFO_THRESHOLD register. This bit is set to 0 when the FIFO is emptied. An interrupt
associated with this flag sets and clears together with the bit.
0 Flag Not Triggered.
1 FIFO Low Threshold Flag Triggered.
2
OVERRUN_FLAG
FIFO Overrun Error Bit. This bit sets depending on the FIFO mode. In watermark mode,
OVERRUN_FLAG is set to 1 when new conversion data is discarded in the FIFO because the
FIFO was not emptied out in time. In streaming mode, OVERRUN_FLAG is set to 1 when the
older data in the FIFO is discarded to make way for new data as the FIFO is already full. This
bit is set to 0 when the FIFO is emptied. An interrupt associated with this flag sets and clears
together with the bit.
0 Flag Not Triggered.
1 Overrun Flag Triggered.
1
WATERMARK_FLAG
FIFO Watermark Flag Bit. This bit indicates that the FIFO stored the number of samples
indicated by the watermark. This bit is set to 1 when the FIFO contains a number of samples
greater than or equal to the indicated samples in the watermark field of the FIFO_CONTROL
register. This bit is set to 0 when the samples in the FIFO are less than indicated in the
watermark field. An interrupt associated with this flag sets and clears together with the bit.
0 Flag Not Triggered.
1 Watermark Flag Triggered.
0
EMPTY_FLAG
0 Flag Not Triggered.
1 Empty Flag Triggered.
FIFO Threshold Values Register
Address: 0x3C, Reset: 0xFFF000, Name: FIFO_THRESHOLD
Contains upper and lower FIFO threshold values.
Figure 125.
Table 91. Bit Descriptions for FIFO_THRESHOLD Register
Bits
Bit Name
[23:12]
THRES_HIGH_VAL
analog.com
Settings
Description
Reset
Access
Upper Threshold Value for FIFO Data. Provided the corresponding THRES_EN_m of CHANNEL_m is set, when a conversion result stored in the FIFO becomes higher than or equal
to the value set in THRES_HIGH_VAL, the THRES_HIGH_FLAG bit from the FIFO_STATUS
register is set to 1. Threshold values are assumed pseudo static. Thus, it is recommended to
flush the FIFO and restart the ADC conversions after changing them to ensure that threshold
comparisons are valid.
0xFFF
R/W
Rev. 0 | 106 of 108
Data Sheet
AD4130-8
AD4130-8 REGISTERS
Table 91. Bit Descriptions for FIFO_THRESHOLD Register
Bits
Bit Name
Settings
[11:0]
THRES_LOW_VAL
Description
Reset
Access
Lower Threshold Value for FIFO Data. Provided the corresponding THRES_EN_m of CHANNEL_m is set, when a conversion result stored in the FIFO becomes lower than or equal
to the value set in THRES_LOW_VAL, the THRES_LOW_FLAG bit from the FIFO_STATUS
register is set to 1. Threshold values are assumed pseudo static. Thus, it is recommended to
flush the FIFO and restart the ADC conversions after changing them to ensure that threshold
comparisons are valid.
0x0
R/W
Description
Reset
Access
FIFO Data Read Address Bits. Perform an SPI read command on this address to read the FIFO
contents.
0x0
R
FIFO Data Register
Address: 0x3D, Reset: 0x000000, Name: FIFO_DATA
Figure 126.
Table 92. Bit Descriptions for FIFO_DATA Register
Bits
Bit Name
[23:0]
FIFO_DATA
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Settings
Rev. 0 | 107 of 108
Data Sheet
AD4130-8
OUTLINE DIMENSIONS
Figure 127. 35-Ball Wafer Level Chip Scale Package [WLCSP]
2.7 mm × 3.56 mm Body and 0.5 mm Package Height
(CB-35-3)
Dimensions shown in millimeters
Updated: May 12, 2022
ORDERING GUIDE
Model1
Temperature Range
Package Description
Packing Quantity
Package
Option
AD4130-8BCBZ-RL7
-40°C to +105°C
CHIPS W/SOLDER BUMPS/WLCSP
Reel, 1500
CB-35-3
1
Z = RoHS Compliant Part.
EVALUATION BOARDS
Model
Description
EVAL-AD4130-8
Evaluation Board
©2022 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887-2356, U.S.A.
Rev. 0 | 108 of 108
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