AD420

a FEATURES 4 mA–20 mA, 0 mA–20 mA or 0 mA–24 mA Current Output 16-Bit Resolution and Monotonicity 0.012% Max Integral Nonlinearity 0.05% Max Offset (Trimmable) 0.15% Max Total Output Error (Trimmable) Flexible Serial Digital Interface (3.3 MBPS) On-Chip Loop Fault Detection On-Chip 5 V Reference (25 ppm/ C Max) Asynchronous CLEAR Function Maximum Power Supply Range of 32 V Output Loop Compliance of 0 V to VCC – 2.5 V 24-Lead SOIC and PDIP Packages PRODUCT DESCRIPTION Serial Input 16-Bit 4 mA–20 mA, 0 mA–20 mA DAC AD420 FUNCTIONAL BLOCK DIAGRAM VCC VLL REF OUT REFERENCE 4k 40 BOOST AD420 REF IN DATA OUT CLEAR LATCH CLOCK DATA IN RANGE SELECT 1 RANGE SELECT 2 CLOCK DATA I/P REGISTER IOUT 16-BIT DAC SWITCHED CURRENT SOURCES AND FILTERING VOUT 1.25k FAULT DETECT The AD420 is a complete digital to current loop output converter, designed to meet the needs of the industrial control market. It provides a high precision, fully integrated, low cost single-chip solution for generating current loop signals in a compact 24-lead SOIC or PDIP package. The output current range can be programmed to 4 mA–20 mA, 0 mA–20 mA or an overrange function of 0 mA–24 mA. The AD420 can alternatively provide a voltage output from a separate pin that can be configured to provide 0 V–5 V, 0 V–10 V, ± 5 V or ± 10 V with the addition of a single external buffer amplifier. The 3.3M Baud serial input logic design minimizes the cost of galvanic isolation and allows for simple connection to commonly used microprocessors. It can be used in three-wire or asynchronous mode and a serial-out pin is provided to allow daisy chaining of multiple DACs on the current loop side of the isolation barrier. The AD420 uses sigma-delta (Σ∆) DAC technology to achieve 16-bit monotonicity at very low cost. Full-scale settling to 0.1% occurs within 3 ms. The only external components that are required (in addition to normal transient protection circuitry) are two low cost capacitors which are used in the DAC output filter. If the AD420 is going to be used at extreme temperatures and supply voltages, an external output transistor can be used to minimize power dissipation on the chip via the “BOOST” pin. The FAULT DETECT pin signals when an open circuit occurs in the loop. The on-chip voltage reference can be used to supply a precision +5 V to external components in addition to the AD420 or, if the user desires temperature stability exceeding 25 ppm/°C, an external precision reference such as the AD586 can be used as the reference. SPI is a registered trademark of Motorola. MICROWIRE is a registered trademark of National Semiconductor. OFFSET CAP 1 TRIM CAP 2 GND The AD420 is available in a 24-lead SOIC and PDIP over the industrial temperature range of –40°C to +85° C. PRODUCT HIGHLIGHTS 1. The AD420 is a single chip solution for generating 4 mA– 20 mA or 0 mA–20 mA signals at the “controller end” of the current loop. 2. The AD420 is specified with a power supply range from 12 V to 32 V. Output loop compliance is 0 V to VCC – 2.5 V. 3. The flexible serial input can be used in three-wire mode with SPI® or MICROWIRE® microcontrollers, or in asynchronous mode which minimizes the number of control signals required. 4. The serial data out pin can be used to daisy chain any number of AD420s together in three-wire mode. 5. At power-up the AD420 initializes its output to the low end of the selected range. 6. The AD420 has an asynchronous CLEAR pin which sends the output to the low end of the selected range (0 mA, 4 mA, or 0 V). 7. The AD420 BOOST pin accommodates an external transistor to off-load power dissipation from the chip. 8. The offset of ± 0.05% and total output error of ± 0.15% can be trimmed if desired, using two external potentiometers. REV. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 AD420–SPECIFICATIONS (T = T A MIN –TMAX, VCC = +24 V, unless otherwise noted) AX-32 Version1 Typ Max Units Bits RL = 500 Ω 20 20 24 VCC – 2.5 V 3 mA mA mA V ms MΩ Bits % % ppm/ °C % ppm/ °C µA/V V Comments Parameter RESOLUTION IOUT CHARACTERISTICS Operating Current Ranges Min 16 4 0 0 0 Current Loop Voltage Compliance Settling Time (to 0.1% of FS)2 Output Impedance (Current Mode) Accuracy 3 Monotonicity Integral Nonlinearity Offset (0 mA or 4 mA) (TA = +25°C) Offset Drift Total Output Error (20 mA or 24 mA) (TA = +25°C) Total Output Error Drift PSRR4 VOUT CHARACTERISTICS FS Output Voltage Range (Pin 17) VOLTAGE REFERENCE REF OUT Output Voltage (T A = +25°C) Drift Externally Available Current Short Circuit Current REF IN Resistance VLL Output Voltage Externally Available Current Short Circuit Current DIGITAL INPUTS VIH (Logic 1) VIL (Logic 0) IIH (V IN = 5.0 V) IIL (V IN = 0 V) Data Input Rate (“3-Wire” Mode) Data Input Rate (“Asynchronous” Mode) DIGITAL OUTPUTS FAULT DEFECT VOH (10 kΩ Pull-Up Resistor to V LL) VOL (10 kΩ Pull-Up Resistor to V LL) VOL @ 2.5 mA DATA OUT VOH (IOH = –0.8 mA) VOL (IOL = 1.6 mA) POWER SUPPLY Operating Range V CC Quiescent Current Quiescent Current (External VLL ) TEMPERATURE RANGE Specified Performance NOTES 1 2 2.5 25 16 ± 0.002 20 20 5 0 ± 0.012 ± 0.05 50 ± 0.15 50 10 5 4.995 5.0 5 7 30 4.5 5 20 5.005 ± 25 V ppm/ °C mA mA kΩ V mA mA V V µA µA MBPS kBPS 2.4 0.8 ± 10 ± 10 3.3 150 No Minimum No Minimum 3.6 4.5 0.2 0.6 4.3 0.3 0.4 V V V V V V mA mA °C 3.6 0.4 32 5.5 12 4.2 3 –40 +85 X refers to package designator, R or N. External capacitor selection must be as described in Figure 5. 3 Total Output Error includes Offset and Gain Error. Total Output Error and Offset Error are with respect to the Full-Scale Output and are measured with an ideal +5 V reference. If the internal reference is used, the reference errors must be added to the Offset and Total Output Errors. 4 PSRR is measured by varying VCC from 12 V to its maximum 32 V. Specifications subject to change without notice. –2– REV. F AD420 ABSOLUTE MAXIMUM RATINGS* VCC 23 VCC to GND AD420AR/AN-32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 V IOUT to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC Digital Inputs to GND . . . . . . . . . . . . . . . . . . . –0.5 V to +7 V Digital Output to GND . . . . . . . . . . . . . –0.5 V to VLL + 0.3 V VLL and REF OUT: Outputs Safe for Indefinite Short to Ground Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C Thermal Impedance: SOIC (R) Package . . . . . . . . . . . . . . . . . . . . . . θJA = 75°C/W PDIP (N) Package . . . . . . . . . . . . . . . . . . . . . . θJA = 50°C/W *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. VLL 2 REF OUT 14 REFERENCE 4k 40 19 AD420 REF IN 15 DATA OUT 10 CLEAR 6 LATCH 7 CLOCK 8 DATA IN 9 BOOST CLOCK 18 IOUT VOUT DATA I/P REGISTER 16-BIT DAC 17 RANGE 5 SELECT 1 RANGE 4 SELECT 2 16 SWITCHED CURRENT SOURCES AND FILTERING 1.25k 3 FAULT DETECT 20 21 11 OFFSET CAP 1 CAP 2 GND TRIM Figure 1. Functional Block Diagram Table I. Truth Table ORDERING GUIDE Model Temperature Range Max Operating Package Voltage Options* 32 V 32 V N-24 R-24 CLEAR 0 1 X X X X Inputs Range Select 2 X X 0 0 1 1 Range Select 1 X X 0 1 0 1 Operation Normal Operation Output at Bottom of Span 0 V–5 V Range 4 mA–20 mA Range 0 mA–20 mA Range 0 mA–24 mA Range AD420AN-32 – 40° C to +85°C AD420AR-32 – 40° C to +85°C *N = Plastic DIP, R = Plastic SOIC. PIN DESIGNATIONS NC VL L FAULT DETECT RANGE SELECT 2 RANGE SELECT 1 CLEAR LATCH CLOCK DATA IN DATA OUT GND NC NC = NO CONNECT NC VCC NC CAP2 AD420 TOP VIEW (Not to Scale) CAP1 BOOST IOUT VOUT OFFSET TRIM REF IN REF OUT NC CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD420 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. F –3– AD420 Timing Requirements (T = –40 C to +85 C, V A CC = +12 V to +32 V) THREE-WIRE INTERFACE CLOCK CLOCK WORD "N" DATA IN 10 (MSB) B15 B14 11 B13 B12 00 B11 B10 1 B9 00 B8 B7 111 B6 B5 B4 00 B3 B2 11 B1 B0 (LSB) WORD "N + 1" 1 B15 00 1 B14 B13 B12 DATA IN 0 START BIT 1 BIT 15 0 BIT 14 BITs 13-1 0 BIT 0 1 STOP BIT NEXT START BIT (INTERNALLY GENERATED LATCH) LATCH EXPANDED TIME VIEW BELOW WORD "N – 1" DATA OUT WORD "N" 10 B15 B14 11 B13 B12 CLOCK 01 DATA IN 2 8 START BIT 16 24 DATA BIT 15 BIT 14 CLOCK COUNTER STARTS HERE CONFIRM START BIT SAMPLE BIT 15 tCK tCL CLOCK tCH tDS tDH DATA IN EXPANDED TIME VIEW BELOW tDW tLD LATCH tACK tACL tLL tLH tSD CLOCK tADS tADW DATA IN tACH tADH DATA OUT Figure 2. Timing Diagram for Three-Wire Interface Table II. Timing Specification for Three-Wire Interface Figure 3. Timing Diagram for Asynchronous Interface Table III. Timing Specifications for Asynchronous Interface Parameter Data Clock Period Data Clock Low Time Data Clock High Time Data Stable Width Data Setup Time Data Hold Time Latch Delay Time Latch Low Time Latch High Time Serial Output Delay Time Clear Pulsewidth Label tCK tCL tCH tDW tDS tDH tLD tLL tLH tSD tCLR Limit 300 80 80 125 40 5 80 80 80 225 50 Units ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max ns min Parameter Asynchronous Clock Period Asynchronous Clock Low Time Asynchronous Clock High Time Data Stable Width (Critical Clock Edge) Data Setup Time (Critical Clock Edge) Data Hold Time (Critical Clock Edge) Clear Pulsewidth ASYNCHRONOUS INTERFACE Label Limit Units tACK tACL tACH tADW tADS tADH tCLR 400 50 150 300 50 20 50 ns min ns min ns min ns min ns min ns min ns min Three-Wire Interface Fast Edges on Digital Input With a fast rising edge (