AD420ARZ-32-REEL

Serial Input 16-Bit 4 mA–20 mA, 0 mA–20 mA DAC AD420 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM VCC VLL REFERENCE 4kΩ REF OUT 40Ω BOOST AD420 REF IN DATA OUT CLEAR LATCH CLOCK DATA IN CLOCK DATA I/P REGISTER IOUT 16-BIT DAC RANGE SELECT 1 SWITCHED CURRENT SOURCES AND FILTERING VOUT 1.25kΩ FAULT DETECT RANGE SELECT 2 OFFSET TRIM CAP 1 CAP 2 GND 00494-001 4 mA–20 mA, 0 mA–20 mA or 0 mA–24 mA current output 16-bit resolution and monotonicity ±0.012% max integral nonlinearity ±0.05% max offset (trimmable) ±0.15% max total output error (trimmable) Flexible serial digital interface (3.3 MBPS) On-Chip loop fault detection On-chip 5 V reference (25 ppm/°C max) Asynchronous CLEAR function Maximum power supply range of 32 V Output loop compliance of 0 V to VCC − 2.75 V 24-Lead SOIC and PDIP packages Figure 1. GENERAL DESCRIPTION The AD420 is a complete digital to current loop output converter, designed to meet the needs of the industrial control market. It provides a high precision, fully integrated, low cost single-chip solution for generating current loop signals in a compact 24-lead SOIC or PDIP package. user desires temperature stability exceeding 25 ppm/°C, an external precision reference such as the AD586 can be used as the reference. The AD420 is available in a 24-lead SOIC and PDIP over the industrial temperature range of −40°C to +85°C. PRODUCT HIGHLIGHTS The output current range can be programmed to 4 mA to 20 mA, 0 mA to 20 mA or to an overrange function of 0 mA to 24 mA. The AD420 can alternatively provide a voltage output from a separate pin that can be configured to provide 0 V to 5 V, 0 V to 10 V, ±5 V, or ±10 V with the addition of a single external buffer amplifier. 1. The AD420 is a single chip solution for generating 4 mA to 20 mA or 0 mA to 20 mA signals at the controller end of the current loop. 2. The AD420 is specified with a power supply range from 12 V to 32 V. Output loop compliance is 0 V to VCC − 2.75 V. The 3.3 M Baud serial input logic design minimizes the cost of galvanic isolation and allows for simple connection to commonly used microprocessors. It can be used in 3-wire or asynchronous mode and a serial-out pin is provided to allow daisy chaining of multiple DACs on the current loop side of the isolation barrier. 3. The flexible serial input can be used in 3-wire mode with SPI® or MICROWIRE® microcontrollers, or in asynchronous mode, which minimizes the number of control signals required. 4. The serial data out pin can be used to daisy chain any number of AD420s together in 3-wire mode. 5. At power-up, the AD420 initializes its output to the low end of the selected range. 6. The AD420 has an asynchronous CLEAR pin, which sends the output to the low end of the selected range (0 mA, 4 mA, or 0 V). 7. The AD420 BOOST pin accommodates an external transistor to off-load power dissipation from the chip. 8. The offset of ±0.05% and total output error of ±0.15% can be trimmed if desired, using two external potentiometers. The AD420 uses sigma-delta (Σ-Δ) DAC technology to achieve 16-bit monotonicity at very low cost. Full-scale settling to 0.1% occurs within 3 ms. The only external components that are required (in addition to normal transient protection circuitry) are two low cost capacitors which are used in the DAC output filter. If the AD420 is used at extreme temperatures and supply voltages, an external output transistor can be used to minimize power dissipation on the chip via the BOOST pin. The FAULT DETECT pin signals when an open circuit occurs in the loop. The on-chip voltage reference can be used to supply a precision +5 V to external components in addition to the AD420 or, if the Rev. I Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD420 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Driving Inductive Loads............................................................ 10 Functional Block Diagram .............................................................. 1 Voltage-Mode Output ................................................................ 10 General Description ......................................................................... 1 Optional Span and Zero Trim .................................................. 10 Product Highlights ........................................................................... 1 Three-Wire Interface ................................................................. 11 Revision History ............................................................................... 2 Using Multiple DACS with Fault Detect ................................. 11 Specifications..................................................................................... 3 Asynchronous Interface Using Optocouplers ........................ 11 Absolute Maximum Ratings ............................................................ 5 Microprocessor Interface............................................................... 12 ESD Caution .................................................................................. 5 AD420-To-MC68HC11 (SPI Bus) Interface ........................... 12 Pin Configuration and Function Descriptions ............................. 6 AD420 to Microwire Interface ................................................. 12 Timing Requirements ...................................................................... 7 External Boost Function............................................................ 13 Three-Wire Interface ................................................................... 7 AD420 Protection ........................................................................... 14 Three-Wire Interface Fast Edges on Digital Input ................... 7 Transient Voltage Protection .................................................... 14 Asynchronous Interface ............................................................... 7 Board Layout And Grounding ................................................. 14 Terminology ...................................................................................... 8 Power Supplies and Decoupling ............................................... 14 Theory of Operation ........................................................................ 9 Outline Dimensions ....................................................................... 15 Applications Information .............................................................. 10 Ordering Guide .......................................................................... 15 Current Output ........................................................................... 10 REVISION HISTORY 3/15—Rev. H to Rev. I Changes to Three-Wire Interface Fast Edges on Digital Input Section ................................................................................................ 7 1/11—Rev. G to Rev. H Changes to Figure 13 ...................................................................... 13 Changes to Ordering Guide .......................................................... 15 11/09—Rev. F to Rev. G Updated Format .................................................................. Universal Changes to Table 2 ............................................................................ 5 Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide .......................................................... 15 9/99—Rev. E to Rev. F Rev. I | Page 2 of 16 Data Sheet AD420 SPECIFICATIONS TA = TMIN − TMAX, VCC = +24 V, unless otherwise noted. Table 1. Parameter RESOLUTION IOUT CHARACTERISTICS Operating Current Ranges Current Loop Voltage Compliance Settling Time (to 0.1% of FS)1 Output Impedance (Current Mode) Accuracy2 Monotonicity Integral Nonlinearity Offset (0 mA or 4 mA) (TA = +25°C) Offset Drift Total Output Error (20 mA or 24 mA) (TA = +25°C) Total Output Error Drift PSRR3 VOUT CHARACTERISTICS FS Output Voltage Range (Pin 17) VOLTAGE REFERENCE REF OUT Output Voltage (TA = +25° C) Drift Externally Available Current Short Circuit Current REF IN Resistance VLL Output Voltage Externally Available Current Short Circuit Current DIGITAL INPUTS VIH (Logic 1) VIL (Logic 0) IIH (VIN = 5.0 V) IIL (VIN = 0 V) Data Input Rate (3-Wire Mode) Data Input Rate (Asynchronous Mode) DIGITAL OUTPUTS FAULT DEFECT VOH (10 kΩ Pull-Up Resistor to VLL) VOL (10 kΩ Pull-Up Resistor to VLL) VOL @ 2.5 mA DATA OUT VOH (IOH = −0.8 mA) VOL (IOL = 1.6 mA) Min 16 AD420-32 Version Typ Max Units Bits Comments RL = 500 Ω 4 0 0 0 2.5 25 20 20 24 VCC − 2.75 V 3 16 ±0.012 ±0.05 50 ±0.15 50 10 Bits % % ppm/° C % ppm/° C µA/V 5 V 5.005 ±25 5 7 V ppm/° C mA mA 30 kΩ 4.5 5 20 V mA mA ±0.002 20 20 5 0 4.995 5.0 2.4 0.8 ±10 ±10 3.3 150 No Minimum No Minimum 3.6 3.6 Rev. I | Page 3 of 16 mA mA mA V ms MΩ 4.5 0.2 0.6 4.3 0.3 0.4 0.4 V V µA µA MBPS kBPS V V V V V AD420 Parameter POWER SUPPLY Operating Range VCC Quiescent Current Quiescent Current (External VLL) TEMPERATURE RANGE Specified Performance Data Sheet Min AD420-32 Version Typ Max 12 4.2 3 −40 Units 32 5.5 V mA mA +85 °C Comments External capacitor selection must be as described in Figure 6. Total Output Error includes Offset and Gain Error. Total Output Error and Offset Error are with respect to the Full-Scale Output and are measured with an ideal +5 V reference. If the internal reference is used, the reference errors must be added to the Offset and Total Output Errors. 3 PSRR is measured by varying VCC from 12 V to its maximum 32 V. 1 2 Rev. I | Page 4 of 16 Data Sheet AD420 ABSOLUTE MAXIMUM RATINGS Table 3. Truth Table Table 2. Parameter VCC to GND IOUT to GND Digital Inputs to GND Digital Output to GND VLL and REF OUT: Outputs Safe for Indefinite Short to Ground Storage Temperature Lead Temperature (Soldering, 10 sec) Lead Temperature, Soldering Reflow Thermal Impedance: SOIC (R) Package PDIP (N) Package Rating 32 V VCC −0.5 V to +7 V −0.5 V to VLL + 0.3 V −65°C to +150°C +300°C +260°C θJA = 75°C/W θJA = 50°C/W CLEAR 0 1 Inputs Range Select 2 X X Range Select 1 X X X X X X 0 0 1 1 0 1 0 1 ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. I | Page 5 of 16 Operation Normal operation Output at bottom of span 0 V–5 V range 4 mA–20 mA range 0 mA–20 mA range 0 mA–24 mA range AD420 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NC 1 24 NC VLL 2 23 VCC FAULT DETECT 3 22 NC RANGE SELECT 2 4 21 CAP 2 CLEAR 6 LATCH 7 CLOCK 8 DATA IN 9 DATA OUT 10 GND 11 NC 12 AD420 20 CAP 1 TOP VIEW 19 BOOST (Not to Scale) 18 IOUT 17 VOUT 16 OFFSET TRIM 15 REF IN 14 REF OUT 13 NC NC = NO CONNECT 00494-002 RANGE SELECT 1 5 Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1, 12, 13, 24 2 Mnemonic NC Function No Connection. No internal connections inside device. VLL 3 FAULT DETECT 4 5 6 RANGE SELECT 2 RANGE SELECT 1 CLEAR 7 LATCH 8 CLOCK 9 10 DATA IN DATA OUT 11 14 15 16 17 18 19 GND REF OUT REF IN OFFSET TRIM VOUT IOUT BOOST 20 21 22 23 CAP 1 CAP 2 NC VCC Auxiliary buffered +4.5 V digital logic voltage. This pin is the internal supply voltage for the digital circuitry and can be used as a termination for pull-up resistors. An external +5 V power supply can be connected to VLL. It will override this buffered voltage, thus reducing the internal power dissipation. The VLL pin should be decoupled to GND with a 0.1 µF capacitor. See the Power Supplies and Decoupling section. FAULT DETECT, connected to a pull-up resistor, is asserted low when the output current does not match the DAC’s programmed value, for example, in case the current loop is broken. Selects the converter’s output operating range. One output voltage range and three output current ranges are available. Valid VIH unconditionally forces the output to go to the minimum of its programmed range. After CLEAR is removed the DAC output will remain at this value. The data in the input register is unaffected. In the 3-wire interface mode a rising edge parallel loads the serial input register data into the DAC. To use the asynchronous mode connect LATCH through a current limiting resistor to VCC. Data Clock Input. The clock period is equal to the input data bit rate in the 3-wire interface mode and is 16 times the bit rate in asynchronous mode. Serial Data Input. Serial Data Output. In the 3-wire interface mode, this output can be used for daisy-chaining multiple AD420s. In the asynchronous mode a positive pulse will indicate a framing error after the stop-bit is received. Ground (Common). +5 V Reference Output. Reference Input. Offset Adjust. Voltage Output. Current Output. Connect to an external transistor to reduce the power dissipated in the AD420 output transistor, if desired. These pins are used for internal filtering. Connect capacitors between each of these pins and VCC. Refer to the description of current output operation. No Connection. Do not connect anything to this pin. Power Supply Input. The VCC pin should always be decoupled to GND with a 0.1 µF capacitor. See the Power Supplies and Decoupling section. Rev. I | Page 6 of 16 Data Sheet AD420 TIMING REQUIREMENTS TA = −40°C to +85°C, VCC = +12 V to +32 V. CLOCK NEXT START BIT 1 STOP BIT (INTERNALLY GENERATED LATCH) 0 BIT0 1 0 0 1 BIT13 TO BIT1 0 START BIT 1 WORD “N + 1” B13 B12 0 1 1 (LSB) B15 B14 0 0 1 1 1 0 B2 B1 B0 B10 B9 B14 B13 B12 B11 (MSB) B15 1 0 1 1 0 0 1 B8 B7 B6 B5 B4 B3 WORD “N” EXPANDED TIME VIEW BELOW LATCH CLOCK COUNTER STARTS HERE CONFIRM START BIT DATA OUT tCK B14 B15 1 0 CLOCK 1 1 0 1 2 DATA IN tCL CLOCK tCH tDH tDS SAMPLE BIT 15 WORD “N” B13 B12 WORD “N – 1” 8 16 START BIT 24 DATA BIT 15 BIT 14 EXPANDED TIME VIEW BELOW tACK tACL DATA IN CLOCK tDW tLL LATCH tADW tLH DATA IN 00494-003 tSD DATA OUT Table 5. Timing Specification for 3-Wire Interface Label tCK tCL tCH tDW tDS tDH tLD tLL tLH tSD tCLR Limit 300 80 80 125 40 5 80 80 80 225 50 Figure 4. Timing Diagram for Asynchronous Interface Table 6. Timing Specifications for Asynchronous Interface Figure 3. Timing Diagram for 3-Wire Interface Parameter Data Clock Period Data Clock Low Time Data Clock High Time Data Stable Width Data Setup Time Data Hold Time Latch Delay Time Latch Low Time Latch High Time Serial Output Delay Time Clear Pulse Width tACH tADH tADS tLD 00494-004 DATA IN 0 BIT14 DATA IN CLOCK BIT15 THREE-WIRE INTERFACE Units ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max ns min THREE-WIRE INTERFACE FAST EDGES ON DIGITAL INPUT With a fast rising edge (