Data Sheet
AD5122A/AD5142A
Dual Channel, 128-/256-Position, I2C, Nonvolatile Digital Potentiometer
FEATURES
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FUNCTIONAL BLOCK DIAGRAM
10 kΩ and 100 kΩ resistance options
Resistor tolerance: 8% maximum
Wiper current: ±6 mA
Low temperature coefficient: 35 ppm/°C
Wide bandwidth: 3 MHz
Fast start-up time < 75 µs
Linear gain setting mode
Single- and dual-supply operation
Independent logic supply: 1.8 V to 5.5 V
Wide operating temperature: −40°C to +125°C
3 mm × 3 mm package option
Qualified for automotive applications
Figure 1.
APPLICATIONS
Portable electronics level adjustment
LCD panel brightness and contrast controls
► Programmable filters, delays, and time constants
► Programmable power supplies
►
►
GENERAL DESCRIPTION
The AD5122A/AD5142A potentiometers provide a nonvolatile solution for 128-/256-position adjustment applications, offering guaranteed low resistor tolerance errors of ±8% and up to ±6 mA current
density in the Ax, Bx, and Wx pins.
operate over the extended industrial temperature range of −40°C to
+125°C.
The low resistor tolerance and low nominal temperature coefficient
simplify open-loop applications as well as applications requiring
tolerance matching.
AD51231
The linear gain setting mode allows independent programming of
the resistance between the digital potentiometer terminals, through
RAW and RWB the string resistors, allowing very accurate resistor
matching.
The high bandwidth and low total harmonic distortion (THD) ensure
optimal performance for ac signals, making it suitable for filter
design.
The low wiper resistance of only 40 Ω at the ends of the resistor
array allows for pin-to-pin connection.
The wiper values can be set through an I2C-compatible digital
interface that is also used to read back the wiper register and
EEPROM contents.
Table 1. Family Models
Model
AD5124
AD5124
AD51431
AD5144
AD5144
AD5144A
AD5122
AD5122A
AD5142
AD5142A
AD5121
AD5141
1
Channel
Quad
Quad
Quad
Quad
Quad
Quad
Quad
Dual
Dual
Dual
Dual
Single
Single
Position
Interface
Package
128
128
128
256
256
256
256
128
128
256
256
128
256
I 2C
LFCSP
LFCSP
TSSOP
LFCSP
LFCSP
TSSOP
TSSOP
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP
LFCSP
SPI/I2C
SPI
I2C
SPI/I2C
SPI
I 2C
SPI
I2C
SPI
I2C
SPI/I2C
SPI/I2C
Two potentiometers and two rheostats.
The AD5122A/AD5142A are available in a compact, 16-lead, 3 mm
× 3 mm LFCSP and a 16-lead TSSOP. The parts are guaranteed to
Rev. C
DOCUMENT FEEDBACK
TECHNICAL SUPPORT
Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to
change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Data Sheet
AD5122A/AD5142A
TABLE OF CONTENTS
Features................................................................ 1
Applications........................................................... 1
Functional Block Diagram......................................1
General Description...............................................1
Specifications........................................................ 3
Electrical Characteristics—AD5122A................. 3
Electrical Characteristics—AD5142A................. 5
Interface Timing Specifications.......................... 8
Shift Register and Timing Diagrams...................9
Absolute Maximum Ratings.................................10
Thermal Resistance......................................... 10
Electrostatic Discharge (ESD) Ratings.............10
ESD Ratings for AD5122A/AD5142A...............10
ESD Caution.....................................................10
Pin Configurations and Function Descriptions.....11
Typical Performance Characteristics................... 12
Test Circuits......................................................... 17
Theory of Operation.............................................18
RDAC Register and EEPROM......................... 18
Input Shift Register...........................................18
I2C Serial Data Interface.................................. 19
Advanced Control Modes................................. 22
EEPROM or RDAC Register Protection...........25
INDEP Pin........................................................ 25
RDAC Architecture........................................... 25
Programming the Variable Resistor..................26
Programming the Potentiometer Divider.......... 26
Terminal Voltage Operating Range.................. 27
Power-Up Sequence........................................ 27
Layout and Power Supply Biasing....................27
Outline Dimensions............................................. 28
Ordering Guide.................................................29
RAB (KΩ), Resolution, and Interface Options... 29
Evaluation Boards............................................ 29
Automotive Products ....................................... 30
REVISION HISTORY
5/2022—Rev. B to Rev. C
Changes to Nominal Resistance Match Parameter, Single-Supply Power Range Parameter, DualSupply Power Range Parameter, and Logic Supply Range Parameter, Table 2........................................... 3
Changes to Nominal Resistance Match Parameter, Single-Supply Power Range Parameter, DualSupply Power Range Parameter, and Logic Supply Range Parameter, Table 3........................................... 5
Deleted FICDM Parameter, Table 5............................................................................................................... 10
Added Electrostatic Discharge (ESD) Ratings Section..................................................................................10
Added ESD Ratings for AD5122A/AD5142A Section, Table 7, and Table 8; Renumbered Sequentially...... 10
Deleted Table 8, Renumbered Sequentially...................................................................................................11
Moved Table 10 and Table 11........................................................................................................................ 18
Added Write Operation Section, Figure 38, and Figure 39; Renumbered Sequentially.................................19
Added EEPROM Write Acknowledge Polling Section................................................................................... 21
Added Read Operation Section and Figure 40.............................................................................................. 21
Moved Table 13, Table 14, and Table 15....................................................................................................... 22
Changes to Table 13...................................................................................................................................... 22
Changes to Ordering Guide........................................................................................................................... 29
Added RAB (KΩ), Resolution, and Interface Options Section........................................................................ 29
analog.com
Rev. C | 2 of 30
Data Sheet
AD5122A/AD5142A
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—AD5122A
VDD = 2.3 V to 5.5 V, VSS = 0 V; VDD = 2.25 V to 2.75 V, VSS = −2.25 V to −2.75 V; VLOGIC = 1.8 V to 5.5 V, −40°C < TA < +125°C, unless
otherwise noted.
Table 2.
Parameter
Symbol
DC CHARACTERISTICS—RHEOSTAT MODE (ALL
RDACs)
Resolution
N
2
Resistor Integral Nonlinearity
R-INL
Resistor Differential Nonlinearity2
Nominal Resistor Tolerance
Resistance Temperature Coefficient3
Wiper Resistance3
Bottom Scale or Top Scale
Nominal Resistance Match
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE (ALL RDACs)
Integral Nonlinearity4
Differential Nonlinearity4
Full-Scale Error
Zero-Scale Error
Voltage Divider Temperature Coefficient3
RESISTOR TERMINALS
Maximum Continuous Current
R-DNL
ΔRAB/RAB
(ΔRAB/RAB)/ΔT × 106
RW
Test Conditions/Comments
Capacitance W3
analog.com
Typ1
Max
7
RAB = 10 kΩ
VDD ≥ 2.7 V
VDD < 2.7 V
RAB = 100 kΩ
VDD ≥ 2.7 V
VDD < 2.7 V
Unit
Bits
−1
−2.5
±0.1
±1
+1
+2.5
LSB
LSB
−0.5
−1
−0.5
−8
+0.5
+1
+0.5
+8
Code = full scale
Code = zero scale
RAB = 10 kΩ
RAB = 100 kΩ
±0.1
±0.25
±0.1
±1
35
LSB
LSB
LSB
%
ppm/°C
55
130
125
400
Ω
Ω
RAB = 10 kΩ
RAB = 100 kΩ
Code = full scale
−1
40
60
±0.2
80
230
+1
Ω
Ω
%
RAB = 10 kΩ
RAB = 100 kΩ
−0.5
−0.25
−0.25
±0.1
±0.1
±0.1
+0.5
+0.25
+0.25
LSB
LSB
LSB
RAB = 10 kΩ
RAB = 100 kΩ
−1.5
−0.5
−0.1
±0.1
+0.5
LSB
LSB
RBS or RTS
RAB1/RAB2
INL
DNL
VWFSE
VWZSE
(ΔVW/VW)/ΔT × 106
RAB = 10 kΩ
RAB = 100 kΩ
Code = half scale
1
0.25
±5
1.5
0.5
LSB
LSB
ppm/°C
+6
+1.5
VDD
mA
mA
V
IA, IB, and IW
RAB = 10 kΩ
RAB = 100 kΩ
Terminal Voltage Range5
Capacitance A, Capacitance B3
Min
CA, CB
CW
−6
−1.5
VSS
f = 1 MHz, measured to GND, code
= half scale
RAB = 10 kΩ
RAB = 100 kΩ
f = 1 MHz, measured to GND, code
= half scale
RAB = 10 kΩ
25
12
pF
pF
12
pF
Rev. C | 3 of 30
Data Sheet
AD5122A/AD5142A
SPECIFICATIONS
Table 2.
Parameter
Symbol
Common-Mode Leakage Current3
DIGITAL INPUTS
Input Logic3
High
Low
Input Hysteresis3
Input Current3
Input Capacitance3
DIGITAL OUTPUTS
Output High Voltage3
Output Low Voltage3
Three-State Leakage Current
Three-State Output Capacitance
POWER SUPPLIES
Single-Supply Power Range
Dual-Supply Power Range
Logic Supply Range
Positive Supply Current
Negative Supply Current
EEPROM Store Current3, 6
EEPROM Read Current3, 7
Logic Supply Current
Power Dissipation8
Power Supply Rejection Ratio
DYNAMIC CHARACTERISTICS9
Bandwidth
Total Harmonic Distortion
Resistor Noise Density
VW Settling Time
Crosstalk (CW1/CW2)
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VINH
Min
Typ1
RAB = 100 kΩ
VA = VW = VB
−500
5
±15
VLOGIC = 1.8 V to 2.3 V
VLOGIC = 2.3 V to 5.5 V
0.8 × VLOGIC
0.7 × VLOGIC
Test Conditions/Comments
VINL
VHYST
IIN
CIN
VOH
VOL
Max
Unit
+500
pF
nA
0.2 × VLOGIC
0.1 × VLOGIC
±1
5
RPULL-UP = 2.2 kΩ to VLOGIC
ISINK = 3 mA
ISINK = 6 mA, VLOGIC > 2.3 V
VLOGIC
−1
0.4
0.6
+1
V
V
V
µA
pF
5.5
±2.75
VDD
VDD
V
V
V
V
5.5
µA
nA
µA
mA
µA
µA
µW
dB
2
VDD
VDD/VSS
VLOGIC
IDD
ISS
IDD_EEPROM_STORE
IDD_EEPROM_READ
ILOGIC
PDISS
PSRR
BW
THD
eN_WB
tS
CT
VSS = GND
Single supply, VSS = GND
Dual supply, VSS < GND
VIH = VLOGIC or VIL = GND
VDD = 5.5 V
VDD = 2.3 V
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
∆VDD/∆VSS = VDD ± 10%, code =
full scale
−3 dB
RAB = 10 kΩ
RAB = 100 kΩ
VDD/VSS = ±2.5 V, VA = 1 V rms, VB
= 0 V, f = 1 kHz
RAB = 10 kΩ
RAB = 100 kΩ
Code = half scale, TA = 25°C, f = 10
kHz
RAB = 10 kΩ
RAB = 100 kΩ
VA = 5 V, VB = 0 V, from zero scale
to full scale, ±0.5 LSB error band
RAB = 10 kΩ
RAB = 100 kΩ
RAB = 10 kΩ
RAB = 100 kΩ
2.3
±2.25
1.8
2.25
−5.5
0.7
400
−0.7
2
320
0.05
3.5
−66
V
V
V
V
µA
pF
1.4
−60
3
0.43
MHz
MHz
−80
−90
dB
dB
7
20
nV/√Hz
nV/√Hz
2
12
10
25
µs
µs
nV-sec
nV-sec
Rev. C | 4 of 30
Data Sheet
AD5122A/AD5142A
SPECIFICATIONS
Table 2.
Parameter
Analog Crosstalk
Endurance10
Symbol
Test Conditions/Comments
Min
CTA
Typ1
Max
−90
1
TA = 25°C
dB
Mcycles
kcycles
Years
100
Data Retention11, 12
Unit
50
1
Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V.
2
Resistor integral nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB.
3
Guaranteed by design and characterization, not subject to production test.
4
INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of
±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground
referenced bipolar signal adjustment.
6
Different from operating current; supply current for EEPROM program lasts approximately 30 ms.
7
Different from operating current; supply current for EEPROM read lasts approximately 20 µs.
8
PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC).
9
All dynamic characteristics use VDD/VSS = ±2.5 V, and VLOGIC = 2.5 V.
10
Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C.
11
Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV, derates
with junction temperature in the Flash/EE memory.
12
50 years apply to an endurance of 1000 cycles. An endurance of 100,000 cycles has an equivalent retention lifetime of 5 years.
ELECTRICAL CHARACTERISTICS—AD5142A
VDD = 2.3 V to 5.5 V, VSS = 0 V; VDD = 2.25 V to 2.75 V, VSS = −2.25 V to −2.75 V; VLOGIC = 1.8 V to 5.5 V, −40°C < TA < +125°C, unless
otherwise noted.
Table 3.
Parameter
Symbol
DC CHARACTERISTICS—RHEOSTAT MODE (ALL
RDACs)
Resolution
N
Resistor Integral Nonlinearity2
R-INL
Resistor Differential Nonlinearity2
Nominal Resistor Tolerance
Resistance Temperature Coefficient3
Wiper Resistance3
Bottom Scale or Top Scale
Nominal Resistance Match
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R-DNL
ΔRAB/RAB
(ΔRAB/RAB)/ΔT × 106
RW
Test Conditions/Comments
Min
Typ1
Max
8
RAB = 10 kΩ
VDD ≥ 2.7 V
VDD < 2.7 V
RAB = 100 kΩ
VDD ≥ 2.7 V
VDD < 2.7 V
Unit
Bits
−2
−5
±0.2
±1.5
+2
+5
LSB
LSB
−1
−2
−0.5
−8
+1
+2
+0.5
+8
Code = full scale
Code = zero scale
RAB = 10 kΩ
RAB = 100 kΩ
±0.1
±0.5
±0.2
±1
35
LSB
LSB
LSB
%
ppm/°C
55
130
125
400
Ω
Ω
RAB = 10 kΩ
RAB = 100 kΩ
Code = full scale
40
60
±0.2
80
230
+1
Ω
Ω
%
RBS or RTS
RAB1/RAB2
−1
Rev. C | 5 of 30
Data Sheet
AD5122A/AD5142A
SPECIFICATIONS
Table 3.
Parameter
Symbol
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE (ALL RDACs)
Integral Nonlinearity4
INL
Differential Nonlinearity4
Full-Scale Error
Zero-Scale Error
Voltage Divider Temperature Coefficient3
RESISTOR TERMINALS
Maximum Continuous Current
Test Conditions/Comments
Min
Typ1
Max
Unit
RAB = 10 kΩ
RAB = 100 kΩ
−1
−0.5
−0.5
±0.2
±0.1
±0.2
+1
+0.5
+0.5
LSB
LSB
LSB
RAB = 10 kΩ
RAB = 100 kΩ
−2.5
−1
−0.1
±0.2
+1
LSB
LSB
DNL
VWFSE
VWZSE
(ΔVW/VW)/ΔT × 106
RAB = 10 kΩ
RAB = 100 kΩ
Code = half scale
Capacitance W3
Common-Mode Leakage Current3
DIGITAL INPUTS
Input Logic3
High
Low
Input Hysteresis3
Input Current3
Input Capacitance3
DIGITAL OUTPUTS
Output High Voltage3
Output Low Voltage3
Three-State Leakage Current
Three-State Output Capacitance
POWER SUPPLIES
Single-Supply Power Range
Dual-Supply Power Range
Logic Supply Range
Positive Supply Current
analog.com
3
1
LSB
LSB
ppm/°C
+6
+1.5
VDD
mA
mA
V
IA, IB, and IW
RAB = 10 kΩ
RAB = 100 kΩ
Terminal Voltage Range5
Capacitance A, Capacitance B3
1.2
0.5
±5
CA, CB
CW
VINH
f = 1 MHz, measured to GND, code
= half scale
RAB = 10 kΩ
RAB = 100 kΩ
f = 1 MHz, measured to GND, code
= half scale
RAB = 10 kΩ
RAB = 100 kΩ
VA = VW = VB
−500
VLOGIC = 1.8 V to 2.3 V
VLOGIC = 2.3 V to 5.5 V
0.8 × VLOGIC
0.7 × VLOGIC
VINL
VHYST
IIN
CIN
VOH
VOL
−6
−1.5
VSS
25
12
pF
pF
12
5
±15
pF
pF
nA
+500
0.2 × VLOGIC
0.1 × VLOGIC
±1
5
RPULL-UP = 2.2 kΩ to VLOGIC
ISINK = 3 mA
ISINK = 6 mA, VLOGIC > 2.3 V
VLOGIC
−1
0.4
0.6
+1
V
V
V
µA
pF
5.5
±2.75
VDD
VDD
V
V
V
V
5.5
µA
nA
2
VDD
VDD/VSS
VLOGIC
IDD
VSS = GND
Single supply, VSS = GND
Dual supply, VSS < GND
VIH = VLOGIC or VIL = GND
VDD = 5.5 V
VDD = 2.3 V
2.3
±2.25
1.8
2.25
0.7
400
V
V
V
V
µA
pF
Rev. C | 6 of 30
Data Sheet
AD5122A/AD5142A
SPECIFICATIONS
Table 3.
Parameter
Negative Supply Current
EEPROM Store Current3, 6
EEPROM Read Current3, 7
Logic Supply Current
Power Dissipation8
Power Supply Rejection Ratio
DYNAMIC CHARACTERISTICS9
Bandwidth
Total Harmonic Distortion
Resistor Noise Density
VW Settling Time
Symbol
Test Conditions/Comments
Min
Typ1
ISS
IDD_EEPROM_STORE
IDD_EEPROM_READ
ILOGIC
PDISS
PSRR
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
∆VDD/∆VSS = VDD ± 10%, code =
full scale
−5.5
−0.7
2
320
0.05
3.5
−66
BW
−3 dB
RAB = 10 kΩ
RAB = 100 kΩ
VDD/VSS = ±2.5 V, VA = 1 V rms, VB
= 0 V, f = 1 kHz
RAB = 10 kΩ
RAB = 100 kΩ
Code = half scale, TA = 25°C, f = 10
kHz
RAB = 10 kΩ
RAB = 100 kΩ
VA = 5 V, VB = 0 V, from zero scale
to full scale, ±0.5 LSB error band
RAB = 10 kΩ
RAB = 100 kΩ
RAB = 10 kΩ
RAB = 100 kΩ
THD
eN_WB
tS
Crosstalk (CW1/CW2)
CT
Analog Crosstalk
Endurance10
CTA
TA = 25°C
1.4
−60
Unit
µA
mA
µA
µA
µW
dB
3
0.43
MHz
MHz
−80
−90
dB
dB
7
20
nV/√Hz
nV/√Hz
2
12
10
25
−90
1
µs
µs
nV-sec
nV-sec
dB
Mcycles
kcycles
Years
100
Data Retention11, 12
Max
50
1
Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V.
2
Resistor integral nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB.
3
Guaranteed by design and characterization, not subject to production test.
4
INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of
±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground
referenced bipolar signal adjustment.
6
Different from operating current; supply current for EEPROM program lasts approximately 30 ms.
7
Different from operating current; supply current for EEPROM read lasts approximately 20 µs.
8
PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC).
9
All dynamic characteristics use VDD/VSS = ±2.5 V, and VLOGIC = 2.5 V.
10
Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C.
11
Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV, derates
with junction temperature in the Flash/EE memory.
12
50 years apply to an endurance of 1000 cycles. An endurance of 100,000 cycles has an equivalent retention lifetime of 5 years.
analog.com
Rev. C | 7 of 30
Data Sheet
AD5122A/AD5142A
SPECIFICATIONS
INTERFACE TIMING SPECIFICATIONS
VLOGIC = 1.8 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1
Test Conditions/Comments
fSCL2
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t11A
t12
tSP3
tRESET
tEEPROM_PROGRAM4
tEEPROM_READBACK
tPOWER_UP5
tRESET
Fast mode
Standard mode
Fast mode
Fast mode
0.1
Min
Typ
4.0
0.6
4.7
1.3
250
100
0
0
4.7
0.6
4
0.6
4.7
1.3
4
0.6
Max
Unit
Description
100
400
kHz
kHz
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
Serial clock frequency
3.45
0.9
1000
300
300
300
1000
300
1000
20 + 0.1 CL
20 + 0.1 CL
20 + 0.1 CL
20 + 0.1 CL
20 + 0.1 CL
0
15
7
30
300
300
300
50
10
50
30
75
ns
ns
ns
ns
µs
ms
µs
µs
µs
SCL high time, tHIGH
SCL low time, tLOW
Data setup time, tSU; DAT
Data hold time, tHD; DAT
Setup time for a repeated start condition, tSU; STA
Hold time (repeated) for a start condition, tHD; STA
Bus free time between a stop and a start condition, tBUF
Setup time for a stop condition, tSU; STO
Rise time of SDA signal, tRDA
Fall time of SDA signal, tFDA
Rise time of SCL signal, tRCL
Rise time of SCL signal after a repeated start condition and after an
acknowledge bit, tRCL1 (not shown in Figure 3)
Fall time of SCL signal, tFCL
Pulse width of suppressed spike (not shown in Figure 3)
RESET low time (not shown in Figure 3)
Memory program time (not shown in Figure 3)
Memory readback time (not shown in Figure 3)
Power-on EEPROM restore time (not shown in Figure 3)
Reset EEPROM restore time (not shown in Figure 3)
1
Maximum bus capacitance is limited to 400 pF.
2
The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate; however, it has a negative effect on the EMC
behavior of the part.
3
Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode.
4
The EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at lower temperatures and higher write cycles.
5
Maximum time after VDD − VSS is equal to 2.3 V.
analog.com
Rev. C | 8 of 30
Data Sheet
AD5122A/AD5142A
SPECIFICATIONS
SHIFT REGISTER AND TIMING DIAGRAMS
Figure 2. Input Shift Register Contents
Figure 3. I2C Serial Interface Timing Diagram (Typical Write Sequence)
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Rev. C | 9 of 30
Data Sheet
AD5122A/AD5142A
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 5.
Parameter
Rating
VDD to GND
VSS to GND
VDD to VSS
VLOGIC to GND
−0.3 V to +7.0 V
+0.3 V to −7.0 V
7V
−0.3 V to VDD + 0.3 V or
+7.0 V (whichever is less)
VSS − 0.3 V, VDD + 0.3 V
+7.0 V (whichever is less)
VA, VW, VB to GND
IA, IW, IB
Pulsed1
Frequency > 10 kHz2
RAW = 10 kΩ
RAW = 100 kΩ
Frequency ≤ 10 kHz2
RAW = 10 kΩ
RAW = 100 kΩ
Digital Inputs
Operating Temperature Range, TA3
Maximum Junction Temperature,
TJ Maximum
Storage Temperature Range
Reflow Soldering
Peak Temperature
Time at Peak Temperature
Package Power Dissipation
1
±6 mA/d
±1.5 mA/d
±6 mA/√d
±1.5 mA/√d
−0.3 V to VLOGIC + 0.3 V or
+7 V (whichever is less)
−40°C to +125°C
150°C
−65°C to +150°C
260°C
20 sec to 40 sec
(TJ max − TA)/θJA
Maximum terminal current is bounded by the maximum current handling of the
switches, maximum power dissipation of the package, and maximum applied
voltage across any two of the A, B, and W terminals at a given resistance.
2
d = pulse duty factor.
3
Includes programming of EEPROM memory.
Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
analog.com
θJA is defined by the JEDEC JESD51 standard, and the value is
dependent on the test board and test environment.
Table 6. Thermal Resistance
Package Type
θJA
θJC
Unit
16-Lead LFCSP
16-Lead TSSOP
89.51
3
27.6
°C/W
°C/W
1
150.41
JEDEC 2S2P test board, still air (0 m/sec airflow).
ELECTROSTATIC DISCHARGE (ESD) RATINGS
The following ESD information is provided for handling of ESD-sensitive devices in and ESD-protected area only.
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
Field induced charged device model (FICDM) and charged device
model (CDM) per ANSI/ESDA/JEDEC JS-002.
ESD RATINGS FOR AD5122A/AD5142A
Table 7. AD5122A/AD5142A, 16-Lead TSSOP and 16-Lead LFCSP
ESD Model
Withstand Threshold
(V)
Class
HBM
4000
3A
FICDM
1250
C3
Table 8. AD5122AW/AD5142AW, 16-Lead LFCSP
ESD Model
Withstand Threshold
(V)
Class
HBM
2000
2
FICDM
1250
C3
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although
this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
Rev. C | 10 of 30
Data Sheet
AD5122A/AD5142A
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 5. 16-Lead TSSOP Pin Configuration
Figure 4. 16-Lead LFCSP Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
16-Lead
LFCSP
16-Lead
TSSOP
Mnemonic
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
GND
A1
W1
B1
VSS
A2
W2
B2
VDD
VLOGIC
SCL
SDA
ADDR1
ADDR0
INDEP
16
2
RESET
Ground Pin, Logic Ground Reference.
Terminal A of RDAC1. VSS ≤ VA ≤ VDD.
Wiper Terminal of RDAC1. VSS ≤ VW ≤ VDD.
Terminal B of RDAC1. VSS ≤ VB ≤ VDD.
Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
Terminal A of RDAC2. VSS ≤ VA ≤ VDD.
Wiper Terminal of RDAC2. VSS ≤ VW ≤ VDD.
Terminal B of RDAC2. VSS ≤ VB ≤ VDD.
Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
Serial Clock Line.
Serial Data Input/Output.
Programmable Address (ADDR1) for Multiple Package Decoding.
Programmable Address (ADDR0) for Multiple Package Decoding.
Linear Gain Setting Mode at Power-Up. Each string resistor is loaded from its associated memory location. If INDEP is enabled,
it cannot be disabled by the software.
Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at logic low. If this pin is not used, tie
RESET to VLOGIC.
Exposed Pad. Connect this exposed pad to the potential of the VSS pin, or, alternatively, leave it electrically unconnected. It is
recommended that the pad be thermally connected to a copper plane for enhanced thermal performance.
EPAD
analog.com
Rev. C | 11 of 30
Data Sheet
AD5122A/AD5142A
TYPICAL PERFORMANCE CHARACTERISTICS
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Figure 6. R-INL vs. Code (AD5142A)
Figure 9. R-DNL vs. Code (AD5142A)
Figure 7. R-INL vs. Code (AD5122A)
Figure 10. R-DNL vs. Code (AD5122A)
Figure 8. INL vs. Code (AD5142A)
Figure 11. DNL vs. Code (AD5142A)
Rev. C | 12 of 30
Data Sheet
AD5122A/AD5142A
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 12. INL vs. Code (AD5122A)
Figure 15. ILOGIC vs. Temperature
Figure 13. Potentiometer Mode Temperature Coefficient ((ΔVW/VW)/ΔT × 106)
vs. Code
Figure 16. DNL vs. Code (AD5122A)
Figure 14. IDD vs. Temperature
Figure 17. Rheostat Mode Temperature Coefficient ((ΔRWB/RWB)/ΔT × 106) vs.
Code
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Rev. C | 13 of 30
Data Sheet
AD5122A/AD5142A
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 18. ILOGIC Current vs. Digital Input Voltage
Figure 21. Normalized Phase Flatness vs. Frequency, RAB = 10 kΩ
Figure 19. 10 kΩ Gain vs. Frequency and Code
Figure 22. 100 kΩ Gain vs. Frequency and Code
Figure 20. Total Harmonic Distortion Plus Noise (THD + N) vs. Frequency
Figure 23. Total Harmonic Distortion Plus Noise (THD + N) vs. Amplitude
analog.com
Rev. C | 14 of 30
Data Sheet
AD5122A/AD5142A
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 24. Normalized Phase Flatness vs. Frequency, RAB = 100 kΩ
Figure 27. Maximum Transition Glitch
Figure 28. Resistor Lifetime Drift
Figure 25. Incremental Wiper On Resistance vs. VDD
Figure 29. Power Supply Rejection Ratio (PSRR) vs. Frequency
Figure 26. Maximum Bandwidth vs. Code and Net Capacitance
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Rev. C | 15 of 30
Data Sheet
AD5122A/AD5142A
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 30. Digital Feedthrough
Figure 31. Shutdown Isolation vs. Frequency
Figure 32. Theoretical Maximum Current vs. Code
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Rev. C | 16 of 30
Data Sheet
AD5122A/AD5142A
TEST CIRCUITS
Figure 33 to Figure 37 define the test conditions used in the Specifications section.
Figure 33. Resistor Integral Nonlinearity Error (Rheostat Operation; R-INL,
R-DNL)
Figure 34. Potentiometer Divider Nonlinearity Error (INL, DNL)
Figure 36. Power Supply Sensitivity and Power Supply Rejection Ratio (PSS,
PSRR)
Figure 37. Incremental On Resistance
Figure 35. Wiper Resistance
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Rev. C | 17 of 30
Data Sheet
AD5122A/AD5142A
THEORY OF OPERATION
The AD5122A/AD5142A digital programmable potentiometers are
designed to operate as true variable resistors for analog signals
within the terminal voltage range of VSS < VTERM < VDD. The resistor wiper position is determined by the RDAC register contents. The
RDAC register acts as a scratchpad register that allows unlimited
changes of resistance settings. A secondary register (the input shift
register) can be used to preload the RDAC register data.
It is possible to both write to and read from the RDAC register using
the digital interface (see Table 10).
The contents of the RDAC register can be stored to the EEPROM
using Command 9 (see Table 10). Thereafter, the RDAC register
always sets at that position for any future on-off-on power supply
sequence. It is possible to read back data saved into the EEPROM
with Command 3 (see Table 10).
The RDAC register can be programmed with any position setting
using the I2C interface. When a desirable wiper position is found,
this value can be stored in the EEPROM memory. Thereafter, the
wiper position is always restored to that position for subsequent
power-ups. The storing of EEPROM data takes approximately 15
ms; during this time, the device is locked and does not acknowledge any new command, preventing any changes from taking
place.
INPUT SHIFT REGISTER
RDAC REGISTER AND EEPROM
If the AD5122A RDAC or EEPROM registers are read from or
written to, the lowest data bit (Bit 0) is ignored.
Alternatively, the EEPROM can be written to independently using
Command 11 (see Table 13).
For the AD5122A/AD5142A, the input shift register is 16 bits wide,
as shown in Figure 2. The 16-bit word consists of four control bits,
followed by four address bits and by eight data bits.
The RDAC register directly controls the position of the digital potentiometer wiper. For example, when the RDAC register is loaded with
0x80 (AD5142A, 256 taps), the wiper is connected to half scale of
the variable resistor. The RDAC register is a standard logic register;
there is no restriction on the number of changes allowed.
Data is loaded MSB first (Bit 15). The four control bits determine the
function of the software command, as listed in Table 10 and Table
13.
Table 10. Reduced Commands Operation Truth Table
Control
Bits[DB15:DB12]
Address
Bits[DB11:DB8]1
Data Bits[DB7:DB0]1
Command
Number
C3
C2
C1
C0
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Operation
0
1
0
0
0
0
0
0
0
1
X
0
X
0
X
0
X
A0
X
D7
X
D6
X
D5
X
D4
X
D3
X
D2
X
D1
X
D0
2
0
0
1
0
0
0
0
A0
D7
D6
D5
D4
D3
D2
D1
D0
3
0
0
1
1
0
0
A1
A0
X
X
X
X
X
X
D1
D0
9
10
14
15
0
0
1
1
1
1
0
1
1
1
1
0
1
1
1
0
0
0
X
A3
0
0
X
0
0
0
X
0
A0
A0
X
A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
X
D0
NOP: do nothing
Write contents of serial register data to
RDAC
Write contents of serial register data to
input shift register
Read back contents
D1
D0
Data
0
1
EEPROM
1
1
RDAC
Copy RDAC register to EEPROM
Copy EEPROM into RDAC
Software reset
Software shutdown
D0
Condition
0
Normal mode
1
Shutdown mode
1
X = don’t care.
Table 11. Reduced Address Bits Table
A3
A2
A1
A0
Channel
Stored Channel Memory
1
0
0
X1
X1
X1
0
0
0
0
0
1
All channels
RDAC1
RDAC2
Not applicable
RDAC1
Not applicable
analog.com
Rev. C | 18 of 30
Data Sheet
AD5122A/AD5142A
THEORY OF OPERATION
Table 11. Reduced Address Bits Table
A3
A2
A1
A0
Channel
Stored Channel Memory
0
0
1
0
Not applicable
RDAC2
1
X = don’t care.
I2C SERIAL DATA INTERFACE
Table 12. Device Address Selection
The AD5122A/AD5142A have 2-wire, I2C-compatible serial interfaces. The device can be connected to an I2C bus as a slave device,
under the control of a master device. See Figure 3 for a timing
diagram of a typical write sequence.
ADDR0 Pin
ADDR1 Pin
7-Bit I2C Device Address
VLOGIC
No connect1
GND
VLOGIC
No connect1
GND
VLOGIC
No connect1
GND
VLOGIC
VLOGIC
VLOGIC
No connect1
No connect1
No connect1
GND
GND
GND
0100000
0100010
0100011
0101000
0101010
0101011
0101100
0101110
0101111
The AD5122A/AD5142A supports standard (100 kHz) and fast
(400 kHz) data transfer modes. Support is not provided for 10-bit
addressing and general call addressing.
The 2-wire serial bus protocol operates as follows:
1. The master initiates a data transfer by establishing a start
condition, which is when a high-to-low transition on the SDA
line occurs while SCL is high. The following byte is the address
byte, which consists of the 7-bit slave address and an R/W
bit. The slave device corresponding to the transmitted address
responds by pulling SDA low during the ninth clock pulse (this is
called the acknowledge bit). At this stage, all other devices on
the bus remain idle while the selected device waits for data to
be written to, or read from, its shift register.If the R/W bit is set
high, the master reads from the slave device. However, if the
R/W bit is set low, the master writes to the slave device.
2. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge bit).
The transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of SCL.
3. When all data bits have been read from or written to, a stop
condition is established. In write mode, the master pulls the
SDA line high during the tenth clock pulse to establish a stop
condition. In read mode, the master issues a no acknowledge
for the ninth clock pulse (that is, the SDA line remains high).
The master then brings the SDA line low before the tenth clock
pulse, and then high again during the tenth clock pulse to
establish a stop condition.
1
Not available in bipolar mode (VSS < 0 V) or in low voltage mode (VLOGIC = 1.8
V).
Write Operation
When writing to the AD5122A/AD5142A, the user must begin with
a start command followed by an address byte (R/W = 0), after
which the device acknowledges that it is prepared to receive data
by pulling SDA low.
Two bytes of data are then written to the DAC, the most significant
byte followed by the least significant byte. Both of these data bytes
are acknowledged by the AD5122A/AD5142A. A stop condition
follows. The write operations for the AD5122A/AD5142A are shown
in Figure 38.
A repeated write function gives the user flexibility to update the
device a number of times after addressing the device only once, as
shown in Figure 39.
I2C Address
The facility to make hardwired changes to ADDR allows the user to
incorporate up to nine of these devices on one bus as outlined in
Table 12.
analog.com
Rev. C | 19 of 30
Data Sheet
AD5122A/AD5142A
THEORY OF OPERATION
Figure 38. AD5122A/AD5142A Interface Write Command
Figure 39. AD5122A/AD5142A Interface Multiple Write
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Rev. C | 20 of 30
Data Sheet
AD5122A/AD5142A
THEORY OF OPERATION
EEPROM Write Acknowledge Polling
After each write operation to the EEPROM, an internal write cycle
begins. The I2C interface of the device is disabled. To determine
if the internal write cycle is complete and the I2C interface is
enabled, interface polling can be executed. I2C interface polling can
be conducted by sending a start condition, followed by the slave
address and the write bit. If the I2C interface responds with an
acknowledge, the write cycle is complete, and the interface is ready
to proceed with further operations. Otherwise, I2C interface polling
can be repeated until it succeeds.
Read Operation
The AD5122A/AD5142A allow readback of the contents of the
RDAC register and EEPROM memory through the I2C interface by
using Command 3 (see Table 13).
When reading data back from the AD5122A/AD5142A, the user
must first issue a readback command to the device. The readback
command begins with a start command, followed by an address
byte (R/W = 0), after which the device acknowledges that it is
prepared to receive data by pulling SDA low.
Two bytes of data are then written to the AD5122A/AD5142A, the
most significant byte followed by the least significant byte. Both
of these data bytes are acknowledged by the AD5122A/AD5142A.
A stop condition follows. These bytes contain the read instruction,
which enables readback of the RDAC register and EEPROM memory. The user can then read back the data. The readback begins
with a start command followed by an address byte (R/W = 1),
after which the device acknowledges that it is prepared to transmit
data by pulling SDA low. Two bytes of data are then read from
the device, which are both acknowledged by the master, as shown
in Figure 40. A stop condition follows. If the master does not
acknowledge the first byte, the second byte is not transmitted by
the AD5122A/AD5142A.
The AD5122A/AD5142A do not support repeat readback.
Figure 40. AD5122A/AD5142A Interface Read Command
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Rev. C | 21 of 30
Data Sheet
AD5122A/AD5142A
THEORY OF OPERATION
ADVANCED CONTROL MODES
►
The AD5122A/AD5142A digital potentiometers include a set of user
programming features to address the wide number of applications
for these universal adjustment devices (see Table 13 and Table 15).
►
►
►
►
Key programming features include the following:
►
►
Input register
►
Linear gain setting mode
A low wiper resistance feature
Linear increment and decrement instructions
±6 dB increment and decrement instructions
Burst mode
Reset
Shutdown mode
Table 13. Advanced Command Operation Truth Table
Command
Bits[DB15:DB12]
Address Bits[DB11:DB8]1
Data Bits[DB7:DB0]1
Command
Number
C3
C2
C1
C0
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Operation
0
1
0
0
0
0
0
0
0
1
X
0
X
A2
X
0
X
A0
X
D7
X
D6
X
D5
X
D4
X
D3
X
D2
X
D1
X
D0
2
0
0
1
0
0
A2
0
A0
D7
D6
D5
D4
D3
D2
D1
D0
3
0
0
1
1
X
A2
A1
A0
X
X
X
X
X
X
D1
D0
4
5
6
7
8
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
0
0
1
1
0
A3
A3
A3
A3
0
A2
A2
A2
A2
A2
0
0
0
0
0
A0
A0
A0
A0
A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
1
0
X
9
10
11
0
0
1
1
1
0
1
1
0
1
1
0
0
0
0
A2
A2
0
0
0
A1
A0
A0
A0
X
X
D7
X
X
D6
X
X
D5
X
X
D4
X
X
D3
X
X
D2
X
X
D1
1
0
D0
12
1
0
0
1
A3
A2
0
A0
1
X
X
X
X
X
X
D0
13
1
0
0
1
A3
A2
0
A0
0
X
X
X
X
X
X
D0
14
15
1
1
0
1
1
0
1
0
X
A3
X
A2
X
0
X
A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D0
16
1
1
0
1
X
X
X
X
X
X
X
X
D3
D2
D1
D0
NOP: do nothing
Write contents of serial register data
to RDAC
Write contents of serial register data
to input register
Read back contents
D1
D0
Data
0
0
Input register
0
1
EEPROM
1
0
Control register
1
1
RDAC
Linear RDAC increment
Linear RDAC decrement
+6 dB RDAC increment
−6 dB RDAC decrement
Copy input register to RDAC
(software LRDAC)
Copy RDAC register to EEPROM
Copy EEPROM into RDAC
Write contents of serial register data
to EEPROM
Top scale
D0 = 0; normal mode
D0 = 1; shutdown mode
Bottom scale
D0 = 1; enter
D0 = 0; exit
Software reset
Software shutdown
D0 = 0; normal mode
D0 = 1; device placed in shutdown
mode
Copy serial register data to control
register, refer to Table 15
1
X = don’t care.
analog.com
Rev. C | 22 of 30
Data Sheet
AD5122A/AD5142A
THEORY OF OPERATION
Table 14. Address Bits
Potentiometer Mode
Linear Gain Setting Mode
A3
A2
A1
A0
Input Register
RDAC Register
Input Register
RDAC Register
Stored Channel Memory
1
0
0
0
0
0
0
X1
0
1
0
1
0
0
X1
0
0
0
0
1
1
X1
0
0
1
1
0
1
All channels
RDAC1
Not applicable
RDAC2
Not applicable
Not applicable
Not applicable
All channels
RDAC1
Not applicable
RDAC2
Not applicable
Not applicable
Not applicable
All channels
RWB1
RAW1
RWB2
RAW2
Not applicable
Not applicable
All channels
RWB1
RAW1
RWB2
RAW2
Not applicable
Not applicable
Not applicable
RDAC1/RWB1
Not applicable
RAW1
Not applicable
RDAC2/RWB2
RAW2
1
X = don’t care.
Table 15. Control Register Bit Descriptions
Bit Name
Description
D0
RDAC register write protect
0 = wiper position frozen to value in EEPROM memory
1 = allows update of wiper position through digital interface (default)
EEPROM program enable
0 = EEPROM program disabled
1 = enables device for EEPROM program (default)
Linear setting mode/potentiometer mode
0 = potentiometer mode (default)
1 = linear gain setting mode
Burst mode (I2C only)
0 = disabled (default)
1 = enabled (no disable after stop or repeated start condition)
D1
D2
D3
analog.com
Rev. C | 23 of 30
Data Sheet
AD5122A/AD5142A
THEORY OF OPERATION
Input Register
The AD5122A/AD5142A include one input register per RDAC register. These registers allow preloading of the value for the associated
RDAC register. These registers can be written to using Command 2
and read back from using Command 3 (see Table 13).
This feature allows a synchronous update of one or both RDAC
registers at the same time.
The transfer from the input register to the RDAC register is done
synchronously by Command 8 (see Table 13).
If new data is loaded in an RDAC register, this RDAC register
automatically overwrites the associated input register.
Linear Gain Setting Mode
The proprietary architecture of the AD5122A/AD5142A allows the
independent control of each string resistor, RAW, and RWB. To
enable linear gain setting mode, use Command 16 (see Table 13)
to set Bit D2 of the control register (see Table 15).
This mode of operation can control the potentiometer as two independent rheostats connected at a single point, W terminal, as
opposed to potentiometer mode where each resistor is complementary, RAW = RAB − RWB.
This mode enables a second input and an RDAC register per
channel, as shown in Table 13; however, the actual RDAC contents
remain unchanged. The same operations are valid for potentiometer and linear gain setting mode.
If the INDEP pin is pulled high, the device powers up in linear gain
setting mode and loads the values stored in the associated memory
locations for each channel (see Table 14). The INDEP pin and the
D2 bit are connected internally to a logic OR gate; if one or both are
set to 1, the parts cannot operate in potentiometer mode.
Low Wiper Resistance Feature
The AD5122A/AD5142A include two commands to reduce the wiper resistance between the terminals when the device achieves full
scale or zero scale. These extra positions are called bottom scale,
BS, and top scale, TS. The resistance between Terminal A and
Terminal W at top scale is specified as RTS. Similarly, the bottom
scale resistance between Terminal B and Terminal W is specified as
RBS.
The contents of the RDAC registers are unchanged by entering in
these positions. There are three ways to exit from top scale and
bottom scale: by using Command 12 or Command 13 (see Table
13); by loading new data in an RDAC register, which includes
increment/decrement operations; or by entering shutdown mode,
Command 15 (see Table 13).
Table 16 and Table 17 show the truth tables for the top scale position and the bottom scale position, respectively, when potentiometer
or linear gain setting mode is enabled.
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Table 16. Top Scale Truth Table
Linear Gain Setting Mode
Potentiometer Mode
RAW
RWB
RAW
RWB
RAB
RAB
RTS
RAB
Table 17. Bottom Scale Truth Table
Linear Gain Setting Mode
Potentiometer Mode
RAW
RWB
RAW
RWB
RTS
RBS
RAB
RBS
Linear Increment and Decrement Instructions
The increment and decrement commands (Command 4 and Command 5 in Table 13) are useful for linear step adjustment applications. These commands simplify microcontroller software coding
by allowing the controller to send an increment or decrement
command to the device. The adjustment can be individual or in a
ganged potentiometer arrangement, where all wiper positions are
changed at the same time.
For an increment command, executing Command 4 automatically
moves the wiper to the next RDAC position. This command can be
executed in a single channel or in multiple channels.
±6 dB Increment and Decrement Instructions
Two programming instructions produce logarithmic taper increment
or decrement of the wiper position control by an individual potentiometer or by a ganged potentiometer arrangement where all
RDAC register positions are changed simultaneously. The +6 dB
increment is activated by Command 6, and the −6 dB decrement
is activated by Command 7 (see Table 13). For example, starting
with the zero-scale position and executing Command 6 ten times
moves the wiper in 6 dB steps to the full-scale position. When the
wiper position is near the maximum setting, the last 6 dB increment
instruction causes the wiper to go to the full-scale position (see
Table 18).
Incrementing the wiper position by +6 dB essentially doubles the
RDAC register value, whereas decrementing the wiper position by
−6 dB halves the register value. Internally, the AD5122A/AD5142A
use shift registers to shift the bits left and right to achieve a ±6
dB increment or decrement. These functions are useful for various
audio/video level adjustments, especially for white LED brightness
settings in which human visual responses are more sensitive to
large adjustments than to small adjustments.
Table 18. Detailed Left Shift and Right Shift Functions for the ±6 dB Step
Increment and Decrement
Left Shift (+6 dB/Step)
Right Shift (−6 dB/Step)
0000 0000
0000 0001
0000 0010
0000 0100
0000 1000
1111 1111
0111 1111
0011 1111
0001 1111
0000 1111
Rev. C | 24 of 30
Data Sheet
AD5122A/AD5142A
THEORY OF OPERATION
Table 18. Detailed Left Shift and Right Shift Functions for the ±6 dB Step
Increment and Decrement
Left Shift (+6 dB/Step)
Right Shift (−6 dB/Step)
0001 0000
0010 0000
0100 0000
1000 0000
1111 1111
0000 0111
0000 0011
0000 0001
0000 0000
0000 0000
EEPROM OR RDAC REGISTER PROTECTION
The EEPROM and RDAC registers can be protected by disabling
any update to these registers. This can be done by using software.
If these registers are protected by software, set Bit D0 and/or Bit D1
(see Table 15), which protects the RDAC and EEPROM registers
independently.
When RDAC is protected, the only operation allowed is to copy the
EEPROM into the RDAC register.
Burst Mode
INDEP PIN
By enabling the burst mode, multiple data bytes can be sent to the
part consecutively. After the command byte, the part interprets the
following consecutive bytes as data bytes for the command.
If the INDEP pin is pulled high at power-up, the part operates in
linear gain setting mode, loading each string resistor, RAWX and
RWBX, with the value stored into the EEPROM (see Table 14). If the
pin is pulled low, the part powers up in potentiometer mode.
A new command can be sent by generating a repeat start or by a
stop and start condition.
The burst mode is activated by setting Bit D3 of the control register
(see Table 15).
The INDEP pin and the D2 bit are connected internally to a logic
OR gate; if one or both are set to 1, the part cannot operate in
potentiometer mode (see Table 15).
RDAC ARCHITECTURE
Reset
The AD5122A/AD5142A can be reset through software by executing Command 14 (see Table 13) or through hardware on the low
pulse of the RESET pin. The reset command loads the RDAC registers with the contents of the EEPROM and takes approximately
30 µs. The EEPROM is preloaded to midscale at the factory, and
initial power-up is, accordingly, at midscale. Tie RESET to VLOGIC if
the RESET pin is not used.
To achieve optimum performance, Analog Devices, Inc., has proprietary RDAC segmentation architecture for all the digital potentiometers. In particular, the AD5122A/AD5142A employ a three‑stage
segmentation approach, as shown in Figure 41. The AD5122A/
AD5142A wiper switch is designed with the transmission gate
CMOS topology and with the gate voltage derived from VDD and
VSS.
Shutdown Mode
The AD5122A/AD5142A can be placed in shutdown mode by executing the software shutdown command, Command 15 (see Table
13), and setting the LSB (D0) to 1. This feature places the RDAC
in a zero power consumption state where the device operates in
potentiometer mode, Terminal A is open-circuited and the wiper,
Terminal W, is connected to Terminal B; however, a finite wiper
resistance of 40 Ω is present. When the device is configured in
linear gain setting mode, the resistor addressed, RAW or RWB,
is internally placed at high impedance. Table 19 shows the truth
table depending on the device operating mode. The contents of
the RDAC register are unchanged by entering shutdown mode.
However, all commands listed in Table 13 are supported while in
shutdown mode. Execute Command 15 (see Table 13) and set the
LSB (D0) to 0 to exit shutdown mode.
Figure 41. AD5122A/AD5142A Simplified RDAC Circuit
Table 19. Truth Table for Shutdown Mode
Linear Gain Setting Mode
Potentiometer Mode
RAW
RWB
RAW
RWB
High impedance
High impedance
High impedance
RBS
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Top Scale/Bottom Scale Architecture
In addition, the AD5122A/AD5142A include new positions to reduce the resistance between terminals. These positions are called
bottom scale and top scale. At bottom scale, the typical wiper
resistance decreases from 130 Ω to 60 Ω (RAB = 100 kΩ). At
top scale, the resistance between Terminal A and Terminal W is
Rev. C | 25 of 30
Data Sheet
AD5122A/AD5142A
THEORY OF OPERATION
decreased by 1 LSB, and the total resistance is reduced to 60 Ω
(RAB = 100 kΩ).
PROGRAMMING THE VARIABLE RESISTOR
If the part is configured in linear gain setting mode, the resistance
between Terminal W and Terminal A is directly proportional to the
code loaded in the associate RDAC register. The general equations
for this operation are
Rheostat Operation—±8% Resistor Tolerance
AD5122A:
The AD5122A/AD5142A operate in rheostat mode when only two
terminals are used as a variable resistor. The unused terminal can
be floating, or it can be tied to Terminal W, as shown in Figure 42.
D
RAW D = 128
× RAB + RW From 0x00 to 0x7F
(5)
D
RAW D = 256
× RAB + RW From 0x00 to 0xFF
(6)
where:
D is the decimal equivalent of the binary code in the 7-bit/8-bit
RDAC register.
RAB is the end-to-end resistance.
RW is the wiper resistance.
Figure 42. Rheostat Mode Configuration
The nominal resistance between Terminal A and Terminal B, RAB,
is 10 kΩ or 100 kΩ, and has 128/256 tap points accessed by the
wiper terminal. The 7-bit/8-bit data in the RDAC latch is decoded
to select one of the 128/256 possible wiper settings. The general
equations for determining the digitally programmed output resistance between Terminal W and Terminal B are
AD5122A:
D
RWB D = 128
× RAB + RW From 0x00 to 0x7F
(1)
D
RWB D = 256
× RAB + RW From 0x00 to 0xFF
(2)
AD5142A:
where:
D is the decimal equivalent of the binary code in the 7-bit/8-bit
RDAC register.
RAB is the end-to-end resistance.
RW is the wiper resistance.
AD5122A:
−D
RAW D = 128
128 × RAB + RW From 0x00 to 0x7F
(3)
−D
RAW D = 256
256 × RAB + RW From 0x00 to 0xFF
(4)
AD5142A:
D is the decimal equivalent of the binary code in the 7-bit/8-bit
RDAC register.
RAB is the end-to-end resistance.
RW is the wiper resistance.
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In the bottom scale condition or top scale condition, a finite total
wiper resistance of 40 Ω is present. Regardless of which setting the
part is operating in, limit the current between Terminal A to Terminal
B, Terminal W to Terminal A, and Terminal W to Terminal B, to
the maximum continuous current or to the pulse current specified
in Table 5. Otherwise, degradation or possible destruction of the
internal switch contact can occur.
PROGRAMMING THE POTENTIOMETER
DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A that is proportional to the input voltage at
A to B, as shown in Figure 43.
In potentiometer mode, similar to the mechanical potentiometer, the
resistance between Terminal W and Terminal A also produces a
digitally controlled complementary resistance, RWA. RWA also gives
a maximum of 8% absolute resistance error. RWA starts at the
maximum resistance value and decreases as the data loaded into
the latch increases. The general equations for this operation are
where:
AD5142A:
Figure 43. Potentiometer Mode Configuration
Connecting Terminal A to 5 V and Terminal B to ground produces
an output voltage at the Wiper W to Terminal B ranging from 0 V
to 5 V. The general equation defining the output voltage at VW with
respect to ground for any valid input voltage applied to Terminal A
and Terminal B is
VW D =
where:
RWB D
RAB
× VA +
RAW D
RAB
× VB
(7)
RWB(D) can be obtained from Equation 1 and Equation 2.
RAW(D) can be obtained from Equation 3 and Equation 4.
Operation of the digital potentiometer in the divider mode results
in a more accurate operation over temperature. Unlike the rheostat
mode, the output voltage is dependent mainly on the ratio of the
Rev. C | 26 of 30
Data Sheet
AD5122A/AD5142A
THEORY OF OPERATION
internal resistors, RAW and RWB, and not the absolute values.
Therefore, the temperature drift reduces to 5 ppm/°C.
TERMINAL VOLTAGE OPERATING RANGE
The AD5122A/AD5142A are designed with internal ESD diodes
for protection. These diodes also set the voltage boundary of the
terminal operating voltages. Positive signals present on Terminal
A, Terminal B, or Terminal W that exceed VDD are clamped by the
forward-biased diode. There is no polarity constraint between VA,
VW, and VB, but they cannot be higher than VDD or lower than VSS.
Figure 44. Maximum Terminal Voltages Set by VDD and VSS
POWER-UP SEQUENCE
Because there are diodes to limit the voltage compliance at Terminal A, Terminal B, and Terminal W (see Figure 44), it is important to
power up VDD first before applying any voltage to Terminal A, Terminal B, and Terminal W. Otherwise, the diode is forward-biased such
that VDD is powered unintentionally. The ideal power-up sequence
is VSS, VDD, VLOGIC, digital inputs, and VA, VB, and VW. The order
of powering VA, VB, VW, and digital inputs is not important as long
as they are powered after VSS, VDD, and VLOGIC. Regardless of
the power-up sequence and the ramp rates of the power supplies,
once VDD is powered, the power-on preset activates, which restores
EEPROM values to the RDAC registers.
LAYOUT AND POWER SUPPLY BIASING
It is always a good practice to use a compact, minimum lead length
layout design. Ensure that the leads to the input are as direct as
possible with a minimum conductor length. Ground paths should
have low resistance and low inductance. It is also good practice to
bypass the power supplies with quality capacitors. Apply low equivalent series resistance (ESR) 1 µF to 10 µF tantalum or electrolytic
capacitors at the supplies to minimize any transient disturbance and
to filter low frequency ripple. Figure 45 illustrates the basic supply
bypassing configuration for the AD5122A/AD5142A.
Figure 45. Power Supply Bypassing
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Rev. C | 27 of 30
Data Sheet
AD5122A/AD5142A
OUTLINE DIMENSIONS
Figure 46. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-22)
Dimensions shown in millimeters
Figure 47. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
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Rev. C | 28 of 30
Data Sheet
AD5122A/AD5142A
OUTLINE DIMENSIONS
Updated: March 08, 2022
ORDERING GUIDE
Model1, 2
Temperature Range
Package Description
Packing Quantity
Package
Option
AD5122ABCPZ100-RL7
AD5122ABCPZ10-RL7
AD5122ABRUZ10
AD5122ABRUZ100
AD5122ABRUZ100-RL7
AD5122ABRUZ10-RL7
AD5122AWBCPZ10-RL7
AD5142ABCPZ100-RL7
AD5142ABCPZ10-RL7
AD5142ABRUZ10
AD5142ABRUZ100
AD5142ABRUZ100-RL7
AD5142ABRUZ10-RL7
AD5142AWBCPZ10-RL7
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
16-Lead LFCSP (3mm x 3mm w/ EP)
16-Lead LFCSP (3mm x 3mm w/ EP)
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead LFCSP (3mm x 3mm w/ EP)
16-Lead LFCSP (3mm x 3mm w/ EP)
16-Lead LFCSP (3mm x 3mm w/ EP)
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead LFCSP (3mm x 3mm w/ EP)
Reel, 1500
Reel, 1500
Tube, 96
Tube, 96
Reel, 1000
Reel, 1000
Reel, 1500
Reel, 1500
Reel, 1500
Tube, 96
Tube, 96
Reel, 1000
Reel, 1000
Reel, 1500
CP-16-22
CP-16-22
RU-16
RU-16
RU-16
RU-16
CP-16-22
CP-16-22
CP-16-22
RU-16
RU-16
RU-16
RU-16
CP-16-22
1
Z = RoHS Compliant Part.
2
W = Qualified for Automotive Applications.
Marking Code
DHG
DHA
DN1
DH4
DH7
DMZ
RAB (KΩ), RESOLUTION, AND INTERFACE OPTIONS
Model1, 2
RAB (kΩ)
Resolution
Interface
AD5122ABCPZ10-RL7
AD5122ABCPZ100-RL7
AD5122AWBCPZ10-RL7
AD5122ABRUZ10
AD5122ABRUZ100
AD5122ABRUZ10-RL7
AD5122ABRUZ100-RL7
AD5142ABCPZ10-RL7
AD5142ABCPZ100-RL7
AD5142AWBCPZ10-RL7
AD5142ABRUZ10
AD5142ABRUZ100
AD5142ABRUZ10-RL7
AD5142ABRUZ100-RL7
10
100
10
10
100
10
100
10
100
10
10
100
10
100
128
128
128
128
128
128
128
256
256
256
256
256
256
256
I 2C
I2C
I2C
I 2C
I2C
I2C
I 2C
I2C
I2C
I 2C
I2C
I2C
I 2C
I2C
1
Z = RoHS Compliant Part.
2
W = Qualified for Automotive Applications.
EVALUATION BOARDS
Model1, 2
Description
EVAL-AD5142ADBZ
Evaluation Board
1
Z = RoHS Compliant Part.
2
The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with both of the available resistor value options.
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Rev. C | 29 of 30
Data Sheet
AD5122A/AD5142A
OUTLINE DIMENSIONS
AUTOMOTIVE PRODUCTS
The AD5122AW/AD5142AW models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should
review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive
applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific
Automotive Reliability reports for these models.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2012-2022 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887-2356, U.S.A.
Rev. C | 30 of 30