AD5124BRUZ10-RL7

Data Sheet AD5124/AD5144/AD5144A Quad Channel, 128-/256-Position, I2C/SPI, Nonvolatile Digital Potentiometer FEATURES ► ► ► ► ► ► ► ► ► ► ► FUNCTIONAL BLOCK DIAGRAM 10 kΩ and 100 kΩ resistance options Resistor tolerance: 8% maximum Wiper current: ±6 mA Low temperature coefficient: 35 ppm/°C Wide bandwidth: 3 MHz Fast start-up time < 75 µs Linear gain setting mode Single- and dual-supply operation Independent logic supply: 1.8 V to 5.5 V Wide operating temperature: −40°C to +125°C 4 mm × 4 mm package option APPLICATIONS Figure 1. AD5124/AD5144 24-Lead LFCSP Portable electronics level adjustment ► LCD panel brightness and contrast controls ► Programmable filters, delays, and time constants ► Programmable power supplies ► GENERAL DESCRIPTION The AD5124/AD5144/AD5144A potentiometers provide a nonvolatile solution for 128-/256-position adjustment applications, offering guaranteed low resistor tolerance errors of ±8% and up to ±6 mA current density in the Ax, Bx, and Wx pins. The low resistor tolerance and low nominal temperature coefficient simplify open-loop applications as well as applications requiring tolerance matching. The linear gain setting mode allows independent programming of the resistance between the digital potentiometer terminals, through the RAW and RWB string resistors, allowing very accurate resistor matching. The high bandwidth and low total harmonic distortion (THD) ensure optimal performance for ac signals, making these devices suitable for filter design. The low wiper resistance of only 40 Ω at the ends of the resistor array allow for pin-to-pin connection. Table 1. Family Models Model Channel Position Interface Package AD51231 AD5124 AD5124 AD51431 AD5144 AD5144 AD5144A AD5122 AD5122A AD5142 AD5142A AD5121 AD5141 Quad Quad Quad Quad Quad Quad Quad Dual Dual Dual Dual Single Single 128 128 128 256 256 256 256 128 128 256 256 128 256 I 2C SPI/I2C SPI I2C SPI/I2C SPI I 2C SPI I2C SPI I2C SPI/I2C SPI/I2C LFCSP LFCSP TSSOP LFCSP LFCSP TSSOP TSSOP LFCSP/TSSOP LFCSP/TSSOP LFCSP/TSSOP LFCSP/TSSOP LFCSP LFCSP 1 Two potentiometers and two rheostats. The wiper values can be set through an SPI-/I2C-compatible digital interface that is also used to read back the wiper register and EEPROM contents. The AD5124/AD5144/AD5144A are available in a compact, 24lead, 4 mm × 4 mm LFCSP and a 20-lead TSSOP. The parts are guaranteed to operate over the extended industrial temperature range of −40°C to +125°C. Rev. D DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Data Sheet AD5124/AD5144/AD5144A TABLE OF CONTENTS Features................................................................ 1 Applications........................................................... 1 Functional Block Diagram......................................1 General Description...............................................1 Functional Block Diagrams—TSSOP.................... 3 Specifications........................................................ 4 Electrical Characteristics—AD5124................... 4 Electrical Characteristics—AD5144 and AD5144A.......................................................... 7 Interface Timing Specifications........................ 10 Shift Register and Timing Diagrams.................12 Absolute Maximum Ratings.................................14 Thermal Resistance......................................... 14 Electrostatic Discharge (ESD) Ratings.............14 ESD Ratings for AD5124/AD5144/AD5144A... 14 ESD Caution.....................................................14 Pin Configurations and Function Descriptions.....15 Typical Performance Characteristics................... 18 Test Circuits......................................................... 23 Theory of Operation.............................................24 RDAC Register and EEPROM......................... 24 Input Shift Register...........................................24 Serial Data Digital Interface Selection, DIS......25 SPI Serial Data Interface..................................25 I2C Serial Data Interface.................................. 27 Advanced Control Modes................................. 30 EEPROM or RDAC Register Protection...........33 Load RDAC Input Register (LRDAC)............... 33 RDAC Architecture........................................... 33 Programming the Variable Resistor..................34 Programming the Potentiometer Divider.......... 35 Terminal Voltage Operating Range.................. 35 Power-Up Sequence........................................ 35 Layout and Power Supply Biasing....................35 Outline Dimensions............................................. 36 Ordering Guide.................................................37 RAB (kΩ), Resolution, and Interface Options....37 Evaluation Boards............................................ 37 REVISION HISTORY 5/2022—Rev. C to Rev. D Changes to Nominal Resistance Match Parameter, Single-Supply Power Range Parameter, DualSupply Power Range Parameter, and Logic Supply Range Parameter, Table 2........................................... 4 Changes to Nominal Resistance Match Parameter, Single-Supply Power Range Parameter, DualSupply Power Range Parameter, and Logic Supply Range Parameter, Table 3........................................... 7 Deleted FICDM Parameter, Table 7............................................................................................................... 14 Added Electrostatic Discharge Ratings Section.............................................................................................14 Added ESD Ratings for AD5124/AD5144/AD5144A Section and Table 9; Renumbered Sequentially......... 14 Moved Table 13 and Table 14........................................................................................................................ 24 Added Write Operation Section, Figure 46, and Figure 47; Renumbered Sequentially.................................27 Added EEPROM Write Acknowledge Polling Section................................................................................... 29 Added Read Operation Section and Figure 48.............................................................................................. 29 Moved Table 17, Table 18, and Table 19....................................................................................................... 30 Added RAB (kΩ), Resolution, and Interface Options Section......................................................................... 37 analog.com Rev. D | 2 of 38 Data Sheet AD5124/AD5144/AD5144A FUNCTIONAL BLOCK DIAGRAMS—TSSOP Figure 2. AD5124/AD5144 20-Lead TSSOP analog.com Figure 3. AD5144A 20-Lead TSSOP Rev. D | 3 of 38 Data Sheet AD5124/AD5144/AD5144A SPECIFICATIONS ELECTRICAL CHARACTERISTICS—AD5124 VDD = 2.3 V to 5.5 V, VSS = 0 V; VDD = 2.25 V to 2.75 V, VSS = −2.25 V to −2.75 V; VLOGIC = 1.8 V to 5.5 V, −40°C < TA < +125°C, unless otherwise noted. Table 2. Parameter Symbol DC CHARACTERISTICS—RHEOSTAT MODE (ALL RDACs) Resolution N 2 Resistor Integral Nonlinearity R-INL Resistor Differential Nonlinearity2 Nominal Resistor Tolerance Resistance Temperature Coefficient3 Wiper Resistance3 Bottom Scale or Top Scale Nominal Resistance Match DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (ALL RDACs) Integral Nonlinearity4 Differential Nonlinearity4 Full-Scale Error Zero-Scale Error Voltage Divider Temperature Coefficient3 RESISTOR TERMINALS Maximum Continuous Current R-DNL ΔRAB/RAB (ΔRAB/RAB)/ΔT × 106 RW Test Conditions/Comments Capacitance W3 analog.com Typ1 Max 7 RAB = 10 kΩ VDD ≥ 2.7 V VDD < 2.7 V RAB = 100 kΩ VDD ≥ 2.7 V VDD < 2.7 V Unit Bits −1 −2.5 ±0.1 ±1 +1 +2.5 LSB LSB −0.5 −1 −0.5 −8 ±0.1 ±0.25 ±0.1 ±1 35 +0.5 +1 +0.5 +8 LSB LSB LSB % ppm/°C 55 130 125 400 Ω Ω −1 40 60 ±0.2 80 230 +1 Ω Ω % RAB = 10 kΩ RAB = 100 kΩ −0.5 −0.25 −0.25 ±0.1 ±0.1 ±0.1 +0.5 +0.25 +0.25 LSB LSB LSB RAB = 10 kΩ RAB = 100 kΩ −1.5 −0.5 −0.1 ±0.1 +0.5 LSB LSB Code = full scale Code = zero scale RAB = 10 kΩ RAB = 100 kΩ RBS or RTS RAB1/RAB2 RAB = 10 kΩ RAB = 100 kΩ Code = full scale INL DNL VWFSE VWZSE (ΔVW/VW)/ΔT × 106 RAB = 10 kΩ RAB = 100 kΩ Code = half scale 1 0.25 ±5 1.5 0.5 LSB LSB ppm/°C +6 +1.5 VDD mA mA V IA, IB, and IW RAB = 10 kΩ RAB = 100 kΩ Terminal Voltage Range5 Capacitance A, Capacitance B3 Min CA, CB CW f = 1 MHz, measured to GND, code = half scale RAB = 10 kΩ RAB = 100 kΩ f = 1 MHz, measured to GND, code = half scale RAB = 10 kΩ −6 −1.5 VSS 25 12 pF pF 12 pF Rev. D | 4 of 38 Data Sheet AD5124/AD5144/AD5144A SPECIFICATIONS Table 2. Parameter Symbol Common-Mode Leakage Current3 DIGITAL INPUTS Input Logic3 High Low Input Hysteresis3 Input Current3 Input Capacitance3 DIGITAL OUTPUTS Output High Voltage3 Output Low Voltage3 Three-State Leakage Current Three-State Output Capacitance POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Logic Supply Range Positive Supply Current Negative Supply Current EEPROM Store Current3, 6 EEPROM Read Current3, 7 Logic Supply Current Power Dissipation8 Power Supply Rejection Ratio DYNAMIC CHARACTERISTICS9 Bandwidth Total Harmonic Distortion Resistor Noise Density VW Settling Time Crosstalk (CW1/CW2) analog.com VINH Min Typ1 RAB = 100 kΩ VA = VW = VB −500 5 ±15 VLOGIC = 1.8 V to 2.3 V VLOGIC = 2.3 V to 5.5 V 0.8 × VLOGIC 0.7 × VLOGIC Test Conditions/Comments VINL VHYST IIN CIN VOH VOL Max Unit +500 pF nA 0.2 × VLOGIC 0.1 × VLOGIC ±1 5 RPULL-UP = 2.2 kΩ to VLOGIC ISINK = 3 mA ISINK = 6 mA, VLOGIC > 2.3 V VLOGIC −1 0.4 0.6 +1 V V V µA pF 5.5 ±2.75 VDD VDD V V V V 5.5 µA nA µA mA µA µA µW dB 2 VDD VDD/VSS VLOGIC IDD ISS IDD_EEPROM_STORE IDD_EEPROM_READ ILOGIC PDISS PSRR BW THD eN_WB tS CT VSS = GND Single supply, VSS = GND Dual supply, VSS < GND VIH = VLOGIC or VIL = GND VDD = 5.5 V VDD = 2.3 V VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND ∆VDD/∆VSS = VDD ± 10%, code = full scale −3 dB RAB = 10 kΩ RAB = 100 kΩ VDD/VSS = ±2.5 V, VA = 1 V rms, VB = 0 V, f = 1 kHz RAB = 10 kΩ RAB = 100 kΩ Code = half scale, TA = 25°C, f = 10 kHz RAB = 10 kΩ RAB = 100 kΩ VA = 5 V, VB = 0 V, from zero scale to full scale, ±0.5 LSB error band RAB = 10 kΩ RAB = 100 kΩ RAB = 10 kΩ RAB = 100 kΩ 2.3 ±2.25 1.8 2.25 −5.5 0.7 400 −0.7 2 320 0.05 3.5 −66 V V V V µA pF 1.4 −60 3 0.43 MHz MHz −80 −90 dB dB 7 20 nV/√Hz nV/√Hz 2 12 10 25 µs µs nV-sec nV-sec Rev. D | 5 of 38 Data Sheet AD5124/AD5144/AD5144A SPECIFICATIONS Table 2. Parameter Analog Crosstalk Endurance10 Symbol Test Conditions/Comments Min CTA Typ1 −90 1 TA = 25°C 100 Data Retention11, 12 50 Max Unit dB Mcycles kcycles Years 1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. 2 Resistor integral nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB. 3 Guaranteed by design and characterization, not subject to production test. 4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar signal adjustment. 6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms. 7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs. 8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC). 9 All dynamic characteristics use VDD/VSS = ±2.5 V, and VLOGIC = 2.5 V. 10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C. 11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV, derates with junction temperature in the Flash/EE memory. 12 50 years apply to an endurance of 1000 cycles. An endurance of 100,000 cycles has an equivalent retention lifetime of 5 years. analog.com Rev. D | 6 of 38 Data Sheet AD5124/AD5144/AD5144A SPECIFICATIONS ELECTRICAL CHARACTERISTICS—AD5144 AND AD5144A VDD = 2.3 V to 5.5 V, VSS = 0 V; VDD = 2.25 V to 2.75 V, VSS = −2.25 V to −2.75 V; VLOGIC = 1.8 V to 5.5 V, −40°C < TA < +125°C, unless otherwise noted. Table 3. Parameter Symbol DC CHARACTERISTICS—RHEOSTAT MODE (ALL RDACs) Resolution N Resistor Integral Nonlinearity2 R-INL Resistor Differential Nonlinearity2 Nominal Resistor Tolerance Resistance Temperature Coefficient3 Wiper Resistance3 Bottom Scale or Top Scale Nominal Resistance Match DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (ALL RDACs) Integral Nonlinearity4 Differential Nonlinearity4 Full-Scale Error Zero-Scale Error Voltage Divider Temperature Coefficient3 RESISTOR TERMINALS Maximum Continuous Current R-DNL ΔRAB/RAB (ΔRAB/RAB)/ΔT × 106 RW Test Conditions/Comments Capacitance W3 analog.com Typ1 Max 8 RAB = 10 kΩ VDD ≥ 2.7 V VDD < 2.7 V RAB = 100 kΩ VDD ≥ 2.7 V VDD < 2.7 V Unit Bits −2 −5 ±0.2 ±1.5 +2 +5 LSB LSB −1 −2 −0.5 −8 +1 +2 +0.5 +8 Code = full scale Code = zero scale RAB = 10 kΩ RAB = 100 kΩ ±0.1 ±0.5 ±0.2 ±1 35 LSB LSB LSB % ppm/°C 55 130 125 400 Ω Ω RAB = 10 kΩ RAB = 100 kΩ Code = full scale −1 40 60 ±0.2 80 230 +1 Ω Ω % RAB = 10 kΩ RAB = 100 kΩ −1 −0.5 −0.5 ±0.2 ±0.1 ±0.2 +1 +0.5 +0.5 LSB LSB LSB RAB = 10 kΩ RAB = 100 kΩ −2.5 −1 −0.1 ±0.2 +1 LSB LSB RBS or RTS RAB1/RAB2 INL DNL VWFSE VWZSE (ΔVW/VW)/ΔT × 106 RAB = 10 kΩ RAB = 100 kΩ Code = half scale 1.2 0.5 ±5 3 1 LSB LSB ppm/°C +6 +1.5 VDD mA mA V IA, IB, and IW RAB = 10 kΩ RAB = 100 kΩ Terminal Voltage Range5 Capacitance A, Capacitance B3 Min CA, CB CW f = 1 MHz, measured to GND, code = half scale RAB = 10 kΩ RAB = 100 kΩ f = 1 MHz, measured to GND, code = half scale RAB = 10 kΩ −6 −1.5 VSS 25 12 pF pF 12 pF Rev. D | 7 of 38 Data Sheet AD5124/AD5144/AD5144A SPECIFICATIONS Table 3. Parameter Symbol Common-Mode Leakage Current3 DIGITAL INPUTS Input Logic3 High Low Input Hysteresis3 Input Current3 Input Capacitance3 DIGITAL OUTPUTS Output High Voltage3 Output Low Voltage3 Three-State Leakage Current Three-State Output Capacitance POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Logic Supply Range Positive Supply Current Negative Supply Current EEPROM Store Current3, 6 EEPROM Read Current3, 7 Logic Supply Current Power Dissipation8 Power Supply Rejection Ratio DYNAMIC CHARACTERISTICS9 Bandwidth Total Harmonic Distortion Resistor Noise Density VW Settling Time Crosstalk (CW1/CW2) analog.com VINH Min Typ1 RAB = 100 kΩ VA = VW = VB −500 5 ±15 VLOGIC = 1.8 V to 2.3 V VLOGIC = 2.3 V to 5.5 V 0.8 × VLOGIC 0.7 × VLOGIC Test Conditions/Comments VINL VHYST IIN CIN VOH VOL Max Unit +500 pF nA 0.2 × VLOGIC 0.1 × VLOGIC ±1 5 RPULL-UP = 2.2 kΩ to VLOGIC ISINK = 3 mA ISINK = 6 mA, VLOGIC > 2.3 V VLOGIC −1 0.4 0.6 +1 V V V µA pF 5.5 ±2.75 VDD VDD V V V V 5.5 µA nA µA mA µA µA µW dB 2 VDD VDD/VSS VLOGIC IDD ISS IDD_EEPROM_STORE IDD_EEPROM_READ ILOGIC PDISS PSRR BW THD eN_WB tS CT VSS = GND Single supply, VSS = GND Dual supply, VSS < GND VIH = VLOGIC or VIL = GND VDD = 5.5 V VDD = 2.3 V VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND ∆VDD/∆VSS = VDD ± 10%, code = full scale −3 dB RAB = 10 kΩ RAB = 100 kΩ VDD/VSS = ±2.5 V, VA = 1 V rms, VB = 0 V, f = 1 kHz RAB = 10 kΩ RAB = 100 kΩ Code = half scale, TA = 25°C, f = 10 kHz RAB = 10 kΩ RAB = 100 kΩ VA = 5 V, VB = 0 V, from zero scale to full scale, ±0.5 LSB error band RAB = 10 kΩ RAB = 100 kΩ RAB = 10 kΩ RAB = 100 kΩ 2.3 ±2.25 1.8 2.25 −5.5 0.7 400 −0.7 2 320 0.05 3.5 −66 V V V V µA pF 1.4 −60 3 0.43 MHz MHz −80 −90 dB dB 7 20 nV/√Hz nV/√Hz 2 12 10 25 µs µs nV-sec nV-sec Rev. D | 8 of 38 Data Sheet AD5124/AD5144/AD5144A SPECIFICATIONS Table 3. Parameter Analog Crosstalk Endurance10 Symbol Test Conditions/Comments Min CTA Typ1 −90 1 TA = 25°C 100 Data Retention11, 12 50 Max Unit dB Mcycles kcycles Years 1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. 2 Resistor integral nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB. 3 Guaranteed by design and characterization, not subject to production test. 4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar signal adjustment. 6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms. 7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs. 8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC). 9 All dynamic characteristics use VDD/VSS = ±2.5 V, and VLOGIC = 2.5 V. 10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C. 11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV, derates with junction temperature in the Flash/EE memory. 12 50 years apply to an endurance of 1000 cycles. An endurance of 100,000 cycles has an equivalent retention lifetime of 5 years. analog.com Rev. D | 9 of 38 Data Sheet AD5124/AD5144/AD5144A SPECIFICATIONS INTERFACE TIMING SPECIFICATIONS VLOGIC = 1.8 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 4. SPI Interface Parameter1 Test Conditions/Comments Min t1 VLOGIC > 1.8 V VLOGIC = 1.8 V VLOGIC > 1.8 V VLOGIC = 1.8 V VLOGIC > 1.8 V VLOGIC = 1.8 V 20 30 10 15 10 15 10 5 5 10 20 t2 t3 t4 t5 t6 t7 t82 t93 t10 Typ Max Unit Description SCLK cycle time 500 ns ns ns ns ns ns ns ns ns ns ns ns ns 50 SCLK high time SCLK low time SYNC-to-SCLK falling edge setup time Data setup time Data hold time SYNC rising edge to next SCLK fall ignored Minimum SYNC high time SCLK rising edge to SDO valid SYNC rising edge to SDO pin disable 1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 2 Refer to tEEPROM_PROGRAM and tEEPROM_READBACK for memory commands operations (see Table 6). 3 RPULL_UP = 2.2 kΩ to VDD with a capacitance load of 168 pF. Table 5. I2C Interface Parameter1 fSCL 2 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 analog.com Test Conditions/Comments Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Min 4.0 0.6 4.7 1.3 250 100 0 0 4.7 0.6 4 0.6 4.7 1.3 4 0.6 20 + 0.1 CL 20 + 0.1 CL 20 + 0.1 CL Typ Max Unit Description 100 400 kHz kHz µs µs µs µs ns ns µs µs µs µs µs µs µs µs µs µs ns ns ns ns ns ns Serial clock frequency 3.45 0.9 1000 300 300 300 1000 300 SCL high time, tHIGH SCL low time, tLOW Data setup time, tSU; DAT Data hold time, tHD; DAT Setup time for a repeated start condition, tSU; STA Hold time (repeated) for a start condition, tHD; STA Bus free time between a stop and a start condition, tBUF Setup time for a stop condition, tSU; STO Rise time of SDA signal, tRDA Fall time of SDA signal, tFDA Rise time of SCL signal, tRCL Rev. D | 10 of 38 Data Sheet AD5124/AD5144/AD5144A SPECIFICATIONS Table 5. I2C Interface Parameter1 Test Conditions/Comments t11A Standard mode t12 tSP3 Min Fast mode Standard mode Fast mode Fast mode Typ 20 + 0.1 CL 20 + 0.1 CL 0 Max Unit Description 1000 ns Rise time of SCL signal after a repeated start condition and after an acknowledge bit, tRCL1 (not shown in Figure 5) 300 300 300 50 ns ns ns ns Fall time of SCL signal, tFCL Pulse width of suppressed spike 1 Maximum bus capacitance is limited to 400 pF. 2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate; however, it has a negative effect on the EMC behavior of the part. 3 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode. Table 6. Control Pins Parameter Min t1 t2 t3 tEEPROM_PROGRAM1 tEEPROM_READBACK tPOWER_UP2 tRESET 1 50 0.1 Typ 15 7 30 Max 10 50 30 75 Unit Description µs ns µs ms µs µs µs End command to LRDAC falling edge Minimum LRDAC low time RESET low time Memory program time (not shown in Figure 8) Memory readback time (not shown in Figure 8) Start-up time (not shown in Figure 8) Reset EEPROM restore time (not shown in Figure 8) 1 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at lower temperatures and higher write cycles. 2 Maximum time after VDD − VSS is equal to 2.3 V. analog.com Rev. D | 11 of 38 Data Sheet AD5124/AD5144/AD5144A SPECIFICATIONS SHIFT REGISTER AND TIMING DIAGRAMS Figure 4. Input Shift Register Contents Figure 5. I2C Serial Interface Timing Diagram (Typical Write Sequence) Figure 6. SPI Serial Interface Timing Diagram, CPOL = 0, CPHA = 1 Figure 7. SPI Serial Interface Timing Diagram, CPOL = 1, CPHA = 0 analog.com Rev. D | 12 of 38 Data Sheet AD5124/AD5144/AD5144A SPECIFICATIONS Figure 8. Control Pins Timing Diagram analog.com Rev. D | 13 of 38 Data Sheet AD5124/AD5144/AD5144A ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 7. Parameter Rating VDD to GND VSS to GND VDD to VSS VLOGIC to GND −0.3 V to +7.0 V +0.3 V to −7.0 V 7V −0.3 V to VDD + 0.3 V or +7.0 V (whichever is less) VSS − 0.3 V, VDD + 0.3 V VA, VW, VB to GND IA, IW, IB Pulsed1 Frequency > 10 kHz2 RAW = 10 kΩ RAW = 100 kΩ Frequency ≤ 10 kHz2 RAW = 10 kΩ RAW = 100 kΩ Digital Inputs Operating Temperature Range, TA3 Maximum Junction Temperature, TJ Maximum Storage Temperature Range Reflow Soldering Peak Temperature Time at Peak Temperature Package Power Dissipation θJA is defined by the JEDEC JESD51 standard, and the value is dependent on the test board and test environment. Table 8. Thermal Resistance Package Type θJA θJC Unit 24-Lead LFCSP 20-Lead TSSOP 351 3 45 °C/W °C/W 1 1431 JEDEC 2S2P test board, still air (0 m/sec airflow). ELECTROSTATIC DISCHARGE (ESD) RATINGS ±6 mA/d ±1.5 mA/d ±6 mA/√d ±1.5 mA/√d −0.3 V to VLOGIC + 0.3 V or +7 V (whichever is less) −40°C to +125°C 150°C −65°C to +150°C 260°C 20 sec to 40 sec (TJ max − TA)/θJA 1 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 d = pulse duty factor. 3 Includes programming of EEPROM memory. The following ESD information is provided for handling of ESD-sensitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Field induced charged device model (FICDM) and charged device model (CDM) per ANSI/ESDA/JEDEC JS-002. ESD RATINGS FOR AD5124/AD5144/AD5144A Table 9. AD5124/AD5144/AD5144A, 24-Lead LFCSP and 20-Lead TSSOP ESD Model Withstand Voltage (V) Class HBM FICDM 4000 1250 3A C3 ESD CAUTION ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. analog.com Rev. D | 14 of 38 Data Sheet AD5124/AD5144/AD5144A PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 9. 20-Lead TSSOP, SPI Interface Pin Configuration (AD5124/AD5144) Table 10. 20-Lead TSSOP, SPI Interface Pin Function Descriptions (AD5124/AD5144) Pin No. Mnemonic Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SYNC GND A1 W1 B1 A3 W3 B3 VSS A2 W2 B2 A4 W4 B4 VDD VLOGIC SCLK SDI SDO Synchronization Data Input, Active Low. When SYNC returns high, data is loaded into the input shift register. Ground Pin, Logic Ground Reference. Terminal A of RDAC1. VSS ≤ VA ≤ VDD. Wiper Terminal of RDAC1. VSS ≤ VW ≤ VDD. Terminal B of RDAC1. VSS ≤ VB ≤ VDD. Terminal A of RDAC3. VSS ≤ VA ≤ VDD. Wiper Terminal of RDAC3. VSS ≤ VW ≤ VDD. Terminal B of RDAC3. VSS ≤ VB ≤ VDD. Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. Terminal A of RDAC2. VSS ≤ VA ≤ VDD. Wiper Terminal of RDAC2. VSS ≤ VW ≤ VDD. Terminal B of RDAC2. VSS ≤ VB ≤ VDD. Terminal A of RDAC4. VSS ≤ VA ≤ VDD. Wiper Terminal of RDAC4. VSS ≤ VW ≤ VDD. Terminal B of RDAC4. VSS ≤ VB ≤ VDD. Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. Serial Clock Line. Data is clocked in at the logic low transition. Serial Data Input. Serial Data Output. This is an open-drain output pin, and it needs an external pull-up resistor. analog.com Rev. D | 15 of 38 Data Sheet AD5124/AD5144/AD5144A PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 10. 20-Lead TSSOP, I2C Interface Pin Configuration (AD5144A) Table 11. 20-Lead TSSOP, I2C Interface Pin Function Descriptions (AD5144A) Pin No. Mnemonic Description 1 RESET 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 GND A1 W1 B1 A3 W3 B3 VSS A2 W2 B2 A4 W4 B4 VDD VLOGIC SCL SDA ADDR Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at the logic low. If this pin is not used, tie RESET to VLOGIC. Ground Pin, Logic Ground Reference. Terminal A of RDAC1. VSS ≤ VA ≤ VDD. Wiper Terminal of RDAC1. VSS ≤ VW ≤ VDD. Terminal B of RDAC1. VSS ≤ VB ≤ VDD. Terminal A of RDAC3. VSS ≤ VA ≤ VDD. Wiper Terminal of RDAC3. VSS ≤ VW ≤ VDD. Terminal B of RDAC3. VSS ≤ VB ≤ VDD. Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. Terminal A of RDAC2. VSS ≤ VA ≤ VDD. Wiper Terminal of RDAC2. VSS ≤ VW ≤ VDD. Terminal B of RDAC2. VSS ≤ VB ≤ VDD. Terminal A of RDAC4. VSS ≤ VA ≤ VDD. Wiper Terminal of RDAC4. VSS ≤ VW ≤ VDD. Terminal B of RDAC4. VSS ≤ VB ≤ VDD. Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. Serial Clock Line. Data is clocked in at the logic low transition. Serial Data Input/Output. Programmable Address for Multiple Package Decoding. analog.com Rev. D | 16 of 38 Data Sheet AD5124/AD5144/AD5144A PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 11. 24-Lead LFCSP Pin Configuration (AD5124/AD5144) Table 12. 24-Lead LFCSP Pin Function Descriptions (AD5124/AD5144) Pin No. Mnemonic Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 GND A1 W1 B1 A3 W3 B3 VSS A2 W2 B2 A4 W4 B4 VDD VLOGIC SCL/SCLK 18 19 DIS SDA/SDI 20 WP 21 ADDR1/SDO 22 ADDR0/SYNC 23 LRDAC 24 RESET EPAD Ground Pin, Logic Ground Reference. Terminal A of RDAC1. VSS ≤ VA ≤ VDD. Wiper Terminal of RDAC1. VSS ≤ VW ≤ VDD. Terminal B of RDAC1. VSS ≤ VB ≤ VDD. Terminal A of RDAC3. VSS ≤ VA ≤ VDD. Wiper Terminal of RDAC3. VSS ≤ VW ≤ VDD. Terminal B of RDAC3. VSS ≤ VB ≤ VDD. Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. Terminal A of RDAC2. VSS ≤ VA ≤ VDD. Wiper Terminal of RDAC2. VSS ≤ VW ≤ VDD. Terminal B of RDAC2. VSS ≤ VB ≤ VDD. Terminal A of RDAC4. VSS ≤ VA ≤ VDD. Wiper Terminal of RDAC4. VSS ≤ VW ≤ VDD. Terminal B of RDAC4. VSS ≤ VB ≤ VDD. Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. I2C Serial Clock Line (SCL). Data is clocked in at the logic low transition. SPI Serial Clock Line (SCLK). Data is clocked in at the logic low transition. Digital Interface Select (SPI/I2C Select). SPI when DIS = 0 (GND), and I2C when DIS = 1 (VLOGIC). This pin cannot be left floating. Serial Data Input/Output (SDA), When DIS = 1. Serial Data Input (SDI), When DIS = 0. Optional Write Protect. This pin prevents any changes to the present RDAC and EEPROM content, except when reloading the content of the EEPROM into the RDAC register. WP is activated at logic low. If this pin is not used, tie WP to VLOGIC. Programmable Address (ADDR1) for Multiple Package Decoding, When DIS = 1. Serial Data Output (SDO). Open-drain output, needs an external pull-up resistor, when DIS = 0. Programmable Address (ADDR0) for Multiple Package Decoding, When DIS = 1. Synchronization Data Input, When DIS = 0. This pin is active low. When SYNC returns high, data is loaded into the input shift register. Load RDAC. Transfers the contents of the input registers to their respective RDAC registers when their associated input registers were previously loaded using Command 2 (see Table 17). This allows simultaneous update of all RDAC registers. LRDAC is activated at the high-to-low transition. If not used, tie LRDAC to VLOGIC. Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at the logic low. If not used, tie RESET to VLOGIC. Exposed Pad. Connect the exposed pad to the potential of the VSS pin, or, alternatively, leave it electrically unconnected. It is recommended that the pad be thermally connected to a copper plane for enhanced thermal performance. analog.com Rev. D | 17 of 38 Data Sheet AD5124/AD5144/AD5144A TYPICAL PERFORMANCE CHARACTERISTICS analog.com Figure 12. R-INL vs. Code (AD5144/AD5144A) Figure 15. R-DNL vs. Code (AD5144/AD5144A) Figure 13. R-INL vs. Code (AD5124) Figure 16. R-DNL vs. Code (AD5124) Figure 14. INL vs. Code (AD5144/AD5144A) Figure 17. DNL vs. Code (AD5144/AD5144A) Rev. D | 18 of 38 Data Sheet AD5124/AD5144/AD5144A TYPICAL PERFORMANCE CHARACTERISTICS Figure 18. INL vs. Code (AD5124) Figure 21. ILOGIC vs. Temperature Figure 19. Potentiometer Mode Temperature Coefficient ((ΔVW/VW)/ΔT × 106) vs. Code Figure 22. DNL vs. Code (AD5124) Figure 20. Supply Current vs. Temperature Figure 23. Rheostat Mode Temperature Coefficient ((ΔRWB/RWB)/ΔT × 106) vs. Code analog.com Rev. D | 19 of 38 Data Sheet AD5124/AD5144/AD5144A TYPICAL PERFORMANCE CHARACTERISTICS Figure 24. ILOGIC Current vs. Digital Input Voltage Figure 27. Normalized Phase Flatness vs. Frequency, RAB = 10 kΩ Figure 25. 10 kΩ Gain vs. Frequency vs. Code Figure 28. 100 kΩ Gain vs. Frequency vs. Code Figure 26. Total Harmonic Distortion Plus Noise (THD + N) vs. Frequency Figure 29. Total Harmonic Distortion Plus Noise (THD + N) vs. Amplitude analog.com Rev. D | 20 of 38 Data Sheet AD5124/AD5144/AD5144A TYPICAL PERFORMANCE CHARACTERISTICS Figure 30. Normalized Phase Flatness vs. Frequency, RAB = 100 kΩ Figure 33. Maximum Transition Glitch Figure 34. Resistor Lifetime Drift Figure 31. Incremental Wiper On Resistance vs. Positive Power Supply (VDD) Figure 35. Power Supply Rejection Ratio (PSRR) vs. Frequency Figure 32. Maximum Bandwidth vs. Code vs. Net Capacitance analog.com Rev. D | 21 of 38 Data Sheet AD5124/AD5144/AD5144A TYPICAL PERFORMANCE CHARACTERISTICS Figure 36. Digital Feedthrough Figure 37. Shutdown Isolation vs. Frequency Figure 38. Theoretical Maximum Current vs. Code analog.com Rev. D | 22 of 38 Data Sheet AD5124/AD5144/AD5144A TEST CIRCUITS Figure 39 to Figure 43 define the test conditions used in the Specifications section. Figure 39. Resistor Integral Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) Figure 40. Potentiometer Divider Nonlinearity Error (INL, DNL) Figure 42. Power Supply Sensitivity and Power Supply Rejection Ratio (PSS and PSRR) Figure 43. Incremental On Resistance Figure 41. Wiper Resistance analog.com Rev. D | 23 of 38 Data Sheet AD5124/AD5144/AD5144A THEORY OF OPERATION The AD5124/AD5144/AD5144A digital programmable potentiometers are designed to operate as true variable resistors for analog signals within the terminal voltage range of VSS < VTERM < VDD. The resistor wiper position is determined by the RDAC register contents. The RDAC register acts as a scratchpad register that allows unlimited changes of resistance settings. A secondary register (the input register) can be used to preload the RDAC register data. It is possible to both write to and read from the RDAC register using the digital interface (see Table 13). The contents of the RDAC register can be stored to the EEPROM using Command 9 (see Table 13). Thereafter, the RDAC register always sets at that position for any future on-off-on power supply sequence. It is possible to read back data saved into the EEPROM with Command 3 (see Table 13). The RDAC register can be programmed with any position setting using the I2C or SPI interface (depending on the model). When a desirable wiper position is found, this value can be stored in the EEPROM memory. Thereafter, the wiper position is always restored to that position for subsequent power-ups. The storing of the EEPROM data takes approximately 15 ms; during this time, the device is locked and does not acknowledge any new command, preventing any changes from taking place. INPUT SHIFT REGISTER RDAC REGISTER AND EEPROM If the AD5124 RDAC or EEPROM registers are read from or written to, the lowest data bit (Bit 0) is ignored. Alternatively, the EEPROM can be written to independently using Command 11 (see Table 17). For the AD5124/AD5144/AD5144A, the input shift register is 16 bits wide, as shown in Figure 4. The 16-bit word consists of four control bits, followed by four address bits and by eight data bits. The RDAC register directly controls the position of the digital potentiometer wiper. For example, when the RDAC register is loaded with 0x80 (AD5144/AD5144A, 256 taps), the wiper is connected to half scale of the variable resistor. The RDAC register is a standard logic register; there is no restriction on the number of changes allowed. Data is loaded MSB first (Bit 15). The four control bits determine the function of the software command, as listed in Table 13 and Table 17. Table 13. Reduced Commands Operation Truth Table Control Bits[DB15:DB12] Address Bits[DB11:DB8]1 Data Bits[DB7:DB0]1 Command Number C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation 0 1 0 0 0 0 0 0 0 1 X 0 X 0 X A1 X A0 X D7 X D6 X D5 X D4 X D3 X D2 X D1 X D02 2 0 0 1 0 0 0 A1 A0 D7 D6 D5 D4 D3 D2 D1 D02 3 0 0 1 1 X 0 A1 A0 X X X X X X D1 D0 9 10 14 15 0 0 1 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 X A3 0 0 X 0 A1 A1 X A1 A0 A0 X A0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 0 X D0 NOP: do nothing. Write contents of serial register data to RDAC Write contents of serial register data to input register Read back contents D1 D0 Data 0 1 EEPROM 1 1 RDAC Copy RDAC register to EEPROM Copy EEPROM into RDAC Software reset Software shutdown D0 Condition 0 Normal mode 1 Shutdown mode 1 X = don’t care. 2 D0 = don’t care for AD5124. Table 14. Reduced Address Bits Table A3 1 0 0 analog.com A2 A1 A0 Channel Stored Channel Memory 0 0 0 X1 X1 0 0 0 1 All channels RDAC1 RDAC2 Not applicable RDAC1 RDAC2 Rev. D | 24 of 38 Data Sheet AD5124/AD5144/AD5144A THEORY OF OPERATION Table 14. Reduced Address Bits Table A3 A2 A1 A0 Channel Stored Channel Memory 0 0 0 0 1 1 0 1 RDAC3 RDAC4 RDAC3 RDAC4 1 X = don’t care. SERIAL DATA DIGITAL INTERFACE SELECTION, DIS The AD5124/AD5144 LFSCP provides the flexibility of a selectable interface. When the digital interface select (DIS) pin is tied low, the SPI mode is engaged. When the DIS pin is tied high, the I2C mode is engaged. SPI SERIAL DATA INTERFACE The AD5124/AD5144 contain a 4-wire, SPI-compatible digital interface (SDI, SYNC, SDO, and SCLK). The write sequence begins by bringing the SYNC line low. The SYNC pin must be held low until the complete data-word is loaded from the SDI pin. Data is loaded in at the SCLK falling edge transition, as shown in Figure 6. When SYNC returns high, the serial data-word is decoded according to the instructions in Table 17. To minimize power consumption in the digital input buffers when the part is enabled, operate all serial interface pins close to the VLOGIC supply rails. SYNC Interruption In a standalone write sequence for the AD5124/AD5144, the SYNC line is kept low for 16 falling edges of SCLK, and the instruction is decoded when SYNC is pulled high. However, if the SYNC line is kept low for less than 16 falling edges of SCLK, the input shift register content is ignored, and the write sequence is considered invalid. SDO Pin The serial data output pin (SDO) serves two purposes: to read back the contents of the control, EEPROM, RDAC, and input registers using Command 3 (see Table 13 and Table 17), and to connect the AD5124/AD5144 in daisy-chain mode. The SDO pin contains an internal open-drain output that needs an external pull-up resistor. The SDO pin is enabled when SYNC is pulled low, and the data is clocked out of SDO on the rising edge of SCLK, as shown in Figure 6 and Figure 7. analog.com Rev. D | 25 of 38 Data Sheet AD5124/AD5144/AD5144A THEORY OF OPERATION Daisy-Chain Connection Daisy chaining minimizes the number of port pins required from the controlling IC. As shown in Figure 44, the SDO pin of one package must be tied to the SDI pin of the next package. The clock period may need to be increased because of the propagation delay of the line between subsequent devices. When two AD5124/AD5144 devices are daisy chained, 32 bits of data are required. The first 16 bits are assigned to U2, and the second 16 bits are assigned to U1, as shown in Figure 45. Keep the SYNC pin low until all 32 bits are clocked into their respective serial registers. The SYNC pin is then pulled high to complete the operation. To prevent data from mislocking (for example, due to noise) the part includes an internal counter, if the SCLK falling edges count is not a multiple of 8, the part ignores the command. A valid clock count is 16, 24, 32, 40, and so on. The counter resets when SYNC returns high. Figure 44. Daisy-Chain Configuration Figure 45. Daisy-Chain Diagram analog.com Rev. D | 26 of 38 Data Sheet AD5124/AD5144/AD5144A THEORY OF OPERATION I2C SERIAL DATA INTERFACE Table 15. 20-Lead TSSOP Device Address Selection The AD5144/AD5144A have 2-wire, I2C-compatible serial interfaces. These devices can be connected to an I2C bus as a slave device, under the control of a master device. See Figure 5 for a timing diagram of a typical write sequence. ADDR 7-Bit I2C Device Address VLOGIC No connect1 GND 0101000 0101010 0101011 The AD5144/AD5144A support standard (100 kHz) and fast (400 kHz) data transfer modes. Support is not provided for 10-bit addressing and general call addressing. 1 Not available in bipolar mode (VSS < 0 V) or in low voltage mode (VLOGIC = 1.8 V). Table 16. 24-Lead LFCSP Device Address Selection The 2-wire serial bus protocol operates as follows: ADDR0 Pin ADDR1 Pin 7-Bit I2C Device Address 1. The master initiates a data transfer by establishing a start condition, which is when a high-to-low transition on the SDA line occurs while SCL is high. The following byte is the address byte, which consists of the 7-bit slave address and an R/W bit. The slave device corresponding to the transmitted address responds by pulling SDA low during the ninth clock pulse (this is called the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its shift register. If the R/W bit is set high, the master reads from the slave device. However, if the R/W bit is set low, the master writes to the slave device. 2. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL. 3. When all data bits have been read from or written to, a stop condition is established. In write mode, the master pulls the SDA line high during the tenth clock pulse to establish a stop condition. In read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the SDA line remains high). The master then brings the SDA line low before the tenth clock pulse, and then high again during the tenth clock pulse to establish a stop condition. VLOGIC No connect1 GND VLOGIC No connect1 GND VLOGIC No connect1 GND VLOGIC VLOGIC VLOGIC No connect1 No connect1 No connect1 GND GND GND 0100000 0100010 0100011 0101000 0101010 0101011 0101100 0101110 0101111 I2C Address The AD5144/AD5144A each have two different device address options available (see Table 15 and Table 16). 1 Not available in bipolar mode (VSS < 0 V) or in low voltage mode (VLOGIC = 1.8 V). Write Operation When writing to the AD5124/AD5144/AD5144A, the user must begin with a start command followed by an address byte (R/W = 0), after which the device acknowledges that it is prepared to receive data by pulling SDA low. Two bytes of data are then written to the DAC, the most significant byte followed by the least significant byte. Both of these data bytes are acknowledged by the AD5124/AD5144/AD5144A. A stop condition follows. The write operations for the AD5124/AD5144/AD5144A are shown in Figure 46 and Figure 47. A repeated write function gives the user flexibility to update the device a number of times after addressing the device only once, as shown in Figure 47. Figure 46. AD5124/AD5144/AD5144A Interface Write Command analog.com Rev. D | 27 of 38 Data Sheet AD5124/AD5144/AD5144A THEORY OF OPERATION Figure 47. AD5124/AD5144/AD5144A Interface Multiple Write analog.com Rev. D | 28 of 38 Data Sheet AD5124/AD5144/AD5144A THEORY OF OPERATION EEPROM Write Acknowledge Polling After each write operation to the EEPROM, an internal write cycle begins. The I2C interface of the device is disabled. To determine if the internal write cycle is complete and the I2C interface is enabled, interface polling can be executed. I2C interface polling can be conducted by sending a start condition, followed by the slave address and the write bit. If the I2C interface responds with an acknowledge, the write cycle is complete, and the interface is ready to proceed with further operations. Otherwise, I2C interface polling can be repeated until it succeeds. Read Operation The AD5124/AD5144/AD5144A allow readback of the contents of the RDAC register and EEPROM memory through the I2C interface by using Command 3 (see Table 17). When reading data back from the AD5124/AD5144/AD5144A, the user must first issue a readback command to the device. The readback begins with a start command, followed by an address byte (R/W = 0), after which the device acknowledges that it is prepared to receive data by pulling SDA low. Two bytes of data are then written to the AD5124/AD5144/ AD5144A, the most significant byte followed by the least significant byte. Both of these data bytes are acknowledged by the AD5124/ AD5144/AD5144A. A stop condition follows. These bytes contain the read instruction, which enables readback of the RDAC register and EEPROM memory. The user can then read back the data. The readback begins with a start command followed by an address byte (R/W = 1), after which the device acknowledges that it is prepared to transmit data by pulling SDA low. Two bytes of data are then read from the device, which are both acknowledged by the master, as shown in Figure 48. A stop condition follows. If the master does not acknowledge the first byte, the second byte is not transmitted by the AD5124/AD5144/AD5144A. The AD5124/AD5144/AD5144A do not support repeat readback. Figure 48. AD5124/AD5144/AD5144A Interface Read Command analog.com Rev. D | 29 of 38 Data Sheet AD5124/AD5144/AD5144A THEORY OF OPERATION ADVANCED CONTROL MODES Key programming features include the following: The AD5124/AD5144/AD5144A digital potentiometers include a set of user programming features to address the wide number of applications for these universal adjustment devices (see Table 17 and Table 19). ► ► ► ► ► ► ► ► Input register Linear gain setting mode Low wiper resistance feature Linear increment and decrement instructions ±6 dB increment and decrement instructions Burst mode (I2C only) Reset Shutdown mode Table 17. Advance Commands Operation Truth Table Control Bits[DB15:DB12] Address Bits[DB11:DB8]1 Data Bits[DB7:DB0]1 Command Number C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation 0 1 0 0 0 0 0 0 0 1 X A3 X A2 X A1 X A0 X D7 X D6 X D5 X D4 X D3 X D2 X D1 X D02 2 0 0 1 0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D02 3 0 0 1 1 X A2 A1 A0 X X X X X X D1 D0 4 5 6 7 8 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 0 A3 A3 A3 A3 A3 A2 A2 A2 A2 A2 A1 A1 A1 A1 A1 A0 A0 A0 A0 A0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 0 1 0 X 9 10 11 0 0 1 1 1 0 1 1 0 1 1 0 0 0 0 0 0 0 A1 A1 A1 A0 A0 A0 X X D7 X X D6 X X D5 X X D4 X X D3 X X D2 X X D1 1 0 D02 12 1 0 0 1 A3 A2 A1 A0 1 X X X X X X D0 13 1 0 0 1 A3 A2 A1 A0 0 X X X X X X D0 14 15 1 1 0 1 1 0 1 0 X A3 X A2 X A1 X A0 X X X X X X X X X X X X X X X D0 16 1 1 0 1 X X X X X X X X D3 D2 D1 D0 NOP: do nothing Write contents of serial register data to RDAC Write contents of serial register data to input register Read back contents D1 D0 Data 0 0 Input register 0 1 EEPROM 1 0 Control register 1 1 RDAC Linear RDAC increment Linear RDAC decrement +6 dB RDAC increment −6 dB RDAC decrement Copy input register to RDAC (software LRDAC) Copy RDAC register to EEPROM Copy EEPROM into RDAC Write contents of serial register data to EEPROM Top scale D0 = 1; enter D0 = 0; exit Bottom scale D0 = 1; enter D0 = 0; exit Software reset Software shutdown D0 = 0; normal mode D0 = 1; device placed in shutdown mode Copy serial register data to control register, refer to Table 19. 1 X = don’t care. 2 D0 = don’t care for AD5124. analog.com Rev. D | 30 of 38 Data Sheet AD5124/AD5144/AD5144A THEORY OF OPERATION Table 18. Address Bits Potentiometer Mode Linear Gain Setting Mode A3 A2 A1 A0 Input Register RDAC Register Input Register RDAC Register Stored RDAC Memory 1 0 0 0 0 0 0 0 0 X1 0 1 0 1 0 1 0 1 X1 0 0 0 0 1 1 1 1 X1 0 0 1 1 0 0 1 1 All channels RDAC1 Not applicable RDAC2 Not applicable RDAC3 Not applicable RDAC4 Not applicable All channels RDAC1 Not applicable RDAC2 Not applicable RDAC3 Not applicable RDAC4 Not applicable All channels RWB1 RAW1 RWB2 RAW2 RWB3 RAW3 RWB4 RAW4 All channels RWB1 RAW1 RWB2 RAW2 RWB3 RAW3 RWB4 RAW4 Not applicable RDAC1 Not applicable RDAC2 Not applicable RDAC3 Not applicable RDAC4 Not applicable 1 X = don’t care. Table 19. Control Register Bit Descriptions Bit Name Description D0 RDAC register write protect 0 = wiper position frozen to value in EEPROM memory 1 = allows update of wiper position through digital interface (default) EEPROM program enable 0 = EEPROM program disabled 1 = enables device for EEPROM program (default) Linear setting mode/potentiometer mode 0 = potentiometer mode (default) 1 = linear gain setting mode Burst mode (I2C only) 0 = disabled (default) 1 = enabled (no disable after stop or repeat start condition) D1 D2 D3 analog.com Rev. D | 31 of 38 Data Sheet AD5124/AD5144/AD5144A THEORY OF OPERATION Input Register The AD5124/AD5144/AD5144A include one input register per RDAC register. These registers allow preloading of the value for the associated RDAC register. These registers can be written to using Command 2 and read back from using Command 3 (see Table 17). Table 20. Top Scale Truth Table Linear Gain Setting Mode Potentiometer Mode RAW RWB RAW RWB RAB RAB RTS RAB Table 21. Bottom Scale Truth Table Linear Gain Setting Mode Potentiometer Mode This feature allows a synchronous and asynchronous update of one or all of the RDAC registers at the same time. RAW RWB RAW RWB RTS RBS RAB RBS The transfer from the input register to the RDAC register is done asynchronously by the LRDAC pin or synchronously by Command 8 (see Table 17). Linear Increment and Decrement Instructions If new data is loaded into an RDAC register, this RDAC register automatically overwrites the associated input register. Linear Gain Setting Mode The proprietary architecture of the AD5124/AD5144/AD5144A allows the independent control of each string resistor, RAW, and RWB. To enable this feature, use Command 16 (see Table 17) to set Bit D2 of the control register (see Table 19). This mode of operation can control the potentiometer as two independent rheostats connected at a single point, the W terminal. This feature enables a second input and an RDAC register per channel, as shown in Table 18, but the actual RDAC contents remain unchanged. The same operations are valid for potentiometer and linear gain setting modes. The EEPROM commands affect the RWB resistance only. The parts restores in potentiometer mode after a reset or power-up. Low Wiper Resistance Feature The AD5124/AD5144/AD5144A include two commands to reduce the wiper resistance between the terminals when the devices achieve full scale or zero scale. These extra positions are called bottom scale, BS, and top scale, TS. The resistance between Terminal A and Terminal W at top scale is specified as RTS. Similarly, the bottom scale resistance between Terminal B and Terminal W is specified as RBS. The contents of the RDAC registers are unchanged by entering into these positions. There are three ways to exit from top scale and bottom scale: by using Command 12 or Command 13 (see Table 17); by loading new data in an RDAC register, which includes increment/decrement operations; or by entering shutdown mode, Command 15 (see Table 17). Table 20 and Table 21 show the truth tables for the top scale position and the bottom scale position, respectively, when the potentiometer or linear gain setting mode is enabled. analog.com The increment and decrement commands (Command 4 and Command 5 in Table 17) are useful for linear step adjustment applications. These commands simplify microcontroller software coding by allowing the controller to send an increment or decrement command to the device. The adjustment can be individual or in a ganged potentiometer arrangement, where all wiper positions are changed at the same time. For an increment command, executing Command 4 automatically moves the wiper to the next RDAC position. This command can be executed in a single channel or multiple channels. ±6 dB Increment and Decrement Instructions Two programming instructions produce logarithmic taper increment or decrement of the wiper position control by an individual potentiometer or by a ganged potentiometer arrangement where all RDAC register positions are changed simultaneously. The +6 dB increment is activated by Command 6, and the −6 dB decrement is activated by Command 7 (see Table 17). For example, starting with the zero-scale position and executing Command 6 ten times moves the wiper in 6 dB steps to the full-scale position. When the wiper position is near the maximum setting, the last 6 dB increment instruction causes the wiper to go to the full-scale position (see Table 22). Incrementing the wiper position by +6 dB essentially doubles the RDAC register value, whereas decrementing the wiper position by −6 dB halves the register value. Internally, the AD5124/AD5144/ AD5144A use shift registers to shift the bits left and right to achieve a ±6 dB increment or decrement. These functions are useful for various audio/video level adjustments, especially for white LED brightness settings in which human visual responses are more sensitive to large adjustments than to small adjustments. Table 22. Detailed Left Shift and Right Shift Functions for the ±6 dB Step Increment and Decrement Left Shift (+6 dB/Step) Right Shift (−6 dB/Step) 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 1111 1111 0111 1111 0011 1111 0001 1111 0000 1111 Rev. D | 32 of 38 Data Sheet AD5124/AD5144/AD5144A THEORY OF OPERATION Table 22. Detailed Left Shift and Right Shift Functions for the ±6 dB Step Increment and Decrement Left Shift (+6 dB/Step) Right Shift (−6 dB/Step) 0001 0000 0010 0000 0100 0000 1000 0000 1111 1111 0000 0111 0000 0011 0000 0001 0000 0000 0000 0000 Burst Mode (I2C Only) By enabling the burst mode, multiple data bytes can be sent to the part consecutively. After the command byte, the part interprets the following consecutive bytes as data bytes for the command. A new command can be sent by generating a repeat start or by a stop and start condition. The burst mode is activated by setting Bit D3 of the control register (see Table 19). Reset EEPROM OR RDAC REGISTER PROTECTION The EEPROM and RDAC registers can be protected by disabling any update to these registers. This can be done by using software or by using hardware. If these registers are protected by software, set Bit D0 and/or Bit D1 (see Table 19), which protects the RDAC and EEPROM registers independently. If the registers are protected by hardware, pull the WP pin low (only available in the LFCSP package). If the WP pin is pulled low when the part is executing a command, the protection is not enabled until the command is completed (only available in the LFCSP package). When RDAC is protected, the only operation allowed is to copy the EEPROM into the RDAC register. LOAD RDAC INPUT REGISTER (LRDAC) LRDAC software or hardware transfers data from the input register to the RDAC register (and therefore updates the wiper position). By default, the input register has the same value as the RDAC register; therefore, only the input register that has been updated using Command 2 is updated. Software LRDAC, Command 8, allows updating of a single RDAC register or all of the channels at once (see Table 17). This is a synchronous update. The AD5124/AD5144/AD5144A can be reset through software by executing Command 14 (see Table 17) or through hardware on the low pulse of the RESET pin. The reset command loads the RDAC register with the contents of the EEPROM and takes approximately 30 µs. The EEPROM is preloaded to midscale at the factory, and initial power-up is, accordingly, at midscale. Tie RESET to VDD if the RESET pin is not used. The hardware LRDAC is completely asynchronous and copies the content of all the input registers into the associated RDAC registers. If a command is being executed, any transition in the LRDAC pin is ignored by the part to avoid data corruption. Shutdown Mode RDAC ARCHITECTURE The AD5124/AD5144/AD5144A can be placed in shutdown mode by executing the software shutdown command, Command 15 (see Table 17), and setting the LSB (D0) to 1. This feature places the RDAC in a zero power consumption state where the device operates in potentiometer mode, Terminal A is open circuited, and the wiper, Terminal W, is connected to Terminal B; however, a finite wiper resistance of 40 Ω is present. When the device is configured in linear gain setting mode, the resistor addressed, RAW or RWB, is internally place at high impedance. Table 23 shows a truth table depending on the device operating mode. The contents of the RDAC register are unchanged by entering shutdown mode. However, all commands listed in Table 17 are supported while in shutdown mode. Execute Command 15 (see Table 17) and set the LSB (D0) to 0 to exit shutdown mode. To achieve optimum performance, Analog Devices, Inc., has proprietary RDAC segmentation architecture for all the digital potentiometers. In particular, the AD5124/AD5144 employ a three‑stage segmentation approach, as shown in Figure 49. The AD5124/AD5144/ AD5144A wiper switch is designed with the transmission gate CMOS topology and with the gate voltage derived from VDD and VSS. Table 23. Shutdown Mode Truth Table Linear Gain Setting Mode Potentiometer Mode RAW RWB RAW RWB High impedance High impedance High impedance RBS analog.com Rev. D | 33 of 38 Data Sheet AD5124/AD5144/AD5144A THEORY OF OPERATION D RWB D = 256 × RAB + RW     From 0x00 to 0xFF (2) where: D is the decimal equivalent of the binary code in the 7-bit/8-bit RDAC register. RAB is the end-to-end resistance. RW is the wiper resistance. In potentiometer mode, similar to the mechanical potentiometer, the resistance between Terminal W and Terminal A also produces a digitally controlled complementary resistance, RWA. RWA also gives a maximum of 8% absolute resistance error. RWA starts at the maximum resistance value and decreases as the data loaded into the latch increases. The general equations for this operation are AD5124: Figure 49. AD5124/AD5144/AD5144A Simplified RDAC Circuit (3) −D RAW D = 256 256 × RAB + RW     From 0x00 to 0xFF (4) AD5144/AD5144A: Top Scale/Bottom Scale Architecture In addition, the AD5124/AD5144/AD5144A include new positions to reduce the resistance between terminals. These positions are called bottom scale and top scale. At bottom scale, the typical wiper resistance decreases from 130 Ω to 60 Ω (RAB = 100 kΩ). At top scale, the resistance between Terminal A and Terminal W is decreased by 1 LSB, and the total resistance is reduced to 60 Ω (RAB = 100 kΩ). PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation—±8% Resistor Tolerance The AD5124/AD5144/AD5144A operate in rheostat mode when only two terminals are used as a variable resistor. The unused terminal can be floating, or it can be tied to Terminal W, as shown in Figure 50. where: D is the decimal equivalent of the binary code in the 7-bit/8-bit RDAC register. RAB is the end-to-end resistance. RW is the wiper resistance. If the part is configured in linear gain setting mode, the resistance between Terminal W and Terminal A is directly proportional to the code loaded in the associate RDAC register. The general equations for this operation are AD5124: D RWB D = 128 × RAB + RW     From 0x00 to 0x7F (5) D RWb D = 256 × RAB + RW     From 0x00 to 0xFF (6) AD5144/AD5144A: where: D is the decimal equivalent of the binary code in the 7-bit/8-bit RDAC register. RAB is the end-to-end resistance. RW is the wiper resistance. Figure 50. Rheostat Mode Configuration The nominal resistance between Terminal A and Terminal B, RAB, is 10 kΩ or 100 kΩ, and has 128/256 tap points accessed by the wiper terminal. The 7-bit/8-bit data in the RDAC latch is decoded to select one of the 128/256 possible wiper settings. The general equations for determining the digitally programmed output resistance between Terminal W and Terminal B are AD5124: D RWB D = 128 × RAB + RW     From 0x00 to 0x7F −D RAW D = 128 128 × RAB + RW     From 0x00 to 0x7F (1) In the bottom scale condition or top scale condition, a finite total wiper resistance of 40 Ω is present. Regardless of which setting the part is operating in, limit the current between Terminal A to Terminal B, Terminal W to Terminal A, and Terminal W to Terminal B to the maximum continuous current of ±6 mA or to the pulse current specified in Table 7. Otherwise, degradation or possible destruction of the internal switch contact can occur. AD5144/AD5144A: analog.com Rev. D | 34 of 38 Data Sheet AD5124/AD5144/AD5144A THEORY OF OPERATION PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates a voltage divider at wiper-to-B and wiper-to-A that is proportional to the input voltage at A to B, as shown in Figure 51. nal B, and Terminal W. Otherwise, the diode is forward-biased such that VDD is powered unintentionally. The ideal power-up sequence is VSS, VDD, VLOGIC, digital inputs, and VA, VB, and VW. The order of powering VA, VB, VW, and digital inputs is not important as long as they are powered after VSS, VDD, and VLOGIC. Regardless of the power-up sequence and the ramp rates of the power supplies, once VDD is powered, the power-on preset activates, which restores EEPROM values to the RDAC registers. LAYOUT AND POWER SUPPLY BIASING Figure 51. Potentiometer Mode Configuration Connecting Terminal A to 5 V and Terminal B to ground produces an output voltage at the Wiper W to Terminal B ranging from 0 V to 5 V. The general equation defining the output voltage at VW with respect to ground for any valid input voltage applied to Terminal A and Terminal B is Vw D = RWB D RAB × VA   + RAW D RAB   × VB It is always a good practice to use a compact, minimum lead length layout design. Ensure that the leads to the input are as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. It is also good practice to bypass the power supplies with quality capacitors. Apply low equivalent series resistance (ESR) 1 µF to 10 µF tantalum or electrolytic capacitors at the supplies to minimize any transient disturbance and to filter low frequency ripple. Figure 53 illustrates the basic supply bypassing configuration for the AD5124/AD5144/AD5144A. (7) where: RWB(D) can be obtained from Equation 1 and Equation 2. RAW(D) can be obtained from Equation 3 and Equation 4. Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors, RAW and RWB, and not the absolute values. Therefore, the temperature drift reduces to 5 ppm/°C. Figure 53. Power Supply Bypassing TERMINAL VOLTAGE OPERATING RANGE The AD5124/AD5144/AD5144A are designed with internal ESD diodes for protection. These diodes also set the voltage boundary of the terminal operating voltages. Positive signals present on Terminal A, Terminal B, or Terminal W that exceed VDD are clamped by the forward-biased diode. There is no polarity constraint between VA, VW, and VB, but they cannot be higher than VDD or lower than VSS. Figure 52. Maximum Terminal Voltages Set by VDD and VSS POWER-UP SEQUENCE Because there are diodes to limit the voltage compliance at Terminal A, Terminal B, and Terminal W (see Figure 52), it is important to power up VDD first before applying any voltage to Terminal A, Termianalog.com Rev. D | 35 of 38 Data Sheet AD5124/AD5144/AD5144A OUTLINE DIMENSIONS Figure 54. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.75 mm Package Height (CP-24-10) Dimensions shown in millimeters Figure 55. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters analog.com Rev. D | 36 of 38 Data Sheet AD5124/AD5144/AD5144A OUTLINE DIMENSIONS Updated: March 09, 2022 ORDERING GUIDE Model1 Temperature Range Package Description Packing Quantity Package Option AD5124BCPZ100-RL7 AD5124BCPZ10-RL7 AD5124BRUZ10 AD5124BRUZ100 AD5124BRUZ100-RL7 AD5124BRUZ10-RL7 AD5144ABRUZ10 AD5144ABRUZ100 AD5144ABRUZ100-RL7 AD5144ABRUZ10-RL7 AD5144BCPZ100-RL7 AD5144BCPZ10-RL7 AD5144BRUZ10 AD5144BRUZ100 AD5144BRUZ100-RL7 AD5144BRUZ10-RL7 -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C 24-Lead LFCSP (4mm x 4mm x 0.75mm w/ EP) 24-Lead LFCSP (4mm x 4mm x 0.75mm w/ EP) 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 24-Lead LFCSP (4mm x 4mm x 0.75mm w/ EP) 24-Lead LFCSP (4mm x 4mm x 0.75mm w/ EP) 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP Reel, 1500 Reel, 1500 Tube Tube Reel, 1000 Reel, 1000 Tube Tube Reel, 1000 Reel, 1000 Reel, 1500 Reel, 1500 Tube Tube Reel, 1000 Reel, 1000 CP-24-10 CP-24-10 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 CP-24-10 CP-24-10 RU-20 RU-20 RU-20 RU-20 1 Z = RoHS Compliant Part. RAB (KΩ), RESOLUTION, AND INTERFACE OPTIONS Model1 RAB (kΩ) Resolution Interface AD5124BCPZ10-RL7 AD5124BCPZ100-RL7 AD5124BRUZ10 AD5124BRUZ100 AD5124BRUZ10-RL7 AD5124BRUZ100-RL7 AD5144BCPZ10-RL7 AD5144BCPZ100-RL7 AD5144BRUZ10 AD5144BRUZ100 AD5144BRUZ10-RL7 AD5144BRUZ100-RL7 AD5144ABRUZ10 AD5144ABRUZ100 AD5144ABRUZ10-RL7 AD5144ABRUZ100-RL7 10 100 10 100 10 100 10 100 10 100 10 100 10 100 10 100 128 128 128 128 128 128 256 256 256 256 256 256 256 256 256 256 SPI/I2C SPI/I2C SPI SPI SPI SPI SPI/I2C SPI/I2C SPI SPI SPI SPI I2C I2C I 2C I2C 1 Z = RoHS Compliant Part. EVALUATION BOARDS Model1, 2 Description EVAL-AD5144DBZ Evaluation Board 1 Z = RoHS Compliant Part. analog.com Rev. D | 37 of 38 Data Sheet AD5124/AD5144/AD5144A OUTLINE DIMENSIONS Model1, 2 2 Description The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with both of the available resistor value options. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2012-2022 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Rev. D | 38 of 38