AD5141WBCPZ10-RL7

Single Channel, 128-/256-Position, I2C/SPI, Nonvolatile Digital Potentiometer AD5121/AD5141 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM VDD VLOGIC 10 kΩ and 100 kΩ resistance options Resistor tolerance: 8% maximum Wiper current: ±6 mA Low temperature coefficient: 35 ppm/°C Wide bandwidth: 3 MHz Fast start-up time < 75 µs Linear gain setting mode Single- and dual-supply operation Independent logic supply: 1.8 V to 5.5 V Wide operating temperature: −40°C to +125°C 3 mm × 3 mm LFCSP Qualified for automotive applications INDEP AD5121/ AD5141 POWER-ON RESET RDAC RESET W B SCLK/SCL SDI/SDA A INPUT REGISTER DIS SERIAL INTERFACE 7/8 EEPROM MEMORY SYNC/ADDR0 APPLICATIONS GND VSS WP 10940-001 SDO/ADDR1 Figure 1. Portable electronics level adjustment LCD panel brightness and contrast controls Programmable filters, delays, and time constants Programmable power supplies GENERAL DESCRIPTION The AD5121/AD5141 potentiometers provide a nonvolatile solution for 128-/256-position adjustment applications, offering guaranteed low resistor tolerance errors of ±8% and up to ±6 mA current density in the A, B, and W pins. The low resistor tolerance and low nominal temperature coefficient simplify open-loop applications as well as applications requiring tolerance matching. The linear gain setting mode allows independent programming of the resistance between the digital potentiometer terminals, through RAW and RWB string resistors, allowing very accurate resistor matching. The high bandwidth and low total harmonic distortion (THD) ensure optimal performance for ac signals, making it suitable for filter design. The low wiper resistance of only 40 Ω at the ends of the resistor array allows for pin-to-pin connection. The wiper values can be set through an SPI-/I2C-compatible digital interface that is also used to read back the wiper register and EEPROM contents. Rev. C The AD5121/AD5141 are available in a compact, 16-lead, 3 mm × 3 mm LFCSP. The devices are guaranteed to operate over the extended industrial temperature range of −40°C to +125°C. Table 1. Family Models Model AD51231 AD5124 AD5124 AD51431 AD5144 AD5144 AD5144A AD5122 AD5122A AD5142 AD5142A AD5121 AD5141 1 Channel Quad Quad Quad Quad Quad Quad Quad Dual Dual Dual Dual Single Single Position 128 128 128 256 256 256 256 128 128 256 256 128 256 Interface I2 C SPI/I2C SPI I2 C SPI/I2C SPI I2 C SPI I2 C SPI I2 C SPI/I2C SPI/I2C Package LFCSP LFCSP TSSOP LFCSP LFCSP TSSOP TSSOP LFCSP/TSSOP LFCSP/TSSOP LFCSP/TSSOP LFCSP/TSSOP LFCSP LFCSP Two potentiometers and two rheostats. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2012–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5121/AD5141 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Serial Data Digital Interface Selection, DIS ............................ 20 Applications ....................................................................................... 1 SPI Serial Data Interface ............................................................ 20 Functional Block Diagram .............................................................. 1 I2C Serial Data Interface ............................................................ 22 General Description ......................................................................... 1 I2C Address.................................................................................. 22 Revision History ............................................................................... 2 Advanced Control Modes ......................................................... 23 Specifications..................................................................................... 3 EEPROM or RDAC Register Protection ................................. 24 Electrical Characteristics—AD5121 .......................................... 3 Load RDAC Input Register (LRDAC) ..................................... 24 Electrical Characteristics—AD5141 .......................................... 6 INDEP Pin................................................................................... 24 Interface Timing Specifications .................................................. 9 RDAC Architecture .................................................................... 27 Shift Register and Timing Diagrams ....................................... 10 Programming the Variable Resistor ......................................... 27 Absolute Maximum Ratings .......................................................... 12 Programming the Potentiometer Divider ............................... 28 Thermal Resistance .................................................................... 12 Terminal Voltage Operating Range ......................................... 29 ESD Caution ................................................................................ 12 Power-Up Sequence ................................................................... 29 Pin Configuration and Function Descriptions ........................... 13 Layout and Power Supply Biasing ............................................ 29 Typical Performance Characteristics ........................................... 14 Outline Dimensions ....................................................................... 30 Test Circuits ..................................................................................... 19 Ordering Guide .......................................................................... 30 Theory of Operation ...................................................................... 20 Automotive Products ................................................................. 30 RDAC Register and EEPROM .................................................. 20 Input Shift Register..................................................................... 20 REVISION HISTORY 5/2017—Rev. B to Rev. C Changes to Figure 7 and Table 9 ................................................... 13 Changes to Figure 16 and Figure 17............................................. 15 Updated Outline Dimensions ....................................................... 30 Changes to Ordering Guide .......................................................... 30 Change to Automotive Products Section .................................... 30 3/2016—Rev. A to Rev. B Changes to Features Section............................................................ 1 Changes to Logic Supply Current Parameter, Table 2 ................. 4 Added Note 12, Table 2 .................................................................... 5 Changes to Logic Supply Current Parameter, Table 3 ................. 7 Added Note 12, Table 3 .................................................................... 8 Changes to Figure 7 ........................................................................ 13 Changes to Figure 16...................................................................... 15 Added Figure 17; Renumbered Sequentially .............................. 15 Changes to Figure 20...................................................................... 16 Change to Linear Gain Setting Mode Section ............................ 23 Changes to RDAC Architecture Section ..................................... 27 Changes to Ordering Guide .......................................................... 30 Added Automotive Products Section .......................................... 30 12/2012—Rev. 0 to Rev. A Changes to Table 10 ....................................................................... 22 10/2012—Revision 0: Initial Version Rev. C | Page 2 of 32 Data Sheet AD5121/AD5141 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—AD5121 VDD = 2.3 V to 5.5 V, VSS = 0 V; VDD = 2.25 V to 2.75 V, VSS = −2.25 V to −2.75 V; VLOGIC = 1.8 V to 5.5 V, −40°C < TA < +125°C, unless otherwise noted. Table 2. Parameter DC CHARACTERISTICS—RHEOSTAT MODE (ALL RDACs) Resolution Resistor Integral Nonlinearity2 Resistor Differential Nonlinearity2 Nominal Resistor Tolerance Resistance Temperature Coefficient3 Wiper Resistance3 Bottom Scale or Top Scale DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (ALL RDACs) Integral Nonlinearity4 Differential Nonlinearity4 Full-Scale Error Zero-Scale Error Voltage Divider Temperature Coefficient3 Symbol Test Conditions/Comments N R-INL Min Typ1 Max 7 RAB = 10 kΩ VDD ≥ 2.7 V VDD < 2.7 V RAB = 100 kΩ VDD ≥ 2.7 V VDD < 2.7 V R-DNL ΔRAB/RAB (ΔRAB/RAB)/ΔT × 106 RW Unit Bits −1 −2.5 ±0.1 ±1 +1 +2.5 LSB LSB −0.5 −1 −0.5 −8 +0.5 +1 +0.5 +8 Code = full scale Code = zero scale RAB = 10 kΩ RAB = 100 kΩ ±0.1 ±0.25 ±0.1 ±1 35 LSB LSB LSB % ppm/°C 55 130 125 400 Ω Ω RAB = 10 kΩ RAB = 100 kΩ 40 60 80 230 Ω Ω RBS or RTS INL RAB = 10 kΩ RAB = 100 kΩ −0.5 −0.25 −0.25 ±0.1 ±0.1 ±0.1 +0.5 +0.25 +0.25 LSB LSB LSB RAB = 10 kΩ RAB = 100 kΩ −1.5 −0.5 −0.1 ±0.1 +0.5 LSB LSB DNL VWFSE VWZSE (ΔVW/VW)/ΔT × 106 RAB = 10 kΩ RAB = 100 kΩ Code = half scale Rev. C | Page 3 of 32 1 0.25 ±5 1.5 0.5 LSB LSB ppm/°C AD5121/AD5141 Parameter RESISTOR TERMINALS Maximum Continuous Current Terminal Voltage Range5 Capacitance A, Capacitance B3 Capacitance W3 Common-Mode Leakage Current3 DIGITAL INPUTS Input Logic3 High Low Input Hysteresis3 Input Current3 Input Capacitance3 DIGITAL OUTPUTS Output High Voltage3 Output Low Voltage3 Data Sheet Symbol Negative Supply Current EEPROM Store Current3, 6 EEPROM Read Current3, 7 Logic Supply Current Power Dissipation8 Power Supply Rejection Ratio Min RAB = 10 kΩ RAB = 100 kΩ −6 −1.5 VSS Typ1 Max Unit +6 +1.5 VDD mA mA V IA, IB, and IW CA, CB CW VINH f = 1 MHz, measured to GND, code = half scale RAB = 10 kΩ RAB = 100 kΩ f = 1 MHz, measured to GND, code = half scale RAB = 10 kΩ RAB = 100 kΩ VA = V W = V B −500 VLOGIC = 1.8 V to 2.3 V VLOGIC = 2.3 V to 5.5 V 0.8 × VLOGIC 0.7 × VLOGIC VINL VHYST IIN CIN VOH VOL Three-State Leakage Current Three-State Output Capacitance POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Logic Supply Range Positive Supply Current Test Conditions/Comments 25 12 pF pF 12 5 ±15 pF pF nA +500 0.2 × VLOGIC 0.1 × VLOGIC ±1 5 RPULL-UP = 2.2 kΩ to VLOGIC ISINK = 3 mA ISINK = 6 mA, VLOGIC > 2.3 V VLOGIC −1 0.4 0.6 +1 V V V µA pF 5.5 ±2.75 VDD VDD V V V V 5.5 µA nA µA mA µA µA µW dB 2 VSS = GND IDD ISS IDD_EEPROM_STORE IDD_EEPROM_READ ILOGIC PDISS PSRR Single supply, VSS = GND Dual supply, VSS < GND VIH = VLOGIC or VIL = GND VDD = 5.5 V VDD = 2.3 V VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND ∆VDD/∆VSS = VDD ± 10%, code = full scale Rev. C | Page 4 of 32 2.3 ±2.25 1.8 2.25 −5.5 0.7 400 −0.7 2 320 0.05 3.5 −66 V V V V µA pF 1.4 −60 Data Sheet Parameter DYNAMIC CHARACTERISTICS9 Bandwidth Total Harmonic Distortion Resistor Noise Density VW Settling Time Endurance10 AD5121/AD5141 Symbol Test Conditions/Comments BW −3 dB RAB = 10 kΩ RAB = 100 kΩ VDD/VSS = ±2.5 V, VA = 1 V rms, VB = 0 V, f = 1 kHz RAB = 10 kΩ RAB = 100 kΩ Code = half scale, TA = 25°C, f = 10 kHz RAB = 10 kΩ RAB = 100 kΩ VA = 5 V, VB = 0 V, from zero scale to full scale, ±0.5 LSB error band RAB = 10 kΩ RAB = 100 kΩ TA = 25°C THD eN_WB tS Min Typ1 MHz MHz −80 −90 dB dB 7 20 nV/√Hz nV/√Hz 2 12 1 µs µs Mcycles kcycles Years 50 1 Unit 3 0.43 100 Data Retention11, 12 Max Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. Resistor integral nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB. 3 Guaranteed by design and characterization, not subject to production test. 4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar signal adjustment. 6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms. 7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs. 8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC). 9 All dynamic characteristics use VDD/VSS = ±2.5 V, and VLOGIC = 2.5 V. 10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C. 11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV, derates with junction temperature in the Flash/EE memory. 12 50 years applies to an endurance of 1000 cycles. An endurance of 100,000 cycles has an equivalent retention lifetime of 5 years. 2 Rev. C | Page 5 of 32 AD5121/AD5141 Data Sheet ELECTRICAL CHARACTERISTICS—AD5141 VDD = 2.3 V to 5.5 V, VSS = 0 V; VDD = 2.25 V to 2.75 V, VSS = −2.25 V to −2.75 V; VLOGIC = 1.8 V to 5.5 V, −40°C < TA < +125°C, unless otherwise noted. Table 3. Parameter DC CHARACTERISTICS—RHEOSTAT MODE (ALL RDACs) Resolution Resistor Integral Nonlinearity2 Resistor Differential Nonlinearity2 Nominal Resistor Tolerance Resistance Temperature Coefficient3 Wiper Resistance3 Bottom Scale or Top Scale Symbol Test Conditions/Comments N R-INL Min Differential Nonlinearity4 Full-Scale Error Zero-Scale Error Voltage Divider Temperature Coefficient3 Max 8 RAB = 10 kΩ VDD ≥ 2.7 V VDD < 2.7 V RAB = 100 kΩ VDD ≥ 2.7 V VDD < 2.7 V R-DNL ΔRAB/RAB (ΔRAB/RAB)/ΔT × 106 RW Unit Bits −2 −5 ±0.2 ±1.5 +2 +5 LSB LSB −1 −2 −0.5 −8 ±0.1 ±0.5 ±0.2 ±1 35 +1 +2 +0.5 +8 LSB LSB LSB % ppm/°C 55 130 125 400 Ω Ω 40 60 80 230 Ω Ω Code = full scale Code = zero scale RAB = 10 kΩ RAB = 100 kΩ RBS or RTS RAB = 10 kΩ RAB = 100 kΩ DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (ALL RDACs) Integral Nonlinearity4 Typ1 INL RAB = 10 kΩ RAB = 100 kΩ −1 −0.5 −0.5 ±0.2 ±0.1 ±0.2 +1 +0.5 +0.5 LSB LSB LSB RAB = 10 kΩ RAB = 100 kΩ −2.5 −1 −0.1 ±0.2 +1 LSB LSB DNL VWFSE VWZSE (ΔVW/VW)/ΔT × 106 RAB = 10 kΩ RAB = 100 kΩ Code = half scale Rev. C | Page 6 of 32 1.2 0.5 ±5 3 1 LSB LSB ppm/°C Data Sheet Parameter RESISTOR TERMINALS Maximum Continuous Current Terminal Voltage Range5 Capacitance A, Capacitance B3 Capacitance W3 Common-Mode Leakage Current3 DIGITAL INPUTS Input Logic3 High Low Input Hysteresis3 Input Current3 Input Capacitance3 DIGITAL OUTPUTS Output High Voltage3 Output Low Voltage3 AD5121/AD5141 Symbol Negative Supply Current EEPROM Store Current3, 6 EEPROM Read Current3, 7 Logic Supply Current Power Dissipation8 Power Supply Rejection Ratio Min RAB = 10 kΩ RAB = 100 kΩ −6 −1.5 VSS Typ1 Max Unit +6 +1.5 VDD mA mA V IA, IB, and IW CA, CB CW VINH f = 1 MHz, measured to GND, code = half scale RAB = 10 kΩ RAB = 100 kΩ f = 1 MHz, measured to GND, code = half scale RAB = 10 kΩ RAB = 100 kΩ VA = V W = V B −500 VLOGIC = 1.8 V to 2.3 V VLOGIC = 2.3 V to 5.5 V 0.8 × VLOGIC 0.7 × VLOGIC VINL VHYST IIN CIN VOH VOL Three-State Leakage Current Three-State Output Capacitance POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Logic Supply Range Positive Supply Current Test Conditions/Comments 25 12 pF pF 12 5 ±15 pF pF nA +500 0.2 × VLOGIC 0.1 × VLOGIC ±1 5 RPULL-UP = 2.2 kΩ to VLOGIC ISINK = 3 mA ISINK = 6 mA, VLOGIC > 2.3V VLOGIC −1 0.4 0.6 +1 V V V µA pF 5.5 ±2.75 VDD VDD V V V V 5.5 µA nA µA mA µA µA µW dB 2 VSS = GND IDD ISS IDD_EEPROM_STORE IDD_EEPROM_READ ILOGIC PDISS PSR Single supply, VSS = GND Dual supply, VSS < GND VIH = VLOGIC or VIL = GND VDD = 5.5 V VDD = 2.3 V VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND ∆VDD/∆VSS = VDD ± 10%, code = full scale Rev. C | Page 7 of 32 2.3 ±2.25 1.8 2.25 −5.5 0.7 400 −0.7 2 320 0.05 3.5 −66 V V V V µA pF 1.4 −60 AD5121/AD5141 Parameter DYNAMIC CHARACTERISTICS9 Bandwidth Total Harmonic Distortion Resistor Noise Density VW Settling Time Endurance10 Data Sheet Symbol Test Conditions/Comments BW −3 dB RAB = 10 kΩ RAB = 100 kΩ VDD/VSS = ±2.5 V, VA = 1 V rms, VB = 0 V, f = 1 kHz RAB = 10 kΩ RAB = 100 kΩ Code = half scale, TA = 25°C, f = 10 kHz RAB = 10 kΩ RAB = 100 kΩ VA = 5 V, VB = 0 V, from zero scale to full scale, ±0.5 LSB error band RAB = 10 kΩ RAB = 100 kΩ TA = 25°C THD eN_WB tS Min Typ1 MHz MHz −80 −90 dB dB 7 20 nV/√Hz nV/√Hz 2 12 1 µs µs Mcycles kcycles Years 50 1 Unit 3 0.43 100 Data Retention11, 12 Max Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. Resistor integral nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB. 3 Guaranteed by design and characterization, not subject to production test. 4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar signal adjustment. 6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms. 7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs. 8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC). 9 All dynamic characteristics use VDD/VSS = ±2.5 V, and VLOGIC = 2.5 V. 10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C. 11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV, derates with junction temperature in the Flash/EE memory. 12 50 years applies to an endurance of 1000 cycles. An endurance of 100,000 cycles has an equivalent retention lifetime of 5 years. 2 Rev. C | Page 8 of 32 Data Sheet AD5121/AD5141 INTERFACE TIMING SPECIFICATIONS VLOGIC = 1.8 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 4. SPI Interface Parameter1 t1 t2 t3 Test Conditions/Comments VLOGIC > 1.8 V VLOGIC = 1.8 V VLOGIC > 1.8 V VLOGIC = 1.8 V VLOGIC > 1.8 V VLOGIC = 1.8 V Min 20 30 10 15 10 15 10 5 5 10 20 t4 t5 t6 t7 t82 t93 t10 Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 50 500 Description SCLK cycle time SCLK high time SCLK low time SYNC-to-SCLK falling edge setup time Data setup time Data hold time SYNC rising edge to next SCLK fall ignored Minimum SYNC high time SCLK rising edge to SDO valid SYNC rising edge to SDO pin disable 1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Refer to tEEPROM_PROGRAM and tEEPROM_READBACK for memory commands operations (see Table 6). 3 RPULL_UP = 2.2 kΩ to VDD with a capacitance load of 168 pF. 2 Table 5. I2C Interface Parameter1 fSCL2 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t11A Test Conditions/Comments Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Min Fast mode 20 + 0.1 CL 4.0 0.6 4.7 1.3 250 100 0 0 4.7 0.6 4 0.6 4.7 1.3 4 0.6 20 + 0.1 CL 20 + 0.1 CL 20 + 0.1 CL Typ Max 100 400 1000 300 300 300 1000 300 1000 Unit kHz kHz µs µs µs µs ns ns µs µs µs µs µs µs µs µs µs µs ns ns ns ns ns ns ns 300 ns 3.45 0.9 Rev. C | Page 9 of 32 Description Serial clock frequency SCL high time, tHIGH SCL low time, tLOW Data setup time, tSU; DAT Data hold time, tHD; DAT Setup time for a repeated start condition, tSU; STA Hold time (repeated) for a start condition, tHD; STA Bus free time between a stop and a start condition, tBUF Setup time for a stop condition, tSU; STO Rise time of SDA signal, tRDA Fall time of SDA signal, tFDA Rise time of SCL signal, tRCL Rise time of SCL signal after a repeated start condition and after an acknowledge bit, tRCL1 (not shown in Figure 3) AD5121/AD5141 Parameter1 t12 Data Sheet Test Conditions/Comments Standard mode Fast mode Fast mode tSP3 Min Typ Max 300 300 50 20 + 0.1 CL 0 Unit ns ns ns Description Fall time of SCL signal, tFCL Pulse width of suppressed spike (not shown in Figure 3) 1 Maximum bus capacitance is limited to 400 pF. The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate; however, it has a negative effect on the EMC behavior of the part. 3 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode. 2 Table 6. Control Pins Parameter t1 t2 t3 tEEPROM_PROGRAM1 tEEPROM_READBACK tPOWER_UP2 tRESET 1 2 Min 1 50 0.1 Typ Max 15 7 10 50 30 75 Unit μs ns μs ms μs μs μs 30 Description End command to LRDAC falling edge Minimum LRDAC low time RESET low time Memory program time (not shown in Figure 6) Memory readback time (not shown in Figure 6) Power-on EEPROM restore time (not shown in Figure 6) Reset EEPROM restore time (not shown in Figure 6) EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at lower temperatures and higher write cycles. Maximum time after VDD − VSS is equal to 2.3 V. SHIFT REGISTER AND TIMING DIAGRAMS C3 C2 C1 C0 A3 A2 A1 DB8 DB7 A0 D7 DB0 (LSB) D6 D5 D4 D3 D2 D0 D1 10940-004 DB15 (MSB) DATA BITS CONTROL BITS ADDRESS BITS Figure 2. Input Shift Register Contents t11 t12 t6 t8 t2 SCL t6 t5 t1 t4 t10 t3 t9 10940-005 SDA t7 P S S P Figure 3. I2C Serial Interface Timing Diagram (Typical Write Sequence) t4 t1 t2 t7 SCLK t3 t8 SYNC t5 C3 C2 C1 C0 D7 D6 D5 SDO C3* C2* C1* C0* D7* D6* D5* t6 D2 D1 D0 D2* D1* D0* t9 t10 *PREVIOUS COMMAND RECEIVED. Figure 4. SPI Serial Interface Timing Diagram, CPOL = 0, CPHA = 1 Rev. C | Page 10 of 32 10940-006 SDI Data Sheet AD5121/AD5141 t4 t1 t2 t7 SCLK t3 t8 SYNC t5 C3 C2 C1 C0 D7 D6 D5 SDO C3* C2* C1* C0* D7* D6* D5* t6 D2 D1 D0 D2* D1* D0* t9 t10 *PREVIOUS COMMAND RECEIVED. 10940-007 SDI Figure 5. SPI Serial Interface Timing Diagram, CPOL = 1, CPHA = 0 SCLK SPI INTERFACE SYNC SCL I2C INTERFACE SDA P t1 t2 t3 RESET Figure 6. Control Pins Timing Diagram Rev. C | Page 11 of 32 10940-008 LRDAC AD5121/AD5141 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 7. Parameter VDD to GND VSS to GND VDD to VSS VLOGIC to GND VA, VW, VB to GND IA, IW, IB Pulsed1 Frequency > 10 kHz RAW = 10 kΩ RAW = 100 kΩ Frequency ≤ 10 kHz RAW = 10 kΩ RAW = 100 kΩ Digital Inputs Operating Temperature Range, TA3 Maximum Junction Temperature, TJ Maximum Storage Temperature Range Reflow Soldering Peak Temperature Time at Peak Temperature Package Power Dissipation Rating −0.3 V to +7.0 V +0.3 V to −7.0 V 7V −0.3 V to VDD + 0.3 V or +7.0 V (whichever is less) VSS − 0.3 V, VDD + 0.3 V or +7.0 V (whichever is less) Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE θJA is defined by the JEDEC JESD51 standard, and the value is dependent on the test board and test environment. Table 8. Thermal Resistance Package Type 16-Lead LFCSP ±6 mA/d2 ±1.5 mA/d2 1 ±6 mA/√d2 ±1.5 mA/√d2 −0.3 V to VLOGIC + 0.3 V or +7 V (whichever is less) −40°C to +125°C 150°C θJA 89.51 JEDEC 2S2P test board, still air (0 m/sec airflow). ESD CAUTION −65°C to +150°C 260°C 20 sec to 40 sec (TJ max − TA)/θJA 1 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 d = pulse duty factor. 3 Includes programming of EEPROM memory. Rev. C | Page 12 of 32 θJC 3 Unit °C/W Data Sheet AD5121/AD5141 13 WP 14 SDO/ADDR1 15 INDEP PIN 1 INDICATOR 16 LRDAC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND 1 12 SDI/SDA A 2 AD5121/ AD5141 W 3 TOP VIEW (Not to Scale) 11 SCLK/SCL 10 VLOGIC 9 VDD NOTES 1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO THE POTENTIAL OF THE VSS PIN, OR, ALTERNATIVELY, LEAVE IT ELECTRICALLY UNCONNECTED. IT IS RECOMMENDED THAT THE PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE. 10940-009 DIS 8 RESET 7 VSS 5 SYNC/ADDR0 6 B 4 Figure 7. Pin Configuration Table 9. Pin Function Descriptions Pin No. 1 2 3 4 5 6 Mnemonic GND A W B VSS SYNC/ADDR0 7 RESET 8 DIS 9 10 11 VDD VLOGIC SCLK/SCL 12 SDI/SDA 13 WP 14 SDO/ADDR1 15 INDEP 16 LRDAC EPAD Description Ground Pin, Logic Ground Reference. Terminal A of RDAC. VSS ≤ VA ≤ VDD. Wiper terminal of RDAC. VSS ≤ VW ≤ VDD. Terminal B of RDAC. VSS ≤ VB ≤ VDD. Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. Programmable Address (ADDR0) for Multiple Package Decoding, DIS = 1. Synchronization Data Input, Active Low. When SYNC returns high, data is loaded into the RDAC register, DIS = 0. Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at logic low. If this pin is not used, tie RESET to VLOGIC. Digital Interface Select (SPI/I2C Select). SPI when DIS = 0 (GND), I2C when DIS = 1 (VLOGIC). This pin cannot be left floating. Positive Power Supply. Decouple this pin with 0.1µF ceramic capacitors and 10 µF capacitors. Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. SPI Serial Clock Line (SCLK). Data is clocked in at logic low transition. I2C Serial Clock Line (SCL). Data is clocked in at logic low transition. Serial Data Input/Output (SDA), When DIS = 1. Serial Data Input (SDI), When DIS = 0. Optional Write Protect. This pin prevents any changes to the present RDAC and EEPROM contents, except when reloading the content of the EEPROM into the RDAC register. WP is activated at logic low. If this pin is not used, tie WP to VLOGIC Programmable Address (ADDR1) for Multiple Package Decoding, When DIS = 1. Serial Data Output (SDO). This is an open-drain output pin, and it needs an external pull-up resistor when DIS = 0. Linear Gain Setting Mode at Power-Up. Each string resistor is loaded from its associate memory location. If INDEP is enabled, it cannot be disabled by the software. Load RDAC. Transfers the contents of the input register to the RDAC register. This allows asynchronous RDAC update. LRDAC is activated low. If this pin is not used, tie LRDAC to VLOGIC. Exposed Pad. Connect this exposed pad to the potential of the VSS pin, or, alternatively, leave it electrically unconnected. It is recommended that the pad be thermally connected to a copper plane for enhanced thermal performance. Rev. C | Page 13 of 32 AD5121/AD5141 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.5 0.2 10kΩ, +125°C 10kΩ, +25°C 10kΩ, –40°C 100kΩ, +125°C 100kΩ, +25°C 100kΩ, –40°C 0.4 0.3 0.1 0 R-DNL (LSB) R-INL (LSB) 0.2 0.1 0 –0.1 –0.1 –0.2 –0.3 –0.2 –0.4 –0.3 100 0 200 CODE (Decimal) –0.6 10940-012 –0.5 10kΩ, +125°C 10kΩ, +25°C 10kΩ, –40°C 0 100kΩ, +125°C 100kΩ, +25°C 100kΩ, –40°C 100 200 CODE (Decimal) Figure 8. R-INL vs. Code (AD5141) 10940-015 –0.5 –0.4 Figure 11. R-DNL vs. Code (AD5141) 0.20 0.10 0.15 0.05 0.10 0 R-DNL (LSB) R-INL (LSB) 0.05 0 –0.05 –0.05 –0.10 –0.15 –0.10 10kΩ, +125°C 10kΩ, +25°C 10kΩ, –40°C 100kΩ, +125°C 100kΩ, +25°C 100kΩ, –40°C –0.25 0 –0.25 50 100 CODE (Decimal) –0.30 10kΩ, +125°C 10kΩ, +25°C 10kΩ, –40°C 0 100 Figure 12. R-DNL vs. Code (AD5121) 0.10 10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C 100kΩ, –40°C 100kΩ, +25°C 100kΩ, +125°C 0.2 50 CODE (Decimal) Figure 9. R-INL vs. Code (AD5121) 0.3 100kΩ, +125°C 100kΩ, +25°C 100kΩ, –40°C 10940-016 –0.20 –0.20 10940-013 –0.15 0.05 0 DNL (LSB) 0 –0.05 –0.10 –0.15 –0.1 –0.20 –0.2 –0.3 0 100 CODE (Decimal) 200 –0.30 10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C 0 100 CODE (Decimal) Figure 13. DNL vs. Code (AD5141) Figure 10. INL vs. Code (AD5141) Rev. C | Page 14 of 32 100kΩ, –40°C 100kΩ, +25°C 100kΩ, +125°C 200 10940-017 –0.25 10940-014 INL (LSB) 0.1 Data Sheet AD5121/AD5141 0.15 1000 10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C 100kΩ, –40°C 100kΩ, +25°C 100kΩ, +125°C 0.10 VLOGIC = 2.3V VLOGIC = 3.3V VLOGIC = 5.5V 800 700 ILOGIC (nA) 0.05 INL (LSB) VDD = VLOGIC VSS = GND 900 0 –0.05 600 500 400 300 200 –0.10 100 0 –40 CODE (Decimal) –20 0.02 300 0 250 –0.02 150 50 –0.10 0 –0.12 –0.14 0 50 100 150 200 255 AD5141 0 25 50 75 CODE (Decimal) 100 127 AD5121 0 50 10940-019 –50 450 RHEOSTAT MODE TEMPERATURE COEFFICIENT (ppm/°C) 400 300 200 VDD = 2.3V VDD = 3.3V VDD = 5.5V 20 40 60 80 TEMPERATURE (°C) Figure 16. IDD vs. Temperature 100 120 350 300 250 200 150 100 50 0 –50 10940-020 IDD (nA) 10kΩ 100kΩ 400 500 0 100 Figure 18. DNL vs. Code (AD5121) VDD = VLOGIC VSS = GND 600 100kΩ, –40°C 100kΩ, +25°C 100kΩ, +125°C CODE (Decimal) Figure 15. Potentiometer Mode Temperature Coefficient ((ΔVW/VW)/ΔT × 106) vs. Code –20 120 –0.06 –0.08 100 100 –0.04 100 0 –40 80 10940-021 200 700 60 10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C 0.04 DNL (LSB) POTENTIOMETER MODE TEMPERATURE COEFFICIENT (ppm/°C) 0.06 350 800 40 Figure 17. ILOGIC vs. Temperature 100kΩ 10kΩ 400 20 TEMPERATURE (°C) Figure 14. INL vs. Code (AD5121) 450 0 0 50 100 150 200 255 AD5142 0 25 50 75 CODE (Decimal) 100 127 AD5122 10940-122 50 0 10940-018 –0.15 10940-060 100 Figure 19. Rheostat Mode Temperature Coefficient ((ΔRWB/RWB)/ΔT × 106) vs. Code Rev. C | Page 15 of 32 AD5121/AD5141 Data Sheet 1.2 0.8 VDD/VSS = ±2.5V RAB = 10kΩ 0 –20 PHASE (Degrees) 1.0 0.6 0.4 –40 –60 0.2 0 1 2 3 4 5 INPUT VOLTAGE (V) 0 0x80 (0x40) 0x20 (0x10) 1M 10M 0x80 (0x40) 0x8 (0x04) –30 0x10 (0x08) GAIN (dB) GAIN (dB) 100k –10 0x40 (0x20) 0x20 (0x10) –20 0x10 (0x08) –10 0x40 (0x20) 0x8 (0x04) 0x4 (0x02) 0x2 (0x01) –40 10k 1k Figure 23. Normalized Phase Flatness vs. Frequency, RAB = 10 kΩ 0 –30 100 FREQUENCY (Hz) Figure 20. ILOGIC Current vs. Digital Input Voltage –20 QUARTER SCALE MIDSCALE FULL-SCALE –100 10 10940-023 0 –80 10940-026 ILOGIC CURRENT (µA) 20 I2C, VLOGIC = 1.8V I2C, VLOGIC = 2.3V I2C, VLOGIC = 3.3V I2C, VLOGIC = 5V I2C, VLOGIC = 5.5V SPI, VLOGIC = 1.8V SPI, VLOGIC = 2.3V SPI, VLOGIC = 3.3V SPI, VLOGIC = 5V SPI, VLOGIC = 5.5V 0x1 (0x00) –40 –50 0x4 (0x02) 0x2 (0x01) 0x1 (0x00) 0x00 –60 0x00 –70 –50 –80 AD5121/AD5141 AD5121/AD5141 1k 10k 100k 1M 10M FREQUENCY (Hz) 100 –50 0 1M 10M 10kΩ 100kΩ –10 –20 –60 –30 THD + N (dB) THD + N (dB) 100k Figure 24. 100 kΩ Gain vs. Frequency vs. Code 10kΩ 100kΩ VDD/VSS = ±2.5V VA = 1V rms VB = GND CODE = HALF SCALE NOISE FILTER = 22kHz 10k FREQUENCY (Hz) Figure 21. 10 kΩ Gain vs. Frequency vs. Code –40 1k 10940-123 100 10940-022 –60 10 –90 10 –70 –80 –40 –50 –60 –70 –80 200 2k FREQUENCY (Hz) 20k 200k –90 0.001 10940-025 –100 20 Figure 22. Total Harmonic Distortion Plus Noise (THD + N) vs. Frequency VDD/VSS = ±2.5V fIN = 1kHz CODE = HALF SCALE NOISE FILTER = 22kHz 0.01 0.1 VOLTAGE (V rms) 1 10940-028 –90 Figure 25. Total Harmonic Distortion Plus Noise (THD + N) vs. Amplitude Rev. C | Page 16 of 32 Data Sheet AD5121/AD5141 10 0.8 0 0.7 –10 RELATIVE VOLTAGE (V) –30 –40 –50 –60 0.5 0.4 0.3 0.2 0.1 –70 100k 10k 1M FREQUENCY (Hz) –0.1 Figure 29. Maximum Transition Glitch 0.0025 100kΩ, V DD = 2.3V 100kΩ, V DD = 2.7V 100kΩ, V DD = 3V 100kΩ, V DD = 3.6V 100kΩ, V DD = 5V 100kΩ, V DD = 5.5V 10kΩ, VDD = 2.3V 10kΩ, VDD = 2.7V 10kΩ, VDD = 3V 10kΩ, VDD = 3.6V 10kΩ, VDD = 5V 10kΩ, VDD = 5.5V 400 300 1.2 1.0 0.0020 PROBABILITY DENSITY 500 15 10 TIME (µs) Figure 26. Normalized Phase Flatness vs. Frequency, RAB = 100 kΩ 600 5 0 200 0.8 0.0015 0.6 0.0010 0.4 0.0005 0.2 100 0 2 1 4 3 5 VOLTAGE (V) 0 0 10940-030 0 –600 –500 –400 –300 –200 –100 0 10kΩ + 0pF 10kΩ + 75pF 10kΩ + 150pF 10kΩ + 250pF 100kΩ + 0pF 100kΩ + 75pF 100kΩ + 150pF 100kΩ + 250pF –10 200 300 400 500 600 10kΩ 100kΩ –20 –30 PSRR (dB) 6 5 4 –40 –50 –60 3 –70 2 –90 10 0 0 20 40 0 10 20 80 100 120 AD5141 40 30 CODE (Decimal) 50 60 60 AD5121 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 31. Power Supply Rejection Ratio (PSRR) vs. Frequency Figure 28. Maximum Bandwidth vs. Code vs. Net Capacitance Rev. C | Page 17 of 32 10940-034 –80 1 10940-031 BANDWIDTH (MHz) 7 100 Figure 30. Resistor Lifetime Drift 10 8 0 RESISTOR DRIFT (ppm) Figure 27. Incremental Wiper On Resistance vs. VDD 9 10940-032 1k CUMULATIVE PROBABILITY 100 10940-029 –90 10 0 VDD/VSS = ±2.5V RAB = 100kΩ 10940-033 QUARTER SCALE MIDSCALE FULL-SCALE –80 WIPER ON RESISTANCE (Ω) VDD/VSS = ±2.5V VA = VDD VB = VSS 0.6 –20 PHASE (Degrees) 0x80 TO 0x7F, 100kΩ 0x80 TO 0x7F, 10kΩ Data Sheet 0.020 7 0.015 6 0.010 THEORETICAL IMAX (mA) RELATIVE VOLTAGE (V) AD5121/AD5141 0.005 0 –0.005 –0.010 5 4 3 2 10kΩ 1 –0.015 1500 1000 500 2000 TIME (ns) Figure 32. Digital Feedthrough 0 10kΩ 100kΩ SHUTDOWN MODE ENABLED –60 –80 –100 1k 10k 100k 1M FREQUENCY (Hz) 10M 10940-036 GAIN (dB) –40 100 0 50 100 0 25 50 75 CODE (Decimal) 150 200 100 250 AD5141 125 AD5121 Figure 34. Theoretical Maximum Current vs. Code –20 –120 10 0 Figure 33. Shutdown Isolation vs. Frequency Rev. C | Page 18 of 32 10940-037 0 10940-035 100kΩ –0.020 Data Sheet AD5121/AD5141 TEST CIRCUITS Figure 35 to Figure 39 define the test conditions used in the Specifications section. NC VA IW V+ = VDD ±10% V+ VMS Figure 35. Resistor Integral Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) PSRR (dB) = 20 LOG W B 10940-038 NC = NO CONNECT ~ A VMS 0.1V ISW CODE = 0x00 RSW = W V+ W B VMS B A = NC 10940-039 A V+ = VDD 1LSB = V+/2N Figure 36. Potentiometer Divider Nonlinearity Error (INL, DNL) IW = VDD/RNOMINAL DUT W VW B RW = VMS1/IW NC = NO CONNECT 10940-040 VMS1 + ISW – VSS TO VDD 0.1V Figure 39. Incremental on Resistance NC A ∆VDD% Figure 38. Power Supply Sensitivity and Power Supply Rejection Ratio (PSS and PSRR) DUT DUT PSS (%/%) = Figure 37. Wiper Resistance Rev. C | Page 19 of 32 ( ∆VMS ∆VDD ) ∆VMS% 10940-045 B VDD 10940-041 DUT A W AD5121/AD5141 Data Sheet THEORY OF OPERATION The AD5121/AD5141 digital programmable potentiometers are designed to operate as true variable resistors for analog signals within the terminal voltage range of VSS < VTERM < VDD. The resistor wiper position is determined by the RDAC register contents. The RDAC register acts as a scratchpad register that allows unlimited changes of resistance settings. A secondary register (the input register) can be used to preload the RDAC register data. The RDAC register can be programmed with any position setting using the I2C or SPI interface (depending on the model). When a desirable wiper position is found, this value can be stored in the EEPROM memory. Thereafter, the wiper position is always restored to that position for subsequent power-ups. The storing of EEPROM data takes approximately 18 ms; during this time, the device is locked and does not acknowledge any new command, preventing any changes from taking place. RDAC REGISTER AND EEPROM The RDAC register directly controls the position of the digital potentiometer wiper. For example, when the RDAC register is loaded with 0x80 (AD5141, 256 taps), the wiper is connected to half scale of the variable resistor. The RDAC register is a standard logic register; there is no restriction on the number of changes allowed. It is possible to both write to and read from the RDAC register using the digital interface (see Table 16). The contents of the RDAC register can be stored to the EEPROM using Command 9 (see Table 16). Thereafter, the RDAC register always sets at that position for any future on-off-on power supply sequence. It is possible to read back data saved into the EEPROM with Command 3 (see Table 16). Alternatively, the EEPROM can be written to independently using Command 1 (see Table 16). INPUT SHIFT REGISTER For the AD5121/AD5141, the input shift register is 16 bits wide, as shown in Figure 2. The 16-bit word consists of four control bits, followed by four address bits and by eight data bits SERIAL DATA DIGITAL INTERFACE SELECTION, DIS The AD5121/AD5141 LFSCP provides the flexibility of a selectable interface. When the digital interface select (DIS) pin is tied low, the SPI mode is engaged. When the DIS pin is tied high, the I2C mode is engaged. SPI SERIAL DATA INTERFACE The AD5121/AD5141 contain a 4-wire, SPI-compatible digital interface (SDI, SYNC, SDO, and SCLK). The write sequence begins by bringing the SYNC line low. The SYNC pin must be held low until the complete data-word is loaded from the SDI pin. Data is loaded in at the SCLK falling edge transition, as shown in Figure 4. When SYNC returns high, the serial data-word is decoded according to the instructions in Table 16. The AD5121/AD5141 do not require a continuous SCLK when SYNC is high. To minimize power consumption in the digital input buffers when the device is enabled, operate all serial interface pins close to the VLOGIC supply rails. SYNC Interruption In a standalone write sequence for the AD5121/AD5141, the SYNC line is kept low for 16 falling edges of SCLK, and the instruction is decoded when SYNC is pulled high. However, if the SYNC line is kept low for less than 16 falling edges of SCLK, the input shift register content is ignored, and the write sequence is considered invalid. SDO Pin The serial data output pin (SDO) serves two purposes: to read back the contents of the control, EEPROM, RDAC, and input registers using Command 3 (see Table 11 and Table 16), and to connect the AD5121/AD5141 to daisy-chain mode. The SDO pin contains an internal open-drain output that needs an external pull-up resistor. The SDO pin is enabled when SYNC is pulled low, and the data is clocked out of SDO on the rising edge of SCLK. If the AD5121 RDAC or EEPROM registers are read from or written to the lowest data bit (Bit 0) is ignored. Data is loaded MSB first (Bit 15). The four control bits determine the function of the software command, as listed in Table 11 and Table 16. Rev. C | Page 20 of 32 Data Sheet AD5121/AD5141 Daisy-Chain Connection To prevent data from mislocking (for example, due to noise) the device includes an internal counter, if the clock falling edges count is not a multiple of 8, the device ignores the command. A valid clock count is 16, 24, or 32. The counter resets when SYNC returns high. Daisy-chaining minimizes the number of port pins required from the controlling IC. As shown in Figure 40, the SDO pin of one package must be tied to the SDI pin of the next package. The clock period may need to be increased because of the propagation delay of the line between subsequent devices. When two AD5121/ AD5141 devices are daisy chained, 32 bits of data are required. The first 16 bits assigned to U2, and the second 16 bits assigned to U1, as shown in Figure 41. Keep the SYNC pin low until all 32 bits are clocked into their respective serial registers. The SYNC pin is then pulled high to complete the operation. A typical connection is shown in Figure 40. VLOGIC VLOGIC AD5121/ AD5141 MOSI SDI SDI SDO U1 AD5121/ AD5141 RP 2.2kΩ RP 2.2kΩ U2 SDO SCLK SYNC SCLK 10940-046 SYNC DAISY-CHAIN MICROCONTROLLER MISO SCLK SS Figure 40. Daisy-Chain Configuration SCLK 1 2 16 17 18 32 SYNC DB15 DB0 INPUT WORD FOR U1 INPUT WORD FOR U2 SDO_U1 DB0 DB15 DB0 DB15 DB15 UNDEFINED DB0 INPUT WORD FOR U2 Figure 41. Daisy-Chain Diagram Rev. C | Page 21 of 32 10940-047 MOSI AD5121/AD5141 Data Sheet I2C SERIAL DATA INTERFACE 3. When all data bits have been read from or written to, a stop condition is established. In write mode, the master pulls the SDA line high during the tenth clock pulse to establish a stop condition. In read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the SDA line remains high). The master then brings the SDA line low before the tenth clock pulse, and then high again during the tenth clock pulse to establish a stop condition. The AD5141 has 2-wire, I2C-compatible serial interface. These devices can be connected to an I2C bus as a slave device, under the control of a master device. See Figure 3 for a timing diagram of a typical write sequence. The AD5141 supports standard (100 kHz) and fast (400 kHz) data transfer modes. Support is not provided for 10-bit addressing and general call addressing. I2C ADDRESS The 2-wire serial bus protocol operates as follows: 1. 2. The AD5141 has two different pin address options available, as shown in Table 10. The master initiates a data transfer by establishing a start condition, which is when a high-to-low transition on the SDA line occurs while SCL is high. The following byte is the address byte, which consists of the 7-bit slave address and an R/W bit. The slave device corresponding to the transmitted address responds by pulling SDA low during the ninth clock pulse (this is called the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its shift register. If the R/W bit is set high, the master reads from the slave device. However, if the R/W bit is set low, the master writes to the slave device. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL. Table 10. 24-Lead LFCSP Device Address Selection ADDR0 Pin VLOGIC No connect1 GND VLOGIC No connect1 GND VLOGIC No connect1 GND 1 ADDR1 Pin VLOGIC VLOGIC VLOGIC No connect1 No connect1 No connect1 GND GND GND 7-Bit I2C Device Address 0100000 0100010 0100011 0101000 0101010 0101011 0101100 0101110 0101111 Not available in bipolar mode (VSS < 0 V) or in low voltage mode (VLOGIC = 1.8 V). Table 11. Simple Command Operation Truth Table Command Number 0 1 Control Bits[DB15:DB12] C3 C2 C1 C0 0 0 0 0 0 0 0 1 Address Bits[DB11:DB8]1 A3 A2 A1 A0 X X X X 0 0 0 0 2 0 0 1 0 0 0 0 3 0 0 1 1 X 0 9 10 14 15 0 0 1 1 1 1 0 1 1 1 1 0 1 1 1 0 X X X 0 X X X 0 1 D7 X D7 Data Bits[DB7:DB0]1 D6 D5 D4 D3 D2 D1 X X X X X X D6 D5 D4 D3 D2 D1 D0 X D0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 X X X X X X D1 D0 0 0 X 0 0 0 X 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 0 X D0 X = don’t care. Rev. C | Page 22 of 32 Operation NOP: do nothing Write contents of serial register data to RDAC Write contents of serial register data to input register Read back contents D1 D0 Data 0 1 EEPROM 1 1 RDAC Copy RDAC register to EEPROM Copy EEPROM into RDAC Software reset Software shutdown D0 Condition 0 Normal mode 1 Shutdown mode Data Sheet AD5121/AD5141 ADVANCED CONTROL MODES Low Wiper Resistance Feature The AD5121/AD5141 digital potentiometers include a set of user programming features to address the wide number of applications for these universal adjustment devices (see Table 16 and Table 18). The AD5121/AD5141 include two commands to reduce the wiper resistance between the terminals when they achieve full scale or zero scale. These extra positions are called bottom scale, BS, and top scale, TS. The resistance between Terminal A and Terminal W at top scale is specified as RTS. Similarly, the bottom scale resistance between Terminal B and Terminal W is specified as RBS. Key programming features include the following: • • • • • • • • Input register Linear gain setting mode Low wiper resistance feature Linear increment and decrement instructions ±6 dB increment and decrement instructions Burst mode (I2C only) Reset Shutdown mode The contents of the RDAC registers are unchanged by entering in these positions. There are two ways to exit from top scale and bottom scale: by using Command 12 or Command 13 (see Table 16); or by loading new data in an RDAC register, which includes increment/decrement operations and a shutdown command. Table 12 and Table 13 show the truth tables for the top scale position and the bottom scale position, respectively, when linear gain setting mode is enabled. Input Register The AD5121/AD5141 include one input register per RDAC register. This register allows preloading of the value for the associated RDAC register. Table 12. Top Scale Truth Table This feature allows a synchronous and asynchronous update of one or all the RDAC registers at the same time. These registers can be written to using Command 2 and read back from using Command 3 (see Table 16). The transfer from the input register to the RDAC register is done asynchronously by the LRDAC pin or synchronously by Command 8 (see Table 16). If new data is loaded in an RDAC register, this RDAC register automatically overwrites the associated input register. Linear Gain Setting Mode The proprietary architecture of the AD5121/AD5141 allows the independent control of each string resistor, RAW and RWB. To enable this feature, use Command 16 (see Table 16) to set Bit D2 of the control register (see Table 18). Linear Gain Setting Mode RAW RWB RAB RAB RAW RTS Potentiometer Mode RWB RAB Table 13. Bottom Scale Truth Table Linear Gain Setting Mode RAW RWB RTS RBS RAW RAB Potentiometer Mode RWB RBS Linear Increment and Decrement Instructions The increment and decrement commands (Command 4 and Command 5 in Table 16) are useful for linear step adjustment applications. These commands simplify microcontroller software coding by allowing the controller to send an increment or decrement command to the device. The adjustment can be individual or in a ganged potentiometer arrangement, where all wiper positions are changed at the same time. This mode of operation can control the potentiometer as two independent rheostats connected at a single point, W terminal, as opposed to potentiometer mode where each resistor is complementary, RAW = RAB − RWB. For an increment command, executing Command 4 automatically moves the wiper to the next resistance segment position. This command can be executed in a single channel or multiple channels. This feature enables a second input and an RDAC register per channel, as shown in Table 16; however, the actual RDAC contents remain unchanged. The same operations are valid for potentiometer and linear gain setting modes. Two programming instructions produce logarithmic taper increment or decrement of the wiper position control by an individual potentiometer or by a ganged potentiometer arrangement where all RDAC register positions are changed simultaneously. The +6 dB increment is activated by Command 6, and the −6 dB decrement is activated by Command 7 (see Table 16). For example, starting with the zero-scale position and executing Command 6 ten times moves the wiper in 6 dB steps to the full-scale position. When the wiper position is near the maximum setting, the last 6 dB increment instruction causes the wiper to go to the full-scale position (see Table 14). If the INDEP pin is pulled high, the device powers up in linear gain setting mode and loads the values stored in the associated memory locations for each channel (see Table 17). The INDEP pin and D2 bit are connected internally to a logic OR gate, if any or both are 1, the devices cannot operate in potentiometer mode. ±6 dB Increment and Decrement Instructions Rev. C | Page 23 of 32 AD5121/AD5141 Data Sheet Incrementing the wiper position by +6 dB essentially doubles the RDAC register value, whereas decrementing the wiper position by −6 dB halves the register content. Internally, the AD5121/AD5141 use shift registers to shift the bits left and right to achieve a ±6 dB increment or decrement. These functions are useful for various audio/video level adjustments, especially for white LED brightness settings in which human visual responses are more sensitive to large adjustments than to small adjustments. Table 14. Detailed Left Shift and Right Shift Functions for the ±6 dB Step Increment and Decrement Left Shift (+6 dB/Step) 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0000 1111 1111 Right Shift (−6 dB/Step) 1111 1111 0111 1111 0011 1111 0001 1111 0000 1111 0000 0111 0000 0011 0000 0001 0000 0000 0000 0000 Table 15. Truth Table for Shutdown Mode A2 0 1 1 Linear Gain Setting Mode AW WB N/A1 Open Open N/A1 Potentiometer Mode AW WB Open RBS N/A1 N/A1 N/A = not applicable. EEPROM OR RDAC REGISTER PROTECTION The EEPROM and RDAC registers can be protected by disabling any update to these registers. This can be done by using software or by using hardware. If these registers are protected by software, set Bit D0 and/or Bit D1 (see Table 18), which protects the RDAC and EEPROM registers independently. If the registers are protected by hardware, pull the WP pin low. If the WP pin is pulled low when the device is executing a command, the protection is not enabled until the command is completed. When RDAC is protected, the only operation allowed is to copy the EEPROM into the RDAC register. LOAD RDAC INPUT REGISTER (LRDAC) Burst Mode (I2C Only) By enabling the burst mode, multiple data bytes can be sent to the device consecutively. After the command byte, the device interprets the consecutive bytes as data bytes for the first command. A new command can be sent by generating a repeat start or by a stop and start condition. The burst mode is activated by setting Bit D3 of the control register (see Table 18), and if a reset or power-down is performed, it automatically resets. Reset The AD5121/AD5141 can be reset through software by executing Command 14 (see Table 16) or through hardware on the low pulse of the RESET pin. The reset command loads the RDAC register with the contents of the EEPROM and takes approximately 30 µs. The EEPROM is preloaded to midscale at the factory, and initial power-up is, accordingly, at midscale. Tie RESET to VDD if the RESET pin is not used. Shutdown Mode The AD5121/AD5141 can be placed in shutdown mode by executing the software shutdown command, Command 15 (see Table 16); and by setting the LSB (D0) to 1. This feature places the RDAC in a special state. The contents of the RDAC register are unchanged by entering shutdown mode. However, all commands listed in Table 16 are supported while in shutdown mode. Execute Command 15 (see Table 16) and set the LSB (D0) to 0 to exit shutdown mode. LRDAC software or hardware transfers data from the input register to the RDAC register (and therefore updates the wiper position). By default, the input register has the same value as the RDAC register; therefore, only the input register that has been updated using Command 2 is updated. Software LRDAC, Command 8, allows updating of a single RDAC register or all of the channels at once (see Table 16). This is a synchronous update. The hardware LRDAC is completely asynchronous and copies the content of all the input registers into the associated RDAC registers. If a command is executed, to avoid data corruption, any transition in the LRDAC pin is ignored by the device. INDEP PIN If the INDEP pin is pulled high at power-up, the device operates in linear gain setting mode, loading each string resistor, RAW and RWB, with the value stored into the EEPROM (see Table 17). If the pin is pulled low, the device powers up in potentiometer mode. The INDEP pin and the D2 bit are connected internally to a logic OR gate, if any or both are 1, the device cannot operate in potentiometer mode (see Table 18). Rev. C | Page 24 of 32 Data Sheet AD5121/AD5141 Table 16. Advance Commands Operation Truth Table Command Number 0 1 Control Bits[DB15:DB12] C3 C2 C1 C0 0 0 0 0 0 0 0 1 Address Bits[DB11:DB8]1 A3 A2 A1 A0 X X X X 0 A2 0 A0 D7 X D7 2 0 0 1 0 0 A2 0 A0 3 0 0 1 1 X A2 A1 4 5 6 7 8 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 0 A3 A3 A3 A3 A3 A2 A2 A2 A2 A2 9 0 1 1 1 0 10 11 0 1 1 0 1 0 1 0 12 1 0 0 13 1 0 14 15 1 1 16 1 1 D6 X D6 Data Bits[DB7:DB0]1 D5 D4 D3 D2 D1 X X X X X D5 D4 D3 D2 D1 D0 X D0 D7 D6 D5 D4 D3 D2 D1 D0 A0 X X X X X X D1 D0 0 0 0 0 0 A0 A0 A0 A0 A0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 0 1 0 X A2 0 A0 X X X X X X X 1 0 0 A2 A2 0 0 A0 A0 X D7 X D6 X D5 X D4 X D3 X D2 X D1 0 D0 1 A3 A2 0 A0 1 X X X X X X D0 0 1 A3 A2 0 A0 0 X X X X X X D0 0 1 1 0 1 0 X A3 X A2 X 0 X A0 X X X X X X X X X X X X X X X D0 1 0 1 X X X X X X X X D3 D2 D1 D0 Operation NOP: do nothing Write contents of serial register data to RDAC Write contents of serial register data to input register Read back contents D1 D0 Data 0 0 Input register 0 1 EEPROM 1 0 Control register 1 1 RDAC Linear RDAC increment Linear RDAC decrement +6 dB RDAC increment −6 dB RDAC decrement Copy input register to RDAC (software LRDAC) Copy RDAC register to EEPROM Copy EEPROM into RDAC Write contents of serial register data to EEPROM Top scale D0 = 0; normal mode D0 = 1; shutdown mode Bottom scale D0 = 1; enter D0 = 0; exit Software reset Software shutdown D0 = 0; normal mode D0 = 1; device placed in shutdown mode Copy serial register data to control register X = don’t care. Table 17. Address Bits A3 1 0 0 0 0 0 1 A2 X1 0 1 0 0 0 A1 X1 0 0 0 1 1 A0 X1 0 0 1 0 1 Potentiometer Mode Input Register RDAC Register All channels All channels RDAC RDAC Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Linear Gain Setting Mode Input Register RDAC Register All channels All channels RWB RWB RAW RAW Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable X = don’t care. Rev. C | Page 25 of 32 Stored RDAC Memory Not applicable RDAC/RWB Not applicable RAW MSB tolerance LSB tolerance AD5121/AD5141 Data Sheet Table 18. Control Register Bit Descriptions Bit Name D0 D1 D2 D3 Description RDAC register write protect 0 = wiper position frozen to value in EEPROM memory 1 = allows update of wiper position through digital interface (default) EEPROM program enable 0 = EEPROM program disabled 1 = enables device for EEPROM program (default) Linear setting mode/potentiometer mode 0 = potentiometer mode (default) 1 = linear gain setting mode Burst mode (I2C only) 0 = disabled (default) 1 = enabled (no disable after stop or repeat start condition) Rev. C | Page 26 of 32 Data Sheet AD5121/AD5141 RDAC ARCHITECTURE PROGRAMMING THE VARIABLE RESISTOR To achieve optimum performance, Analog Devices, Inc., uses a proprietary RDAC segmentation architecture for all the digital potentiometers. In particular, the AD5121/AD5141 employ a three-stage segmentation approach, as shown in Figure 42. The AD5121/AD5141 wiper switch is designed with the transmission gate CMOS topology and with the gate voltage derived from VDD and VSS. Rheostat Operation—±8% Resistor Tolerance A A W STS B B RL W B AD5121: RL RWB (D )  RM RH D  R AB  RW From 0x00 to 0x7F 128 (1) D  R AB  RW From 0x00 to 0xFF 256 (2) AD5141: RM RH W The nominal resistance between Terminal A and Terminal B, RAB, is 10 kΩ or 100 kΩ, and has 128/256 tap points accessed by the wiper terminal. The 7-bit/8-bit data in the RDAC latch is decoded to select one of the 128/256 possible wiper settings. The general equations for determining the digitally programmed output resistance between Terminal W and Terminal B are RM RM 7-BIT/8-BIT ADDRESS DECODER W Figure 43. Rheostat Mode Configuration RH RH A 10940-049 A The AD5121/AD5141 operate in rheostat mode when only two terminals are used as a variable resistor. The unused terminal can be floating, or it can be tied to Terminal W, as shown in Figure 43. RWB ( D )  SBS where: 10940-048 B Figure 42. AD5121/AD5141 Simplified RDAC Circuit Top Scale/Bottom Scale Architecture In addition, the AD5121/AD5141 include new positions to reduce the resistance between terminals. These positions are called bottom scale and top scale. At bottom scale, the typical wiper resistance decreases from 130 Ω to 60 Ω (RAB = 100 kΩ). At top scale, the resistance between Terminal A and Terminal W is decreased by 1 LSB, and the total resistance is reduced to 60 Ω (RAB = 100 kΩ). D is the decimal equivalent of the binary code in the 7-bit/8-bit RDAC register. RAB is the end-to-end resistance. RW is the wiper resistance. In potentiometer mode, similar to the mechanical potentiometer, the resistance of the RDAC between Terminal W and Terminal A also produces a digitally controlled complementary resistance, RWA. RWA also gives a maximum of 8% absolute resistance error. RWA starts at the maximum resistance value and decreases as the data loaded into the latch increases. The general equations for this operation are AD5121: RAW (D )  128  D  RAB  RW 128 From 0x00 to 0x7F (3) AD5141: RAW (D )  256  D  RAB  RW From 0x00 to 0xFF 256 (4) where: D is the decimal equivalent of the binary code in the 7-bit/8-bit RDAC register. RAB is the end-to-end resistance. RW is the wiper resistance. Rev. C | Page 27 of 32 AD5121/AD5141 Data Sheet That is, if the data readback from Address 0x02 is 00000010, and the data readback from Address 0x03 is 10110000, the end-to-end resistance can be calculated as follows. If the device is configured in linear gain setting mode, the resistance between Terminal W and Terminal A is directly proportional to the code loaded in the associate RDAC register. The general equations for this operation are For Memory Map Address 0x02, DB[7] = 0 = negative, and DB[6:0] = 0000010 = 2. AD5121: D  R AB  RW From 0x00 to 0x7F 128 For Memory Map Address 0x03, DB[7:0] = 10110000 = 176 × 2−8 = 0.6875, and therefore, tolerance = −2.6875%, and RAB = 9.731 kΩ. (5) AD5141: R AW ( D )  PROGRAMMING THE POTENTIOMETER DIVIDER D  R AB  RW From 0x00 to 0xFF 256 Voltage Output Operation (6) The digital potentiometer easily generates a voltage divider at wiper-to-B and wiper-to-A that is proportional to the input voltage at A to B, as shown in Figure 44. where: D is the decimal equivalent of the binary code in the 7-bit/8-bit RDAC register. RAB is the end-to-end resistance. RW is the wiper resistance. VA A W In the bottom scale condition or top scale condition, a finite total wiper resistance of 40 Ω is present. Regardless of which setting the device is operating in, limit the current between Terminal A to Terminal B, Terminal W to Terminal A, and Terminal W to Terminal B, to the maximum continuous current of ±6 mA or to the pulse current specified in Table 7. Otherwise, degradation or possible destruction of the internal switch contact can occur. VB VOUT 10940-050 R AW (D )  B Figure 44. Potentiometer Mode Configuration Connecting Terminal A to 5 V and Terminal B to ground produces an output voltage at the Wiper W to Terminal B ranging from 0 V to 5 V. The general equation defining the output voltage at VW with respect to ground for any valid input voltage applied to Terminal A and Terminal B is VW (D)  Calculate the Actual End-to-End Resistance The resistance tolerance is stored in the internal memory during factory testing. Therefore, the actual end-to-end resistance can be calculated (which is valuable for calibration, tolerance matching, and precision applications). R (D) RWB (D)  VA  AW  VB RAB RAB (7) where: RWB(D) can be obtained from Equation 1 and Equation 2. RAW(D) can be obtained from Equation 3 and Equation 4. The resistance tolerance (in percentage) is stored in fixed point format, using a 16-bit sign magnitude binary. The sign bit (0 = negative and 1 = positive) and the integer part are located in Address 0x02, as shown in Table 19. Address 0x03 contains the fractional part, as shown in Table 19. Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors, RAW and RWB, and not the absolute values. Therefore, the temperature drift reduces to 5 ppm/°C. Table 19. End-to-End Resistance Tolerance Bytes Memory Map Address 0x02 0x03 DB7 Sign 2−1 DB6 26 2−2 DB5 25 2−3 Rev. C | Page 28 of 32 DB4 24 2−4 Data Byte DB3 23 2−5 DB2 22 2−6 DB1 21 2−7 DB0 20 2−8 Data Sheet AD5121/AD5141 TERMINAL VOLTAGE OPERATING RANGE LAYOUT AND POWER SUPPLY BIASING The AD5121/AD5141 are designed with internal ESD diodes for protection. These diodes also set the voltage boundary of the terminal operating voltages. Positive signals present on Terminal A, Terminal B, or Terminal W that exceed VDD are clamped by the forward-biased diode. There is no polarity constraint between VA, VW, and VB, but they cannot be higher than VDD or lower than VSS. It is always a good practice to use a compact, minimum lead length layout design. Ensure that the leads to the input are as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. It is also good practice to bypass the power supplies with quality capacitors. Apply low equivalent series resistance (ESR) 1 μF to 10 μF tantalum or electrolytic capacitors at the supplies to minimize any transient disturbance and to filter low frequency ripple. Figure 46 illustrates the basic supply bypassing configuration for the AD5121/AD5141. VDD A VDD W + C3 10µF C1 0.1µF + C4 10µF C2 0.1µF VSS 10940-051 B VSS VDD VLOGIC C5 0.1µF C6 10µF + VLOGIC AD5121/ AD5141 VDD GND 10940-052 Figure 45. Maximum Terminal Voltages Set by VDD and VSS POWER-UP SEQUENCE Because there are diodes to limit the voltage compliance at Terminal A, Terminal B, and Terminal W (see Figure 45), it is important to power up VDD first before applying any voltage to Terminal A, Terminal B, and Terminal W. Otherwise, the diode is forward-biased such that VDD is powered unintentionally. The ideal power-up sequence is VSS, VDD, VLOGIC, digital inputs, and VA, VB, and VW. The order of powering VA, VB, VW, and digital inputs is not important as long as they are powered after VSS, VDD, and VLOGIC. Regardless of the power-up sequence and the ramp rates of the power supplies, once VLOGIC is powered, the power-on preset activates, which restores EEPROM values to the RDAC registers. Rev. C | Page 29 of 32 Figure 46. Power Supply Bypassing AD5121/AD5141 Data Sheet OUTLINE DIMENSIONS 3.10 3.00 SQ 2.90 0.50 BSC 13 PIN 1 INDICATOR AREA OPTIONS 16 (SEE DETAIL A) 12 1 1.75 1.60 SQ 1.45 EXPOSED PAD 9 TOP VIEW 0.80 0.75 0.70 TOP VIEW PKG-005138 SEATING PLANE 0.50 0.40 0.30 4 8 5 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6. 02-23-2017-E PIN 1 INDICATOR DETAIL A (JEDEC 95) 0.30 0.23 0.18 Figure 47. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-16-22) Dimensions shown in millimeters ORDERING GUIDE Model1, 2,3 AD5121BCPZ10-RL7 AD5121BCPZ100-RL7 AD5121WBCPZ10-RL7 AD5141BCPZ10-RL7 AD5141BCPZ100-RL7 AD5141WBCPZ10-RL7 EVAL-AD5141DBZ RAB (kΩ) 10 100 10 10 100 10 Resolution 128 128 128 256 256 256 Interface SPI/I2C SPI/I2C SPI/I2C SPI/I2C SPI/I2C SPI/I2C Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 16-Lead LFCSP 16-Lead LFCSP 16-Lead LFCSP 16-Lead LFCSP 16-Lead LFCSP 16-Lead LFCSP Evaluation Board Package Option CP-16-22 CP-16-22 CP-16-22 CP-16-22 CP-16-22 CP-16-22 Branding DHE DHF DMT DHC DHD DN3 1 Z = RoHS Compliant Part The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with both of the available resistor value options. 3 W = Qualified for Automotive Applications 2 AUTOMOTIVE PRODUCTS The AD5121W and AD5141W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. Rev. C | Page 30 of 32 Data Sheet AD5121/AD5141 NOTES Rev. C | Page 31 of 32 AD5121/AD5141 Data Sheet NOTES ©2012–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10940-0-5/17(C) Rev. C | Page 32 of 32