256-Position SPI Compatible
Digital Potentiometer
AD5160
FUNCTIONAL BLOCK DIAGRAM
FEATURES
256-position
End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Compact SOT-23-8 (2.9 mm × 3 mm) package
SPI compatible interface
Power-on preset to midscale
Single supply 2.7 V to 5.5 V
Low temperature coefficient 45 ppm/°C
Low power, IDD = 8 µA
Wide operating temperature –40°C to +125°C
Evaluation board available
VDD
A
CS
SPI INTERFACE
SDI
W
CLK
WIPER
REGISTER
B
GND
Figure 1.
APPLICATIONS
Mechanical potentiometer replacement in new designs
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment
PIN CONFIGURATION
W 1
VDD 2
8 A
AD5160
7 B
6 CS
TOP VIEW
CLK 4 (Not to Scale) 5 SDI
GND 3
GENERAL OVERVIEW
The AD5160 provides a compact 2.9 mm × 3 mm packaged
solution for 256-position adjustment applications. These devices
perform the same electronic adjustment function as mechanical
potentiometers or variable resistors, with enhanced resolution,
solid-state reliability, and superior low temperature coefficient
performance.
Figure 2.
The wiper settings are controllable through an SPI compatible
digital interface. The resistance between the wiper and either
end point of the fixed resistor varies linearly with respect to the
digital code transferred into the RDAC latch.
Operating from a 2.7 V to 5.5 V power supply and consuming
less than 5 µA allows for usage in portable battery-operated
applications.
Note:
The terms digital potentiometer, VR, and RDAC are used interchangeably.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2003 Analog Devices, Inc. All rights reserved.
AD5160
TABLE OF CONTENTS
Electrical Characteristics—5 kΩ Version ...................................... 3
ESD Protection ........................................................................... 13
Electrical Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions ....... 4
Terminal Voltage Operating Range.......................................... 13
Timing Characteristics—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Versions 5
Power-Up Sequence ................................................................... 13
Absolute Maximum Ratings ........................................................... 5
Layout and Power Supply Bypassing ....................................... 14
Typical Performance Characteristics ............................................. 6
Pin Configuration and Function Descriptions........................... 15
Test Circuits..................................................................................... 10
Pin Configuration ...................................................................... 15
SPI Interface .................................................................................... 11
Pin Function Descriptions ........................................................ 15
Operation......................................................................................... 12
Outline Dimensions ....................................................................... 16
Programming the Variable Resistor ......................................... 12
Ordering Guide .......................................................................... 16
Programming the Potentiometer Divider ............................... 13
ESD Caution................................................................................ 16
SPI Compatible 3-Wire Serial Bus ........................................... 13
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 16
AD5160
ELECTRICAL CHARACTERISTICS—5 kΩ VERSION
(VDD = 5 V ± 10%, or 3 V ± 10%; VA = +VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted.)
Table 1.
Parameter
Symbol
Conditions
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
R-DNL
RWB, VA = no connect
Resistor Integral Nonlinearity2
R-INL
RWB, VA = no connect
Nominal Resistor Tolerance3
∆RAB
TA = 25°C
Resistance Temperature Coefficient
∆RAB/∆T
VAB = VDD, Wiper = no connect
Wiper Resistance
RW
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs)
Resolution
N
Differential Nonlinearity4
DNL
Integral Nonlinearity4
INL
Voltage Divider Temperature Coefficient
∆VW/∆T
Code = 0x80
Full-Scale Error
VWFSE
Code = 0xFF
Zero-Scale Error
VWZSE
Code = 0x00
RESISTOR TERMINALS
Voltage Range5
VA,B,W
Capacitance6 A, B
CA,B
f = 1 MHz, measured to GND,
Code = 0x80
Capacitance6 W
CW
f = 1 MHz, measured to GND,
Code = 0x80
Shutdown Supply Current7
IDD_SD
VDD = 5.5 V
Common-Mode Leakage
ICM
VA = VB = VDD/2
DIGITAL INPUTS AND OUTPUTS
Input Logic High
VIH
Input Logic Low
VIL
Input Logic High
VIH
VDD = 3 V
Input Logic Low
VIL
VDD = 3 V
Input Current
IIL
VIN = 0 V or 5 V
6
Input Capacitance
CIL
POWER SUPPLIES
Power Supply Range
VDD RANGE
Supply Current
IDD
VIH = 5 V or VIL = 0 V
Power Dissipation8
PDISS
VIH = 5 V or VIL = 0 V, VDD = 5 V
Power Supply Sensitivity
PSS
∆VDD = +5 V ± 10%,
Code = Midscale
DYNAMIC CHARACTERISTICS6, 9
Bandwidth –3dB
BW_5K
RAB = 5 kΩ, Code = 0x80
Total Harmonic Distortion
THDW
VA = 1 V rms, VB = 0 V, f = 1 kHz
VW Settling Time
tS
VA= 5 V, VB = 0 V, ±1 LSB error
band
Resistor Noise Voltage Density
eN_WB
RWB = 2.5 kΩ, RS = 0
Rev. 0 | Page 3 of 16
Min
Typ1
Max
Unit
–1.5
–4
–30
±0.1
±0.75
+1.5
+4
+30
LSB
LSB
%
ppm/°C
Ω
45
50
–1.5
–1.5
–6
0
±0.1
±0.6
15
–2.5
+2
GND
120
8
+1.5
+1.5
0
+6
VDD
Bits
LSB
LSB
ppm/°C
LSB
LSB
45
V
pF
60
pF
0.01
1
1
2.4
0.8
2.1
0.6
±1
5
2.7
3
±0.02
5.5
8
0.2
±0.05
µA
nA
V
V
V
V
µA
pF
V
µA
mW
%/%
1.2
0.05
1
MHz
%
µs
6
nV/√Hz
AD5160
ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS
(VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted.)
Table 2.
Parameter
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
Symbol
Conditions
RWB, VA = no connect
RWB, VA = no connect
TA = 25°C
VAB = VDD,
Wiper = no connect
Wiper Resistance
RW
VDD = 5 V
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs)
Resolution
N
Differential Nonlinearity4
DNL
Integral Nonlinearity4
INL
Voltage Divider Temperature Coefficient
∆VW/∆T
Code = 0x80
Full-Scale Error
VWFSE
Code = 0xFF
Zero-Scale Error
VWZSE
Code = 0x00
RESISTOR TERMINALS
Voltage Range5
VA,B,W
Capacitance6 A, B
CA,B
f = 1 MHz, measured to
GND, Code = 0x80
Capacitance6 W
CW
f = 1 MHz, measured to
GND, Code = 0x80
Shutdown Supply Current7
IDD_SD
VDD = 5.5 V
Common-Mode Leakage
ICM
VA = VB = VDD/2
DIGITAL INPUTS AND OUTPUTS
Input Logic High
VIH
Input Logic Low
VIL
Input Logic High
VIH
VDD = 3 V
Input Logic Low
VIL
VDD = 3 V
Input Current
IIL
VIN = 0 V or 5 V
Input Capacitance6
CIL
POWER SUPPLIES
Power Supply Range
VDD RANGE
Supply Current
IDD
VIH = 5 V or VIL = 0 V
Power Dissipation8
PDISS
VIH = 5 V or VIL = 0 V,
VDD = 5 V
Power Supply Sensitivity
PSS
∆VDD = +5 V ± 10%,
Code = Midscale
DYNAMIC CHARACTERISTICS6, 9
Bandwidth –3dB
BW
RAB = 10 kΩ/50 kΩ/100 kΩ,
Code = 0x80
Total Harmonic Distortion
THDW
VA =1 V rms, VB = 0 V,
f = 1 kHz, RAB = 10 kΩ
VW Settling Time (10 kΩ/50 kΩ/100 kΩ)
tS
VA = 5 V, VB = 0 V,
±1 LSB error band
Resistor Noise Voltage Density
eN_WB
RWB = 5 kΩ, RS = 0
R-DNL
R-INL
∆RAB
∆RAB/∆T
Rev. 0 | Page 4 of 16
Min
Typ1
Max
Unit
–1
–2
–30
±0.1
±0.25
+1
+2
+30
LSB
LSB
%
ppm/°C
120
Ω
8
+1
+1
Bits
LSB
LSB
ppm/°C
LSB
LSB
45
50
–1
–1
–3
0
±0.1
±0.3
15
–1
1
GND
0
3
45
VDD
V
pF
60
pF
0.01
1
1
2.4
0.8
2.1
0.6
±1
5
2.7
µA
nA
V
V
V
V
µA
pF
3
5.5
8
0.2
V
µA
mW
±0.02
±0.05
%/%
600/100/40
kHz
0.05
%
2
µs
9
nV/√Hz
AD5160
TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS
(VDD = +5V ± 10%, or +3V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted.)
Table 3.
Parameter
Symbol
Conditions
SPI INTERFACE TIMING CHARACTERISTICS6, 10 (Specifications Apply to All Parts)
Clock Frequency
fCLK
Input Clock Pulsewidth
tCH, tCL
Clock level high or low
Data Setup Time
tDS
Data Hold Time
tDH
tCSS
CS Setup Time
tCSW
CS High Pulsewidth
tCSH0
CLK Fall to CS Fall Hold Time
tCSH1
CLK Fall to CS Rise Hold Time
tCS1
CS Rise to Clock Rise Setup
Min
20
5
5
15
40
0
0
10
Typ1
Max
Unit
25
MHz
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
1
Typical specifications represent average readings at +25°C and VDD = 5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
VAB = VDD, Wiper (VW) = no connect.
4
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8
PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
9
All dynamic characteristics use VDD = 5 V.
10
See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage
level of 1.5 V.
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C, unless otherwise noted.)
Table 4.
Parameter
VDD to GND
VA, VB, VW to GND
IMAX1
Digital Inputs and Output Voltage to GND
Operating Temperature Range
Maximum Junction Temperature (TJMAX)
Storage Temperature
Lead Temperature (Soldering, 10 sec)
Thermal Resistance2 θJA: MSOP-10
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Value
–0.3 V to +7 V
VDD
±20 mA
0 V to +7 V
–40°C to +125°C
150°C
–65°C to +150°C
300°C
230°C/W
NOTES
1
Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2
Package power dissipation = (TJMAX – TA)/θJA.
Rev. 0 | Page 5 of 16
AD5160
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
1.0
5V
0.8
POTENTIOMETER MODE DNL (LSB)
RHEOSTAT MODE INL (LSB)
–40°C
+25°C
+85°C
+125°C
0.8
3V
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
32
64
96
128
160
192
224
256
0
32
64
CODE (Decimal)
160
192
224
256
Figure 6. DNL vs. Code, VDD = 5 V
1.0
1.0
0.8
0.8
5V
3V
0.6
POTENTIOMETER MODE INL (LSB)
RHEOSTAT MODE DNL (LSB)
128
CODE (Decimal)
Figure 3. R-INL vs. Code vs. Supply Voltages
0.4
0.2
0
–0.2
–0.4
–0.6
5V
3V
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–0.8
–1.0
–1.0
0
32
64
96
128
160
192
224
0
256
32
64
96
128
160
192
224
256
CODE (Decimal)
CODE (Decimal)
Figure 7. INL vs. Code vs. Supply Voltages
Figure 4. R-DNL vs. Code vs. Supply Voltages
1.0
1.0
_40°C
+25°C
+85°C
+125°C
0.6
5V
0.8
POTENTIOMETER MODE DNL(LSB)
0.8
POTENTIOMETER MODE INL (LSB)
96
0.4
0.2
0
–0.2
–0.4
–0.6
3V
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–0.8
–1.0
–1.0
0
32
64
96
128
160
192
224
256
0
CODE (Decimal)
32
64
96
128
160
192
CODE (Decimal)
Figure 5. INL vs. Code, VDD = 5 V
Figure 8. DNL vs. Code vs. Supply Voltages
Rev. 0 | Page 6 of 16
224
256
AD5160
1.0
2.5
RHEOSTAT MODE INL (LSB)
0.6
2.0
ZSE, ZERO-SCALE ERROR (µA)
–40 °C
+25°C
+85°C
+125°C
0.8
0.4
0.2
0
–0.2
–0.4
–0.6
VDD = 5.5V
1.5
VDD = 2.7V
1.0
0.5
–0.8
0
–40
–1.0
0
32
64
96
128
160
192
224
256
0
80
120
Figure 12. Zero-Scale Error vs. Temperature
Figure 9. R-INL vs. Code, VDD = 5 V
1.0
10
_40°C
0.8
+25°C
+85°C
+125°C
0.6
IDD SUPPLY CURRENT (µA)
RHEOSTAT MODE DNL (LSB)
40
TEMPERATURE (°C)
CODE (Decimal)
0.4
0.2
0
–0.2
–0.4
–0.6
VDD = 5.5V
1
VDD = 2.7V
–0.8
–1.0
0
32
64
96
128
160
192
224
0.1
–40
256
0
Figure 10. R-DNL vs. Code, VDD = 5 V
80
120
Figure 13. Supply Current vs. Temperature
2.5
70
60
2.0
IA SHUTDOWN CURRENT (nA)
FSE, FULL-SCALE ERROR (LSB)
40
TEMPERATURE (°C)
CODE (Decimal)
1.5
VDD = 2.7V
1.0
VDD = 5.5V
0.5
50
40
30
VDD = 5V
20
10
0
–40
0
40
80
0
–40
120
TEMPERATURE (°C)
0
40
80
TEMPERATURE (°C)
Figure 11. Full-Scale Error vs. Temperature
Figure 14. Shutdown Current vs. Temperature
Rev. 0 | Page 7 of 16
120
AD5160
REF LEVEL
0.000dB
0
RHEOSTAT MODE TEMPCO (ppm/°C)
200
150
–6
0x80
–12
0x40
–18
0x20
MARKER 510 634.725Hz
MAG (A/R)
–9.049dB
0x10
–24
100
0x08
–30
0x04
–36
50
0x02
0x01
–42
–48
0
–54
–50
–60
0
32
64
96
128
160
192
224
1k
START 1 000.000Hz
256
CODE (Decimal)
Figure 15. Rheostat Mode Tempco ∆RWB/∆T vs. Code
10k
100k
1M
STOP 1 000 000.000Hz
Figure 18. Gain vs. Frequency vs. Code, RAB = 10 kΩ
REF LEVEL
0.000dB
0
160
POTENTIOMETER MODE TEMPCO (ppm/°C)
/DIV
6.000dB
140
/DIV
6.000dB
0x80
–6
120
–12
0x40
100
–18
0x20
80
–24
60
–30
0x10
0x08
0x04
–36
40
0x02
–42
20
MARKER 100 885.289Hz
MAG (A/R)
–9.014dB
0x01
–48
0
–54
–20
0
32
64
96
128
160
192
224
–60
256
1k
START 1 000.000Hz
CODE (Decimal)
Figure 16. Potentiometer Mode Tempco ∆VWB/∆T vs. Code
REF LEVEL
0.000dB
0
/DIV
6.000dB
10k
Figure 19. Gain vs. Frequency vs. Code, RAB = 50 kΩ
REF LEVEL
0.000dB
0
MARKER 1 000 000.000Hz
MAG (A/R)
–8.918dB
/DIV
6.000dB
0x80
–6
0x80
–6
0x40
–12
0x40
–12
0x20
–18
0x20
–18
0x10
–24
0x10
–30
0x08
–36
0x04
–42
0x02
–24
0x08
–30
0x04
0x02
0x01
–36
100k
1M
STOP 1 000 000.000Hz
–42
0x01
–48
–48
MARKER 54 089.173Hz
MAG (A/R)
–9.052dB
–54
–54
–60
–60
1k
START 1 000.000Hz
10k
1k
START 1 000.000Hz
100k
1M
STOP 1 000 000.000Hz
10k
100k
1M
STOP 1 000 000.000Hz
Figure 20. Gain vs. Frequency vs. Code, RAB = 100 kΩ
Figure 17. Gain vs. Frequency vs. Code, RAB = 5 kΩ
Rev. 0 | Page 8 of 16
AD5160
REF LEVEL
–5.000dB
/DIV
0.500dB
–5.5
5kΩ – 1.026 MHz
10kΩ – 511 MHz
50kΩ – 101 MHz
100kΩ – 54 MHz
–6.0
–6.5
–7.0
1
–7.5
VW
–8.0
–8.5
R = 50kΩ
CLK
R = 5kΩ
2
–9.0
R = 10kΩ
R = 100kΩ
–9.5
Ch 1
200mV BW Ch 2
5.00 V BW M 100ns
A CH2 3.00 V
–10.0
Figure 24. Digital Feedthrough
–10.5
10k
100k
1M
START 1 000.000Hz
10M
STOP 1 000 000.000Hz
Figure 21. –3 dB Bandwidth @ Code = 0x80
60
CODE = 0x80, VA= VDD, VB = 0V
VA = 5V
VB = 0V
PSRR (dB)
40
1
VW
PSRR @ VDD = 3V DC ± 10% p-p AC
CS
20
2
Ch 1
PSRR @ VDD = 5V DC ± 10% p-p AC
0
100
1k
10k
100k
100mV BW Ch 2
5.00 V BW M 200ns A CH1 152mV
Figure 25. Midscale Glitch, Code 0x80–0x7F
1M
FREQUENCY (Hz)
Figure 22. PSRR vs. Frequency
900
VDD = 5V
800
VA = 5V
VB = 0V
700
IDD (µA)
600
1
500
VW
CODE = 0x55
400
CS
300
CODE = 0xFF
2
200
Ch 1
100
0
10k
100k
1M
FREQUENCY (Hz)
5.00V BW Ch 2
5.00 V BW M 200ns
A CH1 3.00 V
Figure 26. Large Signal Settling Time, Code 0xFF–0x00
10M
Figure 23. IDD vs. Frequency
Rev. 0 | Page 9 of 16
AD5160
TEST CIRCUITS
Figure 27 to Figure 35 illustrate the test circuits that define the
test conditions used in the product specification tables.
OP279
V+ = VDD
1LSB = V+/2N
DUT
A
5V
VIN
W
W
V+
B
OFFSET
GND
VMS
VOUT
A
DUT
B
OFFSET
BIAS
Figure 27. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)
Figure 32. Test Circuit for Noninverting Gain
NO CONNECT
A
DUT
A
IW
W
VMS
–15V
RSW =
DUT
W
I W = VDD /R NOMINAL
VW
0.1V
ISW
CODE = 0x00
W
B
0.1V
ISW
B
VMS1
VOUT
Figure 33. Test Circuit for Gain vs. Frequency
DUT
VMS2
AD8610
B
2.5V
Figure 28. Test Circuit for Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
A
DUT
OFFSET
GND
B
+15V
W
VIN
RW = [VMS1 – VMS2]/I W
VSS TO VDD
Figure 29. Test Circuit for Wiper Resistance
Figure 34. Test Circuit for Incremental ON Resistance
VA
V+ = VDD 10%
VDD
PSRR (dB) = 20 LOG
A
V+
W
PSS (%/%) =
B
∆V MS%
NC
∆V
(∆V MS
)
DD
∆V DD%
VMS
VDD
DUT
A
VSS
GND
B
NC
Figure 30. Test Circuit for Power Supply Sensitivity (PSS, PSSR)
A
DUT
OFFSET
GND
B
W
OP279
ICM
VCM
NC = NO CONNECT
Figure 35. Test Circuit for Common-Mode Leakage current
5V
VIN
W
VOUT
OFFSET
BIAS
Figure 31. Test Circuit for Inverting Gain
Rev. 0 | Page 10 of 16
AD5160
SPI INTERFACE
Table 5. AD5160 Serial Data-Word Format
B7
D7
MSB
27
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
1
SDI
B0
D0
LSB
20
D7
0
D6
D5
D4
D3
D2
D1
D0
1
CLK
0
RDAC REGISTER LOAD
1
CS
VOUT
0
1
0
Figure 36. AD5160 SPI Interface Timing Diagram
(VA = 5 V, VB = 0 V, VW = VOUT)
1
SDI
(DATA IN)
Dx
Dx
0
tCH
1
tDS
tCH
tCS1
CLK
0
tCL
tCSHO
tCSH1
tCSS
1
CS
tCSW
0
tS
VDD
VOUT
±1LSB
0
Figure 37. SPI Interface Detailed Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT)
Rev. 0 | Page 11 of 16
AD5160
OPERATION
The AD5160 is a 256-position digitally controlled variable
resistor (VR) device.
The general equation determining the digitally programmed
output resistance between W and B is
An internal power-on preset places the wiper at midscale
during power-on, which simplifies the fault condition recovery
at power-up.
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the RDAC between terminals A and
B is available in 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The final two
or three digits of the part number determine the nominal
resistance value, e.g., 10 kΩ = 10; 50 kΩ = 50. The nominal
resistance (RAB) of the VR has 256 contact points accessed by
the wiper terminal, plus the B terminal contact. The 8-bit data
in the RDAC latch is decoded to select one of the 256 possible
settings. Assume a 10 kΩ part is used, the wiper’s first
connection starts at the B terminal for data 0x00. Since there is a
60 Ω wiper contact resistance, such connection yields a
minimum of 60 Ω resistance between terminals W and B. The
second connection is the first tap point, which corresponds to
99 Ω (RWB = RAB/256 + RW = 39 Ω + 60 Ω) for data 0x01.
The third connection is the next tap point, representing 177 Ω
(2 × 39 Ω + 60 Ω) for data 0x02, and so on. Each LSB data value
increase moves the wiper up the resistor ladder until the last tap
point is reached at 9961 Ω (RAB – 1 LSB + RW). Figure 38 shows
a simplified diagram of the equivalent RDAC circuit where the
last resistor string will not be accessed; therefore, there is 1 LSB
less of the nominal resistance at full scale in addition to the
wiper resistance.
A
RS
D7
D6
D5
D4
D3
D2
D1
D0
RWB (D ) =
RDAC
LATCH
RS
AND
DECODER
(1)
In summary, if RAB = 10 kΩ and the A terminal is open
circuited, the following output resistance RWB will be set for the
indicated RDAC latch codes.
Table 6. Codes and Corresponding RWB Resistance
D (Dec.)
255
128
1
0
RWB (Ω)
9,961
5,060
99
60
Output State
Full Scale (RAB – 1 LSB + RW)
Midscale
1 LSB
Zero Scale (Wiper Contact Resistance)
Note that in the zero-scale condition a finite wiper resistance of
60 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum pulse current of
no more than 20 mA. Otherwise, degradation or possible
destruction of the internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper W and terminal A also produces a
digitally controlled complementary resistance RWA. When these
terminals are used, the B terminal can be opened. Setting the
resistance value for RWA starts at a maximum value of resistance
and decreases as the data loaded in the latch increases in value.
The general equation for this operation is
RWA (D ) =
W
× R AB + R W
where D is the decimal equivalent of the binary code loaded in
the 8-bit RDAC register, RAB is the end-to-end resistance, and
RW is the wiper resistance contributed by the on resistance of
the internal switch.
RS
RS
D
256
256 − D
× R AB + RW
256
(2)
For RAB = 10 kΩ and the B terminal open circuited, the
following output resistance RWA will be set for the indicated
RDAC latch codes.
Table 7. Codes and Corresponding RWA Resistance
B
Figure 38. AD5160 Equivalent RDAC Circuit
D (Dec.)
255
128
1
0
RWA (Ω)
99
5,060
9,961
10,060
Output State
Full Scale
Midscale
1 LSB
Zero Scale
Typical device to device matching is process lot dependent and
may vary by up to ±30%. Since the resistance element is
processed in thin film technology, the change in RAB with
temperature has a very low 45 ppm/°C temperature coefficient.
Rev. 0 | Page 12 of 16
AD5160
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A-to-B. Unlike the polarity of VDD to GND, which must be
positive, voltage across A-B, W-A, and W-B can be at either
polarity.
ESD PROTECTION
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures shown in Figure 39 and Figure 40.
This applies to the digital input pins SDI, CLK, and CS.
340Ω
VSS
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the
voltage applied across terminal AB divided by the 256 positions
of the potentiometer divider. The general equation defining the
output voltage at VW with respect to ground for any valid input
voltage applied to terminals A and B is
VW (D ) =
D
256
VA +
256 − D
VB
256
(3)
For a more accurate calculation, which includes the effect of
wiper resistance, VW, can be found as
VW (D ) =
RWB (D )
256
VA +
RWA (D )
256
VB
(4)
LOGIC
Figure 39. ESD Protection of Digital Pins
A,B,W
VSS
Figure 40. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5160 VDD and GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer
operation. Supply signals present on terminals A, B, and W that
exceed VDD or GND will be clamped by the internal forward
biased diodes (see Figure 41).
VDD
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors RWA and RWB and not the
absolute values. Therefore, the temperature drift reduces to
15 ppm/°C.
A
W
B
VSS
SPI COMPATIBLE 3-WIRE SERIAL BUS
Figure 41. Maximum Terminal Voltages Set by VDD and VSS
The AD5160 contains a 3-wire SPI compatible digital interface
(SDI, CS, and CLK). The 8-bit serial word must be loaded MSB
first. The format of the word is shown in Table 5.
The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register.
Standard logic families work well. If mechanical switches are
used for product evaluation, they should be debounced by a
flip-flop or other suitable means. When CS is low, the clock
loads data into the serial register on each positive clock edge
(see Figure 36).
The data setup and data hold times in the specification table
determine the valid timing requirements. The AD5160 uses an
8-bit serial input data register word that is transferred to the
internal RDAC register when the CS line returns to logic high.
Extra MSB bits are ignored.
POWER-UP SEQUENCE
Since the ESD protection diodes limit the voltage compliance at
terminals A, B, and W (see Figure 41), it is important to power
VDD/GND before applying any voltage to terminals A, B, and W;
otherwise, the diode will be forward biased such that VDD will be
powered unintentionally and may affect the rest of the user’s
circuit. The ideal power-up sequence is in the following order:
GND, VDD, digital inputs, and then VA/B/W. The relative order of
powering VA, VB, VW, and the digital inputs is not important as
long as they are powered after VDD/GND.
Rev. 0 | Page 13 of 16
AD5160
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to the
device should be bypassed with disc or chip ceramic capacitors
of 0.01 µF to 0.1 µF. Low ESR 1 µF to 10 µF tantalum or
electrolytic capacitors should also be applied at the supplies to
minimize any transient disturbance and low frequency ripple
(see Figure 42). Note that the digital ground should also be
joined remotely to the analog ground at one point to minimize
the ground bounce.
Rev. 0 | Page 14 of 16
VDD
VDD
C3 +
C1
10µF
0.1µF
AD5160
GND
Figure 42. Power Supply Bypassing
AD5160
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
W 1
VDD 2
8 A
AD5160
7 B
6 CS
TOP VIEW
CLK 4 (Not to Scale) 5 SDI
GND 3
Figure 43.
Table 8.
Pin
1
2
3
4
5
6
Name
W
VDD
GND
CLK
SDI
CS
7
8
B
A
Rev. 0 | Page 15 of 16
Description
W Terminal.
Positive Power Supply.
Digital Ground.
Serial Clock Input. Positive edge triggered.
Serial Data Input.
Chip Select Input, Active Low. When CS returns
high, data will be loaded into the DAC register.
B Terminal.
A Terminal.
AD5160
OUTLINE DIMENSIONS
2.90 BSC
8
7
6
5
1
2
3
4
1.60 BSC
2.80 BSC
PIN 1
0.65 BSC
1.95
BSC
1.30
1.15
0.90
1.45 MAX
0.15 MAX
0.38
0.22
0.22
0.08
8°
4°
0°
SEATING
PLANE
0.60
0.45
0.30
COMPLIANT TO JEDEC STANDARDS MO-178BA
Figure 44.
8-Lead Small Outline Transistor Package [SOT-23]
(RJ-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD5160BRJ5-R2
AD5160BRJ5-RL7
AD5160BRJ10-R2
AD5160BRJ10-RL7
AD5160BRJ50-R2
AD5160BRJ50-RL7
AD5160BRJ100-R2
AD5160BRJ100-RL7
AD5160EVAL
RAB (Ω)
5k
5k
10k
10k
50k
50k
100k
100k
See Note 1
Temperature
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Package Description
SOT-23-8
SOT-23-8
SOT-23-8
SOT-23-8
SOT-23-8
SOT-23-8
SOT-23-8
SOT-23-8
Evaluation Board
Package Option
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
1
The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options.
The AD5160 contains 2532 transistors. Die size: 30.7 mil × 76.8 mil = 2,358 sq. mil.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
© 2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.
C03434–0–5/03(0)
Rev. 0 | Page 16 of 16
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