Data Sheet
AD5170
256-Position, Two-Time Programmable, I2C Digital Potentiometer
FEATURES
►
►
►
►
►
►
►
►
►
►
►
►
►
►
►
FUNCTIONAL BLOCK DIAGRAM
256-position digital potentiometer
Two-time programmable (TTP) set-and-forget resistance setting
allows second-chance permanent programming
Unlimited adjustments prior to one-time programming (OTP)
activation
OTP overwrite allows dynamic adjustments with user-defined
preset
End to end resistance: 2.5 kΩ, 10 kΩ, and 50 kΩ
Compact 10-lead MSOP: 3 mm × 4.9 mm package
Fast settling time: tS = 5 µs typical in power-up
Full read/write of wiper register
Power-on preset to midscale
Extra package address decode pins: AD0 and AD1
Single supply: 2.7 V to 5.5 V
Low temperature coefficient: 35 ppm/°C
Low power: IDD = 6 µA maximum
Wide operating temperature: −40°C to +125°C
Software replaces MicroConverter® in factory programming applications
APPLICATIONS
►
►
►
►
►
►
►
Systems calibration
Electronics level setting
Mechanical trimmers replacement in new designs
Permanent factory PCB settings
Transducer adjustment of pressure, temperature, position, chemical, and optical sensors
RF amplifier biasing
Gain control and offset adjustments
Figure 1.
GENERAL DESCRIPTION
The AD5170 is a 256-position, two-time programmable, digital
potentiometer that employs fuse link technology, giving users two
opportunities to permanently program the resistance setting. The
digital potentiometer, VR, and RDAC terms are used interchangeably. For users who do not need to program the digital potentiometer setting in memory more than once, the OTP feature is a
cost-effective alternative to EEMEM. The AD5170 performs the
same electronic adjustment function as mechanical potentiometers
or variable resistors with enhanced resolution, solid-state reliability,
and superior low temperature coefficient performance.
The AD5170 is programmed using a 2-wire, I2C-compatible digital
interface. Unlimited adjustments are allowed before permanently
setting the resistance value, and there are two opportunities for
permanent programming. During OTP activation, a permanent blow
fuse command freezes the wiper position (analogous to placing
epoxy on a mechanical trimmer).
Unlike traditional OTP digital potentiometers, the AD5170 has a
unique temporary OTP overwrite feature that allows for new adjustments even after the fuse is blown. However, the OTP setting is restored during subsequent power-up conditions. This feature allows
users to treat these digital potentiometers as volatile potentiometers
with a programmable preset.
For applications that program the AD5170 at the factory, Analog
Devices, Inc., offers device programming software that runs on Windows NT®, Windows® 2000, and Windows XP operating systems.
This software effectively replaces any external I2C controllers, thus
enhancing the time-to-market of the user’s systems.
Rev. H
DOCUMENT FEEDBACK
TECHNICAL SUPPORT
Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to
change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Data Sheet
AD5170
TABLE OF CONTENTS
Features................................................................ 1
Applications........................................................... 1
Functional Block Diagram......................................1
General Description...............................................1
Specifications........................................................ 3
Electrical Characteristics: 2.5 kΩ ...................... 3
Electrical Characteristics: 10 kΩ and 50 kΩ ......4
Timing Characteristics: 2.5 kΩ, 10 kΩ, and
50 kΩ ...............................................................5
Absolute Maximum Ratings...................................7
ESD Caution.......................................................7
Pin Configuration and Function Descriptions........ 8
Typical Performance Characteristics..................... 9
Test Circuits......................................................... 13
Theory of Operation.............................................14
One-Time Programming (OTP)........................ 14
Programming the Variable Resistor and
Voltage—Rheostat Operation.........................14
Programming the Potentiometer Divider—
Voltage Output Operation...............................15
ESD Protection.................................................16
Terminal Voltage Operating Range.................. 16
Power-Up Sequence........................................ 16
Power Supply Considerations.......................... 16
Layout Considerations......................................16
Controlling the AD5170....................................... 18
Software Programming.....................................18
Device Programming........................................20
I2C Controller Programming............................. 21
I2C-Compatible, 2-Wire Serial Bus...................21
Level Shifting for Different Voltage Operation.. 22
Outline Dimensions............................................. 23
Ordering Guide.................................................23
REVISION HISTORY
1/2022—Rev. G to Rev. H
Changes to Features Section.......................................................................................................................... 1
Changes to Applications Section..................................................................................................................... 1
Changes to Power Supply Range Parameter, OTP Supply Current Parameter, and −3 dB Bandwidth
Parameter, Table 1.........................................................................................................................................3
Changes to OTP Supply Current Parameter, Dynamic Characteristics Parameter, Power Supply Range
Parameter, and VW Settling Time (10 kΩ/50 kΩ) Parameter, Table 2........................................................... 4
Changed Electrical Characteristics: 10 kΩ, 50 kΩ, and 100 kΩ Section to Electrical Characteristics: 10
kΩ and 50 kΩ Section....................................................................................................................................4
Changed Timing Characteristics: 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ Section to Timing Characteristics:
2.5 kΩ, 10 kΩ, and 50 kΩ Section................................................................................................................. 5
Deleted Figure 20; Renumbered Sequentially................................................................................................. 9
Changes to Figure 20.....................................................................................................................................11
Changes to Programming the Variable Resistor and Voltage—Rheostat Operation Section, Table 7,
and Table 8.................................................................................................................................................. 14
Moved Figure 41............................................................................................................................................ 18
Moved Table 9 and Table 10.......................................................................................................................... 19
Moved Table 11..............................................................................................................................................20
Changes to Figure 44.................................................................................................................................... 21
Changes to Figure 45.................................................................................................................................... 21
Changes to Ordering Guide........................................................................................................................... 23
analog.com
Rev. H | 2 of 23
Data Sheet
AD5170
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS: 2.5 KΩ
VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted.
Table 1.
Parameter
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
RWB (Wiper Resistance)
DC CHARACTERISTICS—POTENTIOMETER DIVIDER
MODE (SPECIFICATIONS APPLY TO ALL VRs)
Differential Nonlinearity4
Integral Nonlinearity4
Voltage Divider Temperature Coefficient
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range5
Capacitance A, Capacitance B6
Capacitance W6
Shutdown Supply Current7
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High (SDA and SCL)8
Input Logic Low (SDA and SCL)8
Input Logic High (AD0 and AD1)
Input Logic Low (AD0 and AD1)
Input Current
Input Capacitance6
POWER SUPPLIES
Power Supply Range
OTP Supply Voltage8, 9
Supply Current
OTP Supply Current8, 10, 11
Power Dissipation12
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS13
–3 dB Bandwidth
Total Harmonic Distortion
VW Settling Time
Resistor Noise Voltage Density
Symbol
Conditions
Min
Typ1
Max
Unit
R-DNL
R-INL
∆RAB
(∆RAB/RAB)/∆T
RWB
RWB, VA = no connect
RWB, VA = no connect
TA = 25°C
−2
−14
−20
±0.1
±2
+2
+14
+55
LSB
LSB
%
ppm/°C
Ω
DNL
INL
(∆VW/VW)/∆T
VWFSE
VWZSE
VA, VB, VW
CA, CB
CW
IA_SD
ICM
VIH
VIL
VIH
VIL
IIL
CIL
35
160
Code = 0x00, VDD = 5 V
−1.5
−2
Code = 0x80
Code = 0xFF
Code = 0x00
−14
0
±0.1
±0.6
15
−5.5
4.5
GND
f = 1 MHz, measured to GND,
code = 0x80
f = 1 MHz, measured to GND,
code = 0x80
VDD = 5.5 V
VA = VB = VDD/2
VDD = 5 V
VDD = 5 V
VDD = 3 V
VDD = 3 V
VIN = 0 V or 5 V
200
+1.5
+2
LSB
LSB
ppm/°C
LSB
LSB
0
12
45
VDD
V
pF
60
pF
0.01
1
0.7 VDD
−0.5
2.1
1
µA
nA
VDD + 0.5
+0.3 VDD
V
V
V
V
µA
pF
0.6
±1
5
VDD
VDD_OTP
IDD
IDD_OTP
PDISS
PSS
TA = 25°C
VIH = 5 V or VIL = 0 V
VDD_OTP = 5.7 V, TA = 25°C
VIH = 5 V or VIL = 0 V, VDD = 5 V
VDD = 5 V ± 10%, code = midscale
BW
THDW
tS
eN_WB
RAB = 2.5 kΩ, code = 0x80
VA = 1 V rms, VB = 0 V, f = 1 kHz
VA = 5 V, VB = 0 V, ±1 LSB error band
RWB = 1.25 kΩ, f = 1 kHz
2.7
5.6
5.7
3.5
100
±0.02
4.8
0.1
1
3.2
5.5
5.8
6
33
±0.08
V
V
µA
mA
µW
%/%
MHz
%
µs
nV/√Hz
1
Typical specifications represent average readings at 25°C and VDD = 5 V.
2
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.
3
VAB = VDD, wiper (VW) = no connect.
analog.com
Rev. H | 3 of 23
Data Sheet
AD5170
SPECIFICATIONS
Table 1.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
4
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of
±1 LSB maximum are guaranteed monotonic operating conditions.
5
The A, B, and W resistor terminals have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8
The minimum voltage requirement on the VIH is 0.7 V × VDD. For example, VIH minimum = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled up
to VDD. However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-up
resistors.
9
Different from operating power supply; power supply for OTP is used one time only.
10
Different from operating current; supply current for OTP lasts approximately 400 ms for use one time only.
11
See Figure 25 for the energy plot during OTP program.
12
PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
13
All dynamic characteristics use VDD = 5 V.
ELECTRICAL CHARACTERISTICS: 10 KΩ AND 50 KΩ
VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted.
Table 2.
Parameter
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
RWB (Wiper Resistance)
DC CHARACTERISTICS—POTENTIOMETER DIVIDER
MODE (SPECIFICATIONS APPLY TO ALL VRs)
Differential Nonlinearity4
Integral Nonlinearity4
Voltage Divider Temperature Coefficient
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range5
Capacitance A, Capacitance B6
Capacitance W6
Shutdown Supply Current7
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High (SDA and SCL)8
Input Logic Low (SDA and SCL)8
Input Logic High (AD0 and AD1)
Input Logic Low (AD0 and AD1)
Input Current
Input Capacitance6
analog.com
Symbol
Conditions
Min
Typ1
Max
Unit
R-DNL
R-INL
∆RAB
(∆RAB/RAB)/∆T
RWB
RWB, VA = no connect
RWB, VA = no connect
TA = 25°C
−1
−2.5
−20
±0.1
±0.25
+1
+2.5
+20
LSB
LSB
%
ppm/°C
Ω
DNL
INL
(∆VW/VW)/∆T
VWFSE
VWZSE
VA, VB, VW
CA, CB
CW
IA_SD
ICM
VIH
VIL
VIH
VIL
IIL
CIL
35
160
Code = 0x00, VDD = 5 V
−1
−1
Code = 0x80
Code = 0xFF
Code = 0x00
−2.5
0
±0.1
±0.3
15
−1
1
GND
f = 1 MHz, measured to GND,
code = 0x80
f = 1 MHz, measured to GND,
code = 0x80
VDD = 5.5 V
VA = VB = VDD/2
VDD = 5 V
VDD = 5 V
VDD = 3 V
VDD = 3 V
VIN = 0 V or 5 V
200
+1
+1
LSB
LSB
ppm/°C
LSB
LSB
0
2.5
45
VDD
V
pF
60
pF
0.01
1
0.7 VDD
−0.5
2.1
1
µA
nA
VDD + 0.5
+0.3 VDD
V
V
V
V
µA
pF
0.6
±1
5
Rev. H | 4 of 23
Data Sheet
AD5170
SPECIFICATIONS
Table 2.
Parameter
POWER SUPPLIES
Power Supply Range
OTP Supply Voltage8, 9
Supply Current
OTP Supply Current8, 10, 11
Power Dissipation12
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS13
–3 dB Bandwidth
Symbol
Conditions
VDD
VDD_OTP
IDD
IDD_OTP
PDISS
PSS
Min
2.7
5.6
VIH = 5 V or VIL = 0 V
VDD_OTP = 5.7 V, TA = 25°C
VIH = 5 V or VIL = 0 V, VDD = 5 V
VDD = 5 V ± 10%, code = midscale
Typ1
5.7
3.5
100
±0.02
Max
Unit
5.5
5.8
6
V
V
µA
mA
µW
%/%
33
±0.08
BW
RAB = 10 kΩ, code = 0x80
RAB = 50 kΩ, code = 0x80
600
100
kHz
kHz
Total Harmonic Distortion
THDW
0.1
%
VW Settling Time (10 kΩ/50 kΩ)
tS
2
µs
Resistor Noise Voltage Density
eN_WB
VA =1 V rms, VB = 0 V, f = 1 kHz,
RAB = 10 kΩ
VA = 5 V, VB = 0 V, ±1 LSB error
band
RWB = 5 kΩ, f = 1 kHz
9
nV/√Hz
1
Typical specifications represent average readings at 25°C and VDD = 5 V.
2
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.
3
VAB = VDD, wiper (VW) = no connect.
4
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of
±1 LSB maximum are guaranteed monotonic operating conditions.
5
The A, B, and W resistor terminals have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8
The minimum voltage requirement on the VIH is 0.7 V × VDD. For example, VIH minimum = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled up
to VDD. However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-up
resistors.
9
Different from operating power supply, power supply OTP is used one time only.
10
Different from operating current, supply current for OTP lasts approximately 400 ms for use one time only.
11
See Figure 25 for the energy plot during OTP program.
12
PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
13
All dynamic characteristics use VDD = 5 V.
TIMING CHARACTERISTICS: 2.5 KΩ, 10 KΩ, AND 50 KΩ
VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD; VB = 0 V, −40°C < TA < +125°C, unless otherwise noted.
Table 3.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
400
1.3
0.6
kHz
µs
µs
1.3
0.6
0.6
µs
µs
µs
I2C INTERFACE TIMING CHARACTERISTICS1 (SPECIFICATIONS APPLY
TO ALL PARTS)
SCL Clock Frequency
tBUF Bus Free Time Between Stop and Start
tHD;STA Hold Time (Repeated Start)
tLOW Low Period of SCL Clock
tHIGH High Period of SCL Clock
tSU;STA Setup Time for Repeated Start Condition
analog.com
fSCL
t1
t2
t3
t4
t5
After this period, the first clock
pulse is generated
Rev. H | 5 of 23
Data Sheet
AD5170
SPECIFICATIONS
Table 3.
Parameter
tHD;DAT Data Hold Time2
tSU;DAT Data Setup Time
tF Fall Time of Both SDA and SCL Signals
tR Rise Time of Both SDA and SCL Signals
tSU;STO Setup Time for Stop Condition
OTP Program Time
Symbol
Conditions
t6
t7
t8
t9
t10
t11
1
See Figure 2 for locations of measured values.
2
The maximum tHD;DAT must be met only if the device does not stretch the low period (tLOW) of the SCL signal.
Min
Typ
Max
Unit
0.9
µs
ns
ns
ns
µs
ms
100
300
300
0.6
400
Timing Diagram
Figure 2. I2C Interface Detailed Timing Diagram
analog.com
Rev. H | 6 of 23
Data Sheet
AD5170
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
ESD CAUTION
Table 4.
Parameter
Rating
VDD to GND
VA, VB, VW to GND
Terminal Current, A to B, A to W, B to W1
Pulsed
Continuous
Digital Inputs and Output Voltage to GND
Operating Temperature Range
Maximum Junction Temperature (TJMAX)
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Thermal Resistance2
θJA: 10-Lead MSOP
−0.3 V to +7 V
VDD
±20 mA
±5 mA
0 V to 7 V
−40°C to +125°C
150°C
−65°C to +150°C
300°C
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although
this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
230°C/W
1
Maximum terminal current is bound by the maximum current handling of the
switches, maximum power dissipation of the package, and maximum applied
voltage across any two of the A, B, and W terminals at a given resistance.
2
Package power dissipation = (TJMAX − TA)/θJA.
Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
analog.com
Rev. H | 7 of 23
Data Sheet
AD5170
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
4
5
B
A
AD0
GND
VDD
6
SCL
7
SDA
8
9
10
AD1
NC
W
B Terminal. GND ≤ VB ≤ VDD.
A Terminal. GND ≤ VA ≤ VDD.
Programmable Address Bit 0 for Multiple Package Decoding.
Digital Ground.
Positive Power Supply. Specified for operation from 2.7 V to 5.5 V. For OTP programming, the VDD supply must be within the 5.6 V to 5.8 V
range and capable of driving 100 mA.
Serial Clock Input. Positive edge triggered. Requires a pull-up resistor. If it is driven directly from a logic controller without the pull-up resistor,
ensure that VIH minimum is 0.7 V × VDD.
Serial Data Input/Output. Requires a pull-up resistor. If it is driven directly from a logic controller without the pull-up resistor, ensure that VIH
minimum is 0.7 V × VDD.
Programmable Address Bit 1 for Multiple Package Decoding.
No Connect.
W Terminal. GND ≤ VW ≤ VDD.
analog.com
Rev. H | 8 of 23
Data Sheet
AD5170
TYPICAL PERFORMANCE CHARACTERISTICS
analog.com
Figure 4. R-INL vs. Code vs. Supply Voltages
Figure 7. DNL vs. Code vs. Temperature
Figure 5. R-DNL vs. Code vs. Supply Voltages
Figure 8. INL vs. Code vs. Supply Voltages
Figure 6. INL vs. Code vs. Temperature
Figure 9. DNL vs. Code vs. Supply Voltages
Rev. H | 9 of 23
Data Sheet
AD5170
TYPICAL PERFORMANCE CHARACTERISTICS
analog.com
Figure 10. R-INL vs. Code vs. Temperature
Figure 13. Zero-Scale Error vs. Temperature
Figure 11. R-DNL vs. Code vs. Temperature
Figure 14. IDD, Supply Current vs. Temperature
Figure 12. Full-Scale Error vs. Temperature
Figure 15. Rheostat Mode Tempco ΔRWB/ΔT vs. Code
Rev. H | 10 of 23
Data Sheet
AD5170
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 16. Potentiometer Mode Tempco ΔVWB/ΔT vs. Code
Figure 19. Gain vs. Frequency vs. Code, RAB = 50 kΩ
Figure 17. Gain vs. Frequency vs. Code, RAB = 2.5 kΩ
Figure 20. −3 dB Bandwidth at Code = 0x80
Figure 18. Gain vs. Frequency vs. Code, RAB = 10 kΩ
Figure 21. IDD, Supply Current vs. Digital Input Voltage
analog.com
Rev. H | 11 of 23
Data Sheet
AD5170
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 22. Digital Feedthrough
Figure 23. Midscale Glitch, Code 0x80 to Code 0x7F
analog.com
Figure 24. Large Signal Settling Time
Figure 25. OTP Program Energy Plot for Single Fuse
Rev. H | 12 of 23
Data Sheet
AD5170
TEST CIRCUITS
Figure 26 to Figure 31 illustrate the test circuits that define the test conditions used in the product specification tables.
Figure 26. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)
Figure 29. Test Circuit for Power Supply Sensitivity (PSS, PSRR)
Figure 27. Test Circuit for Resistor Position Nonlinearity Error (Rheostat
Operation; R-INL, R-DNL)
Figure 30. Test Circuit for Gain vs. Frequency
Figure 28. Test Circuit for Wiper Resistance
Figure 31. Test Circuit for Common-Mode Leakage Current
analog.com
Rev. H | 13 of 23
Data Sheet
AD5170
THEORY OF OPERATION
Figure 32. Detailed Functional Block Diagram
The AD5170 is a 256-position, digitally controlled, variable resistor
(VR) that employs fuse link technology to achieve memory retention
of the resistance setting.
An internal power-on preset places the wiper at midscale during
power-on. If the OTP function is activated, the device powers up at
the user-defined permanent setting.
ONE-TIME PROGRAMMING (OTP)
Prior to OTP activation, the AD5170 presets to midscale during
initial power-on. After the wiper is set at the desired position, the
resistance can be permanently set by programming the T bit high
along with the proper coding (see Table 9 and Table 11) and
one-time VDD_OTP. Note that fuse link technology of the AD517x
family of digital potentiometers requires that VDD_OTP between 5.6 V
and 5.8 V blow the fuses to achieve a given nonvolatile setting.
On the other hand, VDD can be 2.7 V to 5.5 V during operation.
For system supplies that are lower than 5.6 V, an external supply
for one-time programming is required. Note that the user is allowed
only one attempt in blowing the fuses. If the user fails to blow the
fuses at the first attempt, the structures of the fuses may have
changed such that they can never be blown, regardless of the
energy applied at subsequent events. For details, see the Power
Supply Considerations section.
The device control circuit has two validation bits, E1 and E0, that
can be read back to check the programming status (see Table
6). Users should always read back the validation bits to ensure
that the fuses are properly blown. After the fuses are blown, all
fuse latches are enabled upon subsequent power-on; therefore,
the output corresponds to the stored setting. Figure 32 shows a
detailed functional block diagram.
analog.com
Table 6. Validation Status
E1
E0
Status
0
1
0
0
1
1
Ready for programming.
Fatal error. Some fuses are not blown. Do not retry. Discard this
unit.
Successful. No further programming is possible.
PROGRAMMING THE VARIABLE RESISTOR
AND VOLTAGE—RHEOSTAT OPERATION
The nominal resistance (RAB) between Terminal A and Terminal B
is available in 2.5 kΩ, 10 kΩ, and 50 kΩ. The nominal resistance
of the VR has 256 contact points that are accessed by the wiper
terminal, plus the B terminal contact. The 8-bit data in the RDAC
latch is decoded to select one of the 256 possible settings.
Figure 33. Rheostat Mode Configuration
Assuming that a 10 kΩ part is used, the first connection of the wiper
starts at Terminal B for Data 0x00. Because there is a 160 Ω wiper
contact resistance, such a connection yields a minimum of 320 Ω
(2 × 160 Ω) resistance between Terminal W and Terminal B. The
second connection is the first tap point, which corresponds to 359 Ω
(RWB = RAB/256 + 2 × RW = 39 Ω + 2 × 160 Ω) for Data 0x01. The
third connection is the next tap point, representing 398 Ω (2 × 39
Ω + 2 × 160 Ω) for Data 0x02, and so on. Each LSB data value
increase moves the wiper up the resistor ladder until the last tap
point is reached at 10,281 Ω (RAB − 1 LSB + 2 × RW).
Rev. H | 14 of 23
Data Sheet
AD5170
THEORY OF OPERATION
Table 8. Codes and Corresponding RWA Resistance
D (Dec)
RWA (Ω)
Output State
255
128
1
0
359
5320
10,281
10,320
Full scale
Midscale
1 LSB
Zero scale
Typical device-to-device matching is process-lot dependent and can
vary by up to ±30%. Because the resistance element is processed
using thin film technology, the change in RAB with temperature has
a very low 35 ppm/°C temperature coefficient.
PROGRAMMING THE POTENTIOMETER
DIVIDER—VOLTAGE OUTPUT OPERATION
Figure 34. Equivalent RDAC Circuit
The general equation that determines the digitally programmed
output resistance between Terminal W and Terminal B is
RWB (D) =
D
256
× RAB + 2 × RW
(1)
The digital potentiometer easily generates a voltage divider at wiper
to B and wiper to A proportional to the input voltage at A to B.
Unlike the polarity of VDD to GND, which must be positive, voltage
across A to B, W to A, and W to B can be at either polarity.
where:
D is the decimal equivalent of the binary code loaded in the 8-bit
RDAC register.
RAB is the end to end resistance.
RW is the wiper resistance contributed by the on resistance of the
internal switch.
Figure 35. Potentiometer Mode Configuration
In summary, if RAB = 10 kΩ and Terminal A is open-circuited, the
output resistance, RWB, is set for the RDAC latch codes, as shown
in Table 7.
Table 7. Codes and Corresponding RWB Resistance
D (Dec)
RWB (Ω)
Output State
255
128
1
0
10,281
5320
359
320
Full scale (RAB − 1 LSB + 2 × RW)
Midscale
1 LSB
Zero scale (wiper contact resistance)
Note that in the zero-scale condition, a finite wiper resistance of 160
Ω is present. Take care to limit the current flow between Terminal W
and Terminal B in this state to a maximum pulse current of no more
than 20 mA. Otherwise, degradation or possible destruction of the
internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper (Terminal W) and Terminal A also produces a digitally controlled, complementary resistance, RWA. When
these terminals are used, Terminal B can be opened. Setting the
resistance value for RWA starts at a maximum value of resistance
and decreases as the data loaded in the latch increases in value.
The general equation for this operation is
RWA (D) =
256 – D
256
× RAB + 2 × RW
If ignoring the effect of the wiper resistance for approximation,
connecting Terminal A to 5 V and Terminal B to ground produces
an output voltage at the wiper to B starting at 0 V up to 1 LSB
less than 5 V. Each LSB of voltage is equal to the voltage applied
across Terminal A and Terminal B divided by the 256 positions of
the potentiometer divider. The general equation defining the output
voltage at VW with respect to ground for any valid input voltage
applied to Terminal A and Terminal B is
VW(D) =
D
256 VA
VW(D) =
RWB(D)
RAB VA
+
256 − D
256 VB
(3)
For a more accurate calculation, which includes the effect of wiper
resistance, VW, the following equation can be used:
+
RWA(D)
RAB VB
(4)
Operation of the digital potentiometer in divider mode results in a
more accurate operation over temperature. Unlike rheostat mode,
the output voltage is dependent mainly on the ratio of the internal
resistors, RWA and RWB, and not the absolute values. Therefore, the
temperature drift reduces to 15 ppm/°C.
(2)
For RAB = 10 kΩ and Terminal B open circuited, Table 8 shows
some examples of the output resistance (RWA) vs. the RDAC latch
codes.
analog.com
Rev. H | 15 of 23
Data Sheet
AD5170
THEORY OF OPERATION
ESD PROTECTION
All digital inputs, SDA, SCL, AD0, and AD1, are protected with a
series input resistor and parallel Zener ESD structures, as shown in
Figure 36 and Figure 37.
When the fuse programming is complete, the VDD_OTP supply must
be removed to allow normal operation at 2.7 V to 5.5 V, and the
device consumes current in the µA range.
Figure 36. ESD Protection of Digital Pins
Figure 39. Isolate 5.7 V OTP Supply from 2.7 V Normal Operating Supply
Figure 37. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5170 VDD-to-GND power supply defines the boundary conditions for proper 3-terminal digital potentiometer operation. Supply
signals present on Terminal A, Terminal B, and Terminal W that
exceed VDD or GND are clamped by the internal forward-biased
diodes (see Figure 38).
Figure 38. Maximum Terminal Voltages Set by VDD and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance at
Terminal A, Terminal B, and Terminal W, it is important to power
VDD/GND before applying any voltage to Terminal A, Terminal B,
and Terminal W (see Figure 38). Otherwise, the diode is forwardbiased such that VDD is powered unintentionally and may affect the
rest of the user’s circuit. The ideal power-up sequence is GND,
VDD, the digital inputs, and then VA/VB/VW. The relative order of
powering VA, VB, VW, and the digital inputs is not important as long
as they are powered up after GND/VDD.
POWER SUPPLY CONSIDERATIONS
To minimize the package pin count, both the one-time programming
and normal operating voltage supplies share the same VDD terminal
of the AD5170. The AD5170 employs fuse link technology that
requires 5.6 V to 5.8 V for blowing the internal fuses to achieve
a given setting, but normal VDD can be anywhere between 2.7 V
and 5.5 V after the fuse programming process. As a result, dual
voltage supplies and isolation are needed if system VDD is lower
than the required VDD_OTP. The fuse programming supply (either an
on-board regulator or rack-mount power supply) must be rated at
5.6 V to 5.8 V and be able to provide a 100 mA current for 400 ms
for successful OTP.
analog.com
For example, for those who operate their systems at 2.7 V, use
of the bidirectional, low threshold, P-Channel MOSFETs is recommended for the isolation of the supply. As shown in Figure 39,
this assumes that the 2.7 V system voltage is applied first, and
the P1 and P2 gates are pulled to ground, thus turning on P1
and, subsequently, P2. As a result, VDD of the AD5170 approaches
2.7 V. When the AD5170 setting is found, the factory tester applies
the VDD_OTP to both the VDD and the MOSFETs gates, turning off
P1 and P2. The OTP command is executed at this time to program
the AD5170 while the 2.7 V source is protected. When the fuse
programming is complete, the tester withdraws the VDD_OTP and the
setting for the AD5170 is permanently fixed.
The AD5170 achieves the OTP function by blowing internal fuses.
Users should always apply the 5.6 V to 5.8 V one-time-program
voltage requirement at the first fuse programming attempt. Failure
to comply with this requirement can lead to a change in the fuse
structures, rendering programming inoperable.
Care should be taken when SCL and SDA are driven from a low
voltage logic controller. Users must ensure that the logic high level
is between 0.7 V × VDD and VDD + 0.5 V. Refer to the Level Shifting
for Different Voltage Operation section.
Poor PCB layout introduces parasitics that can affect the fuse
programming. Therefore, it is recommended to add a 10 µF tantalum capacitor in parallel with a 1 nF ceramic capacitor as close
as possible to the VDD pin. The type and value chosen for both
capacitors are important. This combination of capacitor values
provides both a fast response and larger supply current handling
with minimum supply droop during transients. As a result, these
capacitors increase the OTP programming success by not inhibiting
the proper energy needed to blow the internal fuses. Additionally,
C1 minimizes transient disturbance and low frequency ripple, and
C2 reduces high frequency noise during normal operation.
LAYOUT CONSIDERATIONS
It is good practice to employ compact, minimum lead length, layout
design. The leads to the inputs should be as direct as possible,
with a minimum conductor length. Ground paths should have low
resistance and low inductance.
Rev. H | 16 of 23
Data Sheet
AD5170
THEORY OF OPERATION
Note that the digital ground should also be joined remotely to the
analog ground at one point to minimize the ground bounce.
Figure 40. Power Supply Bypassing
analog.com
Rev. H | 17 of 23
Data Sheet
AD5170
CONTROLLING THE AD5170
There are two ways of controlling the AD5170. Users can program
the device with either computer software or external I2C controllers.
SOFTWARE PROGRAMMING
Due to the advantages of the one-time programmable feature,
consider programming the device in the factory before shipping
the final product to the end users. Analog Devices offers device
programming software that can be implemented in the factory on
PCs running Windows 95 or later. As a result, external controllers
are not required, significantly reducing development time. The program is an executable file that does not require knowledge of
programming languages or programming skills, and it is easy to
set up and to use. Figure 41 shows the software interface. The
software can be downloaded from the AD5170 product page.
Figure 41. AD5170 Computer Software Interface
analog.com
Rev. H | 18 of 23
Data Sheet
AD5170
CONTROLLING THE AD5170
in the upper screen and click Run. The format of writing data to the
device is shown in Table 9. Once the desired setting is found, click
Program Permanent: First Fuse Link to blow the internal fuse
links.
Write
The AD5170 starts at midscale after power-up prior to OTP programming. To increment or decrement the resistance, move the
scroll bars on the left. To write any specific value, use the bit pattern
Table 9. Write Mode
S
0
1
0
1
1
AD1
AD0
W
A
Slave Address Byte
2T
SD
T
0
OW
Instruction Byte
X
X
X
A
D7
D6
D5
D4
D3
D2
D1
D0
A
P
Data Byte
Table 10. SDA Bit Definitions and Descriptions
Bit
Description
S
P
A
AD0, AD1
X
W
R
2T
Start condition.
Stop condition.
Acknowledge.
Package pin-programmable address bits.
Don’t care.
Write.
Read.
Second fuse link array for two-time programming. Logic 0 corresponds to first trim. Logic 1 corresponds to second trim. Note
that blowing Trim 2 before Trim 1 effectively disables Trim 1 and, in turn, allows only one-time programming.
Shutdown connects wiper to Terminal B and open circuits Terminal A. It does not change the contents of the wiper register.
OTP programming bit. Logic 1 permanently programs the wiper.
Overwrite the fuse setting and program the digital potentiometer to a different setting. Note that upon power-up, the digital
potentiometer presets to either midscale or fuse setting, depending on whether the fuse link is blown.
Data bits.
OTP validation bits:
0, 0 = ready to program.
1, 0 = fatal error. Some fuses are not blown. Do not retry. Discard this unit.
1, 1 = programmed successfully. No further adjustments are possible.
SD
T
OW
D7, D6, D5, D4, D3, D2, D1, and D0
E1, E0
analog.com
Rev. H | 19 of 23
Data Sheet
AD5170
CONTROLLING THE AD5170
Read
Table 11. Read Mode
S
0
1
0
1
1
AD1
AD0
R
A
D7
D6
D5
Slave Address Byte
D4
D3
Data Byte
D2
D1
D0
A
E1
E0
X
X
X
X
X
X
A
P
Validation Byte
To read the validation bits and data from the device, click Read.
The format of the read bits is shown in Table 11.
DEVICE PROGRAMMING
To apply the device programming software in the factory, modify
a parallel port cable and configure Pin 2, Pin 3, Pin 15, and
Pin 25 for SDA_write, SCL, SDA_read, and DGND, respectively, for
the control signals (see Figure 42). Also, lay out the PCB of the
AD5170 with SCL and SDA pads, as shown in Figure 43, such that
pogo pins can be inserted for factory programming.
Figure 42. Parallel Port Connection (Pin 2 = SDA_write, Pin 3 = SCL, Pin 15 =
SDA_read, and Pin 25 = DGND)
Figure 43. Recommended AD5170 PCB Layout
analog.com
Rev. H | 20 of 23
Data Sheet
AD5170
CONTROLLING THE AD5170
I2C CONTROLLER PROGRAMMING
Write Bit Pattern
Figure 44. Writing Data to the RDAC Register
Read Bit Pattern
Figure 45. Reading Data from the RDAC Register
I2C-COMPATIBLE, 2-WIRE SERIAL BUS
The following section describes how the 2-wire, I2C serial bus
protocol operates (see Figure 44 and Figure 45).
The master initiates a data transfer by establishing a start condition,
which is when a high-to-low transition on the SDA line occurs while
SCL is high (see Figure 44). The following byte is the slave address
byte, which consists of the slave address followed by an R/W bit
(this bit determines whether data is read from or written to the slave
device). AD0 and AD1 are configurable address bits that allow up to
four devices on one bus (see Table 9).
The slave address corresponding to the transmitted address bits
responds by pulling the SDA line low during the ninth clock pulse
(this is called the acknowledge bit). At this stage, all other devices
on the bus remain idle while the selected device waits for data to be
written to, or read from, its serial register. If the R/W bit is high, the
master reads from the slave device. If the R/W bit is low, the master
writes to the slave device.
In write mode, the second byte is the instruction byte. The first MSB
of the instruction byte, 2T, is the second trim enable bit. A logic
low selects the first array of the fuses, and a logic high selects the
second array of the fuses. This means that after blowing the fuses
with Trim 1, the user still has another chance to blow them again
with Trim 2. Note that using Trim 2 before Trim 1 effectively disables
Trim 1 and, in turn, allows only one-time programming.
The second MSB, SD, is a shutdown bit. A logic high causes
an open circuit at Terminal A and shorts the wiper to Terminal
B. This operation yields almost 0 Ω in rheostat mode or 0 V in
potentiometer mode. Note that the shutdown operation does not
disturb the contents of the register. When brought out of shutdown,
the previous setting is applied to the RDAC. In addition, new
settings can be programmed during shutdown. When the part is
returned from shutdown, the corresponding VR setting is applied to
the RDAC.
analog.com
The third MSB, T, is the OTP programming bit. A logic high blows
the polyfuses and programs the resistor setting permanently. For
example, if the user wants to blow the first array of fuses, the
instruction byte is 00100XXX. To blow the second array of fuses,
the instruction byte is 10100XXX. A logic low of the T bit simply
allows the device to act as a typical volatile digital potentiometer.
The fourth MSB must always be Logic 0.
The fifth MSB, OW, is an overwrite bit. When raised to a logic high,
OW allows the RDAC setting to be changed even after the internal
fuses are blown. However, when OW is returned to Logic 0, the
position of the RDAC returns to the setting prior to the overwrite.
Because OW is not static, if the device is powered off and on, the
RDAC presets to midscale or to the setting at which the fuses were
blown, depending on whether the fuses are permanently set.
The remainder of the bits in the instruction byte are don’t care bits
(see Figure 44).
After acknowledging the instruction byte, the last byte in write
mode is the data byte. Data is transmitted over the serial bus
in sequences of nine clock pulses (eight data bits followed by
an acknowledge bit). The transitions on the SDA line must occur
during the low period of SCL and remain stable during the high
period of SCL (see Figure 2).
In read mode, the data byte follows immediately after the acknowledgment of the slave address byte. Data is transmitted over the
serial bus in sequences of nine clock pulses (a slight difference
from write mode, with eight data bits followed by an acknowledge
bit). Similarly, transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of SCL (see
Figure 45).
Following the data byte, the validation byte contains two validation
bits, E0 and E1. These bits signify the status of the one-time
programming (see Figure 45).
Rev. H | 21 of 23
Data Sheet
AD5170
CONTROLLING THE AD5170
After all the data bits are read or written, a stop condition is established by the master. A stop condition is defined as a low-to-high
transition on the SDA line while SCL is high. In write mode, the
master pulls the SDA line high during the 10th clock pulse to
establish a stop condition (see Figure 44).
In read mode, the master issues a no acknowledge for the 9th clock
pulse (that is, the SDA line remains high). The master brings the
SDA line low before the 10th clock pulse and then brings the SDA
line high to establish a stop condition (see Figure 45).
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and instructing
the part only once. For example, after the RDAC has acknowledged
its slave address and instruction bytes in write mode, the RDAC
output updates on each successive byte. If different instructions
are needed, the write/read mode has to start again with a new
slave address, instruction, and data byte. Similarly, a repeated read
function of the RDAC is also allowed.
LEVEL SHIFTING FOR DIFFERENT VOLTAGE
OPERATION
If the SCL and SDA signals come from a low voltage logic controller
and are below the minimum VIH level (0.7 V × VDD), level shift
the signals for read/write communications between the AD5170
and the controller. Figure 47 shows one of the implementations.
For example, when SDA1 is at 2.5 V, M1 turns off and SDA2
becomes 5 V. When the SDA1 is at 0 V, M1 turns on and the SDA2
approaches 0 V. As a result, proper level shifting is established. M1
and M2 should be low threshold, N-channel power MOSFETs, such
as the FDV301N.
Multiple Devices on One Bus
Figure 46 shows four AD5170s on the same serial bus. Each has
a different slave address because the states of their AD0 and AD1
pins are different, which allows each device on the bus to be written
to or read from independently. The master device output bus line
drivers are open-drain pull-downs in a fully I2C-compatible interface.
Figure 47. Level Shifting for Different Voltage Operation
Figure 46. Multiple AD5170s on One I2C Bus
analog.com
Rev. H | 22 of 23
Data Sheet
AD5170
OUTLINE DIMENSIONS
Figure 48. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
Updated: October 11, 2021
ORDERING GUIDE
Model1
Temperature Range
Package Description
Packing Quantity
Package
Option
Marking Code
AD5170BRMZ10
AD5170BRMZ10-RL7
AD5170BRMZ2.5
AD5170BRMZ2.5-RL7
AD5170BRMZ50
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
Tube, 50
Reel, 1000
Tube, 50
Reel, 1000
Tube, 50
RM-10
RM-10
RM-10
RM-10
RM-10
DD4
DD4
DD7
DD7
DD6
1
Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2003-2022 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887-2356, U.S.A.
Rev. H | 23 of 23
工商网监
湘ICP备2023018690号
