Data Sheet
AD5172/AD5173
256-Position, One-Time Programmable, Dual-Channel, I2C Digital Potentiometers
FEATURES
►
►
►
►
►
►
►
►
►
►
►
►
►
►
FUNCTIONAL BLOCK DIAGRAMS
2-channel, 256-position potentiometers
One-time programmable (OTP) set-and-forget resistance setting
provides a low cost alternative to EEMEM
Unlimited adjustments before OTP activation
OTP overwrite allows dynamic adjustments with user defined
preset
End-to-end resistance: 2.5 kΩ, 10 kΩ, and 100 kΩ
Compact 10-lead MSOP: 3 mm × 4.9 mm
Fast settling time: tS = 5 µs typical on power-up
Full read/write of wiper register
Power-on preset to midscale
Extra package address decode pins: AD0 and AD1 (AD5173)
Single supply: 2.7 V to 5.5 V
Low temperature coefficient: 35 ppm/°C
Low power: IDD = 6 µA maximum
Wide operating temperature: −40°C to +125°C
Figure 1. AD5172 Functional Block Diagram
APPLICATIONS
►
►
►
►
►
►
►
Systems calibration
Electronics level setting
Mechanical trimmers replacement in new designs
Permanent factory PCB setting
Transducer adjustment of pressure, temperature, position, chemical, and optical sensors
RF amplifier biasing
Gain control and offset adjustment
Figure 2. AD5173 Functional Block Diagram
GENERAL DESCRIPTION
The AD5172/AD5173 are dual-channel, 256-position, one-time programmable (OTP) digital potentiometers that employ fuse link technology to achieve memory retention of resistance settings. The digital potentiometer, VR, and RDAC terms are used interchangeably.
OTP is a cost-effective alternative to EEMEM for users who do not
need to program the digital potentiometer setting in memory more
than once. These devices perform the same electronic adjustment
function as mechanical potentiometers or variable resistors but
with enhanced resolution, solid-state reliability, and superior low
temperature coefficient performance.
Unlike traditional OTP digital potentiometers, the AD5172/AD5173
have a unique temporary OTP overwrite feature that allows for new
adjustments even after a fuse is blown. However, the OTP setting is
restored during subsequent power-up conditions. This allows users
to treat these digital potentiometers as volatile potentiometers with
a programmable preset.
TheAD5172/AD5173 are programmed using a 2-wire, I2C-compatible digital interface. Unlimited adjustments are allowed before
permanently setting the resistance value. During OTP activation,
a permanent blow fuse command freezes the wiper position (analogous to placing epoxy on a mechanical trimmer).
Rev. J
DOCUMENT FEEDBACK
TECHNICAL SUPPORT
Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to
change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Data Sheet
AD5172/AD5173
TABLE OF CONTENTS
Features................................................................ 1
Applications........................................................... 1
Functional Block Diagrams....................................1
General Description...............................................1
Specifications........................................................ 3
Electrical Characteristics: 2.5 kΩ....................... 3
Electrical Characteristics: 10 kΩ and 100 kΩ ....4
Timing Characteristics........................................6
Absolute Maximum Ratings...................................7
ESD Caution.......................................................7
Pin Configurations and Function Descriptions.......8
Typical Performance Characteristics..................... 9
Test Circuits......................................................... 13
Theory of Operation.............................................14
One-Time Programming (OTP)........................ 14
Programming the Variable Resistor and
Voltage........................................................... 14
Programming the Potentiometer Divider.......... 15
ESD Protection.................................................15
Terminal Voltage Operating Range.................. 16
Power-Up Sequence........................................ 16
Power Supply Considerations.......................... 16
Layout Considerations......................................16
2
I C Interface.........................................................17
Write Mode....................................................... 17
Read Mode.......................................................17
SDA Bits Descriptions...................................... 17
I2C Controller Programming............................. 17
I2C-Compatible, 2-Wire Serial Bus...................19
Level Shifting for Different Voltage Operation.. 20
Outline Dimensions............................................. 21
Ordering Guide.................................................21
RAB Options......................................................21
Evaluation Boards............................................ 22
REVISION HISTORY
1/2022—Rev. I to Rev. J
Changes to Features Section.......................................................................................................................... 1
Changes to Applications Section..................................................................................................................... 1
Changes to OTP Supply Current Parameter and Power Supply Range Parameter, Table 1.......................... 3
Changed Electrical Characteristics 10 kΩ, 50 kΩ, and 100 kΩ Section to Electrical Characteristics: 10
kΩ and 100 kΩ Section..................................................................................................................................4
Changes to OTP Supply Current Parameter, Bandwidth, −3 dB Parameter, and Power Supply Range
Parameter, Table 2.........................................................................................................................................4
Deleted Figure 21; Renumbered Sequentially................................................................................................. 9
Changes to Figure 22.....................................................................................................................................11
Changes to Rheostat Operation Section, Table 8, and Table 9..................................................................... 14
Moved Figure 46............................................................................................................................................ 16
Moved Table 14..............................................................................................................................................17
Change to Level Shifting for Different Voltage Operation Section................................................................. 20
Changes to Ordering Guide........................................................................................................................... 21
analog.com
Rev. J | 2 of 22
Data Sheet
AD5172/AD5173
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS: 2.5 KΩ
VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.
Table 1.
Parameter
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
Wiper Resistance
DC CHARACTERISTICS—POTENTIOMETER DIVIDER
MODE4
Differential Nonlinearity5
Integral Nonlinearity5
Voltage Divider Temperature Coefficient
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range6
Capacitance A, B7
Capacitance W7
Shutdown Supply Current8
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
SDA and SCL
Input Logic High9
Input Logic Low9
AD0 and AD1
Input Logic High
Input Logic Low
Input Current
Input Capacitance7
POWER SUPPLIES
Power Supply Range
OTP Supply Voltage9, 10
Supply Current
OTP Supply Current9, 11, 12
Power Dissipation13
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS14
Bandwidth, −3 dB
Total Harmonic Distortion
VW Settling Time
Resistor Noise Voltage Density
1
Symbol
Conditions
Min
Typ1
Max
Unit
R-DNL
R-INL
∆RAB
(∆RAB/RAB)/∆T
RWB
RWB, VA = no connect
RWB, VA = no connect
TA = 25°C
−2
−14
−20
±0.1
±2
+2
+14
+55
LSB
LSB
%
ppm/°C
Ω
DNL
INL
(ΔVW/VW)/ΔT
VWFSE
VWZSE
VA, VB, VW
CA, CB
35
160
Code = 0x00, VDD = 5 V
−1.5
−2
Code = 0x80
Code = 0xFF
Code = 0x00
−14
0
GND
IA_SD
ICM
f = 1 MHz, measured to GND,
code = 0x80
f = 1 MHz, measured to GND,
code = 0x80
VDD = 5.5 V
VA = VB = VDD/2
VIH
VIL
VDD = 5 V
VDD = 5 V
0.7 VDD
−0.5
VIH
VIL
IIL
CIL
VDD = 3 V
VDD = 3 V
VIN = 0 V or 5 V
2.1
VDD
VDD_OTP
IDD
IDD_OTP
PDISS
PSS
2.7
TA = 25°C
5.6
VIH = 5 V or VIL = 0 V
VDD_OTP = 5.7 V, TA = 25°C
VIH = 5 V or VIL = 0 V, VDD = 5 V
VDD = 5 V ± 10%, code = midscale
BW
THDW
tS
Code = 0x80
VA = 1 V rms, VB = 0 V, f = 1 kHz
VA = 5 V, VB = 0 V, ±1 LSB error
band
RWB = 1.25 kΩ, RS = 0 Ω
CW
eN_WB
±0.1
±0.6
15
−5.5
4.5
200
+1.5
+2
LSB
LSB
ppm/°C
LSB
LSB
0
12
45
VDD
V
pF
60
pF
0.01
1
1
µA
nA
VDD + 0.5
+0.3 VDD
V
V
0.6
±1
V
V
µA
pF
5
5.7
3.5
100
±0.02
5.5
5.8
6
33
±0.08
V
V
µA
mA
µW
%/%
4.8
0.1
1
MHz
%
µs
3.2
nV/√Hz
Typical specifications represent average readings at 25°C and VDD = 5 V.
analog.com
Rev. J | 3 of 22
Data Sheet
AD5172/AD5173
SPECIFICATIONS
Table 1.
Parameter
Symbol
Conditions
Typ1
Min
Max
Unit
2
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.
3
VA = VDD, VB = 0 V, wiper (VW) = no connect.
4
Specifications apply to all VRs.
5
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of
±1 LSB maximum are guaranteed monotonic operating conditions.
6
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
7
Guaranteed by design, but not subject to production test.
8
Measured at Terminal A. Terminal A is open circuited in shutdown mode.
9
The minimum voltage requirement on the VIH is 0.7 V × VDD. For example, VIH minimum = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled up
to VDD. However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-up
resistors.
10
Different from the operating power supply; the power supply for OTP is used one time only.
11
Different from the operating current; the supply current for OTP lasts approximately 400 ms for one time only.
12
See Figure 29 for an energy plot during an OTP program.
13
PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
14
All dynamic characteristics use VDD = 5 V.
ELECTRICAL CHARACTERISTICS: 10 KΩ AND 100 KΩ
VDD = 5 V ± 10% or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.
Table 2.
Parameter
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
Wiper Resistance
DC CHARACTERISTICS—POTENTIOMETER DIVIDER
MODE4
Differential Nonlinearity5
Integral Nonlinearity5
Voltage Divider Temperature Coefficient
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range6
Capacitance A, B7
Capacitance W7
Shutdown Supply Current8
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
SDA and SCL
Input Logic High9
analog.com
Symbol
Conditions
Min
Typ1
Max
Unit
R-DNL
R-INL
ΔRAB
(ΔRAB/RAB)/ΔT
RWB
RWB, VA = no connect
RWB, VA = no connect
TA = 25°C
−1
−2.5
−20
±0.1
±0.25
+1
+2.5
+20
LSB
LSB
%
ppm/°C
Ω
DNL
INL
(ΔVW/VW)/ΔT
VWFSE
VWZSE
VA, VB, VW
CA, CB
−1
−1
Code = 0x80
Code = 0xFF
Code = 0x00
−2.5
0
±0.1
±0.3
15
−1
1
GND
IA_SD
ICM
f = 1 MHz, measured to GND,
code = 0x80
f = 1 MHz, measured to GND,
code = 0x80
VDD = 5.5 V
VA = VB = VDD/2
VIH
VDD = 5 V
CW
35
160
Code = 0x00, VDD = 5 V
+1
+1
LSB
LSB
ppm/°C
LSB
LSB
0
2.5
45
VDD
V
pF
60
pF
0.01
1
0.7 VDD
200
1
µA
nA
VDD + 0.5
V
Rev. J | 4 of 22
Data Sheet
AD5172/AD5173
SPECIFICATIONS
Table 2.
Parameter
Symbol
Conditions
Min
Input Logic Low9
AD0 and AD1
Input Logic High
Input Logic Low
Input Current
Input Capacitance7
POWER SUPPLIES
Power Supply Range
OTP Supply Voltage9, 10
Supply Current
OTP Supply Current9, 11, 12
Power Dissipation13
VIL
VDD = 5 V
−0.5
VIH
VIL
IIL
CIL
VDD = 3 V
VDD = 3 V
VIN = 0 V or 5 V
2.1
VDD
VDD_OTP
IDD
IDD_OTP
PDISS
Power Supply Sensitivity
PSS
2.7
TA = 25°C
5.6
VIH = 5 V or VIL = 0 V
VDD_OTP = 5.7 V, TA = 25°C
VIH = 5 V or VIL = 0 V, VDD = 5
V
VDD = 5 V ± 10%, code =
midscale
DYNAMIC CHARACTERISTICS14
Bandwidth, −3 dB
BW
Total Harmonic Distortion
THDW
VW Settling Time
tS
Resistor Noise Voltage Density
eN_WB
Typ1
Max
Unit
+0.3 VDD
V
0.6
±1
V
V
µA
pF
5
5.7
3.5
100
±0.02
5.5
5.8
6
33
V
V
µA
mA
µW
±0.08
%/%
RAB = 10 kΩ, code = 0x80
RAB = 100 kΩ, code = 0x80
VA = 1 V rms, VB = 0 V, f = 1
kHz, RAB = 10 kΩ
600
40
0.1
kHz
kHz
%
VA = 5 V, VB = 0 V, ±1 LSB
error band
RWB = 5 kΩ, RS = 0 Ω
2
µs
9
nV/√Hz
1
Typical specifications represent average readings at 25°C and VDD = 5 V.
2
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.
3
VA = VDD, VB = 0 V, wiper (VW) = no connect.
4
Specifications apply to all VRs.
5
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of
±1 LSB maximum are guaranteed monotonic operating conditions.
6
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
7
Guaranteed by design, but not subject to production test.
8
Measured at Terminal A. Terminal A is open circuited in shutdown mode.
9
The minimum voltage requirement on the VIH is 0.7 V × VDD. For example, VIH minimum = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled up
to VDD. However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-up
resistors.
10
Different from the operating power supply; the power supply for OTP is used one time only.
11
Different from the operating current; the supply current for OTP lasts approximately 400 ms for one time only.
12
See Figure 29 for an energy plot during an OTP program.
13
PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
14
All dynamic characteristics use VDD = 5 V.
analog.com
Rev. J | 5 of 22
Data Sheet
AD5172/AD5173
SPECIFICATIONS
TIMING CHARACTERISTICS
VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.
Table 3.
Parameter
Symbol
I2C INTERFACE TIMING CHARACTERISTICS1
SCL Clock Frequency
Bus-Free Time Between Stop and Start, tBUF
Hold Time (Repeated Start), tHD;STA
fSCL
t1
t2
Low Period of SCL Clock, tLOW
High Period of SCL Clock, tHIGH
Setup Time for Repeated Start Condition, tSU;STA
Data Hold Time, tHD;DAT2
Data Setup Time, tSU;DAT
Fall Time of Both SDA and SCL Signals, tF
Rise Time of Both SDA and SCL Signals, tR
Setup Time for Stop Condition, tSU;STO
OTP Program Time
Conditions
After this period, the first clock
pulse is generated.
t3
t4
t5
t6
t7
t8
t9
t10
t11
1
See the timing diagrams for the locations of measured values (that is, see Figure 3 and Figure 47 to Figure 50).
2
The maximum tHD;DAT has to be met only if the device does not stretch the low period (tLOW) of the SCL signal.
Min
Typ
Max
Unit
400
kHz
µs
µs
1.3
0.6
1.3
0.6
0.6
0.9
100
300
300
0.6
400
µs
µs
µs
µs
ns
ns
ns
µs
ms
Timing Diagram
Figure 3. I2C Interface Detailed Timing Diagram
analog.com
Rev. J | 6 of 22
Data Sheet
AD5172/AD5173
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter
Rating
VDD to GND
VA, VB, VW to GND
−0.3 V to +7 V
−0.3 V to +7 V or VDD +
0.3 V (whichever is less)
Terminal Current, Ax to Bx, Ax to Wx, Bx to Wx
Pulsed
Continuous
Digital Inputs and Output Voltage to GND
Operating Temperature Range
Maximum Junction Temperature (TJMAX)
Storage Temperature Range
Reflow Soldering
Peak Temperature
Time at Peak Temperature
Thermal Resistance
θJA for 10-Lead MSOP
analog.com
±20 mA
±5 mA
−0.3 V to +7 V or VDD +
0.3 V (whichever is less)
−40°C to +125°C
150°C
−65°C to +150°C
Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although
this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
260°C
20 sec to 40 sec
200°C/W
Rev. J | 7 of 22
Data Sheet
AD5172/AD5173
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 4. AD5172 Pin Configuration
Figure 5. AD5173 Pin Configuration
Table 5. AD5172 Pin Function Descriptions
Table 6. AD5173 Pin Function Descriptions
Pin
No.
Mnemonic
Description
Pin
No.
Mnemonic
Description
1
2
3
4
5
B1
A1
W2
GND
VDD
1
2
B1
AD0
3
4
5
W2
GND
VDD
6
SCL
B1 Terminal. GND ≤ VB1 ≤ VDD.
A1 Terminal. GND ≤ VA1 ≤ VDD.
W2 Terminal. GND ≤ VW2 ≤ VDD.
Digital Ground.
Positive Power Supply. Specified for operation from 2.7
V to 5.5 V. For OTP programming, VDD needs to be a
minimum of 5.6 V but no more than 5.8 V and to be
capable of driving 100 mA.
Serial Clock Input. Positive-edge triggered. Requires a
pull-up resistor. If this pin is driven directly from a logic
controller without a pull-up resistor, ensure that the VIH
minimum is 0.7 V × VDD.
Serial Data Input/Output. Requires a pull-up resistor. If
this pin is driven directly from a logic controller without
a pull-up resistor, ensure that the VIH minimum is 0.7 V
× VDD.
A2 Terminal. GND ≤ VA2 ≤ VDD.
B2 Terminal. GND ≤ VB2 ≤ VDD.
W1 Terminal. GND ≤ VW1 ≤ VDD.
6
SCL
7
SDA
8
AD1
9
10
B2
W1
B1 Terminal. GND ≤ VB1 ≤ VDD.
Programmable Address Bit 0 for Multiple Package
Decoding.
W2 Terminal. GND ≤ VW2 ≤ VDD.
Digital Ground.
Positive Power Supply. Specified for operation from 2.7
V to 5.5 V. For OTP programming, VDD needs to be a
minimum of 5.6 V but no more than 5.8 V and to be
capable of driving 100 mA.
Serial Clock Input. Positive-edge triggered. Requires a
pull-up resistor. If this pin is driven directly from a logic
controller without a pull-up resistor, ensure that the VIH
minimum is 0.7 V × VDD.
Serial Data Input/Output. Requires a pull-up resistor. If
this pin is driven directly from a logic controller without
a pull-up resistor, ensure that the VIH minimum is 0.7 V
× VDD.
Programmable Address Bit 1 for Multiple Package
Decoding.
B2 Terminal. GND ≤ VB2 ≤ VDD.
W1 Terminal. GND ≤ VW1 ≤ VDD.
7
8
9
10
SDA
A2
B2
W1
analog.com
Rev. J | 8 of 22
Data Sheet
AD5172/AD5173
TYPICAL PERFORMANCE CHARACTERISTICS
analog.com
Figure 6. R-INL vs. Code vs. Supply Voltages
Figure 9. DNL vs. Code vs. Temperature
Figure 7. R-DNL vs. Code vs. Supply Voltages
Figure 10. INL vs. Code vs. Supply Voltages
Figure 8. INL vs. Code vs. Temperature
Figure 11. DNL vs. Code vs. Supply Voltages
Rev. J | 9 of 22
Data Sheet
AD5172/AD5173
TYPICAL PERFORMANCE CHARACTERISTICS
analog.com
Figure 12. R-INL vs. Code vs. Temperature
Figure 15. Zero-Scale Error vs. Temperature
Figure 13. R-DNL vs. Code vs. Temperature
Figure 16. Supply Current vs. Temperature
Figure 14. Full-Scale Error vs. Temperature
Figure 17. Rheostat Mode Tempco ΔRWB/ΔT vs. Code
Rev. J | 10 of 22
Data Sheet
AD5172/AD5173
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 18. AD5172 Potentiometer Mode Tempco ΔVWB/ΔT vs. Code
Figure 21. Gain vs. Frequency vs. Code, RAB = 100 kΩ
Figure 19. Gain vs. Frequency vs. Code, RAB = 2.5 kΩ
Figure 22. −3 dB Bandwidth at Code = 0x80
Figure 20. Gain vs. Frequency vs. Code, RAB = 10 kΩ
Figure 23. Supply Current vs. Digital Input Voltage
analog.com
Rev. J | 11 of 22
Data Sheet
AD5172/AD5173
TYPICAL PERFORMANCE CHARACTERISTICS
analog.com
Figure 24. Digital Feedthrough
Figure 27. Midscale Glitch, Code 0x80 to Code 0x7F
Figure 25. Digital Crosstalk
Figure 28. Large-Signal Settling Time
Figure 26. Analog Crosstalk
Figure 29. OTP Program Energy for Single Fuse
Rev. J | 12 of 22
Data Sheet
AD5172/AD5173
TEST CIRCUITS
Figure 30 to Figure 37 illustrate the test circuits that define the test conditions used in the product specification tables (see Table 1 and Table 2).
Figure 30. Potentiometer Divider Nonlinearity Error (INL, DNL)
Figure 35. Incremental On Resistance
Figure 31. Resistor Position Nonlinearity Error (Rheostat Operation: R-INL,
R-DNL)
Figure 36. Common-Mode Leakage Current
Figure 32. Wiper Resistance
Figure 37. Analog Crosstalk
Figure 33. Power Supply Sensitivity (PSS, PSSR)
Figure 34. Test Circuit for Gain vs. Frequency
analog.com
Rev. J | 13 of 22
Data Sheet
AD5172/AD5173
THEORY OF OPERATION
Figure 38. Detailed Functional Block Diagram
The AD5172/AD5173 are 256-position, digitally controlled variable
resistors (VRs) that employ fuse link technology to achieve memory
retention of the resistance setting.
PROGRAMMING THE VARIABLE RESISTOR
AND VOLTAGE
An internal power-on preset places the wiper at midscale during
power-on. If the OTP function is activated, the device powers up at
the user-defined permanent setting.
Rheostat Operation
ONE-TIME PROGRAMMING (OTP)
Prior to OTP activation, the AD5172/AD5173 presets to midscale
during initial power-on. After the wiper is set to the desired position,
the resistance can be permanently set by programming the T
bit high, with the proper coding (see Table 8 and Table 9), and
one-time VDD_OTP. The fuse link technology of the AD517x family
of digital potentiometers requires VDD_OTP to be between 5.6 V
and 5.8 V to blow the fuses to achieve a given nonvolatile setting.
However, during operation, VDD can be 2.7 V to 5.5 V. As a result,
an external supply is required for one-time programming. The user
is allowed only one attempt to blow the fuses. If the user fails
to blow the fuses during this attempt, the structure of the fuses
can change such that they may never be blown, regardless of
the energy applied during subsequent events. For details, see the
Power Supply Considerations section.
The device control circuit has two validation bits, E1 and E0, that
can be read back to check the programming status (see Table
7). Users should always read back the validation bits to ensure
that the fuses are properly blown. After the fuses are blown, all
fuse latches are enabled upon subsequent power-on; therefore,
the output corresponds to the stored setting. Figure 38 shows a
detailed functional block diagram.
The nominal resistance of the RDAC between Terminal A and
Terminal B is available in 2.5 kΩ, 10 kΩ, and 100 kΩ. The nominal
resistance (RAB) of the VR has 256 contact points accessed by
the wiper terminal and the B terminal contact. The 8-bit data in the
RDAC latch is decoded to select one of the 256 possible settings.
Figure 39. Rheostat Mode Configuration
Assuming a 10 kΩ part is used, the first connection of the wiper
starts at the B terminal for Data 0x00. Because there is a 160 Ω
wiper contact resistance, such a connection yields a minimum of
320 Ω (2 × 160 Ω) resistance between Terminal W and Terminal B.
The second connection is the first tap point, which corresponds
to 359 Ω (RWB = RAB/256 + 2 × RW = 39 Ω + 2 × 160 Ω) for
Data 0x01. The third connection is the next tap point, representing
398 Ω (2 × 39 Ω + 2 × 160 Ω) for Data 0x02, and so on. Each LSB
data value increase moves the wiper up the resistor ladder until the
last tap point is reached at 10281 Ω (RAB − 1 LSB + 2 × RW).
Table 7. Validation Status
E1
E0
Status
0
1
0
0
1
1
Ready for programming.
Fatal error. Some fuses are not blown. Do not retry. Discard this
unit.
Successful. No further programming is possible.
Figure 40. AD5172/AD5173 Equivalent RDAC Circuit
analog.com
Rev. J | 14 of 22
Data Sheet
AD5172/AD5173
THEORY OF OPERATION
The general equation that determines the digitally programmed
output resistance between W and B is
RWB D =
D
256
× RAB + 2 × RW
PROGRAMMING THE POTENTIOMETER
DIVIDER
(1)
where:
D is the decimal equivalent of the binary code loaded in the 8-bit
RDAC register.
RAB is the end-to-end resistance.
RW is the wiper resistance contributed by the on resistance of the
internal switch.
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at wiper
to B and at wiper to A, proportional to the input voltage at A to B.
Unlike the polarity of VDD to GND, which must be positive, voltage
across A to B, W to A, and W to B can be at either polarity.
In summary, if RAB is 10 kΩ and the A terminal is open circuited, the
output resistance, RWB, is set according to the RDAC latch codes,
as listed in Table 8.
Figure 41. Potentiometer Mode Configuration
Table 8. Codes and Corresponding RWB Resistance
D (Dec)
RWB (Ω)
Output State
255
128
1
0
10,281
5320
359
320
Full scale (RAB – 1 LSB + 2 × RW)
Midscale
1 LSB
Zero scale (wiper contact resistance)
Note that in the zero-scale condition, a finite wiper resistance of
160 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum pulse current of no
more than 20 mA. Otherwise, degradation or possible destruction of
the internal switch contact may occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between Wiper W and Terminal A also produces a digitally
controlled complementary resistance, RWA. When these terminals
are used, the B terminal can be opened. Setting the resistance value for RWA starts at a maximum value of resistance and decreases
as the data loaded in the latch increases in value. The general
equation for this operation is
RWA D =
256 – D
256
× RAB + 2 × RW
(2)
When RAB is 10 kΩ and the B terminal is open circuited, the output
resistance, RWA, is set according to the RDAC latch codes, as listed
in Table 9.
Table 9. Codes and Corresponding RWA Resistance
D (Dec)
RWA (Ω)
Output State
255
128
1
0
359
5320
10,281
10,320
Full scale
Midscale
1 LSB
Zero scale
Typical device-to-device matching is process lot dependent and can
vary up to ±30%. Because the resistance element is processed
using thin film technology, the change in RAB with temperature has
a very low temperature coefficient of 35 ppm/°C.
analog.com
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper to B, starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the
voltage applied across Terminal A and Terminal B divided by the
256 positions of the potentiometer divider. The general equation
defining the output voltage at VW with respect to ground for any
valid input voltage applied to Terminal A and Terminal B is
VW(D) =
D
256 VA
VW(D) =
RWB(D)
RAB VA
+
256 − D
256 VB
(3)
A more accurate calculation, which includes the effect of wiper
resistance, VW, is
+
RWA(D)
RAB VB
(4)
Operation of the digital potentiometer in the divider mode results in
more accurate operation over temperature. Unlike in the rheostat
mode, the output voltage is dependent mainly on the ratio of
the internal resistors, RWA and RWB, not on the absolute values.
Therefore, the temperature drift reduces to 15 ppm/°C.
ESD PROTECTION
All digital inputs, SDA, SCL, AD0, and AD1, are protected with a
series input resistor and parallel Zener ESD structures, as shown in
Figure 42 and Figure 43.
Figure 42. ESD Protection of Digital Pins
Figure 43. ESD Protection of Resistor Terminals
Rev. J | 15 of 22
Data Sheet
AD5172/AD5173
THEORY OF OPERATION
TERMINAL VOLTAGE OPERATING RANGE
The AD5172/AD5173 to GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer operation.
Supply signals present on Terminal A, Terminal B, and Terminal
W that exceed VDD or GND are clamped by the internal forwardbiased diodes (see Figure 44).
Figure 44. Maximum Terminal Voltages Set by VDD and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at Terminal A, Terminal B, and Terminal W (see Figure 44), it is
important to power VDD/GND before applying voltage to Terminal A,
Terminal B, and Terminal W. Otherwise, the diode is forward-biased
such that VDD is powered unintentionally and may affect the rest
of the user’s circuit. The ideal power-up sequence is GND, VDD,
digital inputs, and then VA/VB/VW. The relative order of powering
VA, VB, VW, and the digital inputs is not important, as long as they
are powered after VDD/GND.
POWER SUPPLY CONSIDERATIONS
To minimize the package pin count, both the one-time programming
and normal operating voltage supplies are applied to the same
VDD terminal of the device. The AD5172/AD5173 employ fuse link
technology that requires 5.6 V to 5.8 V to blow the internal fuses to
achieve a given setting, but normal VDD can be 2.7 V to 5.5 V. Such
dual-voltage requirements need isolation between the supplies if
VDD is lower than the required VDD_OTP. The fuse programming
supply (either an on-board regulator or rack-mount power supply)
must be rated at 5.6 V to 5.8 V and must be able to provide a
100 mA transient current for 400 ms for successful one-time programming. When programming is completed, the VDD_OTP supply
must be removed to allow normal operation at 2.7 V to 5.5 V; the
device consumes only microamps of current.
For example, for those who operate their systems at 2.7 V, use
of the bidirectional, low threshold, P-channel MOSFETs is recommended for the isolation of the supply. As shown in Figure 45, this
assumes that the 2.7 V system voltage is applied first and that
the P1 and P2 gates are pulled to ground, thus turning on P1 and
then P2. As a result, VDD of the AD5172/AD5173 approaches 2.7
V. When the AD5172/AD5173 setting is found, the factory tester
applies the VDD_OTP to both the VDD and the MOSFET gates, thus
turning P1 and P2 off. To program the AD5172/AD5173 while the
2.7 V source is protected, execute the OTP command at this time.
When the OTP is completed, the tester withdraws the VDD_OTP, and
the setting of the AD5172/AD5173 is fixed permanently.
The AD5172/AD5173 achieve the OTP function by blowing internal
fuses. Always apply the 5.6 V to 5.8 V one-time program voltage
requirement at the first fuse programming attempt. Failure to comply with this requirement may lead to changing the fuse structures,
rendering programming inoperable.
Care should be taken when SCL and SDA are driven from a low
voltage logic controller. Users must ensure that the logic high level
is between 0.7 V × VDD and VDD + 0.5 V.
Poor PCB layout introduces parasitics that can affect fuse programming. Therefore, it is recommended to add a 1 µF to 10 µF tantalum
capacitor in parallel with a 1 nF ceramic capacitor as close as
possible to the VDD pin. The type and value chosen for both
capacitors are important. These capacitors work together to provide
both fast responsiveness and large supply current handling with
minimum supply droop during transients. As a result, these capacitors increase the OTP programming success by not inhibiting the
proper energy needed to blow the internal fuses. Additionally, C1
minimizes transient disturbance and low frequency ripple, whereas
C2 reduces high frequency noise during normal operation.
Figure 46. Power Supply Bypassing
LAYOUT CONSIDERATIONS
In PCB layout, it is a good practice to employ compact, minimum
lead length design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths should
have low resistance and low inductance.
Figure 45. Isolate 5.7 V OTP Supply from 2.7 V Normal Operating Supply
analog.com
Note that the digital ground should also be joined remotely to the
analog ground at one point to minimize the ground bounce.
Rev. J | 16 of 22
Data Sheet
AD5172/AD5173
I2C INTERFACE
WRITE MODE
Table 10. AD5172 Write Mode
S
0
1
0
1
1
1
1
W
A
A0
SD
Slave address byte
T
0
OW
X
X
X
A
D7
D6
D5
Instruction byte
D4
D3
D2
D1
D0
A
P
D2
D1
D0
A
P
X
X
X
A
P
X
X
X
A
P
Data byte
Table 11. AD5173 Write Mode
S
0
1
0
1
1
AD1 AD0
W
A
A0 SD
T
Slave address byte
0
OW
X
X
X
A
D7
D6
D5
Instruction byte
D4
D3
Data byte
READ MODE
Table 12. AD5172 Read Mode
S
0
1
0
1
1
1
1
R
A
D7
D6
Slave address byte
D5
D4
D3
D2
D1
D0
A
E1
E0
X
Instruction byte
X
X
Data byte
Table 13. AD5173 Read Mode
S
0
1
0
1
1
AD1 AD0
R
A
D7
Slave address byte
D6
D5
D4 D3 D2 D1 D0
A
Instruction byte
E1
E0
X
X
X
Data byte
SDA BITS DESCRIPTIONS
Table 14. SDA Bits Descriptions
Bit
Description
S
P
A
AD0, AD1
X
W
R
A0
SD
T
OW
Start condition.
Stop condition.
Acknowledge.
Package pin-programmable address bits.
Don’t care.
Write.
Read.
RDAC subaddress select bit.
Shutdown connects wiper to B terminal and open circuits the A terminal. It does not change the contents of the wiper register.
OTP programming bit. Logic 1 programs the wiper permanently.
Overwrites the fuse setting and programs the digital potentiometer to a different setting. Upon power-up, the digital
potentiometer is preset to either midscale or fuse setting, depending on whether the fuse link was blown.
Data bits.
OTP validation bits.
00 = ready to program.
10 = fatal error. Some fuses not blown. Do not retry. Discard this unit.
11 = programmed successfully. No further adjustments are possible.
D7, D6, D5, D4, D3, D2, D1, D0
E1, E0
I2C CONTROLLER PROGRAMMING
Write Bit Patterns
Figure 47. Writing to the RDAC Register—AD5172
analog.com
Rev. J | 17 of 22
Data Sheet
AD5172/AD5173
I2C INTERFACE
Figure 48. Writing to the RDAC Register—AD5173
Read Bit Patterns
Figure 49. Reading Data from a Previously Selected RDAC Register in Write Mode—AD5172
Figure 50. Reading Data from a Previously Selected RDAC Register in Write Mode—AD5173
analog.com
Rev. J | 18 of 22
Data Sheet
AD5172/AD5173
I2C INTERFACE
I2C-COMPATIBLE, 2-WIRE SERIAL BUS
This section describes how the 2-wire, I2C-compatible serial bus
protocol operates.
The master initiates a data transfer by establishing a start condition,
which is when a high-to-low transition on the SDA line occurs while
SCL is high (see Figure 47 and Figure 48). The following byte is the
slave address byte, which consists of the slave address followed by
an R/W bit (this bit determines whether data is read from or written
to the slave device). The AD5172 has a fixed slave address byte,
whereas the AD5173 has two configurable address bits, AD0 and
AD1 (see Figure 47 and Figure 48).
The slave whose address corresponds to the transmitted address
responds by pulling the SDA line low during the ninth clock pulse
(this is called the acknowledge bit). At this stage, all other devices
on the bus remain idle while the selected device waits for data to be
written to or read from its serial register. If the R/W bit is high, the
master reads from the slave device. If the R/W bit is low, the master
writes to the slave device.
In write mode, the second byte is the instruction byte. The first bit
(MSB) of the instruction byte is the RDAC subaddress select bit.
Logic low selects Channel 1; logic high selects Channel 2.
The second MSB, SD, is a shutdown bit. A logic high causes an
open circuit at Terminal A while shorting the wiper to Terminal B.
This operation yields almost 0 Ω in rheostat mode or 0 V in potentiometer mode. It is important to note that the shutdown operation
does not disturb the contents of the register. When brought out of
shutdown, the previous setting is applied to the RDAC. In addition,
during shutdown, new settings can be programmed. When the part
is returned from shutdown, the corresponding VR setting is applied
to the RDAC.
The third MSB, T, is the OTP programming bit. A logic high blows
the polyfuses and programs the resistor setting permanently. The
OTP program time is 400 ms.
The fourth MSB must always be at Logic 0.
The fifth MSB, OW, is an overwrite bit. When raised to a logic high,
OW allows the RDAC setting to be changed even after the internal
fuses are blown. However, when OW is returned to Logic 0, the
position of the RDAC returns to the setting prior to the overwrite.
Because OW is not static, if the device is powered off and on, the
RDAC presets to midscale or to the setting at which the fuses were
blown, depending on whether the fuses had been permanently set.
The remainder of the bits in the instruction byte are don’t cares (see
Figure 47 and Figure 48).
In read mode, the data byte follows immediately after the acknowledgment of the slave address byte. Data is transmitted over the
serial bus in sequences of nine clock pulses (a slight difference
from the write mode, where there are eight data bits followed by an
acknowledge bit). Similarly, transitions on the SDA line must occur
during the low period of SCL and remain stable during the high
period of SCL (see Figure 49 and Figure 50).
Note that the channel of interest is the one that is previously
selected in write mode. If users need to read the RDAC values of
both channels, they must program the first channel in write mode
and then change to read mode to read the first channel value. After
that, the user must return to write mode with the second channel
selected and read the second channel value in read mode. It is not
necessary for users to issue the Frame 3 data byte in write mode
for subsequent readback operations. Refer to Figure 49 and Figure
50 for the programming format.
Following the data byte, the validation byte contains two validation
bits, E0 and E1 (see Table 7). These bits signify the status of the
one-time programming (see Figure 49 and Figure 50).
After all data bits are read or written, the master establishes a stop
condition. A stop condition is defined as a low-to-high transition on
the SDA line while SCL is high. In write mode, the master pulls
the SDA line high during the 10th clock pulse to establish a stop
condition (see Figure 47 and Figure 48). In read mode, the master
issues a no acknowledge for the ninth clock pulse (that is, the SDA
line remains high). The master brings the SDA line low before the
10th clock pulse and then brings the SDA line high to establish a
stop condition (see Figure 49 and Figure 50).
A repeated write function provides the user with the flexibility of
updating the RDAC output multiple times after addressing and
instructing the part only once. For example, after the RDAC has acknowledged its slave address and instruction bytes in write mode,
the RDAC output is updated on each successive byte. If different
instructions are needed, however, the write/read mode must restart
with a new slave address, instruction, and data byte. Similarly, a
repeated read function of the RDAC is also allowed.
Multiple Devices on One Bus (AD5173 Only)
Figure 51 shows four AD5173 devices on the same serial bus.
Each has a different slave address because the states of the AD0
and AD1 pins are different. This allows each device on the bus to
be written to or read from independently. The master device output
bus line drivers are open-drain pull-downs in a fully I2C-compatible
interface.
After acknowledging the instruction byte, the last byte in write
mode is the data byte. Data is transmitted over the serial bus
in sequences of nine clock pulses (eight data bits followed by
an acknowledge bit). The transitions on the SDA line must occur
during the low period of SCL and remain stable during the high
period of SCL (see Figure 3).
analog.com
Rev. J | 19 of 22
Data Sheet
AD5172/AD5173
I2C INTERFACE
tations. For example, when SDA1 is at 2.5 V, M1 turns off, and
SDA2 becomes 5 V. When SDA1 is at 0 V, M1 turns on, and SDA2
approaches 0 V. As a result, proper level shifting is established. It is
best practice for M1 and M2 to be low threshold N-channel power
MOSFETs, such as the FDV301N from On Semiconductor.
Figure 51. Multiple AD5173 Devices on One I2C Bus
LEVEL SHIFTING FOR DIFFERENT VOLTAGE
OPERATION
If the SCL and SDA signals come from a low voltage logic controller
and are below the minimum VIH level (0.7 V × VDD), level shift
the signals for read/write communications between the AD5172/
AD5173 and the controller. Figure 52 shows one of the implemen-
analog.com
Figure 52. Level Shifting for Different Voltage Operation
Rev. J | 20 of 22
Data Sheet
AD5172/AD5173
OUTLINE DIMENSIONS
Figure 53. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
Updated: October 12, 2021
ORDERING GUIDE
Model1
Temperature Range
Package Description
Packing Quantity
Package
Option
Marking Code
AD5172BRMZ10
AD5172BRMZ100
AD5172BRMZ100-RL7
AD5172BRMZ10-RL7
AD5172BRMZ2.5
AD5173BRMZ10
AD5173BRMZ10-RL7
AD5173BRMZ2.5
AD5173BRMZ2.5-RL7
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
Tube, 50
Tube, 50
Reel, 1000
Reel, 1000
Tube, 50
Tube, 50
Reel, 1000
Tube, 50
Reel, 1000
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
DCT
DCV
DCV
DCT
DCR
DCL
DCL
DCH
DCH
1
Z = RoHS Compliant Part.
RAB OPTIONS
Model1, 2
RAB (kΩ) Options
AD5172BRMZ10
AD5172BRMZ100
AD5172BRMZ100-RL7
AD5172BRMZ10-RL7
AD5172BRMZ2.5
AD5173BRMZ10
AD5173BRMZ10-RL7
AD5173BRMZ2.5
AD5173BRMZ2.5-RL7
10
100
100
10
2.5
10
10
2.5
2.5
1
Z = RoHS Compliant Part.
2
The part has a YWW or #YWW label and an assembly lot number label on the bottom side of the package. The Y shows the year that the part was made, for example, Y =
5 means the part was in 2005. WW shows the work week that the part was made.
analog.com
Rev. J | 21 of 22
Data Sheet
AD5172/AD5173
OUTLINE DIMENSIONS
EVALUATION BOARDS
Model1
Description
EVAL-AD5172SDZ
Evaluation Board
1
Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2003-2022 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887-2356, U.S.A.
Rev. J | 22 of 22
工商网监
湘ICP备2023018690号
