AD5220

a FEATURES 128 Position Potentiometer Replacement 10 k , 50 k , 100 k Very Low Power: 40 A Max Increment/Decrement Count Control APPLICATIONS Mechanical Potentiometer Replacement Remote Incremental Adjustment Applications Instrumentation: Gain, Offset Adjustment Programmable Voltage-to-Current Conversion Programmable Filters, Delays, Time Constants Line Impedance Matching Power Supply Adjustment GENERAL DESCRIPTION CLK CS Increment/Decrement Digital Potentiometer AD5220 FUNCTIONAL BLOCK DIAGRAM VDD EN UP/ 7 DOWN CNTR RS POR 40H D E C O D E A W B GND U/D AD5220 +5V UP/DOWN CS U/D CLK The AD5220 provides a single channel, 128-position digitally controlled variable resistor (VR) device. This device performs the same electronic adjustment function as a potentiometer or variable resistor. These products were optimized for instrument and test equipment push-button applications. A choice between bandwidth or power dissipation are available as a result of the wide selection of end-to-end terminal resistance values. The AD5220 contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digitally controlled UP/DOWN counter. The resistance between the wiper and either end point of the fixed resistor provides a constant resistance step size that is equal to the end-to-end resistance divided by the number of positions (e.g., RSTEP = 10 kΩ/ 128 = 78 Ω). The variable resistor offers a true adjustable value of resistance, between the A terminal and the wiper, or the B terminal and the wiper. The fixed A-to-B terminal resistance of 10 kΩ, 50 kΩ, or 100 kΩ has a nominal temperature coefficient of 800 ppm/°C. The chip select CS, count CLK and U/D direction control inputs set the variable resistor position. These inputs that control the internal UP/DOWN counter can be easily generated with mechanical or push button switches (or other contact closure devices). External debounce circuitry is required for the negative-edge sensitive CLK pin. This simple digital interface eliminates the need for microcontrollers in front panel interface designs. The AD5220 is available in both surface mount (SO-8) and the 8-lead plastic DIP package. For ultracompact solutions selected models are available in the thin µSOIC package. All parts are guaranteed to operate over the extended industrial temperature range of –40°C to +85°C. For 3-wire, SPI compatible interface applications, see the AD7376/AD8400/AD8402/AD8403 products. R EV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. INCREMENT AD5220 Figure 1. Typical Push-Button Control Application 50mV/DIV UPCOUNT DETAIL VDD = 5.5V VA = 5.5V VB = 0V f = 100kHz VWB 5V/DIV CLK Figure 2a. Stair-Step Increment Output VDD = 5.5V VA = 5.5V VB = 0V f = 60kHz COUNT 00H v 3FH v 00H VWR fCLK = 60kHz Figure 2b. Full-Scale Up/Down Count One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 ELECTRICAL CHARACTERISTICS otherwise noted) Parameter Symbol Conditions AD5220–SPECIFICATIONS = +3 V (V DD 10% or +5 V 10%, VA = +VDD, VB = 0 V, –40 C < TA < +85 C unless Min –1 –0.5 –1 –0.5 –30 Typ1 ± 0.4 ± 0.1 ± 0.5 ± 0.1 800 40 7 –1 –0.5 –1 –0.5 –2 0 0 10 48 7.5 2.4/2.1 Max +1 +0.5 +1 +0.5 +30 100 Units LSB LSB LSB LSB % ppm/°C Ω Bits LSB LSB LSB LSB ppm/°C LSB LSB V pF pF nA DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs R-DNL RWB, VA = NC, RAB = 10 kΩ Resistor Differential NL2 RWB, VA = NC, RAB = 50 kΩ or 100 kΩ R-INL RWB, VA = NC, RAB = 10 kΩ Resistor Nonlinearity2 RWB, VA = NC, RAB = 50 kΩ or 100 kΩ Nominal Resistor Tolerance ∆R TA = +25°C VAB = VDD, Wiper = No Connect Resistance Temperature Coefficient ∆RAB/∆T Wiper Resistance RW IW = VDD/R, VDD = +3 V or +5 V DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs Resolution N INL RAB = 10 kΩ Integral Nonlinearity3 RAB = 50 kΩ, 100 kΩ DNL RAB = 10 kΩ Differential Nonlinearity Error3 RAB = 50 kΩ, 100 kΩ Code = 40H Voltage Divider Temperature Coefficient ∆VW/∆T Code = 7FH Full-Scale Error VWFSE Zero-Scale Error VWZSE Code = 00H RESISTOR TERMINALS Voltage Range4 Capacitance5 A, B Capacitance5 W Common-Mode Leakage DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Input Current Input Capacitance5 POWER SUPPLIES Power Supply Range Supply Current Power Dissipation6 Power Supply Sensitivity DYNAMIC CHARACTERISTICS5, 7, 8 Bandwidth –3 dB VA, VB, VW CA, CB f = 1 MHz, Measured to GND, Code = 40H CW f = 1 MHz, Measured to GND, Code = 40H ICM VA = VB = VW VIH VIL IIL CIL VDD IDD PDISS PSS BW_10K BW_50K BW_100K THDW tS eNWB VDD = +5 V/+3 V VDD = +5 V/+3 V VIN = 0 V or +5 V ± 0.5 ± 0.2 ± 0.4 ± 0.1 20 –0.5 +0.5 +1 +0.5 +1 +0.5 0 +1 VDD 5 2.7 VIH = +5 V or VIL = 0 V, VDD = +5 V VIH = +5 V or VIL = 0 V, VDD = +5 V 15 75 0.004 650 142 69 0.002 0.6/3/6 14 25 20 20 10 V 0.8/0.6 V ±1 µA pF 5.5 40 200 0.015 V µA µW %/% kHz kHz kHz % µs nV/√Hz ns ns ns ns Total Harmonic Distortion VW Settling Time Resistor Noise Voltage RAB = 10 kΩ, Code = 40H RAB = 50 kΩ, Code = 40H RAB = 100 kΩ, Code = 40H VA =1 V rms + 2.5 V dc, VB = 2.5 V dc, f = 1 kHz VA = VDD, VB = 0 V, 50% of Final Value, 10K/50K/100K RWB = 5 kΩ, f = 1 kHz INTERFACE TIMING CHARACTERISTICS Applies to All Parts5, 9 Input Clock Pulsewidth tCH, tCL Clock Level High or Low CS to CLK Setup Time tCSS CS Rise to Clock Hold Time tCSH U/D to Clock Fall Setup Time tUDS NOTES 1 Typicals represent average readings at +25 °C and VDD = +5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 29 test circuit. 3 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = V DD and VB = 0 V. DNL specification limits of ± 1 LSB maximum are guaranteed monotonic operating conditions. See Figure 28 test circuit. 4 Resistor terminals A, B, W have no limitations on polarity with respect to each other. 5 Guaranteed by design and not subject to production test. 6 PDISS is calculated from (I DD × VDD). CMOS logic level inputs result in minimum power dissipation. 7 Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 8 All dynamic characteristics use V DD = +5 V. 9 See timing diagrams for location of measured values. All input control voltages are specified with t R = tF = 1 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. Switching characteristics are measured using both V DD = +3 V or +5 V. Specifications subject to change without notice. – 2– REV. 0 AD5220 ABSOLUTE MAXIMUM RATINGS* (TA = +25°C, unless otherwise noted) PIN CONFIGURATION VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD AX–BX, AX–WX, BX–WX . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Digital Input Voltage to GND . . . . . . . . . . . 0 V, VDD + 0.3 V Operating Temperature Range . . . . . . . . . . . –40°C to +85°C Maximum Junction Temperature (TJ MAX) . . . . . . . . +150°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C Package Power Dissipation . . . . . . . . . . . . . . (TJ max–TA)/θJA Thermal Resistance θJA P-DIP (N-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103°C/W SOIC (SO-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W µSOIC (RM-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CLK 1 U/D 2 8 VDD CS AD5220 7 TOP VIEW A1 3 (Not to Scale) 6 B1 GND 4 5 W1 PIN FUNCTION DESCRIPTIONS Pin No. 1 2 3 4 5 6 7 8 Name CLK U/D A1 GND W1 B1 CS VDD Description Serial Clock Input, Negative Edge Triggered UP/DOWN Direction Increment Control Terminal A1 Ground Wiper Terminal Terminal B1 Chip Select Input, Active Low Positive Power Supply Table I. Truth Table CS L L H CLK t t X U/D H L X Operation Wiper Increment Toward Terminal A Wiper Decrement Toward Terminal B Wiper Position Fixed 1 CS 0 tCSS tCL tCH 1 CLK 0 1 U/D 0 tCSH tUDS Figure 3. Detail Timing Diagram ORDERING GUIDE Model AD5220BN10 AD5220BR10 AD5220BRM10 AD5220BN50 AD5220BR50 AD5220BRM50 AD5220BN100 AD5220BR100 AD5220BRM100 k 10 10 10 50 50 50 100 100 100 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Descriptions 8-Lead Plastic DIP 8-Lead (SOIC) 8-Lead µSOIC 8-Lead Plastic DIP 8-Lead (SOIC) 8-Lead µSOIC 8-Lead Plastic DIP 8-Lead (SOIC) 8-Lead µSOIC Package Options N-8 SO-8 RM-8 N-8 SO-8 RM-8 N-8 SO-8 RM-8 NOTE The AD5220 die size is 37 mil × 54 mil, 1998 sq mil; 0.938 mm × 1.372 mm, 1.289 sq mm. Contains 754 transistors. Patent Number 5495245 applies. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5220 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. 0 –3– AD5220–Typical Performance Characteristics 100 PERCENT OF NOMINAL END-TO-END RESISTANCE – % RAB 6 VDD = 5.5V RAB = 50k 48 SS = 300 UNITS VDD = +2.7V TA = +25 C 5 40 75 FREQUENCY 4 VWB – V 32 50 3 24 2 7FH 40H 08H 20H 10H 04H 02H 01H 16 25 1 8 0 RWB 0 0 32 RWA 0 64 96 CODE – Decimal 128 0 40 60 80 100 20 CONDUCTION CURRENT, IWB – A 120 20 28 36 44 52 WIPER RESISTANCE – 60 Figure 4. Wiper to End Terminal Resistance vs. Code Figure 5. Resistance Linearity vs. Conduction Current Figure 6. Wiper Contact Resistance 0.5 0.4 0.3 0.2 50k VERSION 100k VERSION TA = +25 C VDD = +5.5V 0.5 0.4 0.3 0.2 100k VERSION 50k VERSION TA = +25 C VDD = +5.5V 0.5 0.4 0.3 0.2 INL – LSB 10k VERSION 50k VERSION RDNL – LSB RINL – LSB 0.1 0.0 –0.1 –0.2 –0.3 10k –0.4 –0.5 0 16 32 48 64 80 96 CODE – Decimal 112 128 VERSION 0.1 0.0 –0.1 –0.2 –0.3 –0.4 –0.5 0 16 32 48 64 80 96 CODE – Decimal 112 128 10k VERSION 0.1 0.0 –0.1 –0.2 –0.3 –0.4 –0.5 0 16 32 48 64 80 96 CODE – Decimal 112 128 TA = +25 C VDD = +5.5V VA = +5.5V VB = 0V 100k VERSION Figure 7. R-DNL Relative Resistance Step Position Nonlinearity Error vs. Code Figure 8. R-INL Resistance Nonlinearity Error vs. Supply Voltage Figure 9. Potentiometer Divider INL Error vs. Code 0.5 0.4 0.3 0.2 100k VERSION 50k VERSION TA = +25 C VDD = +5.5V VA = +5.5V VB = 0V 0.600 0.525 POTENTIOMETER DIVIDER NONLINEARITY – LSB NOMINAL END-TO-END RESISTANCE – k 100 CODE = 40H RAB = 50k VA = VDD 100k 80 VERSION 0.450 0.375 0.300 0.255 0.150 0.075 0.000 2.00 2.50 3.00 3.50 4.00 4.50 5.00 5.50 6.00 SUPPLY VOLTAGE – V DNL – LSB 0.1 0.0 –0.1 –0.2 –0.3 –0.4 –0.5 0 16 10k 32 VERSION 60 40 50k VERSION 20 10k 0 –40 VERSION 48 64 80 96 CODE – Decimal 112 128 –15 10 35 60 TEMPERATURE – C 85 Figure 10. Potentiometer Divider DNL Error vs. Code Figure 11. Potentiometer Divider INL Error vs. Supply Voltage Figure 12. Nominal Resistance vs. Temperature –4– REV. 0 AD5220 POTENTIOMETER MODE TEMPCO – ppm/ C 60 RHEOSTAT MODE TEMPCO – ppm/ C 60 –55 C < TA < +85 C VDD = +5.5V 53 46 39 32 25 18 11 4 –3 –10 0 16 32 48 64 80 96 CODE – Decimal 112 128 50k AND 100k VERSION GAIN – dB 6 53 46 39 10k 32 25 18 11 4 –3 –10 0 16 32 50k AND 100k VERSION –55 C < TA < +85 C VDD = +5.5V RWB MEASURED VA = NO CONNECT 10k VERSION 0 –6 –12 –18 –24 –30 –36 –42 –48 DATA = 40H VDD = +5V VIN = VA = 100mV rms VB = +2.5V – A B W + 2.5V – + OP42 00H 40H 20H 10H 08H 04H 02H 01H VERSION 48 64 80 96 CODE – Decimal 112 128 –54 1k 10k 100k FREQUENCY – Hz 1M Figure 13. ∆VWB/∆T Potentiometer Mode Tempco (10 kΩ and 50 kΩ) Figure 14. ∆RWB/∆T Rheostat Figure 15. 10 kΩ Gain vs. Frequency vs. Code 6 0 –6 –12 GAIN – dB 00H 40H 20H GAIN – dB 6 0 –6 –12 –18 –24 –30 –36 –42 –48 DATA = 40H VDD = +5V VIN = VA = 100mV rms VB = +2.5V A B W + 2.5V – – + OP42 00H 40H 20H 10H 08H 04H 02H 01H VWB VDD = +5.5V VA = VB = 0V f = 100kHz 20mV/ DIV –18 –24 –30 –36 –42 –48 DATA = 40H VDD = +5V VIN = VA = 100mV rms VB = +2.5V A B – W+ + 2.5V – 10H 08H 04H 02H 01H OP42 –54 1k 10k 100k FREQUENCY – Hz 1M –54 1k 10k 100k FREQUENCY – Hz 1M TIME 2 s / DIV Figure 16. 50 kΩ Gain vs. Frequency vs. Code Figure 17. 100 kΩ Gain vs. Frequency vs. Code Figure 18. Digital Feedthrough 1.00 NORMALIZED GAIN FLATNESS – dB –5.8 0.10 THD + NOISE – % 150mV VWB 100mV 50mV VDD = +5.5V DATA VA = +5.5V 40H v 3FH VB = 0V f = 100kHz 0mV TA = +25 C VDD = +5.0V OFFSET GND = +2.5V RAB = 10k –5.9 –6.0 –6.1 –6.2 –6.3 –6.4 –6.5 –6.6 –6.7 –6.8 10 100 A B 10k 50k 100k 0.01 NONINVERTING TEST CKT 32 DATA = 40H VDD = +5V VIN = VA = 50mV rms VB = +2.5V – W+ + 2.5V – 0.001 5V 0V OP42 INVERTING TEST CKT 31 0.0001 10 100 1k 10k FREQUENCY – Hz 100k CLK TIME 500ns / DIV 1k 10k 100k FREQUENCY – Hz 1M Figure 19. Midscale Transition Glitch Figure 20. Total Harmonic Distortion Plus Noise vs. Frequency Figure 21. Normalized Gain Flatness vs. Frequency REV. 0 –5– AD5220 80 400 350 A IDD – SUPPLY CURRENT – 80 DATA = 3FH VB = 0V TA = +25 C TA = +25 C SEE FIGURE 34 FOR TEST CIRCUIT 60 VDD = +2.7V 60 PSRR – dB 300 250 200 150 100 50 0 VDD = +5.5V VA = +5.5V RON – 40 40 VDD = +5.5V VDD = +5V DC 1V p-p AC 20 TA = +25 C CODE = 40H CL = 10pF VA = 4V, VB = 0V 0 1k 10k 100k FREQUENCY – Hz 1M VDD = +2.7V VA = +2.7V 20 0 1k 10k 100k 1M CLOCK FREQUENCY – Hz 10M 0 1 2 3 4 VB – Volts 5 6 Figure 22. Power Supply Rejection vs. Frequency Figure 23. IDD Supply Current vs. Clock Frequency Figure 24. Incremental Wiper Contact Resistance vs. VB 0.10 LOGIC = 0V OR VDD IDD SUPPLY CURRENT – mA SUPPLY CURRENT – mA 10 TA = +25 C ALL LOGIC INPUT PINS TIED TOGETHER 1 VDD = +5V VD = +5.5V 0.01 0.1 VDD = +3.3V 0.001 VDD = +3V 0.01 0.0001 –40 0.001 –15 10 35 60 TEMPERATURE – C 85 0 1.0 2.0 3.0 4.0 DIGITAL INPUT VOLTAGE – V 5.0 Figure 25. Supply Current vs. Temperature IDD Figure 26. Supply Current vs. Input Logic Voltage –6– REV. 0 Parametric Test Circuits– AD5220 A DUT B W +5V V+ DUT A W B V+ = VDD 1LSB = V+/128 OFFSET GND VIN ~ OP279 VMS 2.5V DC VOUT Figure 27. Potentiometer Divider Nonlinearity Error Test Circuit (INL, DNL) Figure 31. Inverting Programmable Gain Test Circuit +5V NO CONNECT DUT A W B VMS IW OFFSET GND 2.5V VIN ~ A W OP279 VOUT DUT B Figure 28. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) Figure 32. Noninverting Programmable Gain Test Circuit A +15V W VMS2 DUT A W B IW = VDD/RNOMINAL VW OFFSET GND VIN ~ DUT B 2.5V –15V OP42 VOUT VMS1 RW = [ VMS1 – V MS2]/IW Figure 29. Wiper Resistance Test Circuit Figure 33. Gain vs. Frequency Test Circuit VA V+ = VDD ± 10% V+ MS ( ––––– ) V DD DUT V RSW = 0.1V ISW CODE = ØØH ISW 0.1V ~ VDD A B W B W VMS PSRR (dB) = 20 LOG VMS% PSS (%/%) = ––––––– VDD% 0 TO VDD Figure 30. Power Supply Sensitivity Test Circuit (PSS, PSRR) Figure 34. Incremental ON Resistance Test Circuit REV. 0 –7– AD5220 OPERATION The AD5220 provides a 128-position digitally controlled variable resistor (VR) device. Changing the VR settings is accomplished by pulsing the CLK pin while CS is active low. The direction of the increment is controlled by the U/D (UP/DOWN) control input pin. When the wiper hits the end of the resistor (Terminals A or B) additional CLK pulses no longer change the wiper setting. The wiper position is immediately decoded by the wiper decode logic changing the wiper resistance. Appropriate debounce circuitry is required when push button switches are used to control the count sequence and direction of count. The exact timing requirements are shown in Figure 3. The AD5220 powers ON in a centered wiper position exhibiting nearly equal resistances of RWA and RWB. VDD EN UP/ 7 DOWN CNTR RS POR 40H D E C O D E A W B GND Ax D0 D1 D2 D3 D4 D5 D6 RDAC UP/DOWN CNTR & DECODE RS RS Wx RS RS = RNOMINAL/128 Bx Figure 38. AD5220 Equivalent RDAC Circuit PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation CLK CS U/D AD5220 Figure 35. Block Diagram DIGITAL INTERFACING OPERATION The AD5220 contains a three-wire serial input interface. The three inputs are clock (CLK), CS and UP/DOWN (U/D). The negative-edge sensitive CLK input requires clean transitions to avoid clocking multiple pulses into the internal UP/DOWN counter register, see Figure 35. Standard logic families work well. If mechanical switches are used for product evaluation they should be debounced by a flip-flop or other suitable means. When CS is taken active low the clock begins to increment or decrement the internal UP/DOWN counter dependent upon the state of the U/D control pin. The UP/DOWN counter value (D) starts at 40H at system power ON. Each new CLK pulse will increment the value of the internal counter by one LSB until the full scale value of 3FH is reached as long as the U/D pin is logic high. If the U/D pin is taken to logic low the counter will count down stopping at code 00H (zero-scale). Additional clock pulses on the CLK pin are ignored when the wiper is at either the 00H position or the 3FH position. All digital inputs (CS, U/D, CLK) are protected with a series input resistor and parallel Zener ESD structure shown in Figure 36. 1k LOGIC The nominal resistance of the RDAC between terminals A and B is available with values of 10 kΩ, 50 kΩ, and 100 kΩ. The final three characters of the part number determine the nominal resistance value, e.g., 10 kΩ =10; 50 kΩ = 50; 100 kΩ = 100. The nominal resistance (RAB) of the VR has 128 contact points accessed by the wiper terminal, plus the B terminal contact. At power ON the resistance from the wiper to either end Terminal A or B is approximately equal. Clocking the CLK pin will increase the resistance from the Wiper W to Terminal B by one unit of RS resistance (see Figure 38). The resistance RWB is determined by the number of pulses applied to the clock pin. Each segment of the internal resistor string has a nominal resistance value of RS = RAB/128, which becomes 78 Ω in the case of the 10 kΩ AD5220BN10 product. Care should be taken to limit the current flow between W and B in the direct contact state to a maximum value of 5 mA to avoid degradation or possible destruction of the internal switch contact. Like the mechanical potentiometer the RDAC replaces, it is totally symmetrical (see Figure 38). The resistance between the Wiper W and Terminal A also produces a digitally controlled resistance RWA. When these terminals are used the B–terminal should be tied to the wiper. The typical part-to-part distribution of RBA is process lot dependent having a ± 30% variation. The change in RBA with temperature has a 800 ppm/°C temperature coefficient. The RBA temperature coefficient increases as the wiper is programmed near the B-terminal due to the larger percentage contribution of the wiper contact switch resistance, which has a 0.5%/°C temperature coefficient. Figure 14 shows the effect of the wiper contact resistance as a function of code setting. Another performance factor influenced by the switch contact resistance is the relative linearity error performance between the 10 kΩ, and the 50 kΩ or 100 kΩ versions. The same switch contact resistance is used in all three versions. Thus the performance of the 50 kΩ and 100 kΩ devices which have the least impact on wiper switch resistance exhibits the best linearity error, see Figures 7 and 8. Figure 36. Equivalent ESD Protection Digital Pins 20 A, B, W GND Figure 37. Equivalent ESD Protection Analog Pins –8– REV. 0 AD5220 PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation APPLICATIONS INFORMATION The digital potentiometer easily generates an output voltage proportional to the input voltage applied to a given terminal. For example connecting A Terminal to +5 V and B Terminal to ground produces an output voltage at the wiper which can be any value starting at zero volts up to 1 LSB less than +5 V. Each LSB of voltage is equal to the voltage applied across terminals AB divided by the 128-position resolution of the potentiometer divider. The general equation defining the output voltage with respect to ground for any given input voltage applied to terminals AB is: VW(D) = D/128 × VAB + VB (1) The negative-edge sensitive CLK pin does not contain any internal debounce circuitry. This standard CMOS logic input responds to fast negative edges and needs to be debounced externally with an appropriate circuit designed for the type of switch closure device being used. Good performance results at the CLK input pin when the negative logic transition has a minimum slew rate of 1 V/µs. A wide variety of standard circuits can be used such as a one-shot multivibrator, Schmitt Triggered gates, cross coupled flip-flops, or RC filters to drive the CLK pin with uniform negative edges. This will prevent the digital potentiometer from skipping output codes while counting due to switch contact bounce. D represents the current contents of the internal UP/DOWN counter. Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Here the output voltage is dependent on the ratio of the internal resistors, not the absolute value, therefore, the drift improves to 20 ppm/°C. REV. 0 –9– AD5220 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Plastic DIP (N-8) 0.430 (10.92) 0.348 (8.84) 8 5 0.280 (7.11) 0.240 (6.10) 1 4 PIN 1 0.210 (5.33) MAX 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN SEATING PLANE 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.100 0.070 (1.77) 0.014 (0.356) (2.54) 0.045 (1.15) BSC 0.015 (0.381) 0.008 (0.204) 8-Lead SOIC (SO-8) 0.1968 (5.00) 0.1890 (4.80) 8 1 5 4 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) PIN 1 0.0098 (0.25) 0.0040 (0.10) 0.0688 (1.75) 0.0532 (1.35) 0.0196 (0.50) 0.0099 (0.25) 45 0.0500 0.0192 (0.49) SEATING (1.27) 0.0098 (0.25) PLANE BSC 0.0138 (0.35) 0.0075 (0.19) 8 0 0.0500 (1.27) 0.0160 (0.41) 8-Lead SOIC (RM-8) 0.122 (3.10) 0.114 (2.90) 8 5 0.122 (3.10) 0.114 (2.90) 1 4 0.199 (5.05) 0.187 (4.75) PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.112 (2.84) 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) SEATING 0.008 (0.20) PLANE 0.043 (1.09) 0.037 (0.94) 0.011 (0.28) 0.003 (0.08) 0.120 (3.05) 0.112 (2.84) 33 27 0.028 (0.71) 0.016 (0.41) –10– REV. 0 PRINTED IN U.S.A. C3426–8–10/98