Data Sheet
AD5241/AD5242
I2C-Compatible 256-Position Digital Potentiometers
FEATURES
►
►
►
►
►
►
►
►
►
FUNCTIONAL BLOCK DIAGRAM
256 positions
10 kΩ, 100 kΩ, 1 MΩ
Low temperature coefficient: 30 ppm/°C
Internal power on midscale preset
Single-supply 2.7 V to 5.5 V or dual-supply ±2.7 V for ac or
bipolar operation
I2C-compatible interface with readback capability
Extra programmable logic outputs
Self contained shutdown feature
Extended temperature range: −40°C to +105°C
Figure 1. AD5241 Functional Block Diagram
APPLICATIONS
►
►
►
►
►
►
Multimedia, video, and audio
Communications
Mechanical potentiometer replacement
Instrumentation: gain, offset adjustment
Programmable voltage-to-current conversion
Line impedance matching
Figure 2. AD5242 Functional Block Diagram
GENERAL DESCRIPTION
The AD5241/AD52421 provide a single-/dual-channel, 256-position,
digitally controlled variable resistor (VR) device. These devices
perform the same electronic adjustment function as a potentiometer, trimmer, or variable resistor. Each VR offers a completely
programmable value of resistance between the A terminal and the
wiper, or the B terminal and the wiper. For the AD5242, the fixed
A-to-B terminal resistance of 10 kΩ, 100 kΩ, or 1 MΩ has a 1%
channel-to-channel matching tolerance. The nominal temperature
coefficient of both parts is 30 ppm/°C.
Wiper position programming defaults to midscale at system power
on. When powered, the VR wiper position is programmed by an
I2C-compatible, 2-wire serial data interface. Both parts have two
extra programmable logic outputs available that enable users to
drive digital loads, logic gates, LED drivers, and analog switches in
their system.
The AD5241/AD5242 are available in surface-mount, 14-lead SOIC and 16-lead SOIC packages and, for ultracompact solutions,
14-lead TSSOP and 16-lead TSSOP packages. All parts are guaranteed to operate over the extended temperature range of −40°C to
+105°C.
1
Patent Number 5,495,245 applies.
Rev. E
DOCUMENT FEEDBACK
TECHNICAL SUPPORT
Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to
change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Data Sheet
AD5241/AD5242
TABLE OF CONTENTS
Features................................................................ 1
Applications........................................................... 1
Functional Block Diagram......................................1
General Description...............................................1
Specifications........................................................ 3
10 kΩ, 100 kΩ, 1 MΩ Version............................ 3
Timing Specifications......................................... 4
Timing Diagrams ............................................... 5
Absolute Maximum Ratings...................................6
ESD Caution.......................................................6
Pin Configurations and Function Descriptions.......7
Typical Performance Characteristics..................... 8
Test Circuits......................................................... 11
Theory of Operation.............................................12
Programming the Variable Resistor..................12
Programming the Potentiometer Divider.......... 13
Digital Interface................................................ 13
Readback RDAC Value.................................... 14
Multiple Devices on One Bus........................... 14
Level-Shift for Bidirectional Interface................14
Additional Programmable Logic Output............14
Shutdown Function...........................................15
Outline Dimensions............................................. 16
Ordering Guide.................................................17
Evaluation Boards............................................ 17
REVISION HISTORY
1/2022—Rev. D to Rev. E
Deleted Interface Timing Characteristics Parameter, Table 1.......................................................................... 3
Changes to Power Single-Supply Range Parameter and Power Dual-Supply Range Parameter, Table 1..... 3
Added Timing Specifications Section and Table 2; Renumbered Sequentially................................................4
Moved Figure 32............................................................................................................................................ 14
Changes to Ordering Guide........................................................................................................................... 17
analog.com
Rev. E | 2 of 17
Data Sheet
AD5241/AD5242
SPECIFICATIONS
10 KΩ, 100 KΩ, 1 MΩ VERSION
VDD = 2.7 V to 5.5 V, VA = VDD, VB = 0 V, −40°C < TA < +105°C, unless otherwise noted.
Table 1.
Parameter
Symbol
DC CHARACTERISTICS, RHEOSTAT MODE
(SPECIFICATIONS APPLY TO ALL VRs)
Resolution
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance
N
R-DNL
R-INL
ΔRAB/RAB
Resistance Temperature Coefficient
Wiper Resistance
DC CHARACTERISTICS, POTENTIOMETER DIVIDER
MODE (SPECIFICATIONS APPLY TO ALL VRs)
Resolution
Differential Nonlinearity3
Integral Nonlinearity3
Voltage Divider Temperature Coefficient
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range4
Capacitance (A, B)5
Capacitance (W)5
Common-Mode Leakage
DIGITAL INPUTS
Input Logic High (SDA and SCL)
Input Logic Low (SDA and SCL)
Input Logic High (AD0 and AD1)
Input Logic Low (AD0 and AD1)
Input Logic High
Input Logic Low
Input Current
Input Capacitance5
DIGITAL OUTPUT
Output Logic Low (SDA)
Output Logic Low (O1 and O2)
Output Logic High (O1 and O2)
Three-State Leakage Current (SDA)
Output Capacitance5
POWER SUPPLIES
Power Single-Supply Range
Power Dual-Supply Range
Positive Supply Current
Negative Supply Current
analog.com
(ΔRAB/RAB)/ΔT × 106
RW
N
DNL
INL
(ΔVW/VW)/∆T × 106
VWFSE
VWZSE
VA, VB, VW
CA, CB
CW
ICM
VIH
VIL
VIH
VIL
VIH
VIL
IIL
CIL
VOL
VOL
VOL
VOH
IOZ
COZ
VDD
VDD/VSS
IDD
ISS
Conditions
Min
RWB, VA = no connect
RWB, VA = no connect
TA = 25°C, RAB = 10 kΩ
TA = 25°C, RAB = 100 kΩ/1 MΩ
8
−1
−2
−30
−30
VAB = VDD, wiper = no connect
IW = VDD/R
±0.4
±0.5
30
60
8
−1
−2
Code = 0x80
Code = 0xFF
Code = 0x00
Typ1
−1
0
±0.4
±0.5
5
−0.5
0.5
VSS
f = 1 MHz, measured to GND,
code = 0x80
f = 1 MHz, measured to GND,
code = 0x80
VA = VB = VW
VDD = 5 V
VDD = 5 V
VDD = 3 V
VDD = 3 V
VIH = 5 V or VIL = GND
Max
Unit
+1
+2
+30
+50
Bits
LSB
LSB
%
%
120
ppm/°C
Ω
+1
+2
0
1
45
VDD
V
pF
60
pF
1
nA
0.7 × VDD
−0.5
2.4
0
2.1
0
VDD + 0.5 V
+0.3 × VDD
VDD
0.8
VDD
0.6
1
3
±1
8
V
V
V
V
V
V
µA
pF
V
V
V
V
µA
pF
0.1
+0.1
5.5
±2.7
50
−50
V
V
µA
µA
3
IOL = 3 mA
IOL = 6 mA
ISINK = 1.6 mA
ISOURCE = 40 µA
VIH = 5 V or VIL = GND
VSS = 0 V
VIH = 5 V or VIL = GND
VSS = −2.5 V, VDD = +2.5 V
Bits
LSB
LSB
ppm/°C
LSB
LSB
0.4
0.6
0.4
4
2.7
±2.3
Rev. E | 3 of 17
Data Sheet
AD5241/AD5242
SPECIFICATIONS
Table 1.
Parameter
Power Dissipation6
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS5, 7, 8
−3 dB Bandwidth
Symbol
Conditions
PDISS
VIH = 5 V or VIL = GND, VDD = 5
V
PSS
Total Harmonic Distortion
BW_10 kΩ
BW_100 kΩ
BW_1 MΩ
THDW
VW Settling Time
tS
Resistor Noise Voltage
eN_WB
Min
−0.01
RAB = 10 kΩ, code = 0x80
RAB = 100 kΩ, code = 0x80
RAB = 1 MΩ, code = 0x80
VA = 1 V rms + 2 V dc, VB = 2 V
dc, f = 1 kHz
VA = VDD, VB = 0 V, ± 1 LSB
error band, RAB = 10 kΩ
RWB = 5 kΩ, f = 1 kHz
Typ1
Max
0.5
250
+0.002
+0.01
Unit
µW
%/%
650
69
6
0.005
kHz
kHz
kHz
%
2
µs
14
nV√Hz
1
Typicals represent average readings at 25°C, VDD = 5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Test Circuits.
3
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification
limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See Figure 37.
4
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
5
Guaranteed by design, not subject to production test.
6
PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
7
Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth.
The highest R value results in the minimum overall power consumption.
8
All dynamic characteristics use VDD = 5 V.
TIMING SPECIFICATIONS
Table 2.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
400
kHz
INTERFACE TIMING CHARACTERISTICS
(APPLIES TO ALL PARTS1, 2)
SCL Clock Frequency
fSCL
Bus Free Time Between Stop and Start, tBUF
t1
Hold Time (Repeated Start), tHD; STA
t2
Low Period of SCL Clock, tLOW
t3
1.3
High Period of SCL Clock, tHIGH
t4
0.6
Setup Time for Repeated Start Condition, tSU; STA
t5
600
Data Hold Time, tHD; DAT
t6
Data Setup Time, tSU; DAT
t7
Rise Time of Both SDA and SCL Signals, tR
t8
Fall Time of Both SDA and SCL Signals, tF
t9
Setup Time for Stop Condition, tSU; STO
t10
1
Guaranteed by design, not subject to production test.
2
See timing diagram in Figure 3 for location of measured values.
analog.com
0
After this period, the first clock
pulse is generated
1.3
µs
600
ns
µs
50
µs
900
ns
ns
100
0.6
ns
300
ns
300
ns
µs
Rev. E | 4 of 17
Data Sheet
AD5241/AD5242
SPECIFICATIONS
TIMING DIAGRAMS
Figure 3. Detail Timing Diagram
Data of AD5241/AD5242 is accepted from the I2C bus in the following serial format.
Table 3.
S
0
1
0
1
1
AD1
AD0
Slave Address Byte
R/W
A
A/B
R
S
SD
O1
O2
X
X
X
A
D7
D6
D5
Instruction Byte
D4
D3
D2
D1
D0
A
P
Data Byte
where:
S = start condition
P = stop condition
A = acknowledge
X = don’t care
AD1, AD0 = Package pin programmable address bits. Must be matched with the logic states at Pin AD1 and Pin AD0.
R/W = Read enable at high and output to SDA. Write enable at low.
A/B = RDAC subaddress select; 0 for RDAC1 and 1 for RDAC2.
RS = Midscale reset, active high.
SD = Shutdown in active high. Same as except inverse logic.
O1, O2 = Output logic pin latched values
D7, D6, D5, D4, D3, D2, D1, D0 = data bits.
Figure 4. Writing to the RDAC Serial Register
Figure 5. Reading Data from a Previously Selected RDAC Register in Write Mode
analog.com
Rev. E | 5 of 17
Data Sheet
AD5241/AD5242
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter
Rating
VDD to GND
VSS to GND
VDD to VSS
VA, VB, VW to GND
IA, IB, IW
RAB = 10 kΩ in TSSOP-14
RAB = 100 kΩ in TSSOP-14
RAB = 1 MΩ in TSSOP-14
Digital Input Voltage to GND
Operating Temperature Range
Thermal Resistance θJA
14-Lead SOIC
16-Lead SOIC
14-Lead TSSOP
16-Lead TSSOP
Maximum Junction Temperature (TJ max)
Package Power Dissipation
Storage Temperature Range
Lead Temperature
Vapor Phase, 60 sec
Infrared, 15 sec
−0.3 V to +7 V
0 V to −7 V
7V
VSS to VDD
1
5.0 mA1
1.5 mA1
0.5 mA1
0 V to VDD + 0.3 V
−40°C to +105°C
Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although
this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
158°C/W
73°C/W
206°C/W
180°C/W
150°C
PD = (TJ max − TA)/θJA
−65°C to +150°C
215°C
220°C
Maximum current increases at lower resistance and different packages.
analog.com
Rev. E | 6 of 17
Data Sheet
AD5241/AD5242
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 6. AD5241 Pin Configuration
Figure 7. AD5242 Pin Configuration
Table 5. AD5241 Pin Function Descriptions
Table 6. AD5242 Pin Function Descriptions
Pin No.
Mnemonic
Description
Pin No.
Mnemonic
Description
1
2
3
4
A1
W1
B1
VDD
5
SHDN
Resistor Terminal A1.
Wiper Terminal W1.
Resistor Terminal B1.
Positive Power Supply, Specified for Operation
from 2.2 V to 5.5 V.
Active low, asynchronous connection of Wiper W
to Terminal B, and open circuit of Terminal A.
RDAC register contents unchanged. SHDN should
tie to VDD if not used.
Serial Clock Input.
Serial Data Input/Output.
Programmable Address Bit for Multiple Package
Decoding. Bit AD0 and Bit AD1 provide four
possible addresses.
Programmable Address Bit for Multiple Package
Decoding. Bit AD0 and Bit AD1 provide four
possible addresses.
Common Ground.
Negative Power Supply, Specified for Operation
from 0 V to −2.7 V.
Logic Output Terminal O2.
No Connect.
Logic Output Terminal O1.
1
2
3
4
5
O1
A1
W1
B1
VDD
6
SHDN
7
8
9
SCL
SDA
AD0
10
AD1
11
12
DGND
VSS
13
14
15
16
O2
B2
W2
A2
Logic Output Terminal O1.
Resistor Terminal A1.
Wiper Terminal W1.
Resistor Terminal B1.
Positive Power Supply, Specified for Operation
from 2.2 V to 5.5 V.
Active Low, Asynchronous Connection of Wiper W
to Terminal B, and Open Circuit of Terminal A.
RDAC register contents unchanged. SHDN should
tie to VDD, if not used.
Serial Clock Input.
Serial Data Input/Output.
Programmable Address Bit for Multiple Package
Decoding. Bit AD0 and Bit AD1 provide four
possible addresses.
Programmable Address Bit for Multiple Package
Decoding. Bit AD0 and Bit AD1 provide four
possible addresses.
Common Ground.
Negative Power Supply, Specified for Operation
from 0 V to −2.7 V.
Logic Output Terminal O2.
Resistor Terminal B2.
Wiper Terminal W2.
Resistor Terminal A2.
6
7
8
SCL
SDA
AD0
9
AD1
10
11
DGND
VSS
12
13
14
O2
NC
O1
analog.com
Rev. E | 7 of 17
Data Sheet
AD5241/AD5242
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 8. RDNL vs. Code
analog.com
Figure 11. INL vs. Code
Figure 9. RINL vs. Code
Figure 12. Nominal Resistance vs. Temperature
Figure 10. DNL vs. Code
Figure 13. Supply Current vs. Input Logic Voltage
Rev. E | 8 of 17
Data Sheet
AD5241/AD5242
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 14. Shutdown Current vs. Temperature
Figure 15. ΔVWB/ΔT Potentiometer Mode Temperature Coefficient
Figure 16. ΔRWB/ΔT Rheostat Mode Temperature Coefficient
analog.com
Figure 17. Incremental Wiper Contact vs. VDD/VSS
Figure 18. Supply Current vs. Frequency
Figure 19. AD5242 10 k Ω Gain vs. Frequency vs. Code
Rev. E | 9 of 17
Data Sheet
AD5241/AD5242
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 20. AD5242 100 kΩ Gain vs. Frequency vs. Code
analog.com
Figure 21. AD5242 1 MΩ Gain vs. Frequency vs. Code
Rev. E | 10 of 17
Data Sheet
AD5241/AD5242
TEST CIRCUITS
Figure 22 to Figure 30 define the test conditions used in the product specifications table.
Figure 22. Potentiometer Divider Nonlinearity Error (INL, DNL)
Figure 27. Noninverting Gain
Figure 23. Resistor Position Nonlinearity Error(Rheostat Operation; R-INL,
R-DNL)
Figure 28. Gain vs. Frequency
Figure 24. Wiper Resistance
Figure 29. Incremental On Resistance
Figure 25. Power Supply Sensitivity (PSS, PSRR)
Figure 30. Common-Mode Leakage Current
Figure 26. Inverting Gain
analog.com
Rev. E | 11 of 17
Data Sheet
AD5241/AD5242
THEORY OF OPERATION
The AD5241/AD5242 provide a single-/dual-channel, 256-position
digitally controlled variable resistor (VR) device. The terms VR,
RDAC, and programmable resistor are commonly used interchangeably to refer to digital potentiometer.
To program the VR settings, refer to the Digital Interface section.
Both parts have an internal power-on preset that places the wiper in
midscale during power-on that simplifies the fault condition recovery
at power-up. In addition, the shutdown pin (SHDN) of AD5241/
AD5242 places the RDAC in an almost zero power consumption
state where Terminal A is open circuited and Wiper W is connected
to Terminal B, resulting in only leakage current being consumed
in the VR structure. During shutdown, the VR latch contents are
maintained when the RDAC is inactive. When the part returns from
shutdown, the stored VR setting is applied to the RDAC.
The general equation determining the digitally programmed resistance between W and B is
RWB D =
D
256
× RAB + RW
(1)
where:
D is the decimal equivalent of the binary code between 0 and 255,
which is loaded in the 8-bit RDAC register.
RAB is the nominal end-to-end resistance.
RW is the wiper resistance contributed by the on resistance of the
internal switch.
Again, if RAB = 10 kΩ, Terminal A can be either open circuit or tied
to W. Table 7 shows the RWB resistance based on the code set in
the RDAC latch.
Table 7. RWB (D) at Selected Codes for RAB = 10 kΩ
Figure 31. Equivalent RDAC Circuit
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the RDAC between Terminal A and
Terminal B is available in 10 kΩ, 100 kΩ, and 1 MΩ. The final two
or three digits of the part number determine the nominal resistance
value, for example, 10 kΩ = 10, 100 kΩ = 100, and 1 MΩ = 1
M. The nominal resistance (RAB) of the VR has 256 contact points
accessed by the wiper terminal, plus the B terminal contact. The
8-bit data in the RDAC latch is decoded to select one of the 256
possible settings. Assume a 10 kΩ part is used; the first connection
of the wiper starts at the B terminal for Data 0x00. Because
there is a 60 Ω wiper contact resistance, such connection yields
a minimum of 60 Ω resistance between Terminal W and Terminal
B. The second connection is the first tap point that corresponds to
99 Ω (RWB = RAB/256 + RW = 39 + 60) for Data 0x01. The third
connection is the next tap point representing 138 Ω (39 × 2 + 60)
for Data 0x02, and so on. Each LSB data value increase moves
the wiper up the resistor ladder until the last tap point is reached at
10,021 Ω [RAB – 1 LSB + RW].
Figure 31 shows a simplified diagram of the equivalent RDAC
circuit where the last resistor string is not accessed; therefore, there
is 1 LSB less of the nominal resistance at full scale in addition to
the wiper resistance.
analog.com
D (DEC)
RWB (Ω)
Output State
255
128
1
0
10,021
5060
99
60
Full-scale (RWB – 1 LSB + RW)
Midscale
1 LSB
Zero-scale (wiper contact resistance)
Note that in the zero-scale condition, a finite wiper resistance of 60
Ω is present. Care should be taken to limit the current flow between
W and B in this state to a maximum current of no more than 20 mA.
Otherwise, degradation or possible destruction of the internal switch
contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between Wiper W and Terminal A also produces a digitally
controlled resistance, RWA. When these terminals are used, Terminal B can be opened or tied to the wiper terminal. The minimum
RWA resistance is for Data 0xFF and increases as the data loaded
in the latch decreases in value. The general equation for this
operation is
RWA D =
256 − D
256
× RAB + RW
(2)
For RAB = 10 kΩ, Terminal B can be either open circuit or tied to
W. Table 8 shows the RWA resistance based on the code set in the
RDAC latch.
Table 8. RWA (D) at Selected Codes for RAB = 10 kΩ
D (DEC)
RWA (Ω)
Output State
255
128
1
0
99
5060
10,021
10,060
Full-scale
Midscale
1 LSB
Zero-scale
The typical distribution of the nominal resistance RAB from channel to channel matches within ±1% for AD5242. Device-to-device
matching is process lot dependent, and it is possible to have ±30%
variation. Because the resistance element is processed in thin film
Rev. E | 12 of 17
Data Sheet
AD5241/AD5242
THEORY OF OPERATION
technology, the change in RAB with temperature has no more than a
30 ppm/°C temperature coefficient.
by the state of the AD0 and AD1 pins of the device. AD0 and AD1
allow users to use up to four of these devices on one bus.
PROGRAMMING THE POTENTIOMETER
DIVIDER
The 2-wire, I2C serial bus protocol operates as follows:
Voltage Output Operation
The digital potentiometer easily generates output voltages at wiperto-B and wiper-to-A to be proportional to the input voltage at A-to-B.
Unlike the polarity of VDD /VSS, which must be positive, voltage
across terminal A to terminal B, terminal W to terminal A, and
terminal W to terminal B can be at either polarity provided that VSS
is powered by a negative supply.
If ignoring the effect of the wiper resistance for approximation,
connecting Terminal A to 5 V and Terminal B to ground produces
an output voltage at the wiper-to-B starting at 0 V up to 1 LSB less
than 5 V. Each LSB of voltage is equal to the voltage applied across
Terminal AB divided by the 256 positions of the potentiometer divider. Because AD5241/AD5242 can be supplied by dual supplies,
the general equation defining the output voltage at VW with respect
to ground for any valid input voltage applied to Terminal A and
Terminal B is
VW D =
D
256 VA
VW D =
D
256 VAB
+
256 − D
256 VB
(3)
which can be simplified to
+ VB
(4)
where D is the decimal equivalent of the binary code between 0 to
255 that is loaded in the 8-bit RDAC register.
For a more accurate calculation, including the effects of wiper
resistance, VW can be found as
VW D =
RWB(D)
RAB VA
+
RWA(D)
RAB VB
(5)
where RWB(D) and RWA(D) can be obtained from Equation 1 and
Equation 2.
Operation of the digital potentiometer in divider mode results in a
more accurate operation over temperature. Unlike rheostat mode,
the output voltage is dependent on the ratio of the internal resistors,
RWA and RWB, and not the absolute values; therefore, the temperature drift reduces to 5 ppm/°C.
DIGITAL INTERFACE
2-Wire Serial Bus
The AD5241/AD5242 are controlled via an I2C-compatible serial
bus. The RDACs are connected to this bus as slave devices.
Referring to Figure 3 and Figure 4, the first byte of AD5241/AD5242
is a slave address byte. It has a 7-bit slave address and an R/ bit.
The five MSBs are 01011 and the following two bits are determined
analog.com
1. The master initiates a data transfer by establishing a start
condition, which is when a high-to-low transition on the SDA
line occurs while SCL is high (see Figure 4). The following
byte is the Frame 1, slave address byte, which consists of the
7-bit slave address followed by an R/W bit (this bit determines
whether data is read from or written to the slave device).
2. The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth
clock pulse (this is the acknowledge bit). At this stage, all other
devices on the bus remain idle while the selected device waits
for data to be written to or read from its serial register. If the
R/W bit is high, the master reads from the slave device. If the
R/W bit is low, the master writes to the slave device.
3. A write operation contains an extra instruction byte more than
the read operation. The Frame 2 instruction byte in write mode
follows the slave address byte. The MSB of the instruction
byte labeled A/B is the RDAC subaddress select. A low selects RDAC1 and a high selects RDAC2 for the dual-channel
AD5242. Set A/B to low for the AD5241. The second MSB, RS,
is the midscale reset. A logic high of this bit moves the wiper
of a selected RDAC to the center tap where RWA = RWB. The
third MSB, SD, is a shutdown bit. A logic high on SD causes the
RDAC to open circuit at Terminal A while shorting the wiper to
Terminal B. This operation yields almost a 0 Ω rheostat mode
or 0 V in potentiometer mode. This SD bit serves the same
function as the SHDN pin except that the SHDN pin reacts to
active low. The following two bits are O2 and O1. They are extra
programmable logic outputs that users can use to drive other
digital loads, logic gates, LED drivers, analog switches, and the
like. The three LSBs are don’t care (see Figure 4).
4. After acknowledging the instruction byte, the last byte in write
mode is the, Frame 3 data byte. Data is transmitted over the
serial bus in sequences of nine clock pulses (eight data bits
followed by an acknowledge bit). The transitions on the SDA
line must occur during the low period of SCL and remain stable
during the high period of SCL (see Figure 4).
5. Unlike the write mode, the data byte follows immediately after
the acknowledgment of the slave address byte in Frame 2 read
mode. Data is transmitted over the serial bus in sequences of
nine clock pulses (slightly different from the write mode, there
are eight data bits followed by a no acknowledge Logic 1 bit
in read mode). Similarly, the transitions on the SDA line must
occur during the low period of SCL and remain stable during the
high period of SCL (see Figure 5).
6. When all data bits have been read or written, a stop condition
is established by the master. A stop condition is defined as a
low-to-high transition on the SDA line while SCL is high. In write
mode, the master pulls the SDA line high during the tenth clock
pulse to establish a stop condition (see Figure 4). In read mode,
Rev. E | 13 of 17
Data Sheet
AD5241/AD5242
THEORY OF OPERATION
the master issues a no acknowledge for the ninth clock pulse
(that is, the SDA line remains high). The master then brings the
SDA line low before the tenth clock pulse, which goes high to
establish a stop condition (see Figure 5).
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and instructing
the part only once. During the write cycle, each data byte updates
the RDAC output. For example, after the RDAC has acknowledged
its slave address and instruction bytes, the RDAC output is updated. If another byte is written to the RDAC while it is still addressed
to a specific slave device with the same instruction, this byte updates the output of the selected slave device. If different instructions
are needed, the write mode has to start a completely new sequence
with a new slave address, instruction, and data bytes transferred
again. Similarly, a repeated read function of the RDAC is also
allowed.
LEVEL-SHIFT FOR BIDIRECTIONAL
INTERFACE
While most old systems can operate at one voltage, a new component may be optimized at another. When they operate the same
signal at two different voltages, a proper method of level-shifting is
needed. For instance, a 3.3 V E2PROM can be used to interface
with a 5 V digital potentiometer. A level-shift scheme is needed
to enable a bidirectional communication so that the setting of
the digital potentiometer can be stored to and retrieved from the
E2PROM. Figure 33 shows one of the techniques. M1 and M2 can
be N-channel FETs (2N7002) or low threshold FDV301N if VDD falls
below 2.5 V.
READBACK RDAC VALUE
Specific to the AD5242 dual-channel device, the channel of interest
is the one that was previously selected in the write mode. In
addition, to read both RDAC values consecutively, users have to
perform two write-read cycles. For example, users may first specify
the RDAC1 subaddress in write mode (it is not necessary to issue
the data byte and stop condition), and then change to read mode
to read the RDAC1 value. To continue reading the RDAC2 value,
users have to switch back to write mode, specify the subaddress,
and then switch once again to read mode to read the RDAC2 value.
It is not necessary to issue the write mode data byte or the first
stop condition for this operation. Users should refer to Figure 4 and
Figure 5 for the programming format.
MULTIPLE DEVICES ON ONE BUS
Figure 32 shows four AD5242 devices on the same serial bus.
Each has a different slave address because the state of their AD0
and AD1 pins are different. This allows each RDAC within each
device to be written to or read from independently. The master
device output bus line drivers are open-drain pull-downs in a fully
I2C-compatible interface. Note, a device is addressed properly only
if the bit information of AD0 and AD1 in the slave address byte
matches with the logic inputs at the AD0 and AD1 pins of that
particular device.
Figure 33. Level-Shift for Different Voltage Devices Operation
ADDITIONAL PROGRAMMABLE LOGIC
OUTPUT
The AD5241/AD5242 feature additional programmable logic outputs, O1 and O2, that can be used to drive digital load, analog
switches, and logic gates. They can also be used as a self-contained shutdown preset to Logic 0 that is further explained in the
Shutdown Function section. O1 and O2 default to Logic 0 during
power-up. The logic states of O1 and O2 can be programmed in
Frame 2 under the write mode (see Figure 4). Figure 34 shows
the output stage of O1, which employs large P-channel and N-channel MOSFETs in push-pull configuration. As shown in Figure 34,
the output is equal to VDD or VSS, and these logic outputs have
adequate current driving capability to drive milliamperes of load.
Figure 34. Output Stage of Logic Output, O1
Users can also activate O1 and O2 in the following three different
ways without affecting the wiper settings:
Figure 32. Multiple AD5242 Devices on One Bus
analog.com
1. Start, slave address byte, acknowledge, instruction byte with O1
and O2 specified, acknowledge, stop.
2. Complete the write cycle with stop, then start, slave address
byte, acknowledge, instruction byte with O1 and O2 specified,
acknowledge, stop.
3. Do not complete the write cycle by not issuing the stop, then
start, slave address byte, acknowledge, instruction byte with O1
and O2 specified, acknowledge, stop.
Rev. E | 14 of 17
Data Sheet
AD5241/AD5242
THEORY OF OPERATION
All digital inputs are protected with a series input resistor and the
parallel Zener ESD structures shown in Figure 36. This applies to
the digital input pins, SDA, SCL, and SHDN.
SHUTDOWN FUNCTION
Shutdown can be activated by strobing the SHDN pin or programming the SD bit in the write mode instruction byte (see Table 3). If
the RDAC Register 1 or RDAC Register 2 (AD5242 only) is placed
in shutdown mode by the software, SD bit, the part returns the
wiper to its prior position when a new command is received.
In addition, shutdown can be implemented with the device digital
output, as shown in Figure 35. In this configuration, the device is
shutdown during power-up but users are allowed to program the
device. Thus, when O1 is programmed high, the device exits shutdown mode and responds to the new setting. This self-contained
shutdown function allows absolute shutdown during power-up,
which is crucial in hazardous environments, and it does not add
extra components.
analog.com
Figure 35. Shutdown by Internal Logic Output, O1
Figure 36. ESD Protection of Digital Pins
Figure 37. ESD Protection of Resistor Terminals
Rev. E | 15 of 17
Data Sheet
AD5241/AD5242
OUTLINE DIMENSIONS
Figure 38. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
Figure 39. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in milimeters and inches
Figure 40. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
analog.com
Rev. E | 16 of 17
Data Sheet
AD5241/AD5242
OUTLINE DIMENSIONS
Figure 41. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-16)
Dimensions shown in millimeters and inches
Updated: October 05, 2021
ORDERING GUIDE
Model1
Temperature Range
Package Description
Packing Quantity
Package
Option
AD5241BRUZ10
AD5241BRUZ100
AD5241BRUZ100-R7
AD5241BRUZ10-R7
AD5241BRZ10
AD5241BRZ100
AD5241BRZ10-RL7
AD5241BRZ1M
AD5241BRZ1M-REEL
AD5242BRUZ10
AD5242BRUZ100
AD5242BRUZ100-RL7
AD5242BRUZ10-RL7
AD5242BRUZ1M
AD5242BRUZ1M-REEL7
AD5242BRZ10
AD5242BRZ100
AD5242BRZ100-REEL7
AD5242BRZ10-REEL7
AD5242BRZ1M
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead SOIC
14-Lead SOIC
14-Lead SOIC
14-Lead SOIC
14-Lead SOIC
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead SOIC
16-Lead SOIC
16-Lead SOIC
16-Lead SOIC
16-Lead SOIC
Tube, 96
Tube, 96
Reel, 1000
Reel, 1000
Tube, 56
Tube, 56
Reel, 1000
Tube, 56
Reel, 2500
Tube, 96
Tube, 96
Reel, 1000
Reel, 1000
Tube, 96
Reel, 1000
Tube, 48
Tube, 48
Reel, 1000
Reel, 1000
Tube, 48
RU-14
RU-14
RU-14
RU-14
R-14
R-14
R-14
R-14
R-14
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
R-16
R-16
R-16
R-16
R-16
1
Z = RoHS Compliant Part.
EVALUATION BOARDS
Model1
Package Description
EVAL-AD5242DBZ
Evaluation Board
1
Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2001-2022 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887-2356, U.S.A.
Rev. E | 17 of 17
工商网监
湘ICP备2023018690号
