Dual 256-Position I2C Compatible Digital Potentiometer AD5243/AD5248
FEATURES
2-channel, 256-position End-to-end resistance: 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ Compact MSOP-10 (3 mm × 4.9 mm) package Fast settling time: tS = 5 µs typ on power-up Full read/write of wiper register Power-on preset to midscale Extra package address decode pins AD0 and AD1 (AD5248 only) Computer software replaces µC in factory programming applications Single supply: 2.7 V to 5.5 V Low temperature coefficient: 35 ppm/°C Low power: IDD = 6 µA max Wide operating temperature: −40°C to +125°C Evaluation board available
FUNCTIONAL BLOCK DIAGRAMS
A1 W1 B1 A2 W2 B2
VDD WIPER REGISTER 1 GND WIPER REGISTER 2
AD5243
SDA SCL PC INTERFACE
04109-0-001
Figure 1. AD5243
W1 B1 W2 B2
APPLICATIONS
Systems calibrations Electronics level settings Mechanical Trimmers® replacement in new designs Permanent factory PCB setting Transducer adjustment of pressure, temperature, position, chemical, and optical sensors RF amplifier biasing Automotive electronics adjustment Gain control and offset adjustment
VDD RDAC REGISTER 1 GND RDAC REGISTER 2
AD0 AD1 SDA SCL
ADDRESS DECODE
/8
SERIAL INPUT REGISTER
AD5248
04109-0-002
Figure 2. AD5248
GENERAL DESCRIPTION
The AD5243 and AD5248 provide a compact 3 mm × 4.9 mm packaged solution for dual 256-position adjustment applications. These devices perform the same electronic adjustment function as a 3-terminal mechanical potentiometer (AD5243) or a 2-terminal variable resistor (AD5248). Available in four different end-to-end resistance values (2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ), these low temperature coefficient devices are ideal for high accuracy and stability variable resistance adjustments. The wiper settings are controllable through the I2C compatible digital interface. The AD5248 has extra package address decode pins AD0 and AD1, allowing multiple parts to share the same I2C 2-wire bus on a PCB. The resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the RDAC latch.1 Operating from a 2.7 V to 5.5 V power supply and consuming less than 6 µA allows for usage in portable batter y-operated applications. For applications that program the AD5243/AD5258 at the factor y, Analog Devices offers device programming software running on Windows® NT/2000/XP operating systems. This software effectively replaces any external I2C controllers, which in turn enhances users’ systems time-to-market. An AD5243/ AD5248 evaluation kit and software are available. The kit includes a cable and instruction manual.
1
The terms digital potentiometer, VR, and RDAC are used interchangeably.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
AD5243/AD5248 TABLE OF CONTENTS
Electrical Characteristics—2.5 kΩ Version ................................... 3 Electrical Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions ....... 4 Timing Characteristics—All Versions ........................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution .................................................................................. 6 Pin Configurations and Function Descriptions ........................... 7 Typical Performance Characteristics ............................................. 8 Test Circuits ..................................................................................... 12 Theory of Operation ...................................................................... 13 Programming the Variable Resistor and Voltage.................... 13 Programming the Potentiometer Divider ............................... 14 ESD Protection ........................................................................... 14 Terminal Voltage Operating Range .......................................... 14 Power-Up Sequence ................................................................... 14 Layout and Power Supply Bypassing ....................................... 14 Constant Bias to Retain Resistance Setting............................. 15 Evaluation Board ........................................................................ 15 I2C Interface .................................................................................... 16 I2C Compatible 2-Wire Serial Bus ........................................... 16 Outline Dimensions ....................................................................... 19 Ordering Guide .......................................................................... 19
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 20
AD5243/AD5248 ELECTRICAL CHARACTERISTICS—2.5 kΩ VERSION
VDD = 5 V ± 10%, or 3 V ± 10%; VA = +VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted. Table 1.
Parameter Symbol Conditions DC CHARACTERISTICS—RHEOSTAT MODE Resistor Differential Nonlinearity2 R-DNL RWB, VA = no connect Resistor Integral Nonlinearity2 R-INL RWB, VA = no connect Nominal Resistor Tolerance3 TA = 25°C ∆RAB Resistance Temperature Coefficient (∆RAB/RAB )/∆T VAB = VDD, wiper = no connect RWB (Wiper Resistance) RWB Code = 0x00, VDD = 5 V DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs) Differential Nonlinearity4 DNL Integral Nonlinearity INL Code = 0x80 (∆VW/VW)/∆T Voltage Divider Temperature Coefficient Full-Scale Error VWFSE Code = 0xFF Zero-Scale Error VWZSE Code = 0x00 RESISTOR TERMINALS Voltage Range5 VA, VB, VW 6 Capacitance A, B CA, CB f = 1 MHz, measured to GND, Code = 0x80 Capacitance6 W CW f = 1 MHz, measured to GND, Code = 0x80 Shutdown Supply Current7 IA_SD VDD = 5.5 V Common-Mode Leakage ICM VA = VB = VDD/2 DIGITAL INPUTS AND OUTPUTS Input Logic High VIH VDD = 5 V Input Logic Low VIL VDD = 5 V Input Logic High VIH VDD = 3 V Input Logic Low VIL VDD = 3 V Input Current IIL VIN = 0 V or 5 V Input Capacitance6 CIL POWER SUPPLIES Power Supply Range VDD RANGE Supply Current IDD VIH = 5 V or VIL = 0 V Power Dissipation8 PDISS VIH = 5 V or VIL = 0 V, VDD = 5 V Power Supply Sensitivity PSS VDD = 5 V ± 10%, Code = midscale 9 DYNAMIC CHARACTERISTICS Bandwidth −3 dB BW_2.5 K Code = 0x80 Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V, f = 1 kHz VW Settling Time tS VA = 5 V, VB = 0 V, ±1 LSB error band Resistor Noise Voltage Density eN_WB RWB = 1.25 kΩ, RS = 0
See notes at end of section.
Min −2 −6 −20
Typ1 ±0.1 ±0.75 35 160
Max +2 +6 +55 200 +1.5 +2
Unit LSB LSB % ppm/°C Ω LSB LSB ppm/°C LSB LSB V pF pF µA nA V V V V µA pF V µA µW %/% MHz % µs nV/√Hz
−1.5 −2
±0.1 ±0.6 15 −2.5 2
−10 0 GND
0 10 VDD
45 60 0.01 1 2.4
1
0.8 2.1 0.6 ±1 5 2.7 3.5 ±0.02 4.8 0.1 1 3.2 5.5 6 30 ±0.08
Rev. 0 | Page 3 of 20
AD5243/AD5248 ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS
VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < 125°C; unless otherwise noted. Table 2.
Parameter Symbol Conditions DC CHARACTERISTICS—RHEOSTAT MODE Resistor Differential Nonlinearity2 R-DNL RWB, VA = no connect Resistor Integral Nonlinearity2 R-INL RWB, VA = no connect Nominal Resistor Tolerance3 TA = 25°C ∆RAB Resistance Temperature Coefficient (∆RAB/RAB )/∆T VAB = VDD, wiper = no connect RWB (Wiper Resistance) RWB Code = 0x00, VDD =5 V DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs) Differential Nonlinearity4 DNL Integral Nonlinearity4 INL Code = 0x80 (∆VW/VW)/∆T Voltage Divider Temperature Coefficient Full-Scale Error VWFSE Code = 0xFF Zero-Scale Error VWZSE Code = 0x00 RESISTOR TERMINALS Voltage Range5 VA, VB, VW 6 Capacitance A, B CA, CB f = 1 MHz, measured to GND, Code = 0x80 Capacitance6 W CW f = 1 MHz, measured to GND, Code = 0x80 Shutdown Supply Current7 IA_SD VDD = 5.5 V Common-Mode Leakage ICM VA = VB = VDD/2 DIGITAL INPUTS AND OUTPUTS Input Logic High VIH VDD = 5 V Input Logic Low VIL VDD = 5 V Input Logic High VIH VDD = 3 V Input Logic Low VIL VDD = 3 V Input Current IIL VIN = 0 V or 5 V Input Capacitance CIL POWER SUPPLIES Power Supply Range VDD RANGE Supply Current IDD VIH = 5 V or VIL = 0 V Power Dissipation PDISS VIH = 5 V or VIL = 0 V, VDD = 5 V Power Supply Sensitivity PSS VDD = 5 V ± 10%, Code = midscale DYNAMIC CHARACTERISTICS Bandwidth −3 dB Total Harmonic Distortion VW Settling Time (10 kΩ/50 kΩ/100 kΩ) Resistor Noise Voltage Density
See notes at end of section.
Min −1 −2.5 −20
Typ1 ±0.1 ±0.25 35 160
Max +1 +2.5 +20 200 +1 +1
Unit LSB LSB % ppm/°C Ω LSB LSB ppm/°C LSB LSB V pF pF µA nA V V V V µA pF V µA µW %/%
−1 −1
±0.1 ±0.3 15 −1 1
−2.5 0 GND
0 2.5 VDD
45 60 0.01 1 2.4
1
0.8 2.1 0.6 ±1 5 2.7 3.5 ±0.02 5.5 6 30 ±0.0 8
BW THDW tS eN_WB
RAB = 10 kΩ/50 kΩ/100 kΩ, Code = 0x80 VA = 1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 kΩ VA = 5 V, VB = 0 V, ±1 LSB error band RWB = 5 kΩ, RS = 0
600/100/4 0 0.1 2 9
kHz % µs nV/√Hz
Rev. 0 | Page 4 of 20
AD5243/AD5248 TIMING CHARACTERISTICS—ALL VERSIONS
VDD = 5V ± 10%, or 3V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted. Table 3.
Parameter Symbol Conditions I2C INTERFACE TIMING CHARACTERISTICS10 (Specifications Apply to All Parts) SCL Clock Frequency fSCL tBUF Bus Free Time between STOP and START t1 tHD;STA Hold Time (Repeated START) t2 After this period, the first clock pulse is generated. tLOW Low Period of SCL Clock t3 tHIGH High Period of SCL Clock t4 tSU;STA Setup Time for Repeated START Condition t5 tHD;DAT Data Hold Time11 t6 tSU;DAT Data Setup Time t7 tF Fall Time of Both SDA and SCL Signals t8 tR Rise Time of Both SDA and SCL Signals t9 tSU;STO Setup Time for STOP Condition t10
See notes at end of section.
Min 0 1.3 0.6 1.3 0.6 0.6
Typ1
Max 400
Unit kHz µs µs µs µs µs µs ns ns ns µs
0.9 100 300 300 0.6
NOTES
1 2
Typical specifications represent average readings at 25°C and VDD = 5 V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 VAB = VDD, wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor terminals A, B, W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 Measured at the A terminal. The A terminal is open circuited in shutdown mode. 8 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 9 All dynamic characteristics use VDD = 5 V. 10 See timing diagrams for locations of measured values. 11 The maximum tHD:DAT must be met only if the device does not stretch the low period (tLOW) of the SCL signal.
Rev. 0 | Page 5 of 20
AD5243/AD5248 ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless other wise noted. Table 4.
Parameter VDD to GND VA, VB, VW to GND Terminal Current, Ax to Bx, Ax to Wx, Bx to Wx1 Pulsed Continuous Digital Inputs and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJMAX) Storage Temperature Lead Temperature (Soldering, 10 sec) Thermal Resistance2 θJA: MSOP-10
1
Value –0.3 V to +7 V VDD ±20 mA ±5 mA 0 V to 7 V –40°C to +125°C 150°C –65°C to +150°C 300°C 230°C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only ; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Package power dissipation = (TJMAX − TA)/θJA.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 6 of 20
AD5243/AD5248 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
B1 1 A1 2 W2 3 GND 4 VDD 5
10 9
W1 B2 A2
04109-0-027
B1 1 AD0 2 W2 3 GND 4 VDD 5
10 9
W1 B2 AD1
04109-0-028
AD5243
TOP VIEW
8 7 6
AD5248
TOP VIEW
8 7 6
SDA SCL
SDA SCL
Figure 3. AD5243 Pin Configuration
Figure 4. AD5248 Pin Configuration
Table 5. AD5243 Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 Mnemonic B1 A1 W2 GND VDD SCL SDA A2 B2 W1 Description B1 Terminal. A1 Terminal. W2 Terminal. Digital Ground. Positive Power Supply. Serial Clock Input. Positive edge triggered. Serial Data Input/Output. A2 Terminal. B2 Terminal. W1 Terminal.
Table 6. AD5248 Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 Mnemonic B1 AD0 W2 GND VDD SCL SDA AD1 B2 W1 Description B1 Terminal. Programmable Address Bit 0 for Multiple Package Decoding. W2 Terminal. Digital Ground. Positive Power Supply. Serial Clock Input. Positive edge triggered. Serial Data Input/Output. Programmable Address Bit 1 for Multiple Package Decoding. B2 Terminal. W1 Terminal.
Rev. 0 | Page 7 of 20
AD5243/AD5248 TYPICAL PERFORMANCE CHARACTERISTICS
2.0 1.5
RHEOSTAT MODE INL (LSB)
0.5
TA = 25°C RAB = 10kΩ
POTENTIOMETER MODE DNL (LSB)
0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4
04109-0-030
RAB = 10kΩ
1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 32 64
VDD = 2.7V
VDD = 2.7V; TA = –40°C, +25°C, +85°C, +125°C
VDD = 5.5V
96
128
160
192
224
256
0
32
64
96
128
160
192
224
256
CODE (DECIMAL)
CODE (DECIMAL)
Figure 5. R-INL vs. Code vs. Supply Voltages
Figure 8. DNL vs. Code vs. Temperature
0.5 0.4 TA = 25°C RAB = 10kΩ
1.0 0.8 TA = 25°C RAB = 10kΩ
RHEOSTAT MODE DNL (LSB)
0.3 0.2 VDD = 2.7V 0.1 0 –0.1 –0.2 –0.3 –0.4
04109-0-031
POTENTIOMETER MODE INL (LSB)
0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 VDD = 2.7V VDD = 5.5V
VDD = 5.5V
0
32
64
96
128
160
192
224
256
0
32
64
96
128
160
192
224
256
CODE (DECIMAL)
CODE (DECIMAL)
Figure 6. R-DNL vs. Code vs. Supply Voltages
Figure 9. INL vs. Code vs. Supply Voltages
0.5 0.4 RAB = 10kΩ
0.5 0.4 TA = 25°C RAB = 10kΩ
0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4
POTENTIOMETER MODE DNL (LSB)
POTENTIOMETER MODE INL (LSB)
VDD = 5.5V TA = –40°C, +25°C, +85°C, +125°C
0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 VDD = 5.5V VDD = 2.7V
VDD = 2.7V TA = –40°C, +25°C, +85°C, +125°C
04109-0-032
0
32
64
96
128
160
192
224
256
0
32
64
96
128
160
192
224
256
CODE (DECIMAL)
CODE (DECIMAL)
Figure 7. INL vs. Code vs. Temperature
Figure 10. DNL vs. Code vs. Supply Voltages
Rev. 0 | Page 8 of 20
04109-0-035
–0.5
–0.5
04109-0-034
–0.5
–1.0
04109-0-033
–0.5
AD5243/AD5248
2.0 RAB = 10kΩ 1.5 VDD = 2.7V TA = –40°C, +25°C, +85°C, +125°C 4.50 RAB = 10kΩ
1.0 0.5 0 –0.5 –1.0 –1.5
04109-0-036
ZSE, ZERO-SCALE ERROR (LSB)
3.75
RHEOSTAT MODE INL (LSB)
3.00
2.25
VDD = 2.7V, VA = 2.7V
VDD = 5.5V TA = –40°C, +25°C, +85°C, +125°C
1.50 VDD = 5.5V, VA = 5.0V 0.75
0
32
64
96
128
160
192
224
256
–25
–10
5
20
35
50
65
80
95
110
125
CODE (DECIMAL)
TEMPERATURE (°C)
Figure 11. R-INL vs. Code vs. Temperature
Figure 14. Zero-Scale Error vs. Temperature
0.5 0.4 RAB = 10kΩ
10
RHEOSTAT MODE DNL (LSB)
0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 0 32 64 96 128 160 192 224 256
04109-0-037
VDD = 2.7V, 5.5V; TA = –40°C, +25°C, +85°C, +125°C
IDD, SUPPLY CURRENT (µA)
VDD = 5V
1 VDD = 3V
–7
26
59
92
125
CODE (DECIMAL)
TEMPERATURE (°C)
Figure 12. R-DNL vs. Code vs. Temperature
Figure 15. Supply Current vs. Temperature
2.0 RAB = 10kΩ
120 RAB = 10kΩ
1.0 0.5 0 –0.5 –1.0 –1.5
04109-0-038
RHEOSTAT MODE TEMPCO (ppm/°C)
1.5
100
FSE, FULL-SCALE ERROR (LSB)
80 60 VDD = 2.7V TA = –40°C TO +85°C, –40°C TO +125°C VDD = 5.5V TA = –40°C TO +85°C, –40°C TO +125°C
VDD = 5.5V, VA = 5.0V
40
VDD = 2.7V, VA = 2.7V
20
0 –20 0 32 64 96 128 160 192 224 256 CODE (DECIMAL)
–25
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
Figure 13. Full-Scale Error vs. Temperature
Figure 16. Rheostat Mode Tempco ∆RWB/∆T vs. Code
Rev. 0 | Page 9 of 20
04109-0-041
–2.0 –40
04109-0-040
–0.5
0.1 –40
04109-0-039
–2.0
0 –40
AD5243/AD5248
50
0
RAB = 10kΩ
POTENTIOMETER MODE TEMPCO (ppm/°C)
40 30 20 10 0 –10 –20
04109-0-042
–6 –12
0x80 0x40 0x20 0x10 0x08 0x04 0x02
VDD = 2.7V TA = –40°C TO +85°C, –40°C TO +125°C
–18
GAIN (dB)
–24 –30 –36 –42
VDD = 5.5V TA = –40°C TO +85°C, –40°C TO +125°C
0x01 –48 –54
0
32
64
96
128
160
192
224
256
1k
10k
100k FREQUENCY (Hz)
1M
CODE (DECIMAL)
Figure 17. Potentiometer Mode Tempco ∆VWB/∆T vs. Code
Figure 20. Gain vs. Frequency vs. Code, RAB = 50 kΩ
0 –6 –12 –18
GAIN (dB)
0 0x80 –6 0x40 –12 0x20 0x10
GAIN (dB)
0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01
–18 –24 –30 –36 –42 –48 –54
04109-0-043
–24 –30 –36 –42 –48 –54 –60 10k
0x08 0x04
0x02 0x01
100k FREQUENCY (Hz)
1M
10M
1k
10k
100k FREQUENCY (Hz)
1M
Figure 18. Gain vs. Frequency vs. Code, RAB = 2.5 kΩ
Figure 21. Gain vs. Frequency vs. Code, RAB = 100 kΩ
0 –6 –12 –18
GAIN (dB)
0 0x80 0x40 0x20 0x10
GAIN (dB)
–6 –12 –18 –24 –30 –36 –42 –48 –54
04109-0-044
100kΩ 60kHz
–24 –30
50kΩ 120kHz 10kΩ 570kHz 2.5kΩ 2.2MHz
0x08 0x04 –36 –42 –48 –54 –60 1k 10k 100k FREQUENCY (Hz) 1M 0x02 0x01
1k
10k
100k FREQUENCY (Hz)
1M
10M
Figure 19. Gain vs. Frequency vs. Code, RAB = 10 kΩ
Figure 22. –3 dB Bandwidth @ Code = 0x80
Rev. 0 | Page 10 of 20
04109-0-047
–60
04109-0-046
–60
04109-0-045
–30
–60
AD5243/AD5248
10 TA = 25°C
IDD, SUPPLY CURRENT (mA)
1 VDD = 5.5V
VW2
0.1 VDD = 2.7V
VW1
04109-0-052 04109-0-051
0.01 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 DIGITAL INPUT VOLTAGE (V)
Figure 23. IDD vs. Input Voltage
Figure 26. Analog Crosstalk
VW
VW
SCL
04109-0-048 04109-0-053
Figure 24. Digital Feedthrough
Figure 27. Midscale Glitch, Code 0x80 to 0x7F
VW2
VW
VW1
04109-0-049
SCL
04109-0-050
Figure 25. Digital Crosstalk
Figure 28. Large Signal Settling Time
Rev. 0 | Page 11 of 20
AD5243/AD5248 TEST CIRCUITS
Figure 29 through Figure 35 illustrate the test circuits that define the test conditions used in the product specification tables.
DUT A V+ B W
V+ = VDD 1LSB = V+/2N
DUT A VIN B W
+15V
AD8610
VOUT
04109-0-009
VMS
04109-0-003
OFFSET GND 2.5V
–15V
Figure 29. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)
NO CONNECT DUT AW B VMS
04109-0-004
Figure 33. Test Circuit for Gain vs. Frequency
DUT
RSW =
0.1V ISW
IW
B
W ISW
CODE = 0x00 0.1V
04109-0-010
VSS TO VDD
Figure 30. Test Circuit for Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)
DUT A VMS2 B VMS1 W VW
RW = [VMS1 – VMS2]/IW IW = VDD/RNOMINAL
Figure 34. Test Circuit for Incremental On Resistance
NC DUT VDD
04109-0-005
A W GND B
ICM
NC
NC = NO CONNECT
Figure 31. Test Circuit for Wiper Resistance
VA V+ = VDD ± 10%
Figure 35. Test Circuit for Common-Mode Leakage Current
DUT
∆VDD
A W B
V+
∆VMS PSRR (dB) = 20 LOG ∆VDD ∆VMS% PSS (%/%) = ∆VDD%
(
)
04109-0-006
VMS
Figure 32. Test Circuit for Power Supply Sensitivity(PSS, PSSR)
Rev. 0 | Page 12 of 20
04109-0-011
VCM
AD5243/AD5248 THEORY OF OPERATION
The AD5243/AD5248 are 256-position digitally controlled variable resistor (VR) devices. An internal power-on preset places the wiper at midscale during power-on, which simplifies the fault condition recover y at power-up. The general equation determining the digitally programmed output resistance between W and B is
RWB (D ) = D × RAB + 2 × RW 256
(1)
where: D is the decimal equivalent of the binar y code loaded in the 8-bit RDAC register. RAB is the end-to-end resistance. RW is the wiper resistance contributed by the on resistance of the internal switch. In summar y, if RAB = 10 kΩ and the A terminal is open circuited, the following output resistance RWB is set for the indicated RDAC latch codes. Table 7. Codes and Corresponding RWB Resistance
D (Dec) 255 128 1 0 RWB (Ω) 9,961 5,060 139 100 Output State Full scale (RAB − 1 LSB + RW) Midscale 1 LSB Zero scale (wiper contact resistance)
PROGRAMMING THE VARIABLE RESISTOR AND VOLTAGE
Rheostat Operation
The nominal resistance of the RDAC between Terminals A and B is available in 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The nominal resistance (RAB) of the VR has 256 contact points accessed by the wiper terminal, plus the B terminal contact. The 8-bit data in the RDAC latch is decoded to select one of the 256 possible settings.
A W A W A W
04109-0-012
B
B
B
Figure 36. Rheostat Mode Configuration
Assuming that a 10 kΩ part is used, the wiper’s first connection starts at the B terminal for data 0x00. Because there is a 50 Ω wiper contact resistance, such a connection yields a minimum of 100 Ω (2 × 50 Ω) resistance between Terminals W and B. The second connection is the first tap point, which corresponds to 139 Ω (RWB = RAB/256 + 2 × RW = 39 Ω + 2 × 50 Ω) for data 0x01. The third connection is the next tap point, representing 178 Ω (2 × 39 Ω + 2 × 50 Ω) for data 0x02, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10,100 Ω (RAB + 2 × RW).
A RS
Note that, in the zero-scale condition, a finite wiper resistance of 100 Ω is present. Care should be taken to limit the current flow between W and B in this state to a maximum pulse current of no more than 20 mA. Other wise, degradation or possible destruction of the internal switch contact can occur. Similar to the mechanical potentiometer, the resistance of the RDAC between the Wiper W and Terminal A also produces a digitally controlled complementar y resistance, RWA. When these terminals are used, the B terminal can be opened. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. The general equation for this operation is
RWA (D ) = 256 − D × RAB + 2 × RW 256
D7 D6 D5 D4 D3 D2 D1 D0
RS
(2)
RS W
For RAB = 10 kΩ and the B terminal open circuited, the following output resistance RWA is set for the indicated RDAC latch codes. Table 8. Codes and Corresponding RWA Resistance
D (Dec) 255 128 1 0 RWA (Ω) 139 5,060 9,961 10,060 Output State Full scale Midscale 1 LSB Zero scale
RDAC LATCH AND DECODER
RS B
04109-0-013
Figure 37. AD5243 Equivalent RDAC Circuit
Rev. 0 | Page 13 of 20
AD5243/AD5248
Typical device-to-device matching is process lot dependent and may var y by up to ±30%. Because the resistance element is processed in thin film technology, the change in RAB with temperature has a ver y low 35 ppm/°C temperature coefficient.
340Ω LOGIC
04109-0-015
GND
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at wiper-to-B and wiper-to-A proportional to the input voltage at A to B. Unlike the polarity of VDD to GND, which must be positive, voltage across A to B, W to A, and W to B can be at either polarity.
VI A W VO
04109-0-014
Figure 39. ESD Protection of Digital Pins
A, B, W
04109-0-016
GND
Figure 40. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5243/AD5248 VDD and GND power supply defines the boundar y conditions for proper 3-terminal digital potentiometer operation. Supply signals present on Terminals A, B, and W that exceed VDD or GND are clamped by the internal for ward biased diodes (see Figure 41).
VDD
B
Figure 38. Potentiometer Mode Configuration
A
If ignoring the effect of the wiper resistance for approximation, connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at the wiper-to-B starting at 0 V up to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage applied across terminal AB divided by the 256 positions of the potentiometer divider. The general equation defining the output voltage at VW with respect to ground for any valid input voltage applied to terminals A and B is
D 256 − D VW (D ) = VA + VB 256 256
W B
04109-0-017
GND
Figure 41. Maximum Terminal Voltages Set by VDD and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance at Terminals A, B, and W (see Figure 41), it is important to power VDD/GND before applying any voltage to Terminals A, B, and W; other wise, the diode is for ward biased such that VDD is powered unintentionally and may affect the rest of the user’s circuit. The ideal power-up sequence is in the following order: GND, VDD, digital inputs, and then VA, VB, and VW. The relative order of powering VA, VB, VW, and the digital inputs is not important as long as they are powered after VDD/GND.
(3)
A more accurate calculation, which includes the effect of wiper resistance, VW, is
VW (D ) = R (D ) RWB (D ) VA + WA VB RAB RAB
(4)
Operation of the digital potentiometer in the divider mode results in a more accurate operation overtemperature. Unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors RWA and RWB and not the absolute values. Therefore, the temperature drift reduces to 15 ppm/°C.
LAYOUT AND POWER SUPPLY BYPASSING
It is good practice to employ compact, minimum lead length layout design. The leads to the inputs should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. Similarly, it is also good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with disk or chip ceramic capacitors of 0.01 µF to 0.1 µF. Low ESR 1 µF to 10 µF tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple (see Figure 42). Note that the digital ground should also be joined remotely to the analog ground at one point to minimize the ground bounce.
ESD PROTECTION
All digital inputs are protected with a series of input resistors and parallel Zener ESD structures, shown in Figure 39 and Figure 40. This applies to the digital input pins SDA, SCL, AD0, and AD1 (AD5248 only).
Rev. 0 | Page 14 of 20
AD5243/AD5248
VDD C3 10µF VDD C1 0.1µF
+
AD5243
GND
04109-0-018
This demonstrates that constantly biasing the potentiometer is not an impractical approach. Most portable devices do not require the removal of batteries for the purpose of charging. Although the resistance setting of the AD5243/AD5248 is lost when the batter y needs replacement, such events occur rather infrequently such that this inconvenience is justified by the lower cost and smaller size offered by the AD5243/AD5248. If and when total power is lost, the user should be provided with a means to adjust the setting accordingly.
Figure 42. Power Supply Bypassing
EVALUATION BOARD
An evaluation board, along with all necessar y software, is available to program the AD5243/AD5248 from any PC running Windows 98/2000/XP. The graphical user interface, as shown in Figure 44, is straightfor ward and easy to use. More detailed information is available in the user manual, which comes with the board.
CONSTANT BIAS TO RETAIN RESISTANCE SETTING
For users who desire nonvolatility but cannot justify the additional cost for the EEMEM, the AD5243/AD5248 may be considered as low cost alternatives by maintaining a constant bias to retain the wiper setting. The AD5243/AD5248 are designed specifically with low power in mind, which allows low power consumption even in batter y-operated systems. The graph in Figure 43 demonstrates the power consumption from a 3.4 V 450 mAhr Li-Ion cell phone batter y, which is connected to the AD5243/AD5248. The measurement over time shows that the device draws approximately 1.3 µA and consumes negligible power. Over a course of 30 days, the batter y is depleted by less than 2%, the majority of which is due to the intrinsic leakage current of the batter y itself.
110% 108% 106%
BATTERY LIFE DEPLETED
TA = 25°C
104% 102% 100% 98% 96% 94% 92% 90% 0 5 10 15 DAYS 20 25 30
04109-0-019
Figure 44. AD5243 Evaluation Board Software
Figure 43. Battery Operating Life Depletion
The AD5243/AD5248 start at midscale upon power-up. To increment or decrement the resistance, the user may simply move the scrollbars on the left. To write any specific value, the user should use the bit pattern in the upper screen and press the Run button. The format of writing data to the device is shown in Table 9. To read the data out from the device, the user can simply press the Read button. The format of the read bits is shown in Table 10.
Rev. 0 | Page 15 of 20
AD5243/AD5248 I2C INTERFACE
I2C COMPATIBLE 2-WIRE SERIAL BUS
The 2-wire I2C serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a START condition, which is when a high-to-low transition on the SDA line occurs while SCL is high (see Figure 46). The following byte is the slave address byte, which consists of the slave address followed by an R/W bit (this bit determines whether data is read from or written to the slave device). The AD5243 has a fixed slave address byte, while the AD5248 has two configurable address bits AD0 and AD1 (see Table 9). The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. If the R/W bit is high, the master reads from the slave device. On the other hand, if the R/W bit is low, the master writes to the slave device. 2. In the write mode, the second byte is the instruction byte. The first bit (MSB) of the instruction byte is the RDAC subaddress select bit. A Logic Low selects Channel 1 and a Logic High selects Channel 2. The second MSB, SD, is a shutdown bit. A logic high causes an open circuit at Terminal A while shorting the wiper to Terminal B. This operation yields almost 0 Ω in rheostat mode or 0 V in potentiometer mode. It is important to note that the shutdown operation does not disturb the contents of the register. When brought out of shutdown, the previous setting is applied to the RDAC. Also, during shutdown, new settings can be programmed. When the part is returned from shutdown, the corresponding VR setting is applied to the RDAC. The remainder of the bits in the instruction byte are don’t care bits (see Table 9). After acknowledging the instruction byte, the last byte in write mode is the data byte. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 46 and Figure 47). 3. In the read mode, the data byte follows immediately after the acknowledgment of the slave address byte. Data is transmitted over the serial bus in sequences of nine clock pulses (a slight difference with the write mode, eight data bits are followed by an acknowledge bit). Similarly, the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 48 and Figure 49). Note that the channel of interest is the one that is previously selected in the write mode. In the case where users need to read the RDAC values of both channels, they need to program the first channel in the write mode and then change to the read mode to read the first channel value. After that, they need to change back to the write mode with the second channel selected and read the second channel value in the read mode again. It is not necessary for users to issue the Frame 3 data byte in the write mode for subsequent readback operation. Users should refer to Figure 48 and Figure 49 for the programming format. 4. After all data bits have been read or written, a STOP condition is established by the master. A STOP condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during the tenth clock pulse to establish a STOP condition (see Figure 46 and Figure 47). In read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the SDA line remains high). The master then brings the SDA line low before the tenth clock pulse, which goes high to establish a STOP condition (see Figure 48 and Figure 49). A repeated write function gives the user flexibility to update the RDAC output a number of times after addressing and instructing the part only once. For example, after the RDAC has acknowledged its slave address and instruction bytes in the write mode, the RDAC output updates on each successive byte. If different instructions are needed, the write/read mode has to start again with a new slave address, instruction, and data byte. Similarly, a repeated read function of the RDAC is also allowed.
Rev. 0 | Page 16 of 20
AD5243/AD5248
Table 9. Write Mode
AD5243
S 0 1 0 1 1 1 1 W A A0 SD X X X X X X A D7 D6 D5 D4 D3 D2 D1 D0 A P Slave Address Byte Instruction Byte Data Byte
AD5248
S 0 1 0 1 1 AD1 AD0 W A A0 SD X X X X X X A D7 D6 D5 D4 D3 D2 D1 D0 A P Slave Address Byte Instruction Byte Data Byte
Table 10. Read Mode
AD5243
S 0 1 0 1 1 1 1 R A D7 D6 D5 D4 D3 Data Byte D2 D1 D0 A P Slave Address Byte
AD5248
S 0 1 0 1 1 AD1 AD0 R A D7 D6 D5 D4 D3 D2 D1 D0 A P Slave Address Byte Data Byte
LEGEND S = Start condition. P = Stop condition. A = Acknowledge. X = Don’t care. W = Write. AD0, AD1 = Package pin programmable address bits.
R = Read. A0 = RDAC subaddress select bit. SD = Shutdown connects wiper to B terminal and open circuits A terminal. It does not change contents of wiper register. D7, D6, D5, D4, D3, D2, D1, D0 = Data bits.
t8
SCL
t6
t9
t2
t2
t3 t8 t9
t4
t7
t5
t10
SDA
t1
P S S P
Figure 45. I2C Interface Detailed Timing Diagram
1 SCL SDA
9
1
9
1
9
ACK BY AD5243 START BY MASTER FRAME 1 SLAVE ADDRESS BYTE FRAME 2 INSTRUCTION BYTE
ACK BY AD5243 FRAME 3 DATA BYTE
ACK BY AD5243
STOP BY MASTER
Figure 46. Writing to the RDAC Register—AD5243
Rev. 0 | Page 17 of 20
04109-0-022
0
1
0
1
1
1
1
R/W
A0
SD
X
X
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
04109-0-021
AD5243/AD5248
1 SCL SDA
04109-0-023
9
1
9
1
9
0
1
0
1
1
AD1 AD0 R/W
A0
SD
X
X
X
X
X
X
D7 ACK BY AD5248
D6
D5
D4
D3
D2
D1
D0 ACK BY AD5248
ACK BY AD5248 START BY MASTER FRAME 1 SLAVE ADDRESS BYTE FRAME 2 INSTRUCTION BYTE
FRAME 3 DATA BYTE
STOP BY MASTER
Figure 47. Writing to the RDAC Register—AD5248
1 SCL SDA 0 1 0 1 1 1 1 R/W
9
1
9
D7 ACK BY AD5243
D6
D5
D4
D3
D2
D1
D0
04109-0-024 04109-0-025
NO ACK BY MASTER FRAME 2 RDAC REGISTER STOP BY MASTER
START BY MASTER
FRAME 1 SLAVE ADDRESS BYTE
Figure 48. Reading Data from a Previously Selected RDAC Register in Write Mode—AD5243
1 SCL SDA 0 1 0 1 1 AD1 AD0 R/W
9
1
9
D7
D6
D5
D4
D3
D2
D1
D0 NO ACK BY MASTER
ACK BY AD5248 START BY MASTER FRAME 1 SLAVE ADDRESS BYTE FRAME 2 RDAC REGISTER
STOP BY MASTER
Figure 49. Reading Data from a Previously Selected RDAC Register in Write Mode—AD5248
Multiple Devices on One Bus (Applies Only to AD5248)
Figure 50 shows four AD5248 devices on the same serial bus. Each has a different slave address, because the states of their AD0 and AD1 pins are different. This allows each device on the bus to be written to or read from independently. The master device output bus line drivers are open-drain pull-downs in a fully I2C compatible interface.
RP RP
5V
SDA MASTER SCL 5V SDA AD1 AD0 SCL SDA AD1 AD0 SCL 5V SDA AD1 AD0 SCL 5V SDA AD1
04109-0-026
SCL
AD0
AD5248
AD5248
AD5248
AD5248
Figure 50. Multiple AD5248 Devices on One I2C Bus
Rev. 0 | Page 18 of 20
AD5243/AD5248 OUTLINE DIMENSIONS
3.00 BSC
10
6
3.00 BSC
1 5
4.90 BSC
PIN 1 0.50 BSC 0.95 0.85 0.75 0.15 0.00 0.27 0.17 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187BA 1.10 MAX 8° 0° 0.80 0.60 0.40
SEATING PLANE
0.23 0.08
Figure 51. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters
ORDERING GUIDE
Model AD5243BRM2.5 AD5243BRM2.5-RL7 AD5243BRM10 AD5243BRM10-RL7 AD5243BRM50 AD5243BRM50-RL7 AD5243BRM100 AD5243BRM100-RL7 AD5243EVAL AD5248BRM2.5 AD5248BRM2.5-RL7 AD5248BRM10 AD5248BRM10-RL7 AD5248BRM50 AD5248BRM50-RL7 AD5248BRM100 AD5248BRM100-RL7 AD5248EVAL
1
RAB 2.5 kΩ 2.5 kΩ 10 kΩ 10 kΩ 50 kΩ 50 kΩ 100 kΩ 100 kΩ See Note 1 2.5 kΩ 2.5 kΩ 10 kΩ 10 kΩ 50 kΩ 50 kΩ 100 kΩ 100 kΩ See Note 1
Temperature −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C
Package Description MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 Evaluation Board MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 Evaluation Board
Package Option RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10
Branding D0L D0L D0M D0M D0N D0N D0P D0P D1F D1F D1G D1G D1H D1H D1J D1J
The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options.
Rev. 0 | Page 19 of 20
AD5243/AD5248 NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04109–0–1/04(0)
Rev. 0 | Page 20 of 20
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