FEATURES
128 positions
End-to-end resistance: 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Ultracompact, SC70-6 (2 mm × 2.1 mm) package
I2C-compatible interface
Full read/write of wiper register
Power-on preset to midscale
Single-supply 2.7 V to 5.5 V
Rheostat mode temperature coefficient: 45 ppm/°C
Low power, IDD = 0.9 µA at 3.3 V typical
Wide operating temperature range: −40°C to +125°C
APPLICATIONS
FUNCTIONAL BLOCK DIAGRAM
VDD
A
SDA
I2C INTERFACE
SCL
W
WIPER
REGISTER
B
03876-001
Data Sheet
128-Position I2C-Compatible
Digital Potentiometer
AD5247
GND
Figure 1.
Mechanical potentiometer replacement in new designs
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier-biasing
LCD brightness and contrast adjustment
Automotive electronics adjustment
Gain control and offset adjustment
GENERAL DESCRIPTION
The AD5247 provides a compact, 2 mm × 2.1 mm, packaged
solution for 128-position adjustment applications. This device
performs the same electronic adjustment function as a mechanical
potentiometer or a variable resistor. Available in four different
end-to-end resistance values (5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ),
these low temperature coefficient devices are ideal for high
accuracy and stability variable resistance adjustments.
The wiper settings are controllable through the I2C-compatible
digital interface, which can also be used to read back the present
wiper register control word. The 10 kΩ and 100 kΩ options each
have three hard-coded slave address options available to allow
users access to three of these devices on one I2C bus (see Table 8
for a full list of slave address locations).
The resistance between the wiper and either end point of
the fixed resistor varies linearly with respect to the digital
code transferred into the RDAC latch. Note the terms digital
potentiometer, VR (variable resistor), and RDAC are used
interchangeably in this document.
Operating from a 2.7 V to 5.5 V power supply and consuming
0.9 µA (3.3 V) allows the AD5247 to be used in portable
battery-operated applications.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2012 Analog Devices, Inc. All rights reserved.
AD5247
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
I2C Interface .................................................................................... 13
Applications ....................................................................................... 1
Theory of Operation ...................................................................... 14
Functional Block Diagram .............................................................. 1
Programming the Variable Resistor ......................................... 14
General Description ......................................................................... 1
Programming the Potentiometer Divider ............................... 15
Revision History ............................................................................... 2
I2C-Compatible 2-Wire Serial Bus ........................................... 15
Specifications..................................................................................... 3
Level Shifting for Bidirectional Interface ................................ 16
Electrical Characteristics—5 kΩ Version .................................. 3
ESD Protection ........................................................................... 16
Electrical Characteristics—10 kΩ, 50 kΩ, and 100 kΩ
Versions.......................................................................................... 4
Terminal Voltage Operating Range ......................................... 16
Timing Characteristics—5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ
Versions.......................................................................................... 5
Power-Up Sequence ................................................................... 16
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Maximum Operating Current .................................................. 16
Layout and Power Supply Bypassing ....................................... 17
Constant Bias to Retain Resistance Setting............................. 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 18
Test Circuits ..................................................................................... 12
REVISION HISTORY
5/12—Rev. E to Rev. F
3/07—Rev. A to Rev. B
Changes to Features and General Description Sections.............. 1
Changes to IDD Parameters, Table 1 ................................................ 3
Changes to IDD Parameters, Table 2 ................................................ 4
Changes to Figure 15 ........................................................................ 9
Changes to Figure 16 ...................................................................... 10
Removed Evaluation Board Section ............................................. 17
Changes to Ordering Guide .......................................................... 18
Changes to General Description Section .......................................1
Added Table 8 ................................................................................. 13
Changes to I2C-Compatible 2-Wire Serial Bus Section ............ 15
Changes to Ordering Guide .......................................................... 18
1/11—Rev. D to Rev. E
Change to Table 1, Added Output Logic Low .............................. 3
Change to Table 2, Added Output Logic Low .............................. 4
7/06—Rev. 0 to Rev. A
Updated Format .................................................................. Universal
Changes to Absolute Maximum Ratings section ..........................6
Changes to Ordering Guide .......................................................... 18
9/03—Revision 0: Initial Version
3/10—Rev. C to Rev. D
Changes to Table 9 and Table 10................................................... 14
10/09—Rev. B to Rev. C
Changes to Zero-Scale Error (10 kΩ) Parameter, Table 2 ........... 4
Changes to Ordering Guide .......................................................... 18
Rev. F | Page 2 of 20
Data Sheet
AD5247
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 kΩ VERSION
VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD, −40°C < TA < +125°C, unless otherwise noted.
Table 1.
Parameter
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient3
Output Resistance
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE
Differential Nonlinearity4
Integral Nonlinearity4
Voltage Divider Temperature Coefficient
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range5
Capacitance A6
Capacitance W6
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Input Current
Input Capacitance6
Output Logic Low (SDA)
POWER SUPPLIES
Power Supply Range
Supply Current
Power Dissipation7
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS6, 8
Bandwidth –3 dB
Total Harmonic Distortion
VW Settling Time
Resistor Noise Voltage Density
Symbol
Conditions
Min
Typ1
Max
Unit
R-DNL
R-INL
∆RAB
∆RAB/∆T
RWB
RWB, VA = no connect
RWB, VA = no connect
−1.5
−4
−30
±0.1
±0.75
+1.5
+4
+30
LSB
LSB
%
ppm/°C
Ω
DNL
INL
∆VW/∆T
VWFSE
VWZSE
VA, VW
CA
CW
ICM
VIH
VIL
VIH
VIL
IIL
CIL
VOL
VDD RANGE
IDD
PDISS
PSSR
BW_5 K
THDW
tS
eN_WB
45
75
Code = 0x00
−1
−1
Code = 0x40
Code = 0x7F
Code = 0x00
−3
0
±0.1
±0.2
15
−2
1
GND
f = 1 MHz, measured to GND,
code = 0x40
f = 1 MHz, measured to GND,
code = 0x40
VA = VDD/2
VDD = 5 V
VDD = 5 V
VDD = 3 V
VDD = 3 V
VIN = 0 V or 5 V
300
+1
+1
0
2
LSB
LSB
ppm/°C
LSB
LSB
VDD
V
45
pF
60
1
pF
nA
2.4
0.4
0.6
V
V
V
V
μA
pF
V
V
0.8
2.1
0.6
±1
5
IOL = 3 mA
IOL = 6 mA
VDD = 5.5 V; VIH = VDD or VIL = GND
VDD = 5 V; VIH = VDD or VIL = GND
VDD = 3.3 V; VIH = VDD or VIL = GND
VIH = 5 V or VIL = 0 V, VDD = 5 V
VDD = 5 V ± 10%,
code = midscale
2.7
3
2.5
0.9
5.5
7
5.2
2
40
V
μA
μA
μA
μW
±0.003
±0.05
%/%
RAB = 5 kΩ, code = 0x40
VA = 1 V rms, VB = 0 V, f = 1 kHz
VA = 5 V, ±1 LSB error band
RWB = 2.5 kΩ, RS = 0 Ω
1.2
0.05
1
6
1
Typical specifications represent average readings at 25°C and VDD = 5 V.
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
VA = VDD, wiper (VW) = no connect.
4
INL and DNL are measured at VW, with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic under operating conditions.
5
Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8
All dynamic characteristics use VDD = 5 V.
2
Rev. F | Page 3 of 20
MHz
%
μs
nV/√Hz
AD5247
Data Sheet
ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, AND 100 kΩ VERSIONS
VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD, −40°C < TA < +125°C, unless otherwise noted.
Table 2.
Parameter
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity 2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance 3
Resistance Temperature Coefficient3
Output Resistance
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE
Differential Nonlinearity 4
Integral Nonlinearity4
Voltage Divider Temperature Coefficient
Full-Scale Error (50 kΩ, 100 kΩ)
Zero-Scale Error (50 kΩ, 100 kΩ)
Full-Scale Error (10 kΩ)
Zero-Scale Error (10 kΩ)
DNL
INL
∆VW/∆T
VWFSE
VWZSE
VWFSE
VWZSE
RESISTOR TERMINALS
Voltage Range 5
Capacitance A 6
VA, VW
CA
Capacitance W6
Symbol
Conditions
Min
Typ 1
Max
Unit
R-DNL
R-INL
∆RAB
∆RAB/∆T
RWB
RWB, VA = no connect
RWB, VA = no connect
−1
−2
−20
±0.1
±0.25
+1
+2
+20
LSB
LSB
%
ppm/°C
Ω
CW
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Input Current
Input Capacitance6
Output Logic Low (SDA)
VIH
VIL
VIH
VIL
IIL
CIL
VOL
POWER SUPPLIES
Power Supply Range
Supply Current
VDD RANGE
IDD
Power Dissipation 7
Power Supply Sensitivity
ICM
PDISS
PSSR
45
75
Code = 0x00
−1
−1
Code = 0x40
Code = 0x7F
Code = 0x00
Code = 0x7F
VDD = 4.5 V to 5.5 V, code = 0x00
VDD = 2.7 V to 4.4 V, code = 0x00
−1
0
−2
0
0
±0.1
±0.2
15
−1
0.4
−0.5
0.5
0.5
GND
f = 1 MHz, measured to GND,
code = 0x40
f = 1 MHz, measured to GND,
code = 0x40
VA = VDD/2
VDD = 5 V
VDD = 5 V
VDD = 3 V
VDD = 3 V
VIN = 0 V or 5 V
300
+1
+1
0
1
0
1
1.2
LSB
LSB
ppm/°C
LSB
LSB
LSB
LSB
LSB
VDD
V
45
pF
60
1
pF
nA
2.4
0.4
0.6
V
V
V
V
µA
pF
V
V
5.5
7
5.2
2
40
±0.02
V
µA
µA
µA
µW
%/%
0.8
2.1
0.6
±1
5
IOL = 3 mA
IOL = 6 mA
2.7
VDD = 5.5 V; VIH = VDD or VIL = GND
VDD = 5 V; VIH = VDD or VIL = GND
VDD = 3.3 V; VIH = VDD or VIL = GND
VIH = 5 V or VIL = 0 V, VDD = 5 V
VDD = 5 V ± 10%, code = midscale
Rev. F | Page 4 of 20
3
2.5
0.9
±0.01
Data Sheet
AD5247
Parameter
DYNAMIC CHARACTERISTICS6, 8
Bandwidth –3 dB
Total Harmonic Distortion
VW Settling Time (10 kΩ/50 kΩ/100 kΩ)
Resistor Noise Voltage Density
Symbol
Conditions
BW
RAB = 10 kΩ/50 kΩ/100 kΩ,
code = 0x40
VA =1 V rms, f = 1 kHz, RAB = 10 kΩ
VA = 5 V ±1 LSB error band
RWB = 5 kΩ, RS = 0
THDW
tS
eN_WB
Min
Typ 1
Max
Unit
600/100/40
kHz
%
µs
nV/√Hz
0.05
2
9
Typical specifications represent average readings at 25°C and VDD = 5 V.
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
VA = VDD, wiper (VW) = no connect.
4
INL and DNL are measured at VW, with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other.
6
Guaranteed by design, not subject to production test.
7
PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8
All dynamic characteristics use VDD = 5 V.
1
2
TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, AND 100 kΩ VERSIONS
VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD, −40°C < TA < +125°C, unless otherwise noted.
Table 3.
Parameter 1, 2, 3
SCL Clock Frequency
Bus Free Time Between Stop and Start, tBUF
Hold Time (Repeated Start), tHD;STA 5
Low Period of SCL Clock, tLOW
High Period of SCL Clock, tHIGH
Setup Time for Repeated Start Condition, tSU;STA
Data Hold Time, tHD;DAT
Data Setup Time, tSU;DAT
Fall Time of Both SDA and SCL Signals, tF
Rise Time of Both SDA and SCL Signals, tR
Setup Time for Stop Condition, tSU;STO
Symbol
fSCL
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
Min
1.3
0.6
1.3
0.6
0.6
Typ 4
Max
400
Unit
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
50
0.9
100
300
300
0.6
Specifications apply to all parts.
Guaranteed by design, not subject to production test.
See timing diagrams (Figure 2, Figure 33, and Figure 34) for locations of measured values.
4
Typical specifications represent average readings at 25°C and VDD = 5 V.
5
After this period, the first clock pulse is generated.
1
2
3
t8
t2
t9
t6
SCL
t2
t3
t4
t8
t5
t7
t10
t9
t1
P
S
S
2
Figure 2. I C Interface, Detailed Timing Diagram
Rev. F | Page 5 of 20
P
03876-031
SDA
AD5247
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter
VDD to GND
VA, VW to GND
Terminal Current, Ax to Bx, Ax to Wx, Bx to Wx
Pulsed1
Continuous
Digital Inputs and Output Voltage to GND
Operating Temperature Range
Maximum Junction Temperature (TJMAX)
Storage Temperature Range
Thermal Resistance θJA2: (SC70-6)
Reflow Soldering Peak Temperature
SnPb
Pb-Free
Rating
–0.3 V to +7 V
VDD
±20 mA
±5 mA
0 V to VDD + 0.3 V
–40°C to +125°C
150°C
–65°C to +150°C
340°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
240°C
260°C
Maximum terminal current is bounded by the maximum current handling
of the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2
Package power dissipation = (TJMAX – TA)/θJA.
1
Rev. F | Page 6 of 20
Data Sheet
AD5247
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD 1
6
A
GND 2
SCL 3
5 W
TOP VIEW
(Not to Scale)
4
SDA
03876-043
AD5247
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
Mnemonic
VDD
GND
SCL
SDA
W
A
Description
Positive Power Supply.
Digital Ground and B Termination Voltage.
Serial Clock Input; Positive Edge Triggered.
Serial Data Input/Output.
Terminal W.
Terminal A.
Rev. F | Page 7 of 20
AD5247
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0.25
1.0
TA = 25°C
RAB = 10kΩ
0.4
0.2
0
VDD = 5.5V
–0.2
–0.4
–0.6
–0.8
–1.0
0
16
32
64
80
48
CODE (Decimal)
96
112
0.15
0.10
TA = –40°C, +25°C, +85°C, +125°C
0.05
0
–0.05
–0.10
–0.15
03876-005
VDD = 2.7V
03876-002
RHEOSTAT MODE INL (LSB)
0.6
–0.20
–0.25
0
128
Figure 4. R-INL vs. Code vs. Supply Voltages
32
48
64
80
CODE (Decimal)
96
112
128
0.25
TA = 25°C
RAB = 10kΩ
0.2
VDD = 2.7V
0.1
0
VDD = 5.5V
–0.2
03876-003
–0.3
–0.4
–0.5
0
16
32
64
80
48
CODE (Decimal)
96
112
0.15
0.10
VDD = 2.7V
0.05
0
VDD = 5.5V
–0.05
–0.10
–0.15
03876-006
0.3
–0.1
TA = 25°C
RAB = 10kΩ
0.20
POTENTIOMETER MODE INL (LSB)
0.4
RHEOSTAT MODE DNL (LSB)
16
Figure 7. DNL vs. Code vs. Temperature
0.5
–0.20
–0.25
0
128
16
32
64
80
48
CODE (Decimal)
96
112
128
Figure 8. INL vs. Code vs. Supply Voltages
Figure 5. R-DNL vs. Code vs. Supply Voltages
0.25
0.20
TA = +25°C
0.15
POTENTIOMETER MODE DNL (LSB)
VDD = 2.7V
RAB = 10kΩ
TA = –40°C
TA = +85°C
TA = +125°C
0.10
TA = +25°C, +85°C, +125°C
0.05
0
–0.05
TA = –40°C
–0.10
03876-004
–0.15
–0.20
–0.25
0
16
32
64
80
48
CODE (Decimal)
96
112
0.20
VDD = 2.7V
0.15
VDD = 5.5V
TA = 25°C
RAB = 10kΩ
0.10
VDD = 2.7V
0.05
0
–0.05
VDD = 5.5V
–0.10
–0.15
03876-007
0.25
POTENTIOMETER MODE INL (LSB)
VDD = 2.7V
RAB = 10kΩ
–40°C
+25°C
+85°C
+125°C
0.20
POTENTIOMETER MODE DNL (LSB)
0.8
–0.20
–0.25
0
128
16
32
64
80
48
CODE (Decimal)
96
Figure 9. DNL vs. Code vs. Supply Voltages
Figure 6. INL vs. Code vs. Temperature
Rev. F | Page 8 of 20
112
128
Data Sheet
AD5247
1.50
1.0
0.8
ZERO-SCALE ERROR (LSB)
1.25
0.4
0.2
TA = +125°C
–0.2
–0.4
TA = –40°C
TA = +25°C
–0.6
TA = +125°C
–1.0
0
16
32
48
64
80
CODE (Decimal)
96
112
0.50
0.25
TA = +85°C
–0.8
–10
5
20
35
50
65
TEMPERATURE (°C)
80
95
110
125
Figure 13. Zero-Scale Error vs. Temperature
100
0.5
VDD = 2.7V
RAB = 10kΩ
TA = –40°C, +25°C, +85°C, +125°C
0.1
0
–0.1
–0.2
03876-009
–0.3
–0.4
–0.5
0
16
32
48
64
80
CODE (Decimal)
96
112
10
VDD = 5.5V
1
VDD = 2.7V
0.1
0.01
–40 –25 –10
128
5
20
35 50
65
TEMPERATURE (°C)
100
RTHESOSTAT MODE TEMPCO (ppm/°C)
0
–0.5
VDD = 5.5V, VA = 5.5V
–1.0
–1.5
–2.0
VDD = 2.7V, VA = 2.7V
03876-010
–2.5
–25
–10
5
20 35
50
65
TEMPERATURE (°C)
80
95
80
95
110
125
Figure 14. Supply Current vs. Temperature
Figure 11. R-DNL vs. Code vs. Temperature
–3.0
–40
03876-012
0.2
110
125
5V
2.7V
90
80
70
60
50
40
30
20
10 I
WB = 200µA
RAB = 10kΩ
0
1 9 17 25 33 41 49 57 65 73 81 89 97 105 113 121
CODE (Decimal)
Figure 12. Full-Scale Error vs. Temperature
Figure 15. ∆RWB/∆T vs. Code
Rev. F | Page 9 of 20
03876-013
0.3
DIGITAL INPUTS = 0V
CODE = 0x40
IDD, SUPPLY CURRENT (µA)
–40°C
+25°C
+85°C
+125°C
0.4
RHEOSTAT MODE DNL (LSB)
VDD = 2.7V, VA = 2.7V
0
–40 –25
128
Figure 10. R-INL vs. Code vs. Temperature
RHEOSTAT
MODE
INL (LSB)
FULL-SCALE
ERROR
(LSB)
VDD = 5.5V, VA = 5.5V
0.75
03876-011
TA = +25°C
0
1.00
03876-008
RHEOSTAT MODE INL (LSB)
TA = –40°C
TA = +85°C
0.6
AD5247
Data Sheet
0
POTENTIOMETER MODE TEMPCO (ppm/°C)
100
2.7V
5V
80
0x40
–6
60
–12
40
–18
GAIN (dB)
20
0
–20
0x20
0x10
0x08
–24
0x04
–30
0x02
–36
0x01
–60
–48
–80
–54
VA = VDD
RAB = 10kΩ
1
–60
1k
03876-014
10 19 28 37 46 55 64 73 82 91 100 109 118 127
CODE (Decimal)
Figure 16. ∆VWB/∆T vs. Code
100k
FREQUENCY (Hz)
10M
0
0x40
–6
0x20
–12
0x10
–18
0x40
–6
0x20
–12
0x10
–18
0x08
GAIN (dB)
–24
0x04
–30
0x02
0x01
–36
–42
0x08
–24
0x04
–30
0x02
–36
0x01
–42
–48
03876-015
–48
–54
–60
1k
10k
100k
1M
–54
–60
1k
10M
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 17. Gain vs. Frequency vs. Code, RAB = 5 kΩ
Figure 20. Gain vs. Frequency vs. Code, RAB = 100 kΩ
0
0
0x40
–6
–6
5kΩ
0x20
–12
–12
10kΩ
0x10
–18
–18
100kΩ
GAIN (dB)
0x08
–24
0x04
–30
0x02
–36
0x01
–24
50kΩ
–30
–36
–42
–42
–54
–60
1k
10k
100k
1M
03876-019
–48
–48
03876-016
GAIN (dB)
1M
Figure 19. Gain vs. Frequency vs. Code, RAB = 50 kΩ
0
GAIN (dB)
10k
03876-018
–100
03876-017
–42
–40
–54
–60
1k
10M
FREQUENCY (Hz)
10k
100k
1M
FREQUENCY (Hz)
Figure 18. Gain vs. Frequency vs. Code, RAB = 10 kΩ
Figure 21. −3 dB Bandwidth @ Code = 0x80
Rev. F | Page 10 of 20
10M
Data Sheet
AD5247
0.30
IDD (µA)
0.25
VDD = 5.5V
VA = 5.0V
VB = 0V
CODE 0x40 TO CODE 0x3F
TA = 25°C
A-VDD = 5.5V
CODE = 0x55
B-VDD = 5.5V
CODE = 0x7F
0.20
C-VDD = 2.7V
CODE = 0x55
0.15
D-VDD = 2.7V
CODE = 0x7F
TA = 25°C
RAB = 10kΩ
VW
0.10
A
D
10k
100k
FREQUENCY (Hz)
03876-020
C
0
1k
03876-023
B
0.05
1M
200ns/DIV
Figure 22. IDD vs. Frequency
Figure 25. Midscale Glitch, Code 0x40 to Code 0x3F
150
TA = 25°C
RAB = 50kΩ
VDD = 5.5V
VA = 5.0V
VB = 0V
CODE 0x00 TO CODE 0x7F
100
VDD = 2.7V
VW
75
50
25
VDD = 5.5V
03876-021
03876-024
WIPER RESISTANCE (Ω)
125
TA = 25°C
RAB = 10kΩ
0
0
16
32
48
64
80
CODE (Decimal)
96
112
4µs/DIV
128
Figure 23. Wiper Resistance vs. Code vs. VDD
Figure 26. Large Signal Settling Time
TA = 25°C
RAB = 10kΩ
FCLK = 100kHz
VDD = 5.5V
VA = 5.0V
VB = 0V
VW
5V
CLK
03876-022
0V
1µs/DIV
Figure 24. Digital Feedthrough
Rev. F | Page 11 of 20
AD5247
Data Sheet
TEST CIRCUITS
Figure 27 to Figure 32 define the test conditions used in the Specifications section.
VA
A
VDD
W
V+
A
V+
B
V+ = VDD ± 10%
DUT
V+ = VDD
1LSB = V+/2N
PSSR (%/%) =
W
B
Figure 27. Potentiometer Divider Nonlinearity Error (INL, DNL)
ΔVDD%
VMS
03876-025
VMS
ΔVMS%
03876-028
DUT
Figure 30. Power Supply Sensitivity (PSS, PSSR)
NO CONNECT
DUT
DUT
IW
W
W
B
OP27
B
03876-026
VMS
+15V
A
VIN
VOUT
03876-029
A
–15V
Figure 28. Resistor Position Nonlinearity Error (R-INL, R-DNL)
Figure 31. Gain vs. Frequency
NC
DUT
W
VW
IW = VDD/RNOMINAL
VDD
B
RW = [VMS1 – VMS2]/IW
GND B
03876-027
VMS1
A
NC
Figure 29. Wiper Resistance
W
ICM
VCM
03876-030
A
VMS2
DUT
Figure 32. Common-Mode Leakage Current
Rev. F | Page 12 of 20
Data Sheet
AD5247
I2C INTERFACE
The following abbreviations are used in this section:
•
S = start condition
•
W = write
•
P = stop condition
•
R = read
•
A = acknowledge
•
A6, A5, A4, A3, A2, A1, A0 = address bits
•
X = don’t care
•
D6, D5, D4, D3, D2, D1, D0 = data bits
Table 6. Write Mode
S
A6
A5
A4
A3
A2
A1
A0
W
A
X
D6
D5
Slave Address Byte
D4
D3
D2
D1
D0
A
P
D2
D1
D0
A
P
Data Byte
Table 7. Read Mode
S
A6
A5
A4
A3
A2
A1
Slave Address Byte
A0
R
A
1
0
9
D6
D5
D4
D3
Data Byte
9
1
1
SCL
A6
A5
A4
A3
A2
A1
A0
FRAME 1
SLAVE ADDRESS BYTE
START BY
MASTER
X
R/W
D6
D5
ACK ACK BY
AD5247
D4
D3
D2
D1
D0
ACK BY
AD5247
FRAME 2
DATA BYTE
STOP BY
MASTER
03876-032
SDA
Figure 33. Writing to the RDAC Register
1
9
1
9
SCL
A5
A4
A3
A2
A1
A0
D6
ACK BY
AD5247
FRAME 1
SLAVE ADDRESS BYTE
START BY
MASTER
0
R/W
D5
D4
D3
D2
FRAME 2
RDAC REGISTER
D1
D0
NO ACK BY
MASTER
STOP BY
MASTER
03876-033
A6
S
Figure 34. Reading from the RDAC Register
Table 8. I2C Slave Addresses
Model
AD5247BKS5-R2
AD5247BKS5-RL7
AD5247BKSZ5-RL7
AD5247BKS10-R2
AD5247BKS10-RL7
AD5247BKSZ10-RL7
AD5247BKSZ10-1RL7
AD5247BKSZ10-2RL7
AD5247BKS50-R2
Slave Addresses
A6 A5 A4
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
1
0
0
1
0
1
0
A3
1
1
1
1
1
1
0
0
1
A2
1
1
1
1
1
1
1
1
1
A1
1
1
1
1
1
1
1
1
1
A0
0
0
0
0
0
0
1
0
0
Model
AD5247BKS50-RL7
AD5247BKSZ50-RL7
AD5247BKS100-R2
AD5247BKSZ100-R2
AD5247BKS100-RL7
AD5247BKSZ100-RL7
AD5247BKSZ100-1RL7
AD5247BKSZ100-2RL7
Rev. F | Page 13 of 20
Slave Address
A6 A5 A4
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
1
0
0
1
A3
1
1
1
1
1
1
0
0
A2
1
1
1
1
1
1
1
1
A1
1
1
1
1
1
1
1
1
A0
0
0
0
0
0
0
1
0
AD5247
Data Sheet
THEORY OF OPERATION
The AD5247 is a 128-position, digitally-controlled variable
resistor (VR) device. An internal power-on preset places the
wiper at midscale during power-on, which simplifies the
default condition recovery at power-up.
The general equation determining the digitally programmed
output resistance between W and B is
RWB (D) =
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance (RAB) of the RDAC between Terminal A
and Terminal B is available in 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The
final two or three digits of the part number determine the nominal
resistance value; for example, 10 kΩ = 10 and 50 kΩ = 50. The
RAB of the VR has 128 contact points accessed by the wiper
terminal, plus the B terminal contact. The 7-bit data in the
RDAC latch is decoded to select one of the 128 possible settings.
Assuming a 10 kΩ part is used, the wiper’s first connection starts
at the B terminal for Data 0x00. Because there is a 50 Ω wiper
contact resistance, such a connection yields a minimum of 100 Ω
(2 × 50 Ω) resistance between Terminal W and Terminal B. The
second connection is the first tap point, corresponding to 178 Ω
(RWB = RAB/128 + RW = 78 Ω + 2 × 50 Ω) for Data 0x01. The third
connection is the next tap point, representing 256 Ω (2 × 78 Ω
+ 2 × 50 Ω) for Data 0x02, and so on. Each LSB data value increase
moves the wiper up the resistor ladder until the last tap point is
reached at 10,100 Ω (RAB + 2 × RW).
Figure 35 shows a simplified diagram of the equivalent RDAC
circuit where the last resistor string is not accessed.
Ax
D6
D5
D4
D3
D2
D1
D0
(1)
where:
D is the decimal equivalent of the binary code loaded in the
7-bit RDAC register.
RAB is the end-to-end resistance.
RW is the wiper resistance contributed by the on resistance of
the internal switch.
In summary, if RAB = 10 kΩ and the Terminal A is open-circuited,
the output resistance RWB, shown in Table 9, is set for the indicated
RDAC latch codes.
Table 9. Codes and Corresponding RWB Resistance
D (Decimal)
127
64
1
0
RWB (Ω)
10,072
5150
228
150
Output State
Full scale (RAB + 2 × RW)
Midscale
1 LSB
Zero scale (wiper contact resistance)
Note that in the zero-scale condition, a finite resistance of
100 Ω between Terminal W and Terminal B is present. Care
should be taken to limit the current flow between W and B in
this state to a maximum pulse current of no more than 20 mA.
Otherwise, degradation or possible destruction of the internal
switch contact can occur.
Similar to the mechanical potentiometer, the resistance of
the RDAC between Wiper W and Terminal A also produces a
digitally controlled complementary resistance, RWA. When
these terminals are used, the Terminal B can be opened. Set the
resistance value for RWA to start at a maximum value of resistance
and to decrease the data loaded in the latch increases in value.
The general equation for this operation is
RS
RS
Wx
RDAC
RWA (D) =
Bx
03876-034
LATCH
AND
RS
DECODER
D
× R AB + 2 × RW
128
Figure 35. AD5247 Equivalent RDAC Circuit
128 − D
× R AB + 2 × RW
128
(2)
If RAB = 10 kΩ and the B terminal is open-circuited, the output
resistance, RWA, shown in Table 10, is set for the indicated RDAC
latch codes.
Table 10. Codes and Corresponding RWA Resistance
D (Decimal)
127
64
1
0
RWA (Ω)
228
5150
10,071
10,150
Output State
Full scale
Midscale
1 LSB
Zero scale
Typical device-to-device matching is process lot dependent
and can vary by up to ±30%. Because the resistance element
is processed in thin film technology, the change in RAB with
temperature has a very low 45 ppm/°C temperature coefficient.
Rev. F | Page 14 of 20
Data Sheet
AD5247
PROGRAMMING THE POTENTIOMETER DIVIDER
The 2-wire I2C serial bus protocol operates as follows:
Voltage Output Operation
1.
The master initiates a data transfer by establishing a start
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high (see Figure 33). The
following byte is the slave address byte, consisting of the
7-bit slave address followed by an R/W bit (this bit determines
whether data is read from or written to the slave device). The
slave, whose address corresponds to the transmitted address,
responds by pulling the SDA line low during the ninth clock
pulse (this is termed the acknowledge bit). At this stage, all
other devices on the bus remain idle while the selected
device waits for data to be written to or read from its serial
register. If the R/W bit is high, the master reads from the
slave device. If the R/W bit is low, the master writes to the
slave device.
2.
In write mode, after acknowledgement of the slave address
byte, the next byte is the data byte. Data is transmitted over
the serial bus in sequences of nine clock pulses (eight data
bits followed by an acknowledge bit). The transitions on
the SDA line must occur during the low period of SCL
and remain stable during the high period of SCL (see
Figure 33).
3.
In read mode, after acknowledgment of the slave address
byte, data is received over the serial bus in sequences of
nine clock pulses (a slight difference from write mode,
where eight data bits are followed by an acknowledge bit).
Similarly, the transitions on the SDA line must occur
during the low period of SCL and remain stable during
the high period of SCL (see Figure 34).
4.
When all data bits have been read or written, a stop condition is established by the master. A stop condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master pulls the SDA line
high during the 10th clock pulse to establish a stop condition
(see Figure 33). In read mode, the master issues a no
acknowledge for the ninth clock pulse (that is, the SDA
line remains high). The master then brings the SDA line
low before the 10th clock pulse, which goes high to establish
a stop condition (see Figure 34).
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A, proportional to the input voltage
at A-to-B. Unlike the polarity of VDD to GND, which must be
positive, voltage across A-to-B, W-to-A, and W-to-B can be at
either polarity.
If ignoring the effect of the wiper resistance for approximation,
connecting the Terminal A to 5 V and the Terminal B to ground
produces an output voltage at the wiper-to-B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage
applied across Terminal A and Terminal B divided by the 128
positions of the potentiometer divider. The general equation
defining the output voltage at VW with respect to ground for any
valid input voltage applied to Terminal A and Terminal B is
VW (D) =
D
×VA
128
(3)
A more accurate calculation that includes the effect of wiper
resistance, VW, is
VW (D) =
RWB(D)
× VA
RAB
(4)
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
rheostat mode, divider mode makes the output voltage mainly on
the ratio of Internal Resistor RWA to Internal Resistor RWB, and
not the absolute values. Therefore, the temperature drift reduces
to 15 ppm/°C.
I2C-COMPATIBLE 2-WIRE SERIAL BUS
The first byte of the AD5247 is a slave address byte (see the I2C
Interface section). It has a 7-bit slave address and an R/W bit.
The 5 kΩ and 50 kΩ options support one 7-bit slave address
while the 10 kΩ and 100 kΩ options each have three hard-coded
slave address options available (see Table 8 for a full list of slave
address locations). The extra hard coded slave addresses on the
10 kΩ and 100 kΩ options allow users to employ up to three of
these devices on one I2C bus. The seven MSBs of the slave address
are followed by 0 for a write command or 1 to place the device
in read mode.
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing the part only
once. For example, after the RDAC has acknowledged its slave
address in the write mode, the RDAC output updates on each
successive byte. If different instructions are needed, the write/read
mode has to start again with a new slave address and data byte.
Similarly, a repeated read function of the RDAC is also allowed.
Rev. F | Page 15 of 20
AD5247
Data Sheet
LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE
MAXIMUM OPERATING CURRENT
While most legacy systems can be operated at one voltage, a
new component can be optimized at another voltage. When
two systems operate the same signal at two different voltages,
proper level shifting is needed. For instance, users can employ
a 3.3 V E2PROM to interface with a 5 V digital potentiometer. A
level shifting scheme is needed to enable a bidirectional communication so that the setting of the digital potentiometer can be
stored in and retrieved from the E2PROM. Figure 36 shows one
of the level-shifting implementations. M1 and M2 can be any
N-channel signal FETs, or if VDD falls below 2.5 V, M1 and M2
can be low threshold FETs such as the FDV301N.
At low code values, the user should be aware that, due to low
resistance values, the current through the RDAC might exceed
the 5 mA limit. In Figure 39, a 5 V supply is placed on the wiper,
and the current through Terminal W and Terminal B is plotted
with respect to code. A line is also drawn denoting the 5 mA
current limit. Note that at low code values (particularly for the
5 kΩ and 10 kΩ options), the current level increases significantly. Care should be taken to limit the current flow between
W and B in this state to a maximum continuous current of
5 mA and a maximum pulse current of no more than 20 mA.
Otherwise, degradation or possible destruction of the internal
switch contacts can occur.
VDD1 = 3.3V
VDD2 = 5V
100
RP
RP
RP
RP
G
D
S
SDA2
10
D
SCL2
M2
3.3V
5V
03876-035
SCL1
S
AD5247
E2PROM
IWB CURRENT (mA)
G
M1
Figure 36. Level-Shifting for Operation at Different Potentials
5mA CURRENT LIMIT
RAB = 5kΩ
1
RAB = 10kΩ
RAB = 50kΩ
0.1
ESD PROTECTION
RAB = 100kΩ
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures as shown in Figure 37. This applies
to digital input pins (SDA and SCL).
340Ω
GND
0.01
0
16
32
64
80
48
CODE (Decimal)
96
112
128
Figure 39. Maximum Operating Current
POWER-UP SEQUENCE
LOGIC
03876-036
SDA/
SCL
03876-039
SDA1
Figure 37. ESD Protection of Digital Pins
TERMINAL VOLTAGE OPERATING RANGE
The AD5247 VDD and GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer operation.
Supply signals present on Terminal A and Terminal W that exceed
VDD or GND are clamped by the internal forward biased diodes
(see Figure 38).
Because the ESD protection diodes limit the voltage compliance
at Terminal A and Terminal W (see Figure 38), it is important
to power VDD/GND before applying any voltage to Terminal A
and Terminal W; otherwise, the diode is forward-biased such
that VDD is powered unintentionally and can affect the rest of the
user’s circuit. The ideal power-up sequence is in the following
order: GND, VDD, digital inputs, VA, and VW. The relative order
of powering VA and VW and the digital inputs is not important
as long as they are powered after VDD/GND.
VDD
A
GND
03876-038
W
Figure 38. Maximum Terminal Voltages Set by VDD and GND
Rev. F | Page 16 of 20
Data Sheet
AD5247
It is good practice to employ a compact, minimum lead-length
layout design. The leads to the inputs should be as direct as possible with minimum conductor length. Ground paths should
have low resistance and low inductance.
AD5247. The measurement over time shows that the device
draws approximately 1.3 µA and consumes negligible power.
Over a course of 30 days, the battery was depleted by less than
2%, the majority of which was due to the intrinsic leakage
current of the battery itself.
110%
Similarly, it is good practice to bypass the power supplies with
quality capacitors for optimum stability. Supply leads to the device
should be bypassed with 0.01 µF to 0.1 µF disc or chip ceramic
capacitors. Low ESR 1 µF to 10 µF tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient
disturbance and low frequency ripple (see Figure 40). Note that the
digital ground should also be joined remotely to the analog ground
at one point to minimize the ground bounce.
TA = 25°C
BATTERY LIFE DEPLETED
106%
VDD
VDD
C3
10µF
108%
+
104%
102%
100%
98%
96%
94%
03876-041
LAYOUT AND POWER SUPPLY BYPASSING
92%
C1
0.1µF
AD5247
90%
0
5
10
15
DAYS
20
25
30
Figure 41. Battery Operating Life Depletion
03876-040
GND
Figure 40. Power Supply Bypassing
CONSTANT BIAS TO RETAIN RESISTANCE SETTING
For users who desire nonvolatility but cannot justify the additional
cost for the EEMEM, the AD5247 can be considered a low cost
alternative because it maintains a constant bias to retain the
wiper setting. The AD5247 is specifically designed with low
power in mind, which allows low power consumption even in
battery-operated systems.
This demonstrates that constantly biasing the potentiometer
is a practical approach. Most portable devices do not require
the removal of batteries for charging. Although the resistance
setting of the AD5247 is lost when the battery needs replacement, such events occur rather infrequently. As a result, this
inconvenience is justified by the lower cost and smaller size
offered by the AD5247. If total power is lost, the user should
be provided with a means to adjust the setting accordingly.
Figure 41 demonstrates the power consumption from a 3.4 V
450 mA/hr Li-Ion cell phone battery, which is connected to the
Rev. F | Page 17 of 20
AD5247
Data Sheet
OUTLINE DIMENSIONS
2.20
2.00
1.80
6
5
4
1
2
3
0.65 BSC
1.30 BSC
1.00
0.90
0.70
0.10 MAX
COPLANARITY
0.10
2.40
2.10
1.80
1.10
0.80
0.30
0.15
SEATING
PLANE
0.40
0.10
0.22
0.08
0.46
0.36
0.26
COMPLIANT TO JEDEC STANDARDS MO-203-AB
072809-A
1.35
1.25
1.15
Figure 42. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD5247BKSZ5-RL7
AD5247BKSZ10-RL7
AD5247BKSZ10-1RL7
AD5247BKSZ10-2RL7
AD5247BKSZ50-RL7
AD5247BKSZ100-R2
AD5247BKSZ100-RL7
AD5247BKSZ100-1RL7
AD5247BKSZ100-2RL7
EVAL-AD5247DBZ
1
2
RAB (kΩ)
5
10
10
10
50
100
100
100
100
Temperature Range
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Package Description2
6-lead Thin Shrink Small Outline Transistor Package [SC70]
6-lead Thin Shrink Small Outline Transistor Package [SC70]
6-lead Thin Shrink Small Outline Transistor Package [SC70]
6-lead Thin Shrink Small Outline Transistor Package [SC70]
6-lead Thin Shrink Small Outline Transistor Package [SC70]
6-lead Thin Shrink Small Outline Transistor Package [SC70]
6-lead Thin Shrink Small Outline Transistor Package [SC70]
6-lead Thin Shrink Small Outline Transistor Package [SC70]
6-lead Thin Shrink Small Outline Transistor Package [SC70]
Evaluation Board
Package
Option
KS-6
KS-6
KS-6
KS-6
KS-6
KS-6
KS-6
KS-6
KS-6
Z = RoHS compliant part.
The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options.
Rev. F | Page 18 of 20
Branding
D96
D95
D5E
DAK
D97
D98
D98
DAJ
DAL
Data Sheet
AD5247
NOTES
Rev. F | Page 19 of 20
AD5247
Data Sheet
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2003–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03876-0-5/12(F)
Rev. F | Page 20 of 20
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